INTRODUCTION Dr. Cadien has made many significant breakthroughs in all aspects
of chemical mechanical polishing which are documented in his many
patents. Dr. Cadien also has been responsible for numerous breakthroughs
in optical interconnects and plasmons, and in several other areas
of semiconductor processing. In addition to his research and development
activities at Intel, Dr. Cadien was also one of company’s intellectual
property leaders and key experts. In addition to mentoring many
invention disclosures, he was a member of the process patent committees
that decide what invention disclosure should be patented, and he
also is the owner of intellectual property for the Technology and
Manufacturing Group at Intel, this group includes all integrated
circuit manufacturing, process development and research, and materials
and equipment development at Intel. BOOK CHAPTERS “Chemical Mechanical Polishing”, K.C. Cadien, Handbook of Thin
Film Deposition Processes and Techniques, 2nd Ed., Noyes Publication,
2002. REFEREED JOURNALS “Effects of viscosity-dependent diffusion in the analysis of rotating disk electrode data”, J.H. Han, A. M. Bowen, T.N. Andryushchenko, R.P. Chalupa, A.E. Miller, H.S. Simka, K. Cadien, S. Shankar, to be published in the Journal of Applied Electrochemistry “Surface plasmon polarization filtering in a single mode dielectric waveguide”, P. S. Davids, B. A. Block, and K. Cadien, Optics Express, 13, 7063 (2005) “Effects of K3[Fe(CN)6] slurry’s pH value and applied potential
on tungsten removal rate for chemical-mechanical planarization application”,
S.B. Akonko, D.Y. Li, M. Ziomek-Moroz, J. Hawk, A. E. Miller, K.
Cadien, Wear, 259, 1299 (2005) K. Cadien, M.R. Reshotko, B. A. Block, A.M. Bowen, D.L. Kencke, and P. Davids, “Challenges for on-chip optical interconnects”, Proc. SPIE, 5730, 133 (2005) “On-chip optical interconnects”, M.J.Kobrinsky, B.A.Block, J.-F.Zheng, B.C.Barnett, E.Mohammed, M.Reshotko, F.Robertson, S.List, I. Young, and K. Cadien, Intel Technology Journal, 8, No.2, (2004) pp129-143, http://www.intel.com/technology/itj/2004/volume08issue02/art05_on-chip/p01_abstract.htm “An overview of the corrosion-wear interaction for planarizing metallic thin films”, M. Ziomek-Moroz, A. E. Miller, J. Hawk, K. Cadien, D. Li, Wear of Materials, 255, 869(2003). “Advances in characterization of CMP consumables”, M.Moinpour, A.Tregub, A.Oehler, and K.Cadien, MRS Bulletin, 27, 766(2002). “Chemically induced defects during copper polish”, A.E.Miller, P.B.Fischer, A.D.Feller, and K.C.Cadien, Proceedings of the IEEE International, 2001. pp 143-145. Plus 22 referred journal publications prior to 2001. PATENTS FILED/GRANTED T. N. Andreyushchenko, K. Cadien, P. B. Fischer, and V. M. Dubin, “Method to fabricate interconnect structures”, US Patent 7,087,517, granted August 8, 2006 K. Cadien and A. Feller, “Abrasives for chemical mechanical polishing “, US Patent 7,087,188, granted August 8, 2006 A. E. Miller, A. Feller, and K. Cadien, “High pH slurry for chemical mechanical polishing of copper”, US Patent 6,909,193, granted June 21, 2005 K. Cadien and A. Feller, “Abrasives for chemical mechanical polishing “, US Patent 6,881,674, granted April 19, 2005 P. B. Fischer, A.E. Miller, K. Cadien, and C. E. Barns, “Introducing nanotubes in trenches and structures formed thereby”, US Patent application number 20060141222, filed December 29, 2004 H. S. Simka, S. Shankar, L. Jiang, P. B. Fischer, A. E. Miller, and K. Cadien, “Copper containing abrasive particles for copper CMP slurries”, US Patent application number 20060138087, filed December 29, 2004 H-M. Park and K. Cadien, “Interconnects having a recessed capping layer and methods of fabricating”, US Patent application number 20060128144, filed December 15, 2004 A. E. Miller, A. Feller, and K. Cadien, “High pH slurry for chemical
mechanical polishing of copper”, US Patent 6,825,117, granted November
30, 2004 A. E. Miller, A. Feller, and K. Cadien, “Ceric-ion slurry for use in chemical-mechanical polishing”, US Patent 6,752,844, granted June 22, 2004 A. E. Miller, A. Feller, and K. Cadien, “Slurry and method for chemical mechanical polishing of copper”, US Patent 6,740,591, granted May 25, 2004 G. Marcyk and K. Cadien,“Low temperature chemical mechanical polishing of dielectric materials”, US Patent 6,726,529, granted April 27, 2004 A. E. Miller, A. Feller, and K. Cadien, “Method and chemistry for cleaning of oxidized copper during chemical mechanical polishing “, US Patent 6,719,614, granted April 13, 2004 K.Cadien, “Methods for the plasma formation of a microelectronic barrier layer”, US Patent application number 20060141780, filed December 23, 2004 A. E. Miller, A. Feller, and K. Cadien, “Method and chemistry for cleaning of oxidized copper during chemical mechanical polishing “, US Patent 6,464,568, granted October 15, 2002 A. E. Miller, A. Feller, and K. Cadien, “Method and chemistry for cleaning of oxidized copper during chemical mechanical polishing “, US Patent 6,443,814, granted September 3, 2002 K.Cadien and A. Feller, “Slurries for chemical mechanical polishing”,
US Patent K. Cadien, A. Feller, M. Buehler, and P. B. Fischer, “Ceria based slurry for chemical-mechanical polishing”, US Patent 6,358,853, granted March 19, 2002 K.Cadien and A. Feller, “Slurries for chemical mechanical polishing”, US Patent 6,178,585 granted January 30, 2001 Plus 14 patents granted prior to 2001.
K. Cadien, “Fundamental Understanding of Low K Copper Polish”, MIT, Departments of Mechanical Engineering and Electrical Engineering, Boston, Massachusetts, October 16, 2006. K. Cadien, “On-chip optical interconnects”, CMOS Emerging Technologies Workshop, Banff, Alberta, July 19-21, 2006. K. Cadien, M.R. Reshotko, B. A. Block, A.M. Bowen, D.L. Kencke, and P. Davids, “Challenges for on-chip optical interconnects”, Invited Talk, Optoelectronics 2005, Optoelectronic Integration on Silicon III, San Jose, CA, January 22-27 , 2005. K.Cadien, “Analytical and Reliability Challenges for Emerging Si
Technologies”, K. Cadien, “On-Chip Optical Interconnects”, iCore Presentation, University of Alberta, Department of Electrical and Computer Engineering, November 10, 2004. K. Cadien, “Photonics Research in LTD”, School of Engineering, Univerity of Illinois at Champaign-Urbana, April 23, 2004. K. Cadien, M. Kobrinsky, B. Block, “On-Chip Optical Interconnects: an Industry Perspective”, Invited Talk, SPIE, Optoelectronics 2004, Optoelectronic Integration on Silicon II, San Jose, January 27, 2004. K. Cadien, “Working with Components Research…A Glimpse into the Future”, Intel Environmental Health and Safety Map Day, Keynote Speech, November 12, 2003. P.Davids, B.Block, M.Reshotko, K.Cadien, V.Singh, “3D Electromagnetic Simulation of Integrated Optical Devices Compatible with CMOS Processing”, Progress in Electromagnetic Research Symposium (PIERS 2003), Honolulu HI, (2003). K. Cadien, “Why is Scientific Understanding Important at Intel?” Intel Arizona Technical Excellence Conference, keynote talk, Chandler, AZ, October 28, 2003 K. Cadien, “Breaking Barriers to Moore’s Law : The future of Interconnects”, Distinguished Lecture, Department of Electrical and Computer Engineering, University of Rochester, October 15 ,2003. K. Cadien, “Polymers in Microelectronics”, Keynote Speech, Intel Polymer Workshop, October 2002. K. Cadien, “Breaking Barriers to Moore’s Law”, University of British Columbia, Department of Electrical and Computer Engineering Seminar, July, 2002. K. Cadien, “The Future of CMP: Materials and Technologies for the Next Five Years”, NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing, Annual Retreat and Semi-Annual Industrial Advisory Board Meeting, Stanford University, Palo Alto, California, August 8-9, 2001. M. Moinpour, A. Tregub, J. Sorooshian, A. Oehler, R. Golzarian, A.Rawat, A. Miller, P. Fischer, D. Feller, and K. Cadien, “Challenges in CMP Consumables Characterization”, 6th International Symposium on CMP, Lake Placid, NY, August 2001. K. Cadien, “The Future of Interconnects: Materials and Technology”, Materials Science and Engineering Colloquium, University of Illinois at Urbana-Champaign, April 30, 2001.
HONOURS AND AWARDS Intel Teamwork Award for “Development of the world’s first high performance high k/metal gate technology”, 2005. Intel Quality & Reliability Technical Symposium 2004, Best paper in Session 1 award, “Analytical and Reliability Challenges for Emerging Si Technologies”. EXTERNAL PHD EXAMINATION COMMITTEES INTEL COMMITTEE SERVICE Intel’s strategic long range planning committee, Member, 2003 to Present Intel’s strategic roadmap core team, Member, 2003 to Present Intel’s bandwidth and I/O working group, Member, 2004 to Present Intel Materials Principal Engineer selection team, Member, 2003 to Present Intel Fellow Selection Committee (committee of Intel Fellows and VPs that select Intel Fellows from nominated candidates) Member 2003, 2004 Diversity taskforce leader, Components Research, Intel Corporation 2002 Optical and Interconnect Strategic Research Committee (funds university research), Member 2003 to Present INTEL INTELLECTUAL PROPERTY SERVICE UNIVERSITY SERVICE Mentor to Intel graduate fellow students at MIT, RPI, University of Illinois, University of Washington, and Oregon State University 1996 to Present Executive Committee, Rensselaer Polytechnic Institute, 1999 to 2003 Semiconductor Research Corporation. Mentor to many projects over the last five years including CMP projects at Clarkson University, MIT and the University of Arizona, and optical projects at the University of Rochester and University of Washington PROFESSIONAL SERVICE PROFESSIONAL MEMBERSHIPS
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