The SLT is closely integrated into the CTD readout electronics. The sense wires are read out individually by a FADC system containing 16 channels per board (two cells). A DSP on each FADC board analyses the FADC data to produce, amongst other things, drift times. The drift times are the input data to the SLT. The FADC boards are further grouped into 16 crates of 18 boards each.
To simplify the connections for the first level trigger (FLT) and to exploit parallel processing in the SLT, the CTD will be read out in azimuthal sectors. The chamber is divided into 16 azimuthal sectors and each one assigned to a FADC crate.
High 
tracks from the bunch-crossing point are almost
radial.
The cell information for these tracks will resides in
a single sector and hence a single crate.
For NC events, 76% of all tracks are contained in two
sectors and above a of 300 MeV/c a track is always
contained in two sectors [2].
Thus overlapping sector processors will pick up most of the
interesting tracks.
We plan on implementing this by passing the information
from the edges of adjacent sectors to neighbouring sectors
by transputer links between crates.
The CTD SLT will be implemented in an array of transputers
forming an interlocking network with the data acquisition
system.
The SLT transputers will be either T4's or T8's depending
on the need for floating point
arithmetic.
The minimal number of transputers is determined by the
number of links needed for communication by the SLT, data
acquisition system, and monitoring network.
We envision SLT local processing being performed on two or
more transputers on each FADC readout-controller board (one
board per crate).
The transputers search for track segments within local
cell masks and these segments are matched, along with the
adjacent crate segments, to form tracks at a higher level
of processing.
Figure 1 show the readout controller transputer
link connections.
Figure 1: Readout controller transputer link
connections.