Edge triggering is when the flip-flop state is changed as the rising or falling edge of a clock signal passes through a threshold voltage (figure 7.24). This true dynamic clock input is insensitive to the slope or time spent in the high or low state.
Figure 7.24: A slow or delayed gate can be used to convert
a level change into a short pulse.
Both types of dynamic triggering are represented on a schematic diagram by a special symbol near the clock input (figure 7.25). In addition to the clock and data inputs most IC flip-flop packages will also include set and reset (or mark and erase) inputs. The additional inputs allow the flip-flop to be preset to an initial state without using the clocked logic inputs.
Figure 7.25: The schematic symbols for a) a positive
edge-triggered JKFF, b) a negative (falling) edge-triggered JKFF
and c) a negative edge-triggered JKFF with set and reset inputs.