We can simulate a dynamic clock input by putting two flip-flops in tandem, one driving the other in a master/slave arrangement as shown in figure 7.23. The slave is clocked in a complementary fashion to the master.
Figure 7.23: An implementation of the master/slave
flip-flop.
This arrangement is still pulse triggered.
The data inputs are written onto the master flip-flop while the clock
is true and transferred to the slave when the clock becomes false.
The arrangement guarantees that the 
outputs of the slave can
never be connected to the slave's own RS inputs.
The design overcomes signal racing (ie. the input signals never
catch up with the signals already in the flip-flop).
There are however a few special states when a transition can occur in
the master and be transferred to the slave when the clock is high.
These are known as ones catching and are common in master/slave
designs.