Lab 3: VHDL Synthesis and Extracted-Timing Simulation

Please read the requirements for lab assignments.

In this lab, you will design systems in VHDL, synthesize them, extract timing information and simulate using the extracted timing information.  You will also use static timing analysis to find the performance of circuits and to tune a pipelined circuit.  Static timing analysis finds the slowest path through a circuit without simulation or considering specific data, hence the word "static".  Static timing analysis can be used to measure delays, setup/hold times and minimum clock periods.

The use of the MAX+PLUS II "Timing Analyzer" is described.

You will be using the Altera MAX+PLUS II tools (maxplus2 is available on the CAD suns, or sign out  CD-1 for installation on your own PC).

This lab has two parts: an exercise that is not handed in, in which you will become familiar with the tools, and a lab that will be submitted for marking, in which you will create your own design.

Labs are to be done individually.  Please feel free to consult the professor, the T.A. or your fellow students for help with tools and concepts.
 

Hints

Interfaces -> VHDL netlist reader settings...
and select VHDL-1993

Options -> Snap to Grid

Assign -> Device ...
select device family: FLEX10K from the first list
deselect show only fastest speed grades
select EPF10K20RC240-4 from the second list

When things aren't going right...

When things aren't going right and the error messages aren't very meaningful, try these desperate
measures:

• Narrow down what's causing the mystery problems.  Comment out large chunks of VHDL code, including recent additions, until the error goes away.
• See if your code compiles in another tool such as Mentor Graphics.
• Quit max2win and restart it.
• Some of your configuration files (e.g. *.acf) may have become corrupted.  Quit max2win, rename your acf file

( % mv thing.acf thing.acf.backup )
and restart maxplus2.  If all else fails, move your *.vhd files to a new directory and recompile.
• Try removing ~/maxplus2.ini and restarting max2win
• Check you disk quota

% fs lq

Exercise (do not hand in)

1164 Std_logic

Become Familiar with MAX+PLUS II

% mkdir ~/ee552/lab3
% cd ~/ee552/lab3
% max2win &

Simulate a Simple Combinational Circuit

--------------------
-- Adder

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity adder is
        generic(adder_width :positive := 4);
        port(a,b: in std_logic_vector(adder_width-1 downto 0);
                sum: out std_logic_vector(adder_width downto 0)
        );
end adder;

architecture behavioural of adder is
begin

        sum <= a + b;

end behavioural;
 

Delay Analysis

MAX+plus II -> Timing Analyzer ...
Analysis -> Delay Matrix
Start

 Read the online documentation for the maxplus2 Timing Analyzer.

Help -> MAX+plus II Table of Contents

Analysis of Clocked Circuits

Analysis -> Setup & Hold Matrix
Analysis -> Registered Performance

1. What is the shortest clock period (to the nearest ns) where the counter still operates correctly?
2. Simulating, what is the shortest clock period (to the nearest ns) where the least significant bit of the counter still operates correctly?

 

 
 
 
 
 
 
 
 
 
 
 
 
 

Can you find an example of the counter being clocked too quickly and describe the result?  You may observe wavefront pipelining where the data takes more than a clock cycle to flow through.

Lab

Part A: Thoughts on Simulation

1. For the adder above, the propagation delay until the last signal is stable depends on what values were last applied to the two inputs and what new values are currently applied.  Exactly how many pairs of previous inputs and new inputs would you have to test to exhaustively determine the maximum delay between all combinations of inputs?
2. Making reasonable assumptions about the implementation of the adder, what sets of inputs might produce the maximum delay?

Part B: Interfacing and Implementation

The binary counter should have an asynchronous active-low reset.  The binary to 7-segment display decoder should correctly display 0-9,A,b,C,d,E,F.

The asynchronous reset and outputs should be active low.
Use the following numbering for the 7 segments:

----0
|  |
|5 |1
----6
|  |
|4 |2
----3

1. What is the minimum clock period for which the circuit still performs correctly through all states (values of counter)?
2. What is the worst-case delay from clock to output?
3. What is the worst-case delay from reset to output?

Part C: Configuring FPGAs/CPLDs - Bonus for next lab

Transfer your VHDL design from part B above to a chip.  Create an *.sof file in ETLC e5-013.  From a PC in the ETLC e5-001 hardware lab, transfer the *.sof file from cad??.labs.ualberta.ca using ssh.  You'll need your ONE-CARD to get in to the labs and your nyquist account to login to a PC.

Assign the pins according to this procedure.  Use the FLEX pushbuttons (FLEX_PB1 & 2) for input and FLEX 7-segment LEDs (FLEX_DIGIT) for output as described in the UP1 documentation.

Now download the configuration to the chip.  After resetting, you'll see that pushing the button used as the clock input causes the counter to increment more than once.  Record how many clock edges are detected for pushing and for releasing the clock button (reset in-between).

1. What is the maximum and the average count for pressing the button?
2. What is the maximum and the average count for releasing the button?
3. Show this system to your TA during the lab and have your name recorded.

Part D: Behavioural VHDL for Datapaths

/* create a table of factorials */
#include <stdio.h>
#define UPPER_LIMIT 7

main(){
int n, factorial;

factorial = 1;
for( n=1; n<=UPPER_LIMIT; n++) {
    factorial = factorial * n;
    printf("%2d, %4d\n", n, factorial);
}
exit(0);
}
 
 
 

1. Report the minimum clock period for which your circuit behaves correctly.  Simulate with that clock period and a clock period that is too short for the circuit to behave correctly.

Part E: Bonus [10%]