CMPE 480 Advanced Digital Logic Design

Fall  Term  (2006f)       last updated 2006-11-6

Course web page:
Course Resources
Calendar Description Library
Marking Textbook
Problem Sets & Design Assignments
Lecture Notes
General Course Info NSERC Scholarship application (due Oct. 2)
and $ amounts
Newsgroup Manufacturer's info
Lecture notes
Quick reference cards for VHDL etc.

Local copies of language quick reference cards
Use the class newsgroup (web based) to ask questions, answer questions, etc.
Instructions for reading news with text-based pine.
Use email for questions of a confidential nature.
Professor Duncan Elliott 492-5357 ECERF W2-045
Lecture TA Hua Shao

Lab instructor
John Koob

ETLC 5-001
Lab TAs
Meysam Zargham

Xinsheng Zhou


General Course Info

Lectures Mon-Wed-Fri 12:00-12:50 in NRE-2003.
Labs Mon or Wed 14:00-16:50, first labs week of Sept. 18?
    hardware lab ETLC e5-001 open extended hours with card access
    additional CAD lab ETLC e5-013 open extended hours, use AIST (campus) userid

Office hours


(ask more questions and we'll cover less material but in greater depth)


Marking scheme for CMPE 480.

Items [that were] indicated with ?? are tentative and are to be decided by majority vote in class by deadlines set by instructor.
Bonuses may be available on some marked materials.

Term work 15% problem sets (weight 1 each),
quizzes (3),
design assignments (5)
Labs 20% see
lab projects
labs start week of Sept. 18
Midterm 20% Wed. Oct. 25, in class
2 aid sheets 8.5x11 inch, hand written, any information
Final Exam 45% 4?? aid sheets 8.5x11 inch, hand written, any information
 scheduled by registrar's office

Problem sets are due at the beginning of lectures (Wednesdays??).  Mutually beneficial collaboration on these problem sets is encouraged, provided that the names of all collaborators are cited near the student's name.  Marking will be based on effort.  Please do not put student id numbers on problem sets.

Quizzes will be held at the beginning of selected lectures where problem sets have been assigned.  The only permitted aids are the student's own problem set and a calculator.

Design assignments must be completed in groups of one or two without assistance.  Submissions are due by 3:40 pm in the CMPE480 lecture-assignment box in the ECERF-ETLC atrium.   Late submissions will be penalized 20% of the assigned mark per school day.   Architecture assignments should be brief but sufficiently clear and readable that you would be happy to submit them to a busy engineering manager.  If it only takes a sentence to describe something, then it should be described in a sentence.  Architecture assignments should include:

Past CMPE 480 handouts, term work, etc. can be picked up from a box on the counter opposite room ECERF w2-063.  To find it, pass through ECE reception, jog left and you'll find the counter to your right.

Submissions will not normally be re-graded more than two weeks after the first day these have been returned in class.

For lab policies and marking, see

Lab projects are new for this year.  With your professor's permission, you can replace one or both of the last 2 labs with a design project of your choice. A demonstration, presentation and report will be required.  See here for details.

The following calculators are permitted for examinations in this course: faculty approved programmable calculators, faculty approved non-programmable calculators,  slide rules, and instructor approved abacuses (if used quietly).  Programmable calculators will probably offer little or no advantage over non-programmable calculators.  Students must not distract other students during exams, so please turn off the calculator beep.

The midterm and final examination aid sheets must be in the student’s own handwriting (both sides, no photocopies or printouts), may be no larger than 21.59 by 27.94 cm (8.5 by 11 inch) paper, and may contain any information.

Deferred examinations may contain multiple components (including an oral component) as designed by instructor.

Grade Determination Method

In this course, raw marks will be calculated up until after the final exam.  The resulting overall percentage mark will then be converted for each student to a letter grade.  A standard expected distribution of grades, which is provided by the Faculty of Engineering, will be used as a rough guideline when mapping overall marks to grades.  Absolute merit of the work will also be taken into consideration.

Code of Student Behaviour

The University of Alberta is committed to the highest standards of academic integrity and honesty. Students are expected to be familiar with these standards regarding academic honesty and to uphold the policies of the University in this respect. Students are particularly urged to familiarize themselves with the provisions of the Code of Student Behavior (online at ) and avoid any behavior that could potentially result in suspicions of cheating, plagiarism, misrepresentation of facts and/or participation in an offence. Academic dishonesty is a serious offence and can result in suspension or expulsion from the University.

Policy about course outlines can be found in §23.4(2) of the University Calendar.

Library Resources



You will need some kind of VHDL textbook.  This is available in the bookstore:

The Student's Guide to VHDL by Peter J. Ashenden
ISBN 1-55860-520-7

Additional VHDL documentation is available from
VHDL International Users' Forum
VHDL Cookbook (a free textbook by Ashenden)

Lecture Notes

The most important material will be covered on the white board.  Please ensure you have a complete set of notes.
Selected lecture notes will be made available online here within one week after each lecture.

Problem Sets & Design Assignments

updated ~weekly
Due Date Problem Set
default web location
Solution if provided
default web location
Sept 15
PS1 Old EE 280 exam
Sept 20
PS2 counter
Sept 27
hand simulation of D-FF
Oct 4
shift register, counter
Oct 13
hand synthesis
Oct 18
old midterm / quiz
Nov 1
Nov 8
Nov 15
Jeopardy Arbiter

Nov 22
Design Assignment - Counter

Nov 29
PS - exam practice

Dec 6
Design Assignment - Multiplier

Manufacturer's Information

Xilinx tools
Xilinx ISE Webpack tools - free version of ISE FPGA Synthesis tool for download, registration required; different version to lab, interchange VHDL code only
Xilinx Modelsim simulator
Xilinx student software

Altera Quartus tools Wed edition - free FPGA synthesis tool, registration required, Modelsim extra