Trigger rates and data volumes at future colliders (LHC and SSC) will be about two orders of magnitude higher than at HERA. Thus to implement a similar trigger and readout strategy to that of ZEUS would require a new generation of processors and link switches. The IMS T9000 transputer, Texas Instruments TMS320C40 DSP and IMS C104 packet routing switch are promising candidates, among others, for such applications. The IMS T9000 transputer is rated to have a sustained performance of greater than 70 MIPS (200 MIPS peak) and 15 MFLOPS (25 MFLOPS peak) [16]. This is about 10 times faster than the current series of transputers. In addition, the link speed has been increased by about a factor of four to achieve bi-directional transfers of 10 Mbyte/s on each link. The IMS C104 packet routing switch is a 32 by 32 non-blocking self-routing cross-bar switch with low latency and a bi-directional transfer speed of 100 Mbit/s [16]. The TMS320C40 parallel DSP can achieve a performance of 50 MFLOPS or 275 MOPS and has six inter-processor communication port links giving a total bandwidth of 120 Mbyte/s. Data acquisition concepts used in ZEUS may be realized in new hardware at future collider experiments.