Input data arrives at the SLT from two sources: 1) the FADC system and 2) the z-system. Only information from the CTD axial superlayers is used by the SLT. The z-data enters the SLT through the level two processing stage and will be described presently.
The FADC data enters the SLT at level one. Each FADC crate contains 18 digital signal processors (DSP) which parameterise and zero suppress the pulse data from 16 FADC channels each. The parameterised pulse data is read out, via the crate backplane, by a readout controller transputer in each FADC crate. Occasionally, due to time constraints, a DSP many be unable to parameterise all the pulses on its board and the FADC pipeline will be dumped for offline processing.
For each channel with a pulse on it, summary information is
sent from the DSP to the FADC-ROC.
This summary data (r- 
data) is passed to the first
SLT transputer via a transputer link with the harness
protocol running on it.
Each FADC-ROC transputer is also responsible for readout of a 16'th of the chamber and will ship the data to the EVB every global second level trigger (GSLT) accept. The ROC adds information to the SLT summary input data, re-formats the data, and buffers it for readout. The SLT could take a copy of this data but some of it will not be used by the trigger (eg. dE/dx data and pipeline data). In addition, the SLT will save valuable calculation time and memory space by receiving data identified by superlayer, cell, and wire number within the cell, rather than global wire number.