Physics 672
THE VERSA MODULE EUROCARD (VME) BUS
Norm J. Buchanan
September 11, 1996
Introduction The VME bus, or Versa Module Eurocard bus, standard grew from the less familiar VERSAbus standard in the early 80's. Motorola, Mostek, and Sigentics corporations were at the time cooperating in hopes of defining the standard. While the original Sun computer from Sun Microsystems used Multibus, their more recent Sun 2 and Sun 3 machines use VME.
Hardware VME is an asynchronous bus which means that the data transfers are not synchronised with a strobed signal, rather, a handshaking scheme is used to synchronise data transfers between modules. This has the advantage that processors operating at differing speeds can be easily mixed. The slowest participating module will impose the limit on the speed of transfer. While the VME bus is asynchronous, a stable 16 MHz utility clock is provided to all modules. This clock is not used for synchronising data transfers.
The VME bus uses both multiplexed and non-multiplexed architectures. A multiplexed architecture is one where the pins for address lines and data lines are shared. This has the disadvantage that a two part bus cycle is required, one half to pass the address and the other half to pass the data. Busses where separate pins correspond to each type of line are called non-multiplexed. While they don't require the two part bus cycle, they contain more circuitry. For VME busses with 32 pins for addressing and 32 pins for data, multiplexing is not used, but for the newer 64 bit architecture, multiplexing is utilised.
VME modules are connected together using a common backplane, which can connect between 2 and 20 modules. For 32-bit (or less) address width, a backplane called the J1 is used. It handles 24 address bits and 16 data bits, along with some power pins and most of the control signals. Another backplane, called the J2 can expand the capability to 64-bit address and data busses. The backplane is mounted on the back of a crate and the modules slide into the connectors.
The VME bus uses master/slave architecture where a master module can initiate data transfer cycles. Examples of master modules are CPU (central processing unit) and DMA (direct memory access) modules. While a CPU module is self-explanatory, the DMA module is one which controls direct communication between a peripheral and memory. A slave module detects bus cycles generated by a master module and participates in the cycle, if it is selected to do so. If certain addresses are selected by the master module, an on-board signal is sent by the local monitor and a message is broadcast to all modules.
Two additional important features of the VME bus are seven levels of interrupt, and a bus timer. An interrupter generates interrupt requests to an interrupt handler. The interrupt handler can thus be viewed as a slave as it is taking requests and conversely the interrupter can be viewed as a master. Both bus masters and interrupt handlers use a requester to obtain ownership of the data transfer bus. To prevent a system crash, or other problem with data transfer, from locking up the system a bus timer times all transfers and kills transfers which take longer than some specified time interval. Other hardware features of the VME bus are 40/80 Mbytes/second data throughput for 32 and 64 bit busses respectively, dynamic address range selection, dynamic data path width selection, and 1-21 processor multiprocessing capability.
Data Transfers Four of the most important cycles of the VME bus are as follows: read/write, block transfer, read-modify-write and address-only. The read/write passes data between modules (masters and slaves) and is the most commonly used. To determine the protocol used in a typical cycle, the read/write cycle can be examined in more detail. During the read/write cycle a master addresses a slave using address lines A01-A31, a six bit address modifier (defined by lines AM0-AM5), and two control signals IACK (interrupt acknowledge) and LWORD (long word). This is the addressing part of the cycle. Address sizing determines which of the four widths will be used (16, 24, 32, or 64 bits). The size can be changed every bus cycle. Data sizing also occurs to determine the data width (8, 16, 24, 32, or 64 bits). The address modifier code (AM0-AM5) is used to determine which lines to decode. It also determines the type of cycle. During a typical read/write cycle, the master addresses a slave and then transfers data along data lines D00-D31, the read/write signal (WRITE), the data transfer acknowledge (DTACK), and bus error (BERR). BERR is the signal which is asserted if the bus timer times out. If either the DTACK or BERR are asserted, the cycle terminates, obviously with different results. If the BERR signal terminates the cycle, VME bus standard provides no way to isolate the cause of the error. Newer specifications (VME64) of the VME bus provide a RETRY signal which when received with BERR indicates that an error occurred but that the transfer should be retried. The VME standard allows unaligned transfers so that two and four byte data words need not lie on two or four byte boundaries. This can reduce transfers of data from three to two cycles in 32 bit transfers thus speeding up the over speed performance of a VME bus system.
The block cycle or burst mode passes blocks of data rather than words and is thus much faster than the above mentioned mode. An example of a block cycle would be when transferring to a disk from the CPU. The read-modify-write cycle handles reading and writing in a single cycle to prevent alterations between the two actions. This is clearly advantageous to multiprocessor systems, where peripherals are shared by different processors. The address-only cycle is used to broadcast an address. No data is transferred and thus neither the DACK nor BERR signals are needed to terminate a transfer.