EE 652 lab assignments 2001w

You may omit one lab and still receive full credit.

You may do labs individually or in pairs, provided that you don't work with the same person twice.

Lab 0 - Register with CMC

Register with CMC, if you have not already done so, and request access to the restricted TSMC IC processes.
www.cmc.ca
Remember to 
 % chmod 700 .                     <- note the dot
in any directory you use to store confidential information.  Ask me.


Lab 1 - VHDL model of an SRAM chip 

Write and simulate a hierarchical VHDL model of an SRAM chip and simulate a write and a read.  Your model need not include timing.  You will need to use ieee.std_logic_1164 levels to model the bitlines.

Model a 4 row by 2 column memory with an 8 x 1bit external organization.

Include
chip
control logic
datapath
array
rowdecode
columndecode
columnaccess
core
SRAMcell

Hints, including information on column access, to follow


Lab 2 - Design an SRAM cell

Design and layout a 6T planar SRAM cell in the 0.18 micron process.  A metal wordline should connect to the cell access transistors in every cell (no wordline-strap regions).
All transistor lengths should be minimal.
All transistor widths should be equal, except for the inverter NMOSFETs, which should be 3 times as wide.

Try to minimize the cell area - this is a competition.
Hand in a printout of the cell, a 3x3 array of cells (label the cell height and width), the cell area, and some indication that there are no design rule errors (you may also be asked to demonstrate your design to be DRC free).

Lab 3 - SRAM simulation

Extract and simulate the layout from your previous lab (layout of either lab partner).

For the extracted simulation:
Simulate with Vdd=2V, nominal transistor models, junction temperature = 100C
Add 200fF parasitic capacitance to each bitline
Add a 10/0.18um NMOS and PMOS to each bitline for both precharge and write (no layout required)
Use a 2ns rise and fall time for the wordline

Hand in:
Simulation of write-access time (start of rise of WL to 0.5V (positive) deltaV in cell)
Simulation of read-access time (start of rise of WL to 0.5V (positive) deltaV on bitlines)
Simulation of cycle time (explain your criteria)

Lab 4 -SRAM Upset