Dual Configurable Debouncer

Author: Jeff Bazinet
Group: The Reading Book
Other Group Members:
Andrew Chu
Chris Ohlmann
Reid Blumell
Bryce Palmer



What is Debouncing?

When a mechanical button is pressed the intention of the user is that the button is asserted only once. This is not true however at the electrical level. Due to physical contacts and reflection, there is usually bouncing that the signal experiences. An example of what a signal may look like is:




Why Debounce Signals?

When bouncing occurs, the signal is obviously asserted many times. Every bounce that occurs, the controller detects this and performs the corresponding function. The controller has no way of knowing if these assertions are all due to one button press or several. If the signal has do debouncer on the button, then the controller will recieve an unknown number of assertions which may lead to undesired results. The exact number of button presses may be critical to the design of the system and a debouncer must be implemented.



How To Debouncing Signals?

A combination of methods will be used in order to debounce signals. While both individually may work, by using both a designer can have the greatest control to debounce. It also allows for more of a range of debouncing limits. The first method used is to down-sample the clock which the controller uses to detect if a button was pressed. This is most effectively done by having a counter to be used as an enable signal. It is not good practice the use the down-sampled clock to assert the flip-flips to avoid internal bouncing caused by logic gates. The second method used is a buffer of samples. This ensures consistancy of the signal before the controller can declare that the button was pressed and is stable. The buffer can be declared as stable when all the values inside the buffer are equal. Another bit can be used to determine if a press or release of the button had occured. Lastly another bit is used to determine if the stable condition has been delt with by the controller to avoid a loop condition.



Testing The Debouncer

The easiest way to test the debouncing of a signal is to make a simple design to count the number of assertions the controller recieves and then displaying this number to the user. Two simple 7 segent LED works perfect to display the counter value to the user. It then requires some manual testing in the lab to determine what values for the frquency and buffer will work best to ensure that one physical button press corresponds to one value detected by the controller. When testing make sure that both slow and fast presses are tested. Also ensure that button holds are dealt with by the controller the way it is intended.



Debouncing Source Code

debounce.vhd - RTL code used for debouncing
led_counter.vhd - Top level entity for test environment
led_output.vhd - Used by led_counter.vhd to output to LEDs




Instantiating The Debouncer

This debouncer is only usable with simulators capable of using Altera's LPM libraries. The entity of the debouncer is:

entity debounce is 
generic(BUFFER_WIDTH: positive:= 30;
CLOCK_DIV: positive:= 15
);
port( clock: in std_logic;
reset: in std_logic;
signal_in: in std_logic;
signal_out: out std_logic
);
end entity debounce;

BUFFER_WIDTH: This number is the absolute number of bits used to buffer the input. The minimum value that can be used should be 1 but to avoid any logic problems with Maxplus2 it is recommended to use 2 as the minumim.

CLOCK_DIV: This number indicates how much the clock is divided down to sample the button. The downsample is 2^CLOCK_DIV from the original source clock.

clock: Source clock.

reset: Active low reset.

signal_in: Signal bit input of signal to debounce.

signal_out: Signal bit output of debounced signal.




Setting Up Maxplus2

This debouncer can only be used with the Maxplus2 environment or any other software with is capable of using Altera's LPM libraries. There are also ineffiecient implementation methods used due to the limitations presented in Maxplus2. One must remember to set the device to use the FLEX EPF10K20RC240-4 FPGA, and the pins must be assigned in the following order:

clock -> pin 91
clear -> pin 29
signal_in -> pin 28
led_display0[0] -> pin 17
led_display0[1] -> pin 18
led_display0[2] -> pin 19
led_display0[3] -> pin 20
led_display0[4] -> pin 21
led_display0[5] -> pin 23
led_display0[6] -> pin 24
led_display1[0] -> pin 6
led_display1[1] -> pin 7
led_display1[2] -> pin 8
led_display1[3] -> pin 9
led_display1[4] -> pin 11
led_display1[5] -> pin 12
led_display1[6] -> pin 13




Why use this Code?

There are other debouncers available within the application notes but none that do not restrict the configurability. This debounce logic has the ability to work with any kind of input signal. With the dual configurations it is possible to ensure proper debouncing of your input signal in all cases.


Date Posted: February 28, 2002