-- code obtained from Altera web-site
-- bi-directional tri-state bus
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

     ENTITY bidir IS
		 GENERIC (
			busWidth : POSITIVE := 16;
			dataWidth : POSITIVE := 8
		);
         PORT(
             bidir   : INOUT STD_LOGIC_VECTOR (busWidth-1 DOWNTO 0);
             oe, clk : IN STD_LOGIC;
             inp     : IN STD_LOGIC_VECTOR (busWidth-1 DOWNTO 0);
             outp1    : OUT STD_LOGIC_VECTOR (dataWidth-1 DOWNTO 0);
			 outp2	: out std_logic_vector (dataWidth-1 downto 0));
     END bidir;

     ARCHITECTURE maxpld OF bidir IS
     SIGNAL  a  : STD_LOGIC_VECTOR (busWidth-1 DOWNTO 0);  -- DFF that stores 
                                                  -- value from input.
     SIGNAL  b  : STD_LOGIC_VECTOR (busWidth-1 DOWNTO 0);  -- DFF that stores 
     BEGIN                                        -- feedback value.
         PROCESS(clk)
        	 BEGIN
    	     IF clk = '1' AND clk'EVENT THEN  -- Creates the flipflops
            	 a <= inp;                    
             	outp1 <= b(dataWidth-1 downto 0);
			 	outp2 <= b(busWidth-1 downto dataWidth);                  
             END IF;
         END PROCESS;    
         PROCESS (oe, bidir)          -- Behavioral representation 
             BEGIN                    -- of tri-states.
             IF( oe = '0') THEN
                 bidir <= (others => 'Z');
                 --b <= bidir;
             ELSE
                 bidir <= a; 
                 --b <= bidir;
             END IF;
			b <= bidir;
         END PROCESS;
     END maxpld;