External memory is often necessary when relatively large amounts of memory is required by a FPGA application. Such applications include data compression, DSP chips, or any application that requires large amounts of buffering. The on-board memory of a Altera EP10K20 in a UP1 board is limited to only about 12Kbits (6 2Kbit EAB blocks). Using external SRAM, one can command up to 1Mbyte of memory depending on the availability.

The main advantage of using SRAM over DRAM is that it is easier to interface with. To access DRAM, one needs a memory controller that handles the periodic refresh of the DRAM memory. With SRAM, however, one only needs to supply a constant DC source in order for the SRAM to retain its data. Furthermore, in the case of CMOS static memories, the power requirement is extremely small compared to the DRAM counterparts, allowing the implementation to be battery powered.

Here we are assuming that the one Data Bus is used for both the read/write operations. Static RAM is typically accessed as follows:

READ: (Assumes all signals are active low)

• An address is placed on the address inputs and CS and OE are asserted.
• The same time, the user must place the Data Bus on high impedance because the SRAM is now driving the Data Bus
• The latch outputs for the selected memory location are delivered to DOUT (Data Bus).
• It is up to the user to implement a 'done' signal to indicate that it is time to read the valid data across the data bus.

WRITE:

• An address is placed on the address inputs and a data word is placed on the Data Bus. This is of course AFTER the OE is disabled. We don’t want the SRAM to be driving the Data Bus at the same time we are trying drive the bus.
• SRAM stores the input word.
• It is up to the user to implement a 'done' signal to indicate that it is finished writing valid data to the SRAM.

Here is the VHDL code used to implement the SRAM interface: