LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL; 
USE ieee.std_logic_unsigned.ALL; 

package serialPort_pkg is

component serialPort
 
generic (Divisor1: positive := 1311;  -- use this to control baud rate
									  -- defaults to 9600
		 Divisor2: positive := 82);   -- use this to clock to receiver
		 							  -- must be set to 16 times smaller than
		 							  -- Divisor1

port (clock:				IN std_logic; -- global clock freq 25.175MHz (pin 91) 
	  sclr, sset, reset:	IN std_logic; -- resets for in, out and clock divider
      shiftin:  			IN STD_LOGIC; -- serial data stream in from PC       
      q: 					BUFFER STD_LOGIC_VECTOR(7 downto 0); -- 8 bit data word to be read
      data_valid: 			BUFFER STD_LOGIC;  -- indicates data word on q is valid
      
      load: 		IN STD_LOGIC;  -- should transition high to parallel load data word to be 
      							   -- sent out the serial port to the PC
      enableOut: 	IN STD_LOGIC;  -- enable to serialPort out
      data:    		IN std_logic_Vector(7 downto 0); -- 8 bit data word to be loaded to be serially sent
      shiftout:		BUFFER STD_LOGIC;  -- output data bit to PC
      ready:   		BUFFER STD_LOGIC  -- signal to indicate the register has transmitted the data word
    								   -- and is ready to receive/load a new data word
     
     
     );
 


end component serialPort;
end package serialPort_pkg;




LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all;


entity serialPort is 

generic (Divisor1: positive := 1311;  -- use this to control baud rate
									  -- defaults to 9600
		 Divisor2: positive := 82);   -- use this to clock to receiver
		 							  -- must be set to 16 times smaller than
		 							  -- Divisor1

port (clock:				IN std_logic; -- global clock freq 25.175MHz (pin 91) 
	  sclr, sset, reset:	IN std_logic; -- resets for in, out and clock divider
      shiftin:  			IN STD_LOGIC; -- serial data stream in from PC       
      q: 					BUFFER STD_LOGIC_VECTOR(7 downto 0); -- 8 bit data word to be read
      data_valid: 			BUFFER STD_LOGIC;  -- indicates data word on q is valid
      
      load: 		IN STD_LOGIC;  -- should transition high to parallel load data word to be 
      							   -- sent out the serial port to the PC
      enableOut: 	IN STD_LOGIC;  -- enable to serialPort out
      data:    		IN std_logic_Vector(7 downto 0); -- 8 bit data word to be loaded to be serially sent
      shiftout:		BUFFER STD_LOGIC;  -- output data bit to PC
      ready:   		BUFFER STD_LOGIC  -- signal to indicate the register has transmitted the data word
      								   -- and is ready to receive/load a new data word
     
     
     
     
     );

end serialPort;

architecture serial of serialPort is


component RS_232_In	

PORT	(
		clock		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		sclr		: IN STD_LOGIC ;
		q		: buffer STD_LOGIC_VECTOR (7 DOWNTO 0);
		data_valid :buffer std_logic
	);

end component RS_232_In;

component RS_232_Out 

 PORT

	(
		
		clock		: IN STD_LOGIC ; 
		enable		: IN STD_LOGIC ; 
		sset		: IN STD_LOGIC ; 
		load		: IN STD_LOGIC ; 
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		shiftout	: buffer STD_LOGIC; 
        ready 		: buffer STD_LOGIC);

         							  
end component RS_232_Out;

component clkdiv
   Generic (Divisor1: positive := 33554432;
            Divisor2: positive := 33554432);
   PORT(fast_clock : IN STD_LOGIC;
        reset      : IN STD_LOGIC;
        slow_clock1 : OUT STD_LOGIC; 
        slow_clock2:  OUT STD_LOGIC);
END component;


signal slow_clock1, slow_clock2: std_logic; 

begin

clkdiv1 : clkdiv

  generic map (Divisor1 => Divisor1, 
               Divisor2 => Divisor2) 
  port map   (fast_clock => clock, reset => reset, slow_clock1 => slow_clock1,
   			slow_clock2 => slow_clock2);
   			

PortIn1: RS_232_In
  port map (
            clock => slow_clock2,
			shiftin => shiftin,
			sclr   => sclr,
			q => q,
			data_valid => data_valid
            );

PortOut1: RS_232_Out
  port map (
			clock => slow_clock1,
			enable	=> enableOut, 
			sset => sset,
			load => load,
			data => data,
			shiftout => shiftout,
        	ready 	=> ready
           );
			
			
end serial;