--  This package may be used for communcation from the chip to the 
-- RS_232 serial Port.  The clock signal should be set to the same speed as the 
-- RS_232 Port (using a clock divider)
-- This file works with myShiftOut.vhd which is a specially modified
-- module -> lpm_shiftreg

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL; 
USE ieee.std_logic_unsigned.ALL; 


package RS_232_Out_pkg is

component RS_232_Out 
 PORT
	(
		clock		: IN STD_LOGIC ; --clock to register
		enable		: IN STD_LOGIC ; -- set high
		sset		: IN STD_LOGIC ; -- synchronous clear
		load		: IN STD_LOGIC ; -- load should be high for 1 clock cycle to load register
		
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0); --8 bits of data to send 
		            								
		shiftout	: buffer STD_LOGIC; -- data sent out to level converter
        ready 		: buffer STD_LOGIC); -- handshaking signal to indicate register is ready to 
         							  -- receive the next packet
end component RS_232_Out;
end package RS_232_Out_pkg;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL; 
USE ieee.std_logic_unsigned.ALL; 


entity RS_232_out is
 PORT
	(
		clock		: IN STD_LOGIC ; --clock to register
		enable		: IN STD_LOGIC ; -- register enable
		sset		: IN STD_LOGIC ; -- synchronous clear - sets output to one
		load		: IN STD_LOGIC ; -- load high pulsed to load register
		
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0); --8 bits of data to send
		            					--start and stop bits automatically added on
		shiftout	: buffer STD_LOGIC; -- data sent out to level converter
        ready 		: buffer STD_LOGIC); -- handshaking signal to indicate register ready to 
         							  -- receive next packet
      
end RS_232_out;

architecture tenbit of RS_232_Out is

component myShiftOut   
	PORT
	(
		clock		: IN STD_LOGIC ;
		enable		: IN STD_LOGIC ;
		sset		: IN STD_LOGIC ;
		load		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		shiftout	: OUT STD_LOGIC; 
		shiftin		: IN STD_LOGIC -- used to shift in ones behind data going out
	);
end component;

signal tied1: std_logic;
signal dataOut: std_logic_vector(9 downto 0);
constant datawidth: positive:= 8;

begin
tied1 <= '1';
dataOut <= '1' & data & '0';  -- add start and stop bits to frame
								-- least significant bit sent first

register1 : myShiftOut
   
   PORT map ( clock=> clock,
		      enable=> enable,
        	  sset => sset,
       		  shiftin => tied1, --fills in ones behind data shifted out
      		  data=> dataOut,
			  load => load,
			  shiftout => shiftout
			  );
			  			  
                          
process(clock)
variable counter : natural range 0 to 15 := 0;  
begin


if rising_edge(clock) then
  
  if counter > datawidth and load = '0' then
    ready <= '1';
    
  elsif load = '1' then 
    ready <= '0';
    counter := 0;
  
  else
    counter:= counter + 1;
   
  end if;
end if; 

end process;

end tenbit;