--  This package may be used to accept data from an RS_232 Port
--  The clock to this package should be at a rate 16 times that of
--  the RS_232 port.  ie. the input signal will be sampled at 16 times
--  the baud rate for more accurate detection of the start bit for
--  asynchronous communication. Data must be read off immediately when 
--  the data signal valid goes high
--  there is no method provided here to delay the incoming data stream.


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL; 
USE ieee.std_logic_unsigned.ALL; 
library work;


PACKAGE RS_232_In_pkg IS

component RS_232_In 

PORT
	
	(
		clock		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		sclr		: IN STD_LOGIC ; 
		q		: buffer STD_LOGIC_VECTOR (7 DOWNTO 0);
		data_valid :buffer std_logic
	);

end component RS_232_In;

END RS_232_In_pkg;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;



entity RS_232_In is

PORT
	
	(
		clock		: IN STD_LOGIC ; --this clock should be SAMPLE times greater than baud rate
		shiftin		: IN STD_LOGIC ; -- RS_232 data stream in
		sclr		: IN STD_LOGIC ; -- synchrounous clear
		q		: buffer STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit word
		data_valid :buffer std_logic  -- complete word has been received
	);



end RS_232_In;


architecture tenbit of RS_232_In is

component myShiftRight
	PORT
	(
		clock		: IN STD_LOGIC ;
		enable		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		sclr		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
end component;

constant SAMPLE:natural:= 16;  -- how many times faster than baud rate we are sampling at
constant counterOffset: natural:= 24;  --counter offset to take sample in the middle of pulse
constant counterMax: natural:= 172;  -- 10bits * SAMPLE + SAMPLE/2 (SAMPLE/2) to sample middle of pulse
signal qout: std_logic_vector(9 downto 0);
signal   enableSignal, delayValid: std_logic;
begin

register1 : myShiftRight
  port map
    			(
				clock => clock,
				enable => enableSignal,
				shiftin => shiftin,
				sclr => sclr,
				q	=> qout
	     		);
 


process(clock)
variable counter: integer range 0 to SAMPLE*10 := 0; 
variable counter2: integer range 0 to SAMPLE*10;
variable startbit: integer range 0 to 2;


begin

if rising_edge(clock) then
  
  if shiftin = '0' and startbit = 0 then 
   
   startbit := 1; -- have first bit of packet
   counter2 := counterOffset;
   end if;
  
  if startbit = 1 then
  counter := counter +1;
  else counter := 0;
  end if;
    
  if counter = counter2  then
      enableSignal <= '1';
      counter2 := counter2 + SAMPLE;
  else    
    enableSignal <= '0';
 end if;
  
      
If shiftin = '1' and counter = counterMax then  

    startbit := 0;
    counter := 0;
    counter2 := counterOffset;
    q <= qout(8 downto 1);
    delayValid <='1';  -- delay datavalid until qout stabalized
  else 
    data_valid <= delayValid;
    delayValid <= '0';
  end if;
end if;    
end process;
end tenbit;