RS-232

RS-232 Serial Port

Authors:

Tim Bensler &
Eric Chan

The RS-232C standard is used to define asynchronous serial communications. The information must be broken up into data words and is then sent bit by bit across a channel (wire). A common word length is 8 bits (PC's can use 5 to 8 bit words). Both the transmitter and receiver must agree on the number of bits per word, and they must also be programmed to use the same baud rate.

Because the communication is asynchronous, and a data word could start at any moment, a technique must be used to indicate the beginning and end of each data word. We have used a single start bit (logic 0) and a single stop bit (logic 1) to indicate the beginning and end of a data word. When no information is being transmitted the line is held at logic level 1. When the line drops to logic level 0 (i.e. the start bit) the receiver is alerted to the incoming data. The receiver, being at the same bit frequency, can calculate when the next bit will arrive and will check the line voltage at that instant. (Ideally the line voltage will be sampled in the middle of the pulse.) After the last data bit is sent a stop bit (1) is sent to indicate the end of the data word. The cycle repeats with the next start bit being sent. It is important to note that the least significant bit is always sent first.

If, for some reason (noise etc.), the start bit is not received and/or a stop bit is not seen where it "should" be, a framing error has occurred. The receiver must then try to resynchronize on the data coming in, looking for valid start/stop bit pairs. This is possible as long as there is enough variation in the bit patterns. However, data will be lost, and it could take some time for the signal to resynchronize, especially if data value zero is sent repeatedly for example.

The RS232 has 2 states. A negative voltage identifies logic level 1, and a positive voltage identifies logic level 0. For interaction with the logic on the UP1 board, buffers are needed between the board and computer, such as chips MC1488 and MC1489. (See wiring schematic)

The following table outlines the voltage limits for the RS-232.

Level	Transmitter Capable(V)	Receiver Capable (V)
Logic 0	+5......+15	+3......+25
Logic 1	-5......-15	-3.......-25
Undefined	-	-3......+3

The following is the pin assignments for the DB-9 and DB-25

DB-9	DB-25

A file, serialPort.vhd has been created that should make implementing a serial port easy. The component can be instantiated and the signals mapped to the ports as specified below.

For the clock divider(clkdiv):
Divisor1: positive := 1311;	-- used in the clock divider, use this to control baud rate, defaults to 9600
Divisor2: positive := 82;	-- use this to divide down clock for receiving. NOTE: Divisor2 must be set to 16 times smaller than Divisor1
clock: IN std_logic;	-- global clock frequency ( 25.175MHz )
For receiving data(RS_232_In):
shiftin: IN STD_LOGIC;	-- serial data stream in from PC
q: BUFFER STD_LOGIC_VECTOR(7 downto 0);	-- 8 bit data word to be read
data_valid: BUFFER STD_LOGIC;	-- indicates data word on q is valid
To transmit data(RS_232_Out):
load: IN STD_LOGIC;	-- should transition high to parallel load data word to be sent out the serial port to the PC
enableOut: IN STD_LOGIC;	-- enable to serialPort out
data: IN std_logic_Vector(7 downto 0);	-- 8 bit data word to be loaded to be serially sent
shiftout: BUFFER STD_LOGIC;	-- output data bit to PC
ready: BUFFER STD_LOGIC	-- signal to indicate the register has transmitted the data word and is ready to load a new data word
For the respective resets:
sclr, sset, reset: IN std_logic;	-- resets for in, out and clock divider

The file serialPort.vhd uses five files that will need to be in your working directory. The files myShiftOut.vhd and myShiftRight.vhd were created automatically by the wizard in MaxPlus2 to optimize the lpm_shiftreg, and are used by RS_232_Out and RS_232_In respectively.

Reference: Banks, Michael A..The Modem Reference. 1991. Brady, New York NY.