EE 552 High Level Digital ASIC Design Using CAD
Winter Term (2003w) last
updated 2003-2-12
Use the class newsgroup ualberta.courses.ee.552
to ask questions, answer questions, or find project partners.
Use email for questions of a confidential nature.
General Course Info
Lectures Tues & Thurs 9:30-10:50 in ETLC e1-018
The period will wrap up with a seminar or discussion.
Office hours
CAD lab in ETLC e5-013 Fri 2-5pm
Hardware lab in ETLC e5-001 (later in term)
Students are free to use these lab facilities these rooms are not
scheduled for another course.
EE 480 / EE 635 is a prerequisite for EE 552. While exemption
may be granted in individual cases, lectures assume a knowledge of EE 480
material, including VHDL. (I will give all graduate students an exemption
from this prerequisite, but please talk to me first.) If you haven't
used VHDL, plan to do some extra reading and lab work.
In this course, you will develop the necessary skills to design complex
digital ASICs (application specific integrated circuits) and systems on
a chip (SoC) using CAD synthesis tools. Working in a group, you and
your partners will design and implement a significant digital system using
field programmable gate arrays and complex programmable logic devices.
Outline
-
Overview of design methodologies
-
Synchronous design, simulation and testing
-
Hardware description language and synthesis
-
Field programmable gate arrays
-
CMOS circuits
-
Gate arrays and IC process technology
Marking
| Labs |
|
15 |
dates |
| Final Exam |
|
30 |
exam period |
| Project |
|
55 |
|
| Application Notes |
10 |
|
(Mar 4) Mar 25 (electronic submission) |
| Proposal |
5 |
|
Jan 21 |
| Specification |
5 |
|
Feb 3 |
Resource Requirements &
Interface Demonstration |
5 |
|
Feb 25 |
| Simulation Documentation |
5 |
|
Mar 11 |
| Oral Presentation |
10 |
|
Apr 1,3,8 (randomly assigned) |
| Final Report |
15 |
|
Mar 27 |
All lab and project submissions are due by 3:50 pm in the EE 552 assignment
box outside of ECERF w2-023. Oversized final reports should be taken
to Sylvia in ECERF W2-023, for her to timestamp and place in my mailbox.
Late submissions will be penalized 10% of the assigned mark per school
day. Submissions will not normally be re-graded more than two weeks
after the first day these have been returned in class.
The following calculators are permitted for examinations in this course:
faculty approved programmable calculators, faculty approved non-programmable
calculators, instructor approved calculators, instructor approved abacuses
(if used quietly). Programmable calculators will probably offer little
or no advantage over non-programmable calculators.
Marks are periodically posted on my office window.
Grade Determination Method
See section 23.4 in the university calendar.
In this course, raw marks will be calculated up until after the final exam.
The resulting overall percentage mark will then be converted for each student
to a grade on the nine point scale. A standard expected distribution
of grades, which is provided by the Faculty of Engineering, will be used
as a rough guideline when mapping overall marks to grades.
Absolute merit of the work will also be taken into consideration.
Code of Student Behaviour
Refer to section 26 of the university calendar and the Code
of Student Behaviour for a comprehensive discussion of what constitutes
improper conduct for members of the University community and for a description
of disciplinary procedures. In particular, note the definitions of
plagiarism and cheating and the penalties for academic offenses.
Library Resources
These readings are available for short-term loan from Cameron Library:
| Call number |
Title |
| F152 |
Class handouts, etc. |
|
Rapid Prototyping Board (Xilinx)
User's Manual |
| TK 7872 L64 A54 1999 |
Altera MAX+PLUS II software
24 hour loan of CD
or download |
| TK 7895 A38 B67 1996 |
Actel FPGA Data Book
including applications notes |
| TK 7872 L64 X55 1996 |
Xilinx FPGA Data Book |
Textbooks
Course notes TBD (online, handouts, for sale from EE club)
The textbooks are optional. Some reference for VHDL will be necessary.
The university bookstore has copies of:
-
Ashenden, The Student's Guide to VHDL (text recommended for course)
-
Ashenden, The Designer's Guide to VHDL (longer version of above
for enthusiasts)
Additional VHDL documentation is available from
VHDL International Users' Forum
VHDL Cookbook (a free
textbook by Ashenden)
Lab Assignments
Students are to work alone on labs except where stated. See
here for where to submit labs. Labs reports should be brief but sufficiently
clear and readable that you would be happy to submit them to a busy
engineering manager. If it only takes a sentence to describe something,
then it should be described in a sentence.
Lab reports should include:
-
Title page
-
for each part of the lab include:
-
Answers to all numbered questions
-
Assumptions made
-
Any drawings which are an important part of the design (e.g. state transition
diagram)
-
A brief written summary of the results and the work you did to arrive at
them
-
Description of testing technique
-
VHDL code that conforms to the EE 552 coding standard
-
Legible print-outs of simulations, timing analysis, etc. with titles and
annotations added (each page has to explain its self to the TA)
-
Remember that bonus questions are mainly for entertainment. Don't
attempt them if you're pressed for time.
-
Any feedback on how the lab went that could be helpful to the TA or professor
Hints and tutorial information will be made available
here.
Chip Manufacturer's Documentation
Altera
Local UofA copies of documentation
Literature
Altera University
Frequently Asked Questions
Altera University
Program
Applications notes
Altera is a trademark and service mark of Altera Corporation
in the United States and other countries. Altera products are the
intellectual property
of Altera Corporation and are protected by copyright laws
Actel
Local UofA copies of documentation
Xilinx