Graduate project - EE653

last updated 2002-4-12

Students taking EE653 are required to do a design project worth 30% of the course. This project can be done individually or in groups of two.

A one-page proposal (two copies please), plus appendices and block diagrams, is due in my ECERF mailbox Mar 5, 3pm.

The final report is due April 12, 3pm. The marking of projects submitted after this date will not be completed in time for end-of-term reporting.

Oral presentations will be 5-10 minutes using paper diagrams, overhead slides, or computer projector.
April 18, 2pm, ECERF W2-036 (if you handed in your report by April 12) else
May 2, 2pm, ECERF W2-021

The project will involve the creation and verification of a chip design, and must include:

Complete chip layout (you will probably want to plot this as well)
digital logic
including IO pads (optional)
some transistor level layout (full-custom design)
DRC
LVS
pad-to-pad simulation of entire design
measurements of

design size and important cell sizes
speed
power consumption

The report must also include

Title page
abstract
table of contents
brief explanation of design goals (speed, power, area) and what options you considered to acheive these

Your design may include the use of:

mixed digital analog circuits (analog design is not emphasized in the course lectures so you would be drawing on other projects)
HDL (VHDL or Verilog)
Use of place and route tools is recommended

You will necessarily have to read documentation and figure out some parts of tools on your own. See:
place and route
digital design flow (partially out of date, tools have changed)

Try to keep your project goals flexible. It's hard to predict how much effort a design will take before you are familiar with all of the tools.

Project suggestions:
(You'll be spending a lot of time on this, so best pick something that interests you.)

Get a head start on your thesis / MEng project
Pipelined multiplier-accumulator (full custom layout)
A memory
Communications switch
Processors embedded in memory
Application specific co-processor
Radio transceiver with fractional frequency synthesis (see me - requires mixed analog-digital)

Use of 0.18 micron CMOS

There is no requirement to use the 0.18 micron CMOS process, but you may wish to if you intent to have your chip design manufactured as part of your graduate research program.

If you wish to use the 0.18 micron CMOS process, you must register with CMC and sign a confidential disclosure (or non-disclosure) agreement. Follow the links below:

http://www.cmc.ca/about/membership/
http://www.cmc.ca/about/membership/registration/
http://www.cmc.ca/about/membership/cda_instructions.html

Print and sign the CDA, have your supervisor sign it, and fax it to CMC. CMC will notify us when it has been approved.