| Parameter (Description) | Value |
|---|---|
| VDD | 3.3V |
| µn | 4.8x1010µm2/V/s |
| µp | 1.6x1010µm2/V/s |
| Lmin | 0.35µm |
| Wmin | 0.4µm |
| Lateral Diffusion NMOS ((delta L)/2 or xd) | 51nm |
| Lateral Diffusion PMOS ((delta L)/2 or xd) | 7nm |
| X or LD,S | 0.85µm |
| Cox | 4.7x10-3pF/µm2 |
| VTN | 0.60V |
| VTP | -0.80V |
| eta | 6 |
| GAMMAn | 0.621 |
| GAMMAp | 0.452 |
| LAMBDAn | 0.12/L(µm) |
| LAMBDAp | 0.10/L(µm) |
| Cj-n at 0V bias | 1.003x10-3F/m2 |
| Cj-p at 0V bias | 1.431x10-3F/m2 |
| Cjsw-n at 0V bias | 3.008x10-10F/m |
| Cjsw-p at 0V bias | 4.076x10-10F/m |
| Cg(s,d)overlap-n | 1.90x10-10F/m |
| Cg(s,d)overlap-p | 2.76x10-10F/m |
1.
A 5-inverter CMOS ring oscillator is built with 10micron/0.35micron
transistors. The source and drain widths (x) are 1 micron.
Estimate the frequency.
What is the power consumption.
2.
A hypothetical set of domino gates have Tprop0-1 = 100ps (from all
inputs) and Tprop1-0 = 210ps. Ideal 4-phase clocking is used.
Find the maximum clock frequency for cascaded gates using the following
gate orders. Assume the input data is available before the first
evaluation clock.
c1 c2 c3 c4 c1
c1 c1 c2 c2 c3 c3 c4 c4 c1 c1
c1 c2 c2 c3 c4 c4 c1
c1 c2 c2 c2 c3 c3 c4
3.
Draw schematics and stick diagrams for the following circuits:
static CMOS 3-input OR
domino 2-input AND gate
domino DCVS logic 2-input XOR