EE 483 Integrated Circuit Design / 
EE 653 Integrated Circuit Design with Project (post-graduate course)

Winter  Term  (2002w)       last updated 2002-4-12
 
Course Resources
Calendar Description Library
Marking Textbooks
Labs and  Assignments Study Materials
General Course Info Textbook Errata
Newsgroup Reading
NSERC scholarships
Use the class newsgroup ualberta.courses.ee.483 to ask questions, answer questions, or find project partners.
Use email for questions of a confidential nature.
Professor Duncan Elliott 492-5357 ECERF W2-036
TAs Tyler Brandon
Daniel Leder

 

General Course Info

Lectures M-W-F 10:00-10:50 in V-102

Office hours

CAD lab in CEB 531 Tues, Fri 2-5pm
Odd weeks: Jan 22, Feb 5, Mar 5, 19, Apr 2
If you have the flexibility, please come to the Tuesday lab where you have a better chance of getting a fast workstation (look for a "tower box").
Students are free to use the facilities in CEB 531  when this lab is not scheduled for another course.

EE 480 and EE 570 will be prerequisites for this course next year.

In this course, you will develop the necessary skills to design digital VLSI circuits.
 

Outline

Marking

 
EE 483
Labs and Assignments 45 dates
Midterm Test 10 Feb 13 - PhysEd PE E 120
Final Exam 45 Apr 17 - see exam timetable
EE 483 total 100
EE 653 
grade as for EE 483 70 as above
project 30 individual or in pairs
Apr 30  - ECERF mail slot
project proposal Mar 5 - ECERF mail slot
oral presentation April 18 or
May 2
place and route lab no submission
EE 653 total 100

All lab and project submissions are due by 3:00 pm in the EE 483 assignment box outside of CEB 238.  (Each instructor must pick up their own assignments, so there are no standard submission times.)  Late submissions (and oversized final reports) should be taken to Silvia in ECERF W2-063, for her to place in my mailbox.  Assignments left in the assignment box after the due date will not be discovered for another week.  Late submissions will be penalized 10% of the assigned mark per school day.  Submissions will not normally be re-graded more than two weeks after the first day these have been returned in class.

Marks are periodically posted.

Grade Determination Method

See section 23.4 in the university calendar.  In this course, raw marks will be calculated up until after the final exam.  The resulting overall percentage mark will then be converted for each student to a grade on the nine point scale.  A standard expected distribution of grades, which is provided by the Faculty of Engineering, will be used as a rough guideline when mapping overall marks to grades.  Absolute merit of the work will also be taken into consideration.

Code of Student Behaviour

Refer to section 26 of the university calendar for a comprehensive discussion of what constitutes improper conduct for members of the University community and for a description of disciplinary procedures.  In particular, note the definitions of plagiarism and cheating in section 26.1.4 and the penalties for academic offenses specified in section 26.1.5.
 

Library Resources

These readings are available for short-term loan from Cameron Library:
Course text TK 7874 U39 2002
 

Textbooks

recommended text: John Uyemura, Introduction to VLSI Circuits and Systems, isbn 0-471-12704-3

supplementary text: Dan Clein, CMOS IC Layout, isbn 0-7506-7194-7
 

Labs and Assignments

 
First
Lab
Date		 Due
Lab 1 Jan 22 Jan 31
Lab 2 Feb 5 Feb 27
Assignment 3
solution		 Feb 8 Mar 1
Lab 4 Mar 5 Mar 13
Lab 5
  +
reading		 Mar 19 Apr 10
Assignment 6 not marked
Students are to work alone on labs except where stated.  See here for where to submit labs. Labs reports should be brief but sufficiently clear and readable that you would be happy to submit them to a busy engineering manager.  If it only takes a sentence to describe something, then it should be described in a sentence.

Most final lab designs will require TA inspection and sign-off in scheduled labs.

Lab reports should include: