ECE 553 Digital Integrated Circuit
Winter Term (2018w)
last updated 2018-1-8
Course web page:
For questions concerning labs 0-3, please use the eClass
discussion forum. If you know the answer to a question
(not the solution of a marked course component), by all means post
it. Please read prior postings to see if your question has
been asked and answered. Create a new topic for most questions
(unless it's a request for elaboration).
For questions concerning the lectures or project, see me in class,
during office hours or send email.
Use email for questions of a confidential nature.
General Course Info
Lectures Tues., Thurs. 11:00-12:20 in ECERF w6-087.
Some lectures may be held at different times.
If you prefer, you may work on the labs on your own time, so don't
worry about schedule conflicts (attendance isn't taken in the labs
for this grad course).
Lab TA support should be available on specified Tuesdays
CAD lab ETLC e5-013 is open
extended hours, use your AICT (campus computer) userid
- Review of Static CMOS Circuits and Simulation
- Review MOS transistor theory
- IC Process Technology
- Parameter extraction and performance estimation
- IC Layout, including transistor sizing and Logical Effort
- Review Logic Circuit Families, Memories
- Synchronous Systems, Clocking and Clock Distribution
- Extreme circuits (pushing the power and speed envelope)
(ask more questions and we'll cover less material but in greater
Tentative Marking scheme for ECE 553.
Bonuses may be available on some marked materials. Marks of
>100% may be recorded.
(>60% of term work),
Problem Sets due Thursdays,
||Group design of an (at least partially) digital IC
including a custom design component
Topics offered by instructor, or see me about your ideas
Mark based on reports and public presentation
Proposal Feb 27
Presentation Apr 12
Reports due April 13
||??4 aid sheets 8.5x11 inch, hand written, any information
during exam period
Problem sets are due at
the beginning of lectures. Mutually beneficial
collaboration is encouraged, provided that the names of all
collaborators are cited on the problem set, immediately below the
student's name. Marking may either be based on content or
effort at the instructor's discretion. Please do not put
student id numbers on problem sets or any other materials to be
handed out in class.
Labs 0,1,2,3 must
be completed individually without outside assistance beyond
general advice on tools (certainly no sharing of files or
printouts). Pre-lab work should be submitted with the
lab. Submissions are due by 18:00 in the ECE 553
email. Late submissions will be penalized 20% of the
assigned mark per school day. Labs and problem
sets should be brief but sufficiently clear and readable that you
would be happy to submit them to a busy engineering
manager. If it only takes a sentence to describe something,
then it should be described in a sentence. Assignments
- Title page with names, but no student ID numbers
- for each part include:
- Assumptions made
- Legible schematics, diagrams, tables, etc. as required (each
page has to explain its self)
- A brief written summary of the results and the work you did
to arrive at them
- annotate any simulations
- Remember that bonus questions are mainly for
entertainment. Don't attempt them if you're pressed for
- Any feedback on how the lab went that could be helpful to your
instructor or future students
Labs will be graded at the end of term.
Submissions will not normally be re-graded more than two weeks
after the first day these have been returned in class.
The following calculators are permitted for examinations in this
course: faculty approved programmable calculators, faculty
approved non-programmable calculators, slide rules, and
instructor approved abacuses (if used quietly). Programmable
calculators will probably offer little or no advantage over
non-programmable calculators. Students must not distract
other students during exams, so please turn off the calculator
The final examination aid
sheets must be in the studentís own handwriting (both
sides, no photocopies or printouts), may be no larger than 21.59
by 27.94 cm paper, and may contain any information.
Deferred examinations and
contain multiple components (including an oral component) as
designed by instructor.
Credit may only be received for one of ECE403, EE453, ECE553, EE483
Students requiring specialized support should provide letters from Student Accessibility
Services (SAS) to the instructor in the first 2 weeks of
If you wish to discuss private information, let me know that you'd
rather not talk in the classroom.
In the past, students have indicated that audio recording stifles
the asking of questions in lectures. To keep everyone
comfortable, audio or video recording or photographs by students
requires the written consent of all students, unless SAS indicates
Grade Determination Method
In this course, raw marks will be calculated up until after the
final exam. The percentage grade will be converted to a letter
grade according to the calendar definitions of those grades and the
degree of mastery of the material.
Code of Student Behaviour
The University of Alberta is committed to the highest standards of
academic integrity and honesty. Students are expected to be familiar
with these standards regarding academic honesty and to uphold the
policies of the University in this respect. Students are
particularly urged to familiarize themselves with the provisions of
the Code of Student Behaviour (online at www.governance.ualberta.ca)
and avoid any behaviour which could potentially result in suspicions
of cheating, plagiarism, misrepresentation of facts and/or
participation in an offence. Academic dishonesty is a serious
offence and can result in suspension or expulsion from the
Policy about course outlines can be found in Course Requirements,
Evaluation Procedures and Grading of the University Calendar.
Design a significant integrated circuit and verify its functionality
and performance through pin-to-pin simulation and other
verification. Your design (or one of your designs) must
contain a full-custom portion and must contain some digital
circuits. Pick a topic you are passionate about. Some of
my suggestions are online.
Present your work and results in a 10-20 minute seminar plus
questions. You will need to rehearse your presentation in
advance. Bring a USB memory key with a PDF or PPT
presentation, or your own laptop. In this short presentation
time, give an overview of the application of your chip, the chip's
overall performance, and then descend into a few details where you
employed clever tricks, found some interesting trade-offs, or
otherwise have a chance to teach your fellow designers something
The main part of final report will be in the form of a
well-written 3-8 page "IEEE
2-column format paper" with embedded figures [LaTeX
and MS Word templates]. (See me if you want to use a
different format.) In your abstract and introduction, clearly
describe what you achieved. Devote approximately a column to
background and past work, with references to the literature,
properly cited. Properly quote and reference text and figures
from other sources. Describe analysis, simulations and, if
applicable, selection between design alternatives. Discuss
speed-power-area trade-offs. Compare standard cell to full
custom implementations if applicable. Include block diagrams,
schematics and layouts (including full chip and custom
blocks). In a box, summarize:
Power supply voltages and power
Circuit families used
Summarize number of pins used for what purpose and total (e.g.
Vdd/Vss-core, Vdd/Vss-IO, data in, data out, control, ...)
Your report may contain any number of pages of appendix in
any format (separate PDF preferred, hard copy permitted).
Include as applicable:
index to appendices
VHDL/Verilog code, commented and human readable
Each page must have a title or enough information for me to figure
out what I'm looking at.
hierarchical schematics, if applicable
custom and chip layouts, hierarchical if applicable
annotated simulations, hierarchical if applicable
other verification: evidence (i.e. summaries, without killing too
many trees) of DRC, LVS, static timing
Your report must be submitted electronically and will become public
unless other arrangements have been made.
Submit a hard copy declaration with the quoted text below
and your list of exceptions..All group members must sign and date
their own signature.
"The design elements of this project and the report are entirely the
original work of the authors and have not been submitted for credit
in any other course except as follows:"
provide a descriptive list of exceptions that reference your
citations , e.g.
oscillator schematic adapted from 
portions of the parity check code were previously submitted in
CMOS VLSI Design - A Circuits and Design Perspective, 4th Edition
N.H.E. Weste & D. Harris
including selected problem solutions
The most important material will be covered on the white
board. Please ensure you have a complete set of notes.
Selected lecture notes will be made
available online one week after the lecture. A
preliminary version may be available beforehand.
Use your ccid
(Campus Computer ID) to access course materials.
Use your ccid
(Campus Computer ID) to access labs.
|Report Due Date
|Mar 6, 20, 27
Mar 6, 20, 27