ECE 511 2004f 2004-10-27

Lab 6: Memory and MicroProcessor

Exercise

Part A: Code Revision Control

In your projects and labs, you may occasionally find you wish to return to an earlier version of your code. You may have a mysterious error and wish to find out what happened. You may have attempted a major reorganization that didn't work out. Here's a quick tutorial on the unix Revision Control System (RCS). Go to your lab4 directory and change one of your files "myfile.vhd" after first making a copy with RCS. The "-l" option (lower case L) leaves the file "locked" or ready to be edited.

% cd ~/ee552/lab4

% mkdir RCS

% ci -l myfile.vhd

Type a description of the file. End the description with a line with only a ".". You now have a backup copy. In fact, you can go back to any previous version.

Next, use an editor to add several lines (of anything) to your code.

Then: examine the difference between the files, check in the new revision, view the log, and note where the revision history is stored.

% rcsdiff myfile.vhd

% ci -l myfile.vhd

% rlog myfile.vhd

% ls RCS

By now, you have decided that your changes were a mistake and wish to undo them.

Release your lock on the current version, and check out the older version 1.1 (one dot one).

% rcs -u myfile.vhd

% co -l1.1 myfile.vhd

RCS stores only the differences between each version, so it saves disk space.

Locking of files so multiple group members won't be editing the same file is supported. Find out more in the manual pages.

Lab

Part A: Memory

In Xilinx there are two ways to create a RAM: component instaniation and inference. Inference means you describe the RAM behaviouraly. In the Spartan2s there are two types of RAM: block RAM and distributed RAM. Block RAM refers to the special memory blocks built into the FPGA device. Distributed RAM uses logic cells to form the RAM.

Create a new project. In Xilinx select Edit -> Language Templates. Expand VHDL (click the + sign beside VHDL). Under "Component Instantiation" you will find a folder for "Block RAM" and "Distrubuted RAM". In "Synthesis Templates" you will find a folder for "RAM". Each of these folders contain VHDL examples that you can use to create your RAMs (and ROMs if needed).

Build a 16 bit by 4 row synchronous RAM. In your VHDL code initialize the RAM to the following values:
h ABCD
h DCBA
h 0FF0
h F00F

Write a test bench that reads all four rows then writes all zeros into the four rows, then reads all four rows again. Hand in simulatin output for both the behavioural and post place & route. Make sure you have the time scale on your graph (and that it starts at 0) and that all inputs/output are in hexadecimal format. Report the number of: slices and memory blocks used.

Repeat above, but with an asynchrounous RAM.

Part B: MicroProcessor Synthesis

MicroBlaze ...

Add the following lines to your .cshrc file:
setenv PATH {$PATH}:/usr/ccs/bin source /CAD/scripts/setenv.xilinx62.csh source /CAD/tools/edk_6.2i/setup.csh setenv PATH {$PATH}:/CAD/tools/edk_6.2i/gnu/microblaze/sol/lib/gcc-lib/microblaze/2.95.3-4 Start a new terminal.

Copy the User_Area.zip file from the /CAD/tools/edk_6.2i/doc/ directory and unzip it:
% mkdir mb % cd mb % cp /CAD/tools/edk_6.2i/doc/User_Area.zip . % unzip User_Area.zip % cp /CAD/tools/edk_6.2i/doc/lab_solutions_xbdfile.zip . % unzip lab_solutions_xbdfile.zip

Start Xilinx Platform Studio
% XPS_GUI

The following are adjustments to Lab 1 and 2 from the User_Area

Lab 1
1. In Unix, type: XPS_GUI
14. An additional menu is displayed asking if it should generate: "Sample Application and Linker Script". Leave it selected and click next.
17. Skip.
18. Instead, add the code from lab1.c to TestApp.c. In the Application tab, expand Sources and edit TestApp.c
19. Skip.
20. Skip.
22. Tools -> Build All User Apps (there is no Compile)
23. In the Applications tab, right click "Default: microblaze_0_xmdstub" and click "Mark to Initialize BRAMS". Proceed with the rest of 23.
36. Compiler options are access via right clicking "compiler options" in the Application tab.

Lab 2
8. NA.