-------------------------------------------------
-- adder_test.vhd
--
-- Revised 2001/02/09
--
-- Authors:  John Koob, Raymond Sung & Duncan Elliott
-- Date:     Feb 2001
-- Course:   EE552
-- Desc:
--
-- Testbench for adder.vhd.  This file is to 
-- be compiled using Mentor Graphics.  The adder.vho 
-- file should have been generated by MaxPlusII before
-- compiling this testbench.
--
-- This testbench serves as a template for testing
-- other designs that require pseudo-random input
-- data and signature analysis
--

library ieee;
use ieee.std_logic_1164.all;
-- library work;
use work.adder_pkg.all;

-- textfixture
entity testbench is
end testbench;

architecture mixed of testbench is
	
    -- this component is used to create the PRPG and Signature Compactor
    component LFSR_GENERIC is
    generic(Width: positive := 4);		-- length of pseudo-random sequence
    port    (	
	clock: in std_logic;
	reset: in std_logic;	-- active low reset
	load: in std_logic;		-- active high load (assert this to use as regular reg)
	enable: in std_logic;	-- active high enable
	parallel_in: in std_logic_vector(Width-1 downto 0);	-- parallel seed input
	parallel_out: out std_logic_vector(Width-1 downto 0); -- parallel data out
	serial_out: out std_logic	-- serial data out (From last shift register)
    );
    end component LFSR_GENERIC;


constant T_halfclock : time := 100 ns;
constant T_prop: time := 10 ns; -- avoid hold time violations

signal a_internal, b_internal : datapath := (others => '0'); 
signal a_internal_delayed, b_internal_delayed : datapath := (others => '0'); 
signal seed_a, seed_b : datapath;
signal sum_internal_x : datapath; 
signal signature_x, signature_y : datapath := (others => '0'); 
signal clock, reset : std_logic; 
signal load_prpg, load_compact : std_logic;
signal serial_prpg_a, serial_prpg_b, serial_compact_x, serial_compact_y : std_logic;
signal datain_request_internal, dataout_valid_internal : std_logic;
signal dataout_request_internal, datain_valid_internal : std_logic;
signal datain_valid_internal_delayed, datain_valid_internal_buf : std_logic;
signal one : std_logic;

begin

	--insert delay elements - Do you know why this is necessary?
	a_internal_delayed <= a_internal after T_prop;
	b_internal_delayed <= b_internal after T_prop; 
	datain_valid_internal_delayed <= datain_valid_internal_buf after T_prop;

	--initial seed value - DO NOT EDIT - 
	seed_a <= X"AAAA";
	seed_b <= X"0014";
	one <= '1';

	----------------------------------------
	-- Your adder component port map here --
	adder_part : component adder 
		port map(
		ain => a_internal_delayed,
		bin => b_internal_delayed,
		sum => sum_internal_x,
		clock => clock,
		datain_valid => datain_valid_internal_delayed, 
		dataout_request => dataout_request_internal,
		reset => reset,
		datain_request => datain_request_internal,
		dataout_valid => dataout_valid_internal
	);    

	----------------------------------------

	datain_valid_input_ff: process (clock) is
	begin	
   		if reset = '1' then                 -- if reset line low = active and clock edge received
			datain_valid_internal_buf <= '0';
      	elsif clock = '1' and clock'event then  -- if rising edge of clock
     		if datain_request_internal = '1' then
      			datain_valid_internal_buf <= 
				datain_valid_internal;  -- latch input and drive to outputs
	  		end if;
    	end if;
	end process datain_valid_input_ff; 

	-- instantiate a PRPG for input a
	prpg_input_a : component LFSR_GENERIC 
	generic map(Width => data_width)	
	port map 	(clock => clock,
				reset => reset,
				load => load_prpg,
				enable => datain_request_internal,
				parallel_in => seed_a,
		 		parallel_out => a_internal,
				serial_out => serial_prpg_a
			);

	-- instantiate a PRPG for input b
	prpg_input_b : component LFSR_GENERIC 
	generic map(Width => data_width)	
	port map 	(clock => clock,
				reset => reset,
				load => load_prpg,
				enable => datain_request_internal,
				parallel_in => seed_b,
		 		parallel_out => b_internal,
				serial_out => serial_prpg_b
			);

	-- instantiate a Signature compactor for output x 
	-- (output x can be used as the sum of an adder) 
	compactor_x : component LFSR_GENERIC 
	generic map(Width => data_width)	
	port map 	(clock => clock,
				reset => reset,
				load => load_compact,
				enable => dataout_valid_internal,
				parallel_in => sum_internal_x,
		 		parallel_out => signature_x,
				serial_out => serial_compact_x
			); 


	-- clock generator
	clock_gen : process
	begin
		clock <= '1';
		wait for T_halfclock;
		clock <= '0';
		wait for T_halfclock;
	end process clock_gen;

	-- process to control the load_compact and load_prpg
	ctrl_1 : process
	begin
		
		load_prpg <= '1';
		load_compact <= '1';
		
		-- pulse reset to avoid "don't cares" on input 
--		reset <= '0';
		reset <= '1';
		wait for 250 ns;
		reset <= '1';
		wait for 250 ns;
		reset <= '0';
		wait for 200 ns;

		-- start compacting
		load_compact <= '0';
		wait for 400 ns;

		-- start generating random data 
		load_prpg <= '0';
		wait for 5000 ns;

		wait;
	end process ctrl_1;

	-- process to control handshaking signals
	ctrl_2 : process
	begin
		
		-- normal operation
		dataout_request_internal <= '1';
		datain_valid_internal <= '1';
		wait for 2700 ns;

		-- our first pipeline stall
		dataout_request_internal <= '0';
		wait for 600 ns;

		-- end of pipeline stall 
		dataout_request_internal <= '1';
		wait for 1000 ns;

		-- invalid data region
		datain_valid_internal <= '0';
		wait for 400 ns;

		-- pipeline stall 
		dataout_request_internal <= '0';
		wait for 400 ns;

		datain_valid_internal <= '1';
		dataout_request_internal <= '1';
		wait for 1200 ns;

		datain_valid_internal <= '0';

		wait;
	end process ctrl_2;	

end mixed;