-------------------------------------------------
-- adder.vhd
--
-- Revised 2001/02/09
--
-- This pipelined combinational logic does nothing interesting
--
-- No handshaking between stages is included.
--
--                                                       
--                                                       
-- R              R              R                      R
-- e  -- XORs --- e ------------ e ------ ... --------- e
-- g              g              g                      g
--                                                       
--                                                       
--                                                       
-- If you have questions, post 'em to the newsgroup.
--
library ieee;
use ieee.std_logic_1164.all;
--library work;
use work.adder_pkg.all;

entity adder is
    PORT ( 
      ain : IN std_logic_vector(15 downto 0); 
      bin : IN std_logic_vector(15 downto 0); 
      sum : OUT std_logic_vector(15 downto 0); 
      clock : IN std_logic; 
      datain_valid : IN std_logic; 
      dataout_request : IN std_logic; 
      reset : IN std_logic; 
      datain_request : OUT std_logic; 
      dataout_valid : OUT std_logic); 
end entity adder;

architecture RTL of adder is

signal a_registered, b_registered, stage1, stage2, stage3 : datapath;
signal temp1, temp2 : std_logic;
begin

-- hand shaking in not implemented
datain_request <= '1';
dataout_valid  <= '1';

pipeline: process is
begin
	wait until rising_edge(clock);
	if reset = '1' then
		a_registered <= (others => '0');
		b_registered <= (others => '0');
		stage1 <= (others => '0');
		stage2 <= (others => '0');
		stage3 <= (others => '0');
		sum    <= (others => '0');
	else
		a_registered <= ain;
		b_registered <= bin;
		temp1 <= datain_valid xor stage1(0);
		temp2 <= dataout_request or stage1(1);
		stage1 <= a_registered xor b_registered;
		stage2 <= stage1(data_width-1 downto 2) & temp2 & temp1;
		stage3 <= stage2;
		sum    <= stage3;
	end if;
end process pipeline;

end RTL;