For some general information on the tools used in this lab see:
http://www.ece.ualberta.ca/~ee480/lab/labs.htm
Create a lab2 directory under ~/ece511
% mkdir ~/ece511/lab2
We are going to use Xilinx to synthesized and simulate a synchronous counter.
Save the following files in your ~/ece511/lab2/ directory
counter.vhd - counter_tb.vhd -
counter.do - counter.testvec
Open Xilinx
% cd ~/ece511/lab2
% xilinx &
When Xilinx opens, click:
File -> New Project
In the "New Project" window that pops up, set the project location to:
/ceb531/home/YOURLOGINNAME/ece511/lab2/
Set the Project Name to: counter
Under the Project Device Options, set the following:
Device Family: Spartan2
Device: xc2s200
Package: pq208
Speed Grade: -5
Design Flow: XST VHDL
Click Ok
Click Project -> Add Source
In the window that pops up select VHDL files counter.vhd (VHDL Module) and counter_tb.vhd (VHDL testbench) from your ece511/lab2 directory.
Make sure "counter" is highlighted, it should show up under xc2s200-5pq208 in the "Sources in Project" sub-window. In the "Processes for Current Source" double click "Implement Design". Expand "Synthesize" by clicking the "+" next to the name. View the Synthesis report by double clicking "synthesis report".
Find Tclk_min, Tclk-out, Tsetup (and Tcomb NA). Note Thold does not appear in the synthesis report. FPGA synthesis tools do not allow designers to violate hold times.
Back in the "Sources in Project" sub-window, select "counter_tb" under "counter". Go to the "Processes for Current Source" sub-window and double click "Simulate Behavioral VHDL Model". Examine examine the wave forms, pay close attention to when "count" changes relative to the clock and reset.
After verifying the behavioral simulation is correct, run the extracted simulation. Back in the "Sources in Project" sub-window, select "counter_tb" under "counter". Go to the "Processes for Current Source" sub-window and right click "Simulate Post-Place & Route VHDL Model". Goto "Properties" and set the time to 400 ns and the UUT to "counter_inst". Click Ok. And then double click "Simulate Post-Place & Route VHDL Model". Again, verify the waveforms are correct and note when "count" changes relative to the clock and reset.
In this lab, you will find the reciprocal (1/b) of an input (b), using multiplication and subtraction in an iterative algorithm. (Finding (1/b) is a step in calculating (a/b).)
This iteration is derived from Newton's method for finding the "zero" of an equation:
X[i+1] = X[i](2-X[i]b)
where i is the iteration count. X[0] is an initial guess. The final X[i] calculated is the calculated value of 1/b.
Write HDL code that implements 1/b and signals "complete" when the result has
converged (X[i] has stopped significantly changing). Use 9 bit fixed point signed
values for X and b with 7 binary digits to the right of the implied binary point. e.g.:
decimal, two's complement binary with written binary point, hex with implied binary point
1.5 = 01.1000000 = 0x0c0
0.5 = 00.1000000 = 0x040
0.125 = 00.0010000 = 0x010
-1.0 = 11.0000000 = 0x180
Inputs: b(9 bits), start, clock
Outputs: x(9 bits, provides intermediate results as well), iteration_count, complete
Choose a single value for X[0] for all simulations submitted for this lab. Try these values for b={0x080, c0, 42, ff, 63, 82} as well as some of your own. Explain what happens with b={40, 10, 180, 00}. Provide a table of your observations.
Hand in the wave form for the extracted simulation and find Tcomb, Tclk_min, Tsetup, Tclk-out
Using a stopwatch or the unix "time" command, compare how long it takes in Xilinx and ModelSim to:
1. compile the following code
2. simulate the following code, both behavioral and post-place & route, for 1000 cycles (or some smaller number if you have a slow workstation)
If you're not convinced that behavioural simulations can save time, try increasing counterWidth. If it runs too slowly on your workstation, decrease counterWidth. Either way, if you change counterWidth, also change the second parameter to conv_unsigned().