ECE 511 2004f 2004-9-22

Lab 1:

In this lab, you will write a behavioural description of a design in VHDL, suitable for synthesis.

Detailed directions for Mentor Graphics tools are given.  You will need to be able to use Mentor Graphics for later labs and the project.  Mentor Graphics also has a command line interface, which you are welcome to use.

This lab has two parts: an exercise that is not handed in, in which you will become familiar with the tools, and a lab that will be submitted for marking, in which you will create your own design.

Labs are to be done individually.  Please feel free to consult the professor, the T.A. or your fellow students for help with tools and concepts.  Please review the  lab requirements.

You are permitted to hand in code for this lab that contains "magic numbers" and does not use generics.
 

Bonus [10%]

Submit the bonus question on a separate page.

Provide a legible photocopy, enlarged 200%, of your One Card (and driver's license if you have one).  Please submit one full 8.5x11 inch photocopy page per person.  Feel free to delete any text other than your name.

When the projects begin, I'd like to give you the courtesy of addressing you and your team members by name.

Exercise (do not hand in)

Login and create a directory "~/ece511/lab1/".

Part 1: Finite State Machine Description

In this exercise, you will simulate behavioural VHDL code for a Mealy machine that detects non-overlapping occurrences of the pattern "1101" and counts up to at least 100 occurrences.

Part 2: Design Entry

Save the following two VHDL files (shift+left_click) to the ece511/lab1/ directory.

pattern.vhd
count.vhd

Now you are ready to load the VHDL design files:

Monitor the output of the vcom commands for any errors. Fix any errors that occur.

Part 3: Simulation

Start ModelSim in graphical mode and load the design pattern (which is stored in the work directory)

From the ModelSim toolbar, bring up a list of signals

Now bring up the waveform display with all signals: Create some simulation stimuli.  At the VSIM prompt in the ModelSim window, type: The force command takes a signal name, pairs of numbers describing an event (level and time), and options.  The first number in each pair is the signal level and the second is the delay in ns after which the signal is applied.

To test long bit patterns, it is easier to specify all of the waveform stimulus into a command file such as the example that follows. Save the following text into a file called "cmd.do" in the ~/ece511/lab1/ directory.

force reset 1 0, 0 10 -repeat 100
force clock 0 0, 1 5 -repeat 10
force bitstream 0 0, 0 10, 1 20, 0 30, 1 40, 0 50, 1 80
run 130

Then in the ModelSim window, you can run this wave stimulus file using the command:

This will save you having to type in long sequences of force commands when testing your circuit.  Furthermore, to reset the simulation run so that the time is at 0 ns use: restart -f   Also, remember that if you make changes to your VHDL code you have to recompile (which can be done at the VSIM prompt):

Click the run button to advance the simulation time further (or type: run). Now, get a printout:

You can also add stimuli to the simulation from the signals window.  This is useful for debugging individual architectures.

Try testing your system with the bit sequence "00010110001110111001101101011001011001100111" or a sequence of your choosing.


 

Lab

You have been asked to design a circuit that converts a serial bit stream (data_in) into an 8-bit wide parallel signal (data_out).  The least significant bit, bit-0, arrives first, indicated by a high level on the signal, first_bit (always seen every 8 clock cycles).  When new data is placed on the output, data_out_valid should be raised for one clock cycle.  Use the rising edge of the clock.  Write commented synthesizable RTL VHDL code for this circuit. Try to keep the implementation (code and synthesized hardware complexity) as small as possible.  You may be surprised how short the solution can be.