ECE 511 Digital ASIC Design
Fall Term (2004f) last
updated 2004-11-2
Use the class newsgroup ualberta.courses.ece.511
to ask questions, answer questions, or find project partners.
Use email for questions of a confidential nature.
General Course Info
Lectures Tues & Thurs 12:3--13:50 GSB 859
The period will wrap up with a seminar or discussion.
Office hours
Lab Wed 14:00-16:50 and other times as needed
CAD lab in ETLC e5-013
Hardware lab in ETLC e5-001
Students have card access to e5-013 and are free to use these lab
facilities
when these rooms are
not
scheduled for another course.
In this course, you will develop the necessary skills to design
complex
digital ASICs (application specific integrated circuits) and systems on
a chip (SoC) using CAD synthesis tools. Working in a group, you
and
your partners will design and implement a significant digital system
using
field programmable gate arrays and complex programmable logic devices.
Outline
- Overview of design methodologies
- Synchronous design, simulation and testing
- Design flows for FPGA and ASIC designs
- Hardware description language and synthesis
- Field programmable gate arrays
- Overview of gate arrays and IC process technology
Marking
| Labs |
|
15 |
dates |
| Final Exam |
|
30 |
exam period
2 "cheat sheets"
|
| Project |
|
55 |
|
| Application Notes |
15 |
|
|
| Proposal |
0
|
|
Oct 4
|
| Specification |
5 |
|
Oct 25
|
Resource Requirements &
Interface Demonstration |
5 |
|
Nov 10
|
| Simulation Documentation |
5 |
|
Nov 25
|
| Oral Presentation |
10 |
|
Dec 7
ECERF w3-087
|
| Final Report |
15 |
|
Dec 8
|
All lab and project submissions are due by 3:50 pm in the ECE 511
assignment
box outside of ECERF w2-023. Oversized final reports should be
taken
to Sylvia in ECERF W2-023, for her to timestamp and place in my
mailbox.
Late submissions will be penalized 20% of the assigned mark per school
day. Submissions will not normally be re-graded more than two
weeks
after the first day these have been returned in class.
The following calculators are permitted for examinations in this
course:
faculty approved programmable calculators, faculty approved
non-programmable
calculators, instructor approved abacuses
(if used quietly). Programmable calculators will probably offer
little
or no advantage over non-programmable calculators.
Grade Determination Method
In this course, raw marks will be calculated up until after the final
exam.
The resulting overall percentage mark will then be converted for each
student
to a letter grade. A standard expected distribution
of grades, which is provided by the Faculty of Engineering, will be
used
as a rough guideline when mapping overall marks to
grades.
Absolute merit of the work will also be taken into consideration.
Code of Student Behaviour
The University of Alberta is
committed to the highest standards of academic integrity and honesty.
Students are expected to be familiar with these standards regarding
academic honesty and to uphold the policies of the University in this
respect. Students are particularly urged to familiarize themselves with
the provisions of the Code of Student Behavior (online at http://www.ualberta.ca/secretariat/appeals.htm
) and avoid any behavior that could potentially result in suspicions of
cheating, plagiarism, misrepresentation of facts and/or participation
in an offence. Academic dishonesty is a serious offence and can result
in suspension or expulsion from the University.
Policy about course outlines can be found in §23.4(2) of the
University Calendar.
Library Resources
These readings are available for short-term loan from Cameron Library:
Textbooks
Course notes will be handed out as the term progresses.
You will need some kind of VHDL textbook. These are available in
the bookstore:
recommended
The Student's Guide to VHDL by Peter J. Ashenden
ISBN 1-55860-520-7
extra reading
Digital System Design with VHDL by M. Zwolinski
ISBN 0-201-36063-2
Additional VHDL documentation is available from
VHDL International Users' Forum
VHDL
Cookbook (a free
textbook by Ashenden)
Lab Assignments
Students are to work alone on labs except where stated. See
here for where to submit labs. Labs reports should be brief but
sufficiently
clear and readable that you would be happy to submit them to a busy
engineering manager. If it only takes a sentence to describe
something,
then it should be described in a sentence.
Lab reports should include:
- Title page
- for each part of the lab include:
- Answers to all numbered questions
- Assumptions made
- Any drawings which are an important part of the design (e.g.
state
transition
diagram)
- A brief written summary of the results and the work you did to
arrive
at
them
- Description of testing technique
- VHDL code that conforms to the ECE 511 coding standard
- Legible print-outs of simulations, timing analysis, etc. with
titles
and
annotations added (each page has to explain its self to the TA)
- Remember that bonus questions are mainly for
entertainment. Don't
attempt them if you're pressed for time.
- Any feedback on how the lab went that could be helpful to the TA
or
professor
Hints and tutorial information will be made available
here.
Chip Manufacturer's Documentation
Altera
Local UofA copies of documentation
Literature
Altera
University
Frequently Asked Questions
Altera
University
Program
Applications
notes
Altera is a trademark and service mark of Altera
Corporation
in the United States and other countries. Altera products are the
intellectual property
of Altera Corporation and are protected by
copyright
laws
Actel
Local UofA copies of documentation
Xilinx
Vertex
2 Datasheets
FPGA
Multimedia Board (HW-V2000-MLTA)