Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
u1|u0 27 0 0 0 3 0 0 0 1 0 0 0 0
u1 2 0 0 0 1 0 0 0 1 0 0 0 0
u0|system_0_reset_clk_domain_synch 3 1 0 1 1 1 1 1 0 0 0 0 0
u0|system_0_reset_altpll_0_c1_out_domain_synch 3 1 0 1 1 1 1 1 0 0 0 0 0
u0|the_uart_0|the_uart_0_regs 41 10 6 10 41 10 10 10 0 0 0 0 0
u0|the_uart_0|the_uart_0_rx|the_uart_0_rx_stimulus_source 15 0 14 0 1 0 0 0 0 0 0 0 0
u0|the_uart_0|the_uart_0_rx 17 1 0 1 13 1 1 1 0 0 0 0 0
u0|the_uart_0|the_uart_0_tx 25 0 0 0 4 0 0 0 0 0 0 0 0
u0|the_uart_0 26 0 0 0 20 0 0 0 0 0 0 0 0
u0|the_uart_0_s1 54 0 11 0 48 0 0 0 0 0 0 0 0
u0|the_tri_state_bridge_0_avalon_slave 86 0 6 0 43 0 0 0 8 0 0 0 0
u0|the_timer_1 23 0 0 0 17 0 0 0 0 0 0 0 0
u0|the_timer_1_s1 52 0 11 0 44 0 0 0 0 0 0 0 0
u0|the_timer_0 23 0 0 0 17 0 0 0 0 0 0 0 0
u0|the_timer_0_s1 52 0 11 0 44 0 0 0 0 0 0 0 0
u0|the_system_0_clock_0|endofpacket_bit_pipe 5 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_system_0_clock_0|master_FSM 5 0 0 0 4 0 0 0 0 0 0 0 0
u0|the_system_0_clock_0|write_request_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_system_0_clock_0|read_request_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_system_0_clock_0|slave_FSM 6 0 0 0 3 0 0 0 0 0 0 0 0
u0|the_system_0_clock_0|write_done_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_system_0_clock_0|read_done_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_system_0_clock_0 82 1 0 1 78 1 1 1 0 0 0 0 0
u0|the_system_0_clock_0_out 81 0 41 0 38 0 0 0 0 0 0 0 0
u0|the_system_0_clock_0_in 88 0 7 0 84 0 0 0 0 0 0 0 0
u0|the_system_0_burst_9 54 0 1 0 53 0 0 0 0 0 0 0 0
u0|the_system_0_burst_9_downstream 48 1 21 1 24 1 1 1 0 0 0 0 0
u0|the_system_0_burst_9_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_9_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_9_upstream|burstcount_fifo_for_system_0_burst_9_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_9_upstream 118 0 18 0 57 0 0 0 0 0 0 0 0
u0|the_system_0_burst_8 87 0 2 0 84 0 0 0 0 0 0 0 0
u0|the_system_0_burst_8_downstream 82 1 40 1 39 1 1 1 0 0 0 0 0
u0|the_system_0_burst_8_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_8_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_8_upstream|burstcount_fifo_for_system_0_burst_8_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_8_upstream 134 0 0 0 90 0 0 0 0 0 0 0 0
u0|the_system_0_burst_7 103 0 2 0 100 0 0 0 0 0 0 0 0
u0|the_system_0_burst_7_downstream 89 0 37 0 47 0 0 0 0 0 0 0 0
u0|the_system_0_burst_7_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_7_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_7_upstream|burstcount_fifo_for_system_0_burst_7_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_7_upstream 134 0 0 0 106 0 0 0 0 0 0 0 0
u0|the_system_0_burst_6 99 32 6 32 100 32 32 32 0 0 0 0 0
u0|the_system_0_burst_6_downstream 89 0 37 0 47 0 0 0 0 0 0 0 0
u0|the_system_0_burst_6_upstream|rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_6_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_6_upstream|burstcount_fifo_for_system_0_burst_6_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_6_upstream 72 6 0 6 70 6 6 6 0 0 0 0 0
u0|the_system_0_burst_5 92 0 4 0 91 0 0 0 0 0 0 0 0
u0|the_system_0_burst_5_downstream 69 0 21 0 43 0 0 0 0 0 0 0 0
u0|the_system_0_burst_5_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_5_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_5_upstream|burstcount_fifo_for_system_0_burst_5_upstream 11 3 0 3 6 3 3 3 0 0 0 0 0
u0|the_system_0_burst_5_upstream 104 1 1 1 97 1 1 1 0 0 0 0 0
u0|the_system_0_burst_4 88 16 5 16 91 16 16 16 0 0 0 0 0
u0|the_system_0_burst_4_downstream 69 0 21 0 43 0 0 0 0 0 0 0 0
u0|the_system_0_burst_4_upstream|rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_4_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_4_upstream|burstcount_fifo_for_system_0_burst_4_upstream 11 3 0 3 6 3 3 3 0 0 0 0 0
u0|the_system_0_burst_4_upstream 58 5 1 5 75 5 5 5 0 0 0 0 0
u0|the_system_0_burst_35 89 0 2 0 86 0 0 0 0 0 0 0 0
u0|the_system_0_burst_35_downstream 83 1 40 1 40 1 1 1 0 0 0 0 0
u0|the_system_0_burst_35_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_35_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_35_upstream|burstcount_fifo_for_system_0_burst_35_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_35_upstream 134 0 0 0 92 0 0 0 0 0 0 0 0
u0|the_system_0_burst_34 91 0 2 0 88 0 0 0 0 0 0 0 0
u0|the_system_0_burst_34_downstream 84 0 38 0 41 0 0 0 0 0 0 0 0
u0|the_system_0_burst_34_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_34_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_34_upstream|burstcount_fifo_for_system_0_burst_34_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_34_upstream 134 0 0 0 94 0 0 0 0 0 0 0 0
u0|the_system_0_burst_33 87 32 6 32 88 32 32 32 0 0 0 0 0
u0|the_system_0_burst_33_downstream 84 0 38 0 41 0 0 0 0 0 0 0 0
u0|the_system_0_burst_33_upstream|rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_33_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_33_upstream|burstcount_fifo_for_system_0_burst_33_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_33_upstream 72 6 0 6 58 6 6 6 0 0 0 0 0
u0|the_system_0_burst_32 91 0 2 0 88 0 0 0 0 0 0 0 0
u0|the_system_0_burst_32_downstream 83 1 39 1 41 1 1 1 0 0 0 0 0
u0|the_system_0_burst_32_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_32_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_32_upstream|burstcount_fifo_for_system_0_burst_32_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_32_upstream 134 0 0 0 94 0 0 0 0 0 0 0 0
u0|the_system_0_burst_31 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_31_downstream 22 8 12 8 14 8 8 8 0 0 0 0 0
u0|the_system_0_burst_31_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_31_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_31_upstream|burstcount_fifo_for_system_0_burst_31_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_31_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_30 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_30_downstream 22 8 12 8 14 8 8 8 0 0 0 0 0
u0|the_system_0_burst_30_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_30_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_30_upstream|burstcount_fifo_for_system_0_burst_30_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_30_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_3 72 0 4 0 73 0 0 0 0 0 0 0 0
u0|the_system_0_burst_3_downstream 50 0 10 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_3_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_3_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_3_upstream|burstcount_fifo_for_system_0_burst_3_upstream 12 4 0 4 7 4 4 4 0 0 0 0 0
u0|the_system_0_burst_3_upstream 88 0 0 0 76 0 0 0 0 0 0 0 0
u0|the_system_0_burst_29 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_29_downstream 22 8 12 8 14 8 8 8 0 0 0 0 0
u0|the_system_0_burst_29_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_29_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_29_upstream|burstcount_fifo_for_system_0_burst_29_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_29_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_28 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_28_downstream 22 8 12 8 14 8 8 8 0 0 0 0 0
u0|the_system_0_burst_28_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_28_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_28_upstream|burstcount_fifo_for_system_0_burst_28_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_28_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_27 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_27_downstream 22 8 12 8 14 8 8 8 0 0 0 0 0
u0|the_system_0_burst_27_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_27_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_27_upstream|burstcount_fifo_for_system_0_burst_27_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_27_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_26 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_26_downstream 22 8 12 8 14 8 8 8 0 0 0 0 0
u0|the_system_0_burst_26_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_26_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_26_upstream|burstcount_fifo_for_system_0_burst_26_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_26_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_25 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_25_downstream 22 8 12 8 14 8 8 8 0 0 0 0 0
u0|the_system_0_burst_25_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_25_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_25_upstream|burstcount_fifo_for_system_0_burst_25_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_25_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_24 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_24_downstream 22 8 12 8 14 8 8 8 0 0 0 0 0
u0|the_system_0_burst_24_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_24_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_24_upstream|burstcount_fifo_for_system_0_burst_24_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_24_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_23 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_23_downstream 22 8 12 8 14 8 8 8 0 0 0 0 0
u0|the_system_0_burst_23_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_23_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_23_upstream|burstcount_fifo_for_system_0_burst_23_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_23_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_22 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_22_downstream 22 8 12 8 14 8 8 8 0 0 0 0 0
u0|the_system_0_burst_22_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_22_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_22_upstream|burstcount_fifo_for_system_0_burst_22_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_22_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_21 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_21_downstream 22 8 12 8 14 8 8 8 0 0 0 0 0
u0|the_system_0_burst_21_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_21_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_21_upstream|burstcount_fifo_for_system_0_burst_21_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_21_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_20 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_20_downstream 22 8 12 8 14 8 8 8 0 0 0 0 0
u0|the_system_0_burst_20_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_20_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_20_upstream|burstcount_fifo_for_system_0_burst_20_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_20_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_2 68 8 4 8 73 8 8 8 0 0 0 0 0
u0|the_system_0_burst_2_downstream 50 0 10 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_2_upstream|rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_2_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_2_upstream|burstcount_fifo_for_system_0_burst_2_upstream 12 4 0 4 7 4 4 4 0 0 0 0 0
u0|the_system_0_burst_2_upstream 50 3 0 3 63 3 3 3 0 0 0 0 0
u0|the_system_0_burst_19 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_19_downstream 22 8 12 8 14 8 8 8 0 0 0 0 0
u0|the_system_0_burst_19_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_19_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_19_upstream|burstcount_fifo_for_system_0_burst_19_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_19_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_18 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_18_downstream 22 8 12 8 14 8 8 8 0 0 0 0 0
u0|the_system_0_burst_18_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_18_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_18_upstream|burstcount_fifo_for_system_0_burst_18_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_18_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_17 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_17_downstream 22 8 12 8 14 8 8 8 0 0 0 0 0
u0|the_system_0_burst_17_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_17_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_17_upstream|burstcount_fifo_for_system_0_burst_17_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_17_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_16 48 0 1 0 47 0 0 0 0 0 0 0 0
u0|the_system_0_burst_16_downstream 45 1 22 1 21 1 1 1 0 0 0 0 0
u0|the_system_0_burst_16_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_16_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_16_upstream|burstcount_fifo_for_system_0_burst_16_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_16_upstream 118 0 18 0 51 0 0 0 0 0 0 0 0
u0|the_system_0_burst_15 84 0 4 0 83 0 0 0 0 0 0 0 0
u0|the_system_0_burst_15_downstream 64 0 19 0 39 0 0 0 0 0 0 0 0
u0|the_system_0_burst_15_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_15_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_15_upstream|burstcount_fifo_for_system_0_burst_15_upstream 11 3 0 3 6 3 3 3 0 0 0 0 0
u0|the_system_0_burst_15_upstream 104 1 1 1 89 1 1 1 0 0 0 0 0
u0|the_system_0_burst_14 80 16 5 16 83 16 16 16 0 0 0 0 0
u0|the_system_0_burst_14_downstream 64 0 19 0 39 0 0 0 0 0 0 0 0
u0|the_system_0_burst_14_upstream|rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_14_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_14_upstream|burstcount_fifo_for_system_0_burst_14_upstream 11 3 0 3 6 3 3 3 0 0 0 0 0
u0|the_system_0_burst_14_upstream 58 5 1 5 67 5 5 5 0 0 0 0 0
u0|the_system_0_burst_13 85 0 2 0 82 0 0 0 0 0 0 0 0
u0|the_system_0_burst_13_downstream 48 33 40 33 38 33 33 33 0 0 0 0 0
u0|the_system_0_burst_13_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_13_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_13_upstream|burstcount_fifo_for_system_0_burst_13_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_13_upstream 134 0 0 0 88 0 0 0 0 0 0 0 0
u0|the_system_0_burst_12 32 0 0 0 33 0 0 0 0 0 0 0 0
u0|the_system_0_burst_12_downstream 30 1 12 1 14 1 1 1 0 0 0 0 0
u0|the_system_0_burst_12_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_12_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_12_upstream|burstcount_fifo_for_system_0_burst_12_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_12_upstream 110 0 27 0 35 0 0 0 0 0 0 0 0
u0|the_system_0_burst_11 54 0 1 0 53 0 0 0 0 0 0 0 0
u0|the_system_0_burst_11_downstream 48 1 21 1 24 1 1 1 0 0 0 0 0
u0|the_system_0_burst_11_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_11_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_11_upstream|burstcount_fifo_for_system_0_burst_11_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_11_upstream 118 0 18 0 57 0 0 0 0 0 0 0 0
u0|the_system_0_burst_10 54 0 1 0 53 0 0 0 0 0 0 0 0
u0|the_system_0_burst_10_downstream 48 1 21 1 24 1 1 1 0 0 0 0 0
u0|the_system_0_burst_10_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_10_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_10_upstream|burstcount_fifo_for_system_0_burst_10_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_10_upstream 118 0 18 0 57 0 0 0 0 0 0 0 0
u0|the_system_0_burst_1 103 0 2 0 100 0 0 0 0 0 0 0 0
u0|the_system_0_burst_1_downstream 89 0 37 0 47 0 0 0 0 0 0 0 0
u0|the_system_0_burst_1_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_1_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_1_upstream|burstcount_fifo_for_system_0_burst_1_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_1_upstream 134 0 0 0 106 0 0 0 0 0 0 0 0
u0|the_system_0_burst_0 99 32 6 32 100 32 32 32 0 0 0 0 0
u0|the_system_0_burst_0_downstream 89 0 37 0 47 0 0 0 0 0 0 0 0
u0|the_system_0_burst_0_upstream|rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_0_upstream 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_system_0_burst_0_upstream|burstcount_fifo_for_system_0_burst_0_upstream 10 2 0 2 5 2 2 2 0 0 0 0 0
u0|the_system_0_burst_0_upstream 72 6 0 6 70 6 6 6 0 0 0 0 0
u0|the_sram_0|the_SRAM_16Bit_512K 40 0 1 0 39 0 0 0 16 0 0 0 0
u0|the_sram_0 40 0 0 0 39 0 0 0 16 0 0 0 0
u0|the_sram_0_avalon_slave_0 110 0 4 0 65 0 0 0 0 0 0 0 0
u0|the_sdram_0|the_sdram_0_input_efifo_module 45 0 0 0 45 0 0 0 0 0 0 0 0
u0|the_sdram_0 45 1 1 1 39 1 1 1 16 0 0 0 0
u0|the_sdram_0_s1|rdv_fifo_for_system_0_burst_5_downstream_to_sdram_0_s1 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_sdram_0_s1|rdv_fifo_for_system_0_burst_4_downstream_to_sdram_0_s1 7 2 0 2 2 2 2 2 0 0 0 0 0
u0|the_sdram_0_s1 120 0 4 0 72 0 0 0 0 0 0 0 0
u0|the_noteG 5 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_noteG_s1 17 0 9 0 9 0 0 0 0 0 0 0 0
u0|the_noteF 5 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_noteF_s1 17 0 9 0 9 0 0 0 0 0 0 0 0
u0|the_noteE 5 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_noteE_s1 17 0 9 0 9 0 0 0 0 0 0 0 0
u0|the_noteD 5 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_noteD_s1 17 0 9 0 9 0 0 0 0 0 0 0 0
u0|the_noteC 5 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_noteC_s1 17 0 9 0 9 0 0 0 0 0 0 0 0
u0|the_noteB 5 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_noteB_s1 17 0 9 0 9 0 0 0 0 0 0 0 0
u0|the_noteA 5 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_noteA_s1 17 0 9 0 9 0 0 0 0 0 0 0 0
u0|the_lcd_16207_0 13 0 1 0 11 0 0 0 8 0 0 0 0
u0|the_lcd_16207_0_control_slave 33 0 9 0 27 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram2 24 0 0 0 8 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r 13 0 1 0 16 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram2 24 0 0 0 8 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w 12 0 0 0 16 0 0 0 0 0 0 0 0
u0|the_jtag_uart_0 38 10 23 10 36 10 10 10 0 0 0 0 0
u0|the_jtag_uart_0_avalon_jtag_slave 84 0 10 0 78 0 0 0 0 0 0 0 0
u0|the_i2c_master|i2c_master|i2c_top_inst|u1|u1 27 2 0 2 7 2 2 2 0 0 0 0 0
u0|the_i2c_master|i2c_master|i2c_top_inst|u1 35 0 0 0 15 0 0 0 0 0 0 0 0
u0|the_i2c_master|i2c_master|i2c_top_inst 19 1 0 1 14 1 1 1 0 0 0 0 0
u0|the_i2c_master|i2c_master 39 24 24 24 37 24 24 24 1 0 0 0 0
u0|the_i2c_master 39 0 0 0 37 0 0 0 1 0 0 0 0
u0|the_i2c_master_avalon_slave_0 126 0 6 0 81 0 0 0 0 0 0 0 0
u0|the_epcs_controller|the_boot_copier_rom|auto_generated 8 0 0 0 32 0 0 0 0 0 0 0 0
u0|the_epcs_controller|the_tornado_epcs_controller_atom 4 1 0 1 1 1 1 1 0 0 0 0 0
u0|the_epcs_controller|the_epcs_controller_sub 25 0 0 0 23 0 0 0 0 0 0 0 0
u0|the_epcs_controller 46 0 17 0 36 0 0 0 0 0 0 0 0
u0|the_epcs_controller_epcs_control_port 140 0 6 0 90 0 0 0 0 0 0 0 0
u0|the_dist_sensor 8 0 0 0 2 0 0 0 0 0 0 0 0
u0|the_dist_sensor_s1 26 0 16 0 13 0 0 0 0 0 0 0 0
u0|the_cpu_0 151 4 21 4 131 4 4 4 0 0 0 0 0
u0|the_cpu_0_instruction_master 210 0 16 0 62 0 0 0 0 0 0 0 0
u0|the_cpu_0_data_master 751 21 73 21 118 21 21 21 0 0 0 0 0
u0|the_cpu_0_jtag_debug_module 147 0 6 0 92 0 0 0 0 0 0 0 0
u0|the_altpll_0|stdsync2|dffpipe3 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_altpll_0|stdsync2 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_altpll_0 38 31 30 31 36 31 31 31 0 0 0 0 0
u0|the_altpll_0_pll_slave 72 1 2 1 74 1 1 1 0 0 0 0 0
u0|the_SEG7_Display|the_SEG7_LUT_8|u7 4 0 0 0 7 0 0 0 0 0 0 0 0
u0|the_SEG7_Display|the_SEG7_LUT_8|u6 4 0 0 0 7 0 0 0 0 0 0 0 0
u0|the_SEG7_Display|the_SEG7_LUT_8|u5 4 0 0 0 7 0 0 0 0 0 0 0 0
u0|the_SEG7_Display|the_SEG7_LUT_8|u4 4 0 0 0 7 0 0 0 0 0 0 0 0
u0|the_SEG7_Display|the_SEG7_LUT_8|u3 4 0 0 0 7 0 0 0 0 0 0 0 0
u0|the_SEG7_Display|the_SEG7_LUT_8|u2 4 0 0 0 7 0 0 0 0 0 0 0 0
u0|the_SEG7_Display|the_SEG7_LUT_8|u1 4 0 0 0 7 0 0 0 0 0 0 0 0
u0|the_SEG7_Display|the_SEG7_LUT_8|u0 4 0 0 0 7 0 0 0 0 0 0 0 0
u0|the_SEG7_Display|the_SEG7_LUT_8 35 0 0 0 56 0 0 0 0 0 0 0 0
u0|the_SEG7_Display 35 0 0 0 56 0 0 0 0 0 0 0 0
u0|the_SEG7_Display_avalon_slave_0 44 0 8 0 39 0 0 0 0 0 0 0 0
u0|the_SD_DAT 7 0 0 0 1 0 0 0 1 0 0 0 0
u0|the_SD_DAT_s1 25 0 16 0 12 0 0 0 0 0 0 0 0
u0|the_SD_CMD 7 0 0 0 1 0 0 0 1 0 0 0 0
u0|the_SD_CMD_s1 25 0 16 0 12 0 0 0 0 0 0 0 0
u0|the_SD_CLK 7 0 0 0 2 0 0 0 0 0 0 0 0
u0|the_SD_CLK_s1 25 0 16 0 12 0 0 0 0 0 0 0 0
u0|the_RST 8 0 0 0 2 0 0 0 0 0 0 0 0
u0|the_RST_s1 26 0 16 0 13 0 0 0 0 0 0 0 0
u0|the_Oct_UP 8 0 0 0 2 0 0 0 0 0 0 0 0
u0|the_Oct_UP_s1 26 0 16 0 13 0 0 0 0 0 0 0 0
u0|the_Oct_DOWN 8 0 0 0 2 0 0 0 0 0 0 0 0
u0|the_Oct_DOWN_s1 26 0 16 0 13 0 0 0 0 0 0 0 0
u0|the_MS 8 0 0 0 2 0 0 0 0 0 0 0 0
u0|the_MS_s1 26 0 16 0 13 0 0 0 0 0 0 0 0
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|wrfull_eq_comp 18 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|rdempty_eq_comp 18 0 0 0 1 0 0 0 0 0 0 0 0
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|ws_dgrp|dffpipe20 11 0 0 0 9 0 0 0 0 0 0 0 0
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|ws_dgrp 11 0 0 0 9 0 0 0 0 0 0 0 0
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|rs_dgwp|dffpipe17 11 0 0 0 9 0 0 0 0 0 0 0 0
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|rs_dgwp 11 0 0 0 9 0 0 0 0 0 0 0 0
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|rdaclr 3 1 0 1 1 1 1 1 0 0 0 0 0
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|fifo_ram|altsyncram14 56 17 0 17 16 17 17 17 0 0 0 0 0
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|fifo_ram 38 0 0 0 16 0 0 0 0 0 0 0 0
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|wrptr_gp 3 0 0 0 9 0 0 0 0 0 0 0 0
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|wrptr_g1p 3 0 0 0 0 0 0 0 0 0 0 0 0
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 9 0 0 0 0 0 0 0 0
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated 21 0 0 0 17 0 0 0 0 0 0 0 0
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0 21 0 0 0 17 0 0 0 0 0 0 0 0
u0|the_Audio_0|the_AUDIO_DAC_FIFO 20 15 0 15 20 15 15 15 0 0 0 0 0
u0|the_Audio_0 20 0 0 0 20 0 0 0 0 0 0 0 0
u0|the_Audio_0_avalon_slave_0 44 0 7 0 39 0 0 0 0 0 0 0 0
u0|the_Accel_Control|accel_control 47 0 42 0 33 0 0 0 2 0 0 0 0
u0|the_Accel_Control 47 0 0 0 33 0 0 0 2 0 0 0 0
u0|the_Accel_Control_avalon_slave 83 0 7 0 80 0 0 0 0 0 0 0 0
u0 19 0 0 0 142 0 0 0 53 0 0 0 0
PLL2 2 0 0 0 1 0 0 0 0 0 0 0 0
delay1 2 0 0 0 1 0 0 0 0 0 0 0 0