niosII_system

2015.04.08.14:42:35 Datasheet
Overview
  clk_0  niosII_system
Processor
   nios2_qsys_0 Nios II 12.1
All Components
   nios2_qsys_0 altera_nios2_qsys 12.1
   onchip_memory2_0 altera_avalon_onchip_memory2 12.1
   sysid_qsys_0 altera_avalon_sysid_qsys 12.1
   jtag_uart_0 altera_avalon_jtag_uart 12.1
   altpll_0 altpll 12.1
   sdram_0 altera_avalon_new_sdram_controller 12.1
   sram_0 altera_up_avalon_sram 12.0
   timer_0 altera_avalon_timer 12.1
   midiOut_0 midiOut 1.0
Memory Map
nios2_qsys_0
 data_master  instruction_master
  nios2_qsys_0
jtag_debug_module  0x01108800 0x01108800
  onchip_memory2_0
s1  0x01104000 0x01104000
  sysid_qsys_0
control_slave  0x01109038
  jtag_uart_0
avalon_jtag_slave  0x01109030
  altpll_0
pll_slave  0x01109020
  sdram_0
s1  0x00800000 0x00800000
  sram_0
avalon_sram_slave  0x01080000 0x01080000
  timer_0
s1  0x01109000
  midiOut_0
s0  0x01109040

clk_0

clock_source v12.1


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

nios2_qsys_0

altera_nios2_qsys v12.1
clk_0 clk_reset   nios2_qsys_0
  reset_n
altpll_0 c1  
  clk
jtag_debug_module_reset   onchip_memory2_0
  reset1
data_master  
  s1
instruction_master  
  s1
jtag_debug_module_reset   sysid_qsys_0
  reset
data_master  
  control_slave
jtag_debug_module_reset   jtag_uart_0
  reset
data_master  
  avalon_jtag_slave
d_irq  
  irq
jtag_debug_module_reset   altpll_0
  inclk_interface_reset
data_master  
  pll_slave
jtag_debug_module_reset   sram_0
  clock_reset_reset
data_master  
  avalon_sram_slave
instruction_master  
  avalon_sram_slave
data_master   sdram_0
  s1
instruction_master  
  s1
jtag_debug_module_reset  
  reset
data_master   timer_0
  s1
jtag_debug_module_reset  
  reset
d_irq  
  irq
jtag_debug_module_reset   midiOut_0
  reset_n
data_master  
  s0


Parameters

setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_bit31BypassDCache true
setting_bigEndian false
setting_export_large_RAMs false
setting_asic_enabled false
setting_asic_synopsys_translate_on_off false
setting_oci_export_jtag_signals false
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
muldiv_divider false
mpu_useLimit false
mpu_enabled false
mmu_enabled false
mmu_autoAssignTlbPtrSz true
manuallyAssignCpuID true
debug_triggerArming true
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
dcache_omitDataMaster false
cpuReset false
is_hardcopy_compatible false
setting_shadowRegisterSets 0
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mmu_TLBMissExcOffset 0
debug_jtagInstanceID 0
resetOffset 0
exceptionOffset 32
cpuID 0
cpuID_stored 0
breakOffset 32
userDefinedSettings
resetSlave onchip_memory2_0.s1
mmu_TLBMissExcSlave
exceptionSlave onchip_memory2_0.s1
breakSlave nios2_qsys_0.jtag_debug_module
setting_perfCounterWidth 32
setting_interruptControllerType Internal
setting_branchPredictionType Automatic
setting_bhtPtrSz 8
muldiv_multiplierType EmbeddedMulFast
mpu_minInstRegionSize 12
mpu_minDataRegionSize 12
mmu_uitlbNumEntries 4
mmu_udtlbNumEntries 6
mmu_tlbPtrSz 7
mmu_tlbNumWays 16
mmu_processIDNumBits 8
impl Tiny
icache_size 4096
icache_ramBlockType Automatic
icache_numTCIM 0
icache_burstType None
dcache_bursts false
debug_level Level1
debug_OCIOnchipTrace _128
dcache_size 2048
dcache_ramBlockType Automatic
dcache_numTCDM 0
dcache_lineSize 32
regfile_ramBlockType Automatic
mmu_ramBlockType Automatic
bht_ramBlockType Automatic
resetAbsoluteAddr 17842176
exceptionAbsoluteAddr 17842208
breakAbsoluteAddr 17860640
mmu_TLBMissExcAbsAddr 0
translate_on "synthesis translate_on"
translate_off "synthesis translate_off"
instAddrWidth 25
dataAddrWidth 25
tightlyCoupledDataMaster0AddrWidth 1
tightlyCoupledDataMaster1AddrWidth 1
tightlyCoupledDataMaster2AddrWidth 1
tightlyCoupledDataMaster3AddrWidth 1
tightlyCoupledInstructionMaster0AddrWidth 1
tightlyCoupledInstructionMaster1AddrWidth 1
tightlyCoupledInstructionMaster2AddrWidth 1
tightlyCoupledInstructionMaster3AddrWidth 1
instSlaveMapParam <address-map><slave name='sdram_0.s1' start='0x800000' end='0x1000000' /><slave name='sram_0.avalon_sram_slave' start='0x1080000' end='0x1100000' /><slave name='onchip_memory2_0.s1' start='0x1104000' end='0x1108000' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x1108800' end='0x1109000' /></address-map>
dataSlaveMapParam <address-map><slave name='sdram_0.s1' start='0x800000' end='0x1000000' /><slave name='sram_0.avalon_sram_slave' start='0x1080000' end='0x1100000' /><slave name='onchip_memory2_0.s1' start='0x1104000' end='0x1108000' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x1108800' end='0x1109000' /><slave name='timer_0.s1' start='0x1109000' end='0x1109020' /><slave name='altpll_0.pll_slave' start='0x1109020' end='0x1109030' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1109030' end='0x1109038' /><slave name='sysid_qsys_0.control_slave' start='0x1109038' end='0x1109040' /><slave name='midiOut_0.s0' start='0x1109040' end='0x1109044' /></address-map>
clockFrequency 50000000
deviceFamilyName CYCLONEII
internalIrqMaskSystemInfo 3
customInstSlavesSystemInfo <info/>
deviceFeaturesSystemInfo NOT_LISTED 0 INSTALLED 1 IS_DEFAULT_FAMILY 0 ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 1 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 0 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 1 HAS_JITTER_SUPPORT 0 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 1 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 0 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 1 HAS_SPLIT_IO_SUPPORT 0 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 0 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 1 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 IS_CONFIG_ROM 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 1 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 0 MRAM_MEMORY 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 1 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 1 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 1 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 0 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 0 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster3MapParam
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster3MapParam
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIG_ENDIAN 0
BREAK_ADDR 0x01108820
CPU_FREQ 50000000u
CPU_ID_SIZE 1
CPU_ID_VALUE 0x00000000
CPU_IMPLEMENTATION "tiny"
DATA_ADDR_WIDTH 25
DCACHE_LINE_SIZE 0
DCACHE_LINE_SIZE_LOG2 0
DCACHE_SIZE 0
EXCEPTION_ADDR 0x01104020
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 0
HARDWARE_MULX_PRESENT 0
HAS_DEBUG_CORE 1
HAS_DEBUG_STUB
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE 0
ICACHE_LINE_SIZE_LOG2 0
ICACHE_SIZE 0
INST_ADDR_WIDTH 25
RESET_ADDR 0x01104000

onchip_memory2_0

altera_avalon_onchip_memory2 v12.1
clk_0 clk_reset   onchip_memory2_0
  reset1
nios2_qsys_0 jtag_debug_module_reset  
  reset1
data_master  
  s1
instruction_master  
  s1
altpll_0 c1  
  clk1


Parameters

allowInSystemMemoryContentEditor false
autoInitializationFileName niosII_system_onchip_memory2_0
blockType AUTO
dataWidth 32
deviceFamily CYCLONEII
dualPort false
initMemContent true
initializationFileName onchip_memory2_0
instanceID NONE
memorySize 16384
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
simMemInitOnlyFilename 0
singleClockOperation false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "onchip_memory2_0"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SINGLE_CLOCK_OP 0
SIZE_VALUE 16384u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

sysid_qsys_0

altera_avalon_sysid_qsys v12.1
clk_0 clk_reset   sysid_qsys_0
  reset
nios2_qsys_0 jtag_debug_module_reset  
  reset
data_master  
  control_slave
altpll_0 c1  
  clk


Parameters

id 0
timestamp 1428525755
AUTO_CLK_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY CYCLONEII
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

ID 0
TIMESTAMP 1428525755

jtag_uart_0

altera_avalon_jtag_uart v12.1
clk_0 clk_reset   jtag_uart_0
  reset
nios2_qsys_0 jtag_debug_module_reset  
  reset
data_master  
  avalon_jtag_slave
d_irq  
  irq
altpll_0 c1  
  clk


Parameters

allowMultipleConnections false
avalonSpec 2.0
hubInstanceID 0
legacySignalAllow false
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_INPUT_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 64
writeIRQThreshold 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

altpll_0

altpll v12.1
clk_0 clk_reset   altpll_0
  inclk_interface_reset
clk  
  inclk_interface
nios2_qsys_0 jtag_debug_module_reset  
  inclk_interface_reset
data_master  
  pll_slave
c1   nios2_qsys_0
  clk
c1   onchip_memory2_0
  clk1
c1   sysid_qsys_0
  clk
c1   jtag_uart_0
  clk
c1   sdram_0
  clk
c1   sram_0
  clock_reset
c1   timer_0
  clk
c1   frequencyDivider_0
  clock_in
c1   midiOut_0
  clock


Parameters

HIDDEN_CUSTOM_ELABORATION altpll_avalon_elaboration
HIDDEN_CUSTOM_POST_EDIT altpll_avalon_post_edit
INTENDED_DEVICE_FAMILY Cyclone II
WIDTH_CLOCK
WIDTH_PHASECOUNTERSELECT
PRIMARY_CLOCK
INCLK0_INPUT_FREQUENCY 20000
INCLK1_INPUT_FREQUENCY
OPERATION_MODE NORMAL
PLL_TYPE
QUALIFY_CONF_DONE
COMPENSATE_CLOCK CLK0
SCAN_CHAIN
GATE_LOCK_SIGNAL NO
GATE_LOCK_COUNTER
LOCK_HIGH
LOCK_LOW
VALID_LOCK_MULTIPLIER 1
INVALID_LOCK_MULTIPLIER 5
SWITCH_OVER_ON_LOSSCLK
SWITCH_OVER_ON_GATED_LOCK
ENABLE_SWITCH_OVER_COUNTER
SKIP_VCO
SWITCH_OVER_COUNTER
SWITCH_OVER_TYPE
FEEDBACK_SOURCE
BANDWIDTH
BANDWIDTH_TYPE
SPREAD_FREQUENCY
DOWN_SPREAD
SELF_RESET_ON_GATED_LOSS_LOCK
SELF_RESET_ON_LOSS_LOCK
CLK0_MULTIPLY_BY 1
CLK1_MULTIPLY_BY 1
CLK2_MULTIPLY_BY
CLK3_MULTIPLY_BY
CLK4_MULTIPLY_BY
CLK5_MULTIPLY_BY
CLK6_MULTIPLY_BY
CLK7_MULTIPLY_BY
CLK8_MULTIPLY_BY
CLK9_MULTIPLY_BY
EXTCLK0_MULTIPLY_BY
EXTCLK1_MULTIPLY_BY
EXTCLK2_MULTIPLY_BY
EXTCLK3_MULTIPLY_BY
CLK0_DIVIDE_BY 1
CLK1_DIVIDE_BY 1
CLK2_DIVIDE_BY
CLK3_DIVIDE_BY
CLK4_DIVIDE_BY
CLK5_DIVIDE_BY
CLK6_DIVIDE_BY
CLK7_DIVIDE_BY
CLK8_DIVIDE_BY
CLK9_DIVIDE_BY
EXTCLK0_DIVIDE_BY
EXTCLK1_DIVIDE_BY
EXTCLK2_DIVIDE_BY
EXTCLK3_DIVIDE_BY
CLK0_PHASE_SHIFT -3000
CLK1_PHASE_SHIFT 0
CLK2_PHASE_SHIFT
CLK3_PHASE_SHIFT
CLK4_PHASE_SHIFT
CLK5_PHASE_SHIFT
CLK6_PHASE_SHIFT
CLK7_PHASE_SHIFT
CLK8_PHASE_SHIFT
CLK9_PHASE_SHIFT
EXTCLK0_PHASE_SHIFT
EXTCLK1_PHASE_SHIFT
EXTCLK2_PHASE_SHIFT
EXTCLK3_PHASE_SHIFT
CLK0_DUTY_CYCLE 50
CLK1_DUTY_CYCLE 50
CLK2_DUTY_CYCLE
CLK3_DUTY_CYCLE
CLK4_DUTY_CYCLE
CLK5_DUTY_CYCLE
CLK6_DUTY_CYCLE
CLK7_DUTY_CYCLE
CLK8_DUTY_CYCLE
CLK9_DUTY_CYCLE
EXTCLK0_DUTY_CYCLE
EXTCLK1_DUTY_CYCLE
EXTCLK2_DUTY_CYCLE
EXTCLK3_DUTY_CYCLE
PORT_clkena0 PORT_UNUSED
PORT_clkena1 PORT_UNUSED
PORT_clkena2 PORT_UNUSED
PORT_clkena3 PORT_UNUSED
PORT_clkena4 PORT_UNUSED
PORT_clkena5 PORT_UNUSED
PORT_extclkena0
PORT_extclkena1
PORT_extclkena2
PORT_extclkena3
PORT_extclk0 PORT_UNUSED
PORT_extclk1 PORT_UNUSED
PORT_extclk2 PORT_UNUSED
PORT_extclk3 PORT_UNUSED
PORT_CLKBAD0 PORT_UNUSED
PORT_CLKBAD1 PORT_UNUSED
PORT_clk0 PORT_USED
PORT_clk1 PORT_USED
PORT_clk2 PORT_UNUSED
PORT_clk3 PORT_UNUSED
PORT_clk4 PORT_UNUSED
PORT_clk5 PORT_UNUSED
PORT_clk6
PORT_clk7
PORT_clk8
PORT_clk9
PORT_SCANDATA PORT_UNUSED
PORT_SCANDATAOUT PORT_UNUSED
PORT_SCANDONE PORT_UNUSED
PORT_SCLKOUT1
PORT_SCLKOUT0
PORT_ACTIVECLOCK PORT_UNUSED
PORT_CLKLOSS PORT_UNUSED
PORT_INCLK1 PORT_UNUSED
PORT_INCLK0 PORT_USED
PORT_FBIN PORT_UNUSED
PORT_PLLENA PORT_UNUSED
PORT_CLKSWITCH PORT_UNUSED
PORT_ARESET PORT_UNUSED
PORT_PFDENA PORT_UNUSED
PORT_SCANCLK PORT_UNUSED
PORT_SCANACLR PORT_UNUSED
PORT_SCANREAD PORT_UNUSED
PORT_SCANWRITE PORT_UNUSED
PORT_ENABLE0
PORT_ENABLE1
PORT_LOCKED PORT_UNUSED
PORT_CONFIGUPDATE PORT_UNUSED
PORT_FBOUT
PORT_PHASEDONE PORT_UNUSED
PORT_PHASESTEP PORT_UNUSED
PORT_PHASEUPDOWN PORT_UNUSED
PORT_SCANCLKENA PORT_UNUSED
PORT_PHASECOUNTERSELECT PORT_UNUSED
PORT_VCOOVERRANGE
PORT_VCOUNDERRANGE
DPA_MULTIPLY_BY
DPA_DIVIDE_BY
DPA_DIVIDER
VCO_MULTIPLY_BY
VCO_DIVIDE_BY
SCLKOUT0_PHASE_SHIFT
SCLKOUT1_PHASE_SHIFT
VCO_FREQUENCY_CONTROL
VCO_PHASE_SHIFT_STEP
USING_FBMIMICBIDIR_PORT
SCAN_CHAIN_MIF_FILE
AVALON_USE_SEPARATE_SYSCLK NO
HIDDEN_CONSTANTS CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#VALID_LOCK_MULTIPLIER 1 CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#CLK0_PHASE_SHIFT -3000 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#INVALID_LOCK_MULTIPLIER 5 CT#INTENDED_DEVICE_FAMILY {Cyclone II} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#GATE_LOCK_SIGNAL NO CT#PORT_LOCKED PORT_UNUSED
HIDDEN_PRIVATES PT#GLOCKED_FEATURE_ENABLED 1 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 0 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 1 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 0 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_ENA_CHECK 0 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 0 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 0.00000000 PT#PHASE_SHIFT0 -3.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#BANDWIDTH_USE_CUSTOM 0 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 50.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 ns PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone II} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423267866175616.mif PT#ACTIVECLK_CHECK 0
HIDDEN_USED_PORTS UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used
HIDDEN_IS_NUMERIC IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#VALID_LOCK_MULTIPLIER 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#INVALID_LOCK_MULTIPLIER 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1
HIDDEN_MF_PORTS MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1
HIDDEN_IF_PORTS IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}
HIDDEN_IS_FIRST_EDIT 0
AUTO_INCLK_INTERFACE_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY CYCLONEII
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

sdram_0

altera_avalon_new_sdram_controller v12.1
clk_0 clk_reset   sdram_0
  reset
altpll_0 c1  
  clk
nios2_qsys_0 data_master  
  s1
instruction_master  
  s1
jtag_debug_module_reset  
  reset


Parameters

TAC 5.5
TMRD 3
TRCD 20.0
TRFC 70.0
TRP 20.0
TWR 14.0
casLatency 3
clockRate 50000000
columnWidth 8
dataWidth 16
generateSimulationModel false
initNOPDelay 0.0
initRefreshCommands 2
masteredTristateBridgeSlave
model custom
numberOfBanks 4
numberOfChipSelects 1
pinsSharedViaTriState false
powerUpDelay 100.0
refreshPeriod 15.625
registerDataIn true
rowWidth 12
size 8388608
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

REGISTER_DATA_IN 1
SIM_MODEL_BASE 0
SDRAM_DATA_WIDTH 16
SDRAM_ADDR_WIDTH 22
SDRAM_ROW_WIDTH 12
SDRAM_COL_WIDTH 8
SDRAM_NUM_CHIPSELECTS 1
SDRAM_NUM_BANKS 4
REFRESH_PERIOD 15.625
POWERUP_DELAY 100.0
CAS_LATENCY 3
T_RFC 70.0
T_RP 20.0
T_MRD 3
T_RCD 20.0
T_AC 5.5
T_WR 14.0
INIT_REFRESH_COMMANDS 2
INIT_NOP_DELAY 0.0
SHARED_DATA 0
STARVATION_INDICATOR 0
TRISTATE_BRIDGE_SLAVE ""
IS_INITIALIZED 1
SDRAM_BANK_WIDTH 2
CONTENTS_INFO ""

sram_0

altera_up_avalon_sram v12.0
clk_0 clk_reset   sram_0
  clock_reset_reset
nios2_qsys_0 jtag_debug_module_reset  
  clock_reset_reset
data_master  
  avalon_sram_slave
instruction_master  
  avalon_sram_slave
altpll_0 c1  
  clock_reset


Parameters

board DE2
pixel_buffer false
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY CYCLONEII
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

timer_0

altera_avalon_timer v12.1
clk_0 clk_reset   timer_0
  reset
altpll_0 c1  
  clk
nios2_qsys_0 data_master  
  s1
jtag_debug_module_reset  
  reset
d_irq  
  irq


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 50000000
timeoutPulseOutput false
timerPreset CUSTOM
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 1
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 50000000u
LOAD_VALUE 49999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 1000u

frequencyDivider_0

frequencyDivider v1.0
altpll_0 c1   frequencyDivider_0
  clock_in
clock_out   midiOut_0
  clk_midi


Parameters

AUTO_CLOCK_IN_CLOCK_RATE 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

midiOut_0

midiOut v1.0
altpll_0 c1   midiOut_0
  clock
frequencyDivider_0 clock_out  
  clk_midi
clk_0 clk_reset  
  reset_n
nios2_qsys_0 jtag_debug_module_reset  
  reset_n
data_master  
  s0


Parameters

AUTO_CLOCK_CLOCK_RATE 50000000
AUTO_CLK_MIDI_CLOCK_RATE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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