----------------------------------------------------------
-- PWM_top
-- Robert Hood
-- Maps the PWM core to the input and output pads
----------------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY sorting_network_top IS
  port (
        padcsi_myclock_clk,csi_myclock_reset, avs_pwm_write_navs_pwm_chipselect : IN  STD_LOGIC;
        padavs_pwm_address     : IN  STD_LOGIC_VECTOR(1 downto 0);
	padavs_pwm_readdata    : IN STD_LOGIC_VECTOR(15 downto 0);
	padavs_pwm_writedata   : OUT STD_LOGIC_VECTOR(15 downto 0);
	padcoe_pwm_output_export: OUT STD_LOGIC
	);
END sorting_network_top;

ARCHITECTURE Structure of sorting_network_top IS 

component pwm is

port(
     
     csi_myclock_clk 	   : in std_logic; --clk is standard for both PWM and Avalon memory slave   

     csi_myclock_reset	   : in std_logic; --clk reset 
     avs_pwm_write_n 	   : in std_logic; --write
     avs_pwm_chipselect	   : in std_logic; -- chip select

     avs_pwm_address 	   : in std_logic_vector(1 downto 0); --address

     avs_pwm_readdata 	   : out std_logic_vector(15 downto 0); --Needed for the Avalon interface

     avs_pwm_writedata 	   : in std_logic_vector(15 downto 0); -- Data to be input represents the duty cycle
     coe_pwm_output_export : out std_logic-- Ouput either 1 (high) or 0 (low)	
		
);
end component;

component PDO12CDG 
  port(A     : in  std_logic;
       PAD   : out std_logic);
end component;

component PDUDGZ 
  port(Y     : out  std_logic;
       PAD   : in   std_logic);
end component;

signal  clk,reset,write_n,chipselect,output  : STD_LOGIC;
signal  address                              :STD_LOGIC_VECTOR(1 downto 0); 
signal  readdata,writedata                   : STD_LOGIC_VECTOR(15 downto 0);


--for all : PDUDGZ use entity Work.PDUDGZ(inpad_arc);
--for all : PDO12CDG use entity Work.PDO12CDG(outpad_arc);

begin

-- Input clk pad mapping
  padcsi_myclock_clkGen: for i in 0 downto 0 generate
    begin
        inpclk: PDUDGZ port map (Y => clk(i), PAD => padclk(i));
    
  end generate;

-- Input reset pad mapping
  padcsi_myclock_resetGen: for i in 0 downto 0 generate
    begin
        inpreset: PDUDGZ port map (Y => reset(i), PAD => padreset(i));

  end generate;
-- Input write_n pad mapping
  padavs_pwm_write_nGen: for i in 0 downto 0 generate
    begin
        inpwrite_n: PDUDGZ port map (Y => write_n(i), PAD => padwrite_n(i));
    
  end generate;

-- Input chipselect pad mapping
  padDGen: for i in 0 downto 0 generate
    begin
        inpchipselect: PDUDGZ port map (Y => chipselect(i), PAD => padchipselect(i));
    
  end generate;
  
-- Input Adress pad mapping
  padDGen: for i in 1 downto 0 generate
    begin
        inpaddress: PDUDGZ port map (Y => address(i), PAD => padaddress(i));
    
  end generate;
-- Input writedata pad mapping
  padDGen: for i in 15 downto 0 generate
    begin
        inpwritedata: PDUDGZ port map (Y => writedata(i), PAD => padwritedata(i));
    
  end generate;

-- Output output pad mapping
  padP1Gen: for i in 0 downto 0 generate
    begin
       opoutput: PDO12CDG port map (PAD => padoutput(i), A => output(i));
    
  end generate;

-- Output readdata pad mapping
  padP2Gen: for i in 15 downto 0 generate
    begin
        opreaddata: PDO12CDG port map (PAD => padreaddata(i), A => readdata(i));
    
  end generate;

-- Misc pad mapping
  padClkG: 	PDUDGZ port map (Y => Clk, PAD => padClk);
  coreG:        sorting_network port map (Clk => csi_myclock_clk, write_n => avs_pwm_write_n , reset =>  csi_myclock_reset, chipselect => avs_pwm_chipselect, 
					address => avs_pwm_address,readdata => avs_pwm_readdata, writedata => avs_pwm_writedata, output => coe_pwm_output_export);
END Structure;