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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:53:12 03/20/2010 
-- Design Name: 
-- Module Name:    pw_input - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pw_input is
	generic
	(
		PULSEWIDTH_PERIOD : integer := 2000000
	);
	port
	(
		clk	: in std_logic;
		input : in std_logic;
		rst	: in std_logic;
		pw 	: out std_logic_vector(0 to 31)
	);	
			
end pw_input;

architecture Behavioral of pw_input is

	signal cnt : std_logic_vector(0 to 31); --TODO: make this generic

begin

count_pw: process(clk,input,rst)
begin
	if(rst = '1') then
		cnt <= (others => '0');
	else
		if( clk'event and clk = '1' ) then
			if ( input = '1' ) then
				cnt <= cnt + 1;
			else
				cnt <= (others => '0');
			end if;
		end if;	
	end if;	
	
end process count_pw;

do_out: process(input,rst)
begin
	if(rst = '1') then
		pw <= (others => '0');
	else
		if(input'event and input = '0' ) then 
			pw <= cnt;
		end if;
	end if;	
end process do_out;


end Behavioral;