############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################

#Net sys_clk_pin LOC=B15;
Net sys_clk_pin LOC=AJ15;
Net sys_clk_pin IOSTANDARD = LVCMOS33;
#Net sys_rst_pin LOC=E16;
Net sys_rst_pin LOC=G25;
Net sys_rst_pin PULLUP;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
Net sys_rst_pin TIG;

## IO Devices constraints

#### Module ORGate_1 constraints

Net fpga_0_ORGate_1_Res_pin LOC=K4;
Net fpga_0_ORGate_1_Res_pin IOSTANDARD = PCI33_3;
Net fpga_0_ORGate_1_Res_pin TIG;
Net fpga_0_ORGate_1_Res_1_pin LOC=M1;
Net fpga_0_ORGate_1_Res_1_pin IOSTANDARD = PCI33_3;
Net fpga_0_ORGate_1_Res_1_pin TIG;
Net fpga_0_ORGate_1_Res_2_pin LOC=N8;
Net fpga_0_ORGate_1_Res_2_pin IOSTANDARD = PCI33_3;


Net pwm_io_0_AP_input_pin<0>  LOC = T8  ; # IO_45
#Net pwm_io_0_AP_input_pin<0>  IOSTANDARD = PCI33_3; # IO_45 we can actually put this to 3.3v I think
Net pwm_io_0_AP_input_pin<1>  LOC = U5  ; # IO_47
Net pwm_io_0_AP_input_pin<2>  LOC = W2  ; # IO_49
Net pwm_io_0_AP_input_pin<3>  LOC = U9  ; # IO_51
Net pwm_io_0_AP_input_pin<4>  LOC = V4  ; # IO_53
Net pwm_io_0_AP_input_pin<5>  LOC = Y1  ; # IO_55
Net pwm_io_0_AP_input_pin<6>  LOC = U8  ; # IO_57
Net pwm_io_0_output_pin<0>  LOC = N5  ;	 # IO_9
Net pwm_io_0_output_pin<0>  IOSTANDARD = PCI33_3;
Net pwm_io_0_output_pin<1>  LOC = L4  ;	 # IO_11
Net pwm_io_0_output_pin<1>  IOSTANDARD = PCI33_3;
Net pwm_io_0_output_pin<2>  LOC = N2  ;	 # IO_13
Net pwm_io_0_output_pin<2>  IOSTANDARD = PCI33_3;
Net pwm_io_0_output_pin<3>  LOC = R9  ;	 # IO_15
Net pwm_io_0_output_pin<3>  IOSTANDARD = PCI33_3;
Net pwm_io_0_output_pin<4>  LOC = M3  ;	 # IO_17
Net pwm_io_0_output_pin<4>  IOSTANDARD = PCI33_3;
Net pwm_io_0_output_pin<5>  LOC = P1  ;	 # IO_19
Net pwm_io_0_output_pin<5>  IOSTANDARD = PCI33_3;
Net pwm_io_0_output_pin<6>  LOC = P7  ;	 # IO_21
Net pwm_io_0_output_pin<6>  IOSTANDARD = PCI33_3;
Net pwm_io_0_RC_input_pin<0>  LOC = V2  ; # IO_48
Net pwm_io_0_RC_input_pin<1>  LOC = T9  ; # IO_50
Net pwm_io_0_RC_input_pin<2>  LOC = V3  ; # IO_52
Net pwm_io_0_RC_input_pin<3>  LOC = W1  ; # IO_54
Net pwm_io_0_RC_input_pin<4>  LOC = U7  ; # IO_56
Net pwm_io_0_RC_input_pin<5>  LOC = V5  ; # IO_58
Net pwm_io_0_RC_input_pin<6>  LOC = Y2  ; # IO_60