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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:44:26 03/03/2010 
-- Design Name: 
-- Module Name:    unglitched_input - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity unglitched_input is
	generic( sample : natural := 3);
    Port ( input : in  STD_LOGIC;
			  clk 	: in  STD_LOGIC;
           output : out  STD_LOGIC);
end unglitched_input;



architecture Behavioral of unglitched_input is


--signal past_values: std_logic_vector(sample-1 downto 0);


signal state: std_logic;
signal cnt : integer :=0 ;


begin

-- should we change on input here?
main: process(clk) is
	
begin
	if( clk'event and clk = '1' ) then
		if (state = input) then
			if(cnt = sample-1) then
				state <= input;
			end if;
			cnt <= 0;
		else
			cnt <= cnt+1;
		end if;
	end if;	
end process main;


output_choose: process(state)
begin
	output <= state;	
end process output_choose;


end Behavioral;