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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:08:59 03/04/2010 
-- Design Name: 
-- Module Name:    top_level - Structural 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top_level is

    Port (
			  clk : in std_logic;
			  rst : in std_logic;
			  RC_switch : in std_logic;
--			  AP_switch : in std_logic;
			  RC_health : in std_logic;
--			  AP_health : in std_logic;
			  RC_input : in  STD_LOGIC_VECTOR(6 downto 0);
           AP_input : in  STD_LOGIC_VECTOR(6 downto 0);
			  output : out  STD_LOGIC_VECTOR(6 downto 0)
			  );
			  
end top_level;

architecture Structural of top_level is



component failsafe_unit is

	Generic (	AP_input_size: natural := 7;
					RC_input_size: natural := 7;
					output_size: natural := 7
				 );
    Port (
			  clk : in std_logic;
			  rst : in std_logic;
			  RC_switch : in std_logic;
--			  AP_switch : in std_logic;
			  RC_health : in std_logic;
--			  AP_health : in std_logic;
			  RC_input : in  STD_LOGIC_VECTOR(6 downto 0);
           AP_input : in  STD_LOGIC_VECTOR(6 downto 0);
			  output : out  STD_LOGIC_VECTOR(6 downto 0)
			  );
end component;

begin

c1:	failsafe_unit port map(clk, rst, RC_switch, RC_health, RC_input, AP_input, output);


end Structural;