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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:52:22 04/07/2010 
-- Design Name: 
-- Module Name:    signal_high_detect - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity signal_high_detect is
	generic(    count_len : natural := 32; --enough for 42 sec on a 100mhz clk
					len : natural := 5--100000000 --1s,
	);
		
    Port ( input : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           output : out  STD_LOGIC);
end signal_high_detect;

architecture Behavioral of signal_high_detect is

signal cnt : std_logic_vector(count_len-1 downto 0);

begin

do_count: process(clk,input)
begin 
--	if( input'event and input = '1' ) then
--		cnt <= (others => '0');
--	else
--		if( input'event and input = '0' ) then
--			cnt <= (others => '0');
--		else
--			if( clk'event and clk = '1' ) then
--				if(cnt <  len) then
--					cnt <= cnt + 1;
--				end if;	
--			end if;
--		end if;	
--	end if;
	if(input = '0') then
		cnt <= (others => '0');
	else
		if( clk'event and clk = '1' ) then
			if(cnt <  len) then
				cnt <= cnt + 1;
			end if;	
		end if;	
	end if;		
end process;

do_out: process(cnt)
begin
	if(cnt < len) then
		output <= '0';
	else
		output <= '1';
	end if;
	
end process;

end Behavioral;