----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:47:24 04/06/2010 
-- Design Name: 
-- Module Name:    los_detecter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity los_detecter is
	generic( los_check_len : natural := 2000 --3;--195000, --15ms to 20ms
	 );
		
    Port ( input : in  STD_LOGIC;
			  clk : in  STD_LOGIC;
           output : out  STD_LOGIC);
end los_detecter;

architecture structural of los_detecter is


component rising_edge_bound is
--		generic( los_check_len : natural := 5;
--					lower_bound : natural := 1500000; --3;--195000, --15ms to 25ms
--					upper_bound : natural := 3500000 --6 --215000,
--		);
		
    Port ( input : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           output : out  STD_LOGIC);
end component;

--component signal_high_detect is
--	generic(    count_len : natural := 32; --enough for 42 sec on a 100mhz clk
--					len : natural := 100000 --2000000--2 --.002s
--					);
--		
--    Port ( input : in  STD_LOGIC;
--           clk : in  STD_LOGIC;
--           output : out  STD_LOGIC);
--end component;

signal s1: std_logic;


begin

c1:	rising_edge_bound port map (input => input, clk => clk, output => s1);

output <= s1;
--c2:	signal_high_detect port map (input => s1, clk => clk, output => output);

end structural;