# TCL File Generated by Component Editor 10.1sp1
# Thu Feb 21 14:12:57 MST 2013
# DO NOT MODIFY


# +-----------------------------------
# | 
# | isp1362 "ISP1362" v1.0.1
# | null 2013.02.21.14:12:57
# | 
# | 
# | /afs/ualberta.ca/home/e/j/ejong/ece492/DE2_SD_Card_Audio/ISP1362/hdl/ISP1362_IF.v
# | 
# |    ./hdl/ISP1362_IF.v syn, sim
# | 
# +-----------------------------------

# +-----------------------------------
# | request TCL package from ACDS 10.1
# | 
package require -exact sopc 10.1
# | 
# +-----------------------------------

# +-----------------------------------
# | module isp1362
# | 
set_module_property NAME isp1362
set_module_property VERSION 1.0.1
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Terasic Technologies Inc"
set_module_property DISPLAY_NAME ISP1362
set_module_property TOP_LEVEL_HDL_FILE hdl/ISP1362_IF.v
set_module_property TOP_LEVEL_HDL_MODULE ISP1362_IF
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE false
set_module_property ANALYZE_HDL TRUE
# | 
# +-----------------------------------

# +-----------------------------------
# | files
# | 
add_file hdl/ISP1362_IF.v {SYNTHESIS SIMULATION}
# | 
# +-----------------------------------

# +-----------------------------------
# | parameters
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | display items
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point clk
# | 
add_interface clk clock end
set_interface_property clk clockRate 0

set_interface_property clk ENABLED true

add_interface_port clk iCLK clk Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point avalon_slave_0_export
# | 
add_interface avalon_slave_0_export conduit end

set_interface_property avalon_slave_0_export ENABLED true

add_interface_port avalon_slave_0_export OTG_DATA export Bidir 16
add_interface_port avalon_slave_0_export OTG_ADDR export Output 2
add_interface_port avalon_slave_0_export OTG_RD_N export Output 1
add_interface_port avalon_slave_0_export OTG_WR_N export Output 1
add_interface_port avalon_slave_0_export OTG_CS_N export Output 1
add_interface_port avalon_slave_0_export OTG_RST_N export Output 1
add_interface_port avalon_slave_0_export OTG_INT0 export Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point avalon_slave_0
# | 
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressAlignment NATIVE
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clk
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 explicitAddressSpan 4
set_interface_property avalon_slave_0 holdTime 100
set_interface_property avalon_slave_0 isMemoryDevice false
set_interface_property avalon_slave_0 isNonVolatileStorage false
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 printableDevice false
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitStates 100
set_interface_property avalon_slave_0 readWaitTime 100
set_interface_property avalon_slave_0 setupTime 100
set_interface_property avalon_slave_0 timingUnits Nanoseconds
set_interface_property avalon_slave_0 writeWaitStates 100
set_interface_property avalon_slave_0 writeWaitTime 100

set_interface_property avalon_slave_0 ENABLED true

add_interface_port avalon_slave_0 iDATA writedata Input 16
add_interface_port avalon_slave_0 iADDR address Input 2
add_interface_port avalon_slave_0 iRD_N read_n Input 1
add_interface_port avalon_slave_0 iWR_N write_n Input 1
add_interface_port avalon_slave_0 iCS_N chipselect_n Input 1
add_interface_port avalon_slave_0 oDATA readdata Output 16
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point avalon_slave_0_irq
# | 
add_interface avalon_slave_0_irq interrupt end
set_interface_property avalon_slave_0_irq associatedAddressablePoint avalon_slave_0
set_interface_property avalon_slave_0_irq associatedClock clk

set_interface_property avalon_slave_0_irq ENABLED true

add_interface_port avalon_slave_0_irq oINT0_N irq_n Output 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point conduit_end
# | 
add_interface conduit_end conduit end

set_interface_property conduit_end ENABLED true

# | 
# +-----------------------------------
