# TCL File Generated by Component Editor 10.1sp1
# Fri Mar 22 13:17:53 MDT 2013
# DO NOT MODIFY


# +-----------------------------------
# | 
# | opencores_i2c_master "OpenCores I2C Master" v1.0
# | null 2013.03.22.13:17:53
# | 
# | 
# | /afs/ualberta.ca/home/t/a/tadavis/ECE492/Project/Source_Code/ip/altera_avalon_opencores_i2c/opencores_i2c_master.vhd
# | 
# |    ./opencores_i2c_master.vhd syn
# |    ./i2c_master_top.vhd syn
# |    ./i2c_master_byte_ctrl.vhd syn
# |    ./i2c_master_bit_ctrl.vhd syn
# | 
# +-----------------------------------

# +-----------------------------------
# | request TCL package from ACDS 10.1
# | 
package require -exact sopc 10.1
# | 
# +-----------------------------------

# +-----------------------------------
# | module opencores_i2c_master
# | 
set_module_property DESCRIPTION ""
set_module_property NAME opencores_i2c_master
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Interface Protocols/I2C"
set_module_property DISPLAY_NAME "OpenCores I2C Master"
set_module_property TOP_LEVEL_HDL_FILE opencores_i2c_master.vhd
set_module_property TOP_LEVEL_HDL_MODULE opencores_i2c_master
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
# | 
# +-----------------------------------

# +-----------------------------------
# | files
# | 
add_file opencores_i2c_master.vhd SYNTHESIS
add_file i2c_master_top.vhd SYNTHESIS
add_file i2c_master_byte_ctrl.vhd SYNTHESIS
add_file i2c_master_bit_ctrl.vhd SYNTHESIS
# | 
# +-----------------------------------

# +-----------------------------------
# | parameters
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | display items
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point avalon_slave_0_clock
# | 
add_interface avalon_slave_0_clock clock end
set_interface_property avalon_slave_0_clock clockRate 0

set_interface_property avalon_slave_0_clock ENABLED true

add_interface_port avalon_slave_0_clock wb_clk_i clk Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point avalon_slave_0_clock_reset
# | 
add_interface avalon_slave_0_clock_reset reset end
set_interface_property avalon_slave_0_clock_reset associatedClock avalon_slave_0_clock
set_interface_property avalon_slave_0_clock_reset synchronousEdges DEASSERT

set_interface_property avalon_slave_0_clock_reset ENABLED true

add_interface_port avalon_slave_0_clock_reset wb_rst_i reset Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point global_signals_export
# | 
add_interface global_signals_export conduit end

set_interface_property global_signals_export ENABLED true

add_interface_port global_signals_export scl_pad_io export Output 1
add_interface_port global_signals_export sda_pad_io export Bidir 1
add_interface_port global_signals_export sda_padoen_out export Output 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point avalon_slave_0
# | 
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressAlignment DYNAMIC
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock avalon_slave_0_clock
set_interface_property avalon_slave_0 associatedReset avalon_slave_0_clock_reset
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 isMemoryDevice true
set_interface_property avalon_slave_0 isNonVolatileStorage false
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 printableDevice false
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitStates 0
set_interface_property avalon_slave_0 readWaitTime 0
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitTime 0

set_interface_property avalon_slave_0 ENABLED true

add_interface_port avalon_slave_0 wb_ack_o waitrequest_n Output 1
add_interface_port avalon_slave_0 wb_adr_i address Input 3
add_interface_port avalon_slave_0 wb_cs_i chipselect Input 1
add_interface_port avalon_slave_0 wb_dat_i writedata Input 32
add_interface_port avalon_slave_0 wb_dat_o readdata Output 32
add_interface_port avalon_slave_0 wb_we_i write Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point avalon_slave_0_irq
# | 
add_interface avalon_slave_0_irq interrupt end
set_interface_property avalon_slave_0_irq associatedAddressablePoint avalon_slave_0
set_interface_property avalon_slave_0_irq associatedClock avalon_slave_0_clock
set_interface_property avalon_slave_0_irq associatedReset avalon_slave_0_clock_reset

set_interface_property avalon_slave_0_irq ENABLED true

add_interface_port avalon_slave_0_irq wb_inta_o irq Output 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point avalon_slave_0_export
# | 
add_interface avalon_slave_0_export conduit end

set_interface_property avalon_slave_0_export ENABLED true

add_interface_port avalon_slave_0_export wb_err_o export Output 1
# | 
# +-----------------------------------
