Analysis & Synthesis report for DE2_Board
Thu Nov 17 16:23:50 2005
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Registers Protected by SYN_PRESERVE, DONT_TOUCH
  9. General Register Statistics
 10. Inverted Register Statistics
 11. Multiplexer Restructuring Statistics (Restructuring Performed)
 12. Source assignments for DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated
 13. Source assignments for DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated
 14. Source assignments for DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated
 15. Source assignments for DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2
 16. Source assignments for DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3
 17. Source assignments for DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2
 18. Source assignments for DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3
 19. Source assignments for DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated
 20. Source assignments for DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave
 21. Source assignments for DE2_Board:inst|DE2_Board_reset_clk_domain_synch_module:DE2_Board_reset_clk_domain_synch
 22. Parameter Settings for User Entity Instance: DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf
 23. Parameter Settings for User Entity Instance: DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram
 24. Parameter Settings for User Entity Instance: DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram
 25. Parameter Settings for User Entity Instance: DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram
 26. Parameter Settings for User Entity Instance: DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo
 27. Parameter Settings for User Entity Instance: DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo
 28. Parameter Settings for User Entity Instance: DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic
 29. Parameter Settings for User Entity Instance: DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram
 30. Parameter Settings for User Entity Instance: delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component
 31. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 32. scfifo Parameter Settings by Entity Instance
 33. Analysis & Synthesis Equations
 34. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Thu Nov 17 16:23:49 2005    ;
; Quartus II Version                 ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name                      ; DE2_Board                                ;
; Top-level Entity Name              ; DE2_Board_top                            ;
; Family                             ; Cyclone II                               ;
; Total combinational functions      ; 1419                                     ;
; Total registers                    ; 812                                      ;
; Total pins                         ; 40                                       ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 177,152                                  ;
; Embedded Multiplier 9-bit elements ; 0                                        ;
; Total PLLs                         ; 0                                        ;
+------------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C35F672C6       ;                    ;
; Top-level entity name                                              ; DE2_Board_top      ; DE2_Board          ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; -1                 ; -1                 ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone II                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; -1                 ; -1                 ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                        ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                        ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; DE2_Board_top.bdf                ; yes             ; User Block Diagram/Schematic File  ; C:/DE2/DE2_Board/system/DE2_Board_top.bdf                           ;
; DE2_Board.v                      ; yes             ; Other                              ; C:/DE2/DE2_Board/system/DE2_Board.v                                 ;
; asmi.v                           ; yes             ; Other                              ; C:/DE2/DE2_Board/system/asmi.v                                      ;
; cpu_0.v                          ; yes             ; Encrypted File                     ; C:/DE2/DE2_Board/system/cpu_0.v                                     ;
; cpu_0_test_bench.v               ; yes             ; Other                              ; C:/DE2/DE2_Board/system/cpu_0_test_bench.v                          ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf          ;
; stratix_ram_block.inc            ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/stratix_ram_block.inc   ;
; lpm_mux.inc                      ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/lpm_mux.inc             ;
; lpm_decode.inc                   ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/lpm_decode.inc          ;
; aglobal51.inc                    ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/aglobal51.inc           ;
; altsyncram.inc                   ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/altsyncram.inc          ;
; a_rdenreg.inc                    ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_rdenreg.inc           ;
; altrom.inc                       ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/altrom.inc              ;
; altram.inc                       ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/altram.inc              ;
; altdpram.inc                     ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/altdpram.inc            ;
; altqpram.inc                     ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/altqpram.inc            ;
; db/altsyncram_r0r1.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/altsyncram_r0r1.tdf                      ;
; data_RAM.v                       ; yes             ; Other                              ; C:/DE2/DE2_Board/system/data_RAM.v                                  ;
; db/altsyncram_8c21.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/altsyncram_8c21.tdf                      ;
; firmware_ROM.v                   ; yes             ; Other                              ; C:/DE2/DE2_Board/system/firmware_ROM.v                              ;
; db/altsyncram_cs21.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/altsyncram_cs21.tdf                      ;
; jtag_uart_0.v                    ; yes             ; Other                              ; C:/DE2/DE2_Board/system/jtag_uart_0.v                               ;
; scfifo.tdf                       ; yes             ; Megafunction                       ; c:/altera/quartus51/libraries/megafunctions/scfifo.tdf              ;
; a_regfifo.inc                    ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_regfifo.inc           ;
; a_dpfifo.inc                     ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_dpfifo.inc            ;
; a_i2fifo.inc                     ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_i2fifo.inc            ;
; a_fffifo.inc                     ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_fffifo.inc            ;
; a_f2fifo.inc                     ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_f2fifo.inc            ;
; db/scfifo_46p.tdf                ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/scfifo_46p.tdf                           ;
; db/a_dpfifo_bcp.tdf              ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/a_dpfifo_bcp.tdf                         ;
; db/a_fefifo_odf.tdf              ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/a_fefifo_odf.tdf                         ;
; db/cntr_uj7.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/cntr_uj7.tdf                             ;
; db/dpram_scp.tdf                 ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/dpram_scp.tdf                            ;
; db/altsyncram_3pc1.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/altsyncram_3pc1.tdf                      ;
; db/altsyncram_0431.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/altsyncram_0431.tdf                      ;
; db/cntr_gl8.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/cntr_gl8.tdf                             ;
; alt_jtag_atlantic.v              ; yes             ; Encrypted Megafunction             ; c:/altera/quartus51/libraries/megafunctions/alt_jtag_atlantic.v     ;
; payload_buffer.v                 ; yes             ; Other                              ; C:/DE2/DE2_Board/system/payload_buffer.v                            ;
; db/altsyncram_l331.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/altsyncram_l331.tdf                      ;
; db/decode_1oa.tdf                ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/decode_1oa.tdf                           ;
; db/mux_0kb.tdf                   ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/mux_0kb.tdf                              ;
; sysid.v                          ; yes             ; Other                              ; C:/DE2/DE2_Board/system/sysid.v                                     ;
; delay_reset_block.bdf            ; yes             ; Other                              ; C:/DE2/DE2_Board/system/delay_reset_block.bdf                       ;
; reset_counter.v                  ; yes             ; Other                              ; C:/DE2/DE2_Board/system/reset_counter.v                             ;
; lpm_counter.tdf                  ; yes             ; Megafunction                       ; c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                 ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/lpm_constant.inc        ;
; lpm_add_sub.inc                  ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/alt_counter_stratix.inc ;
; db/cntr_8bc.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/cntr_8bc.tdf                             ;
; sld_hub.vhd                      ; yes             ; Encrypted Megafunction             ; c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd             ;
; lpm_shiftreg.tdf                 ; yes             ; Megafunction                       ; c:/altera/quartus51/libraries/megafunctions/lpm_shiftreg.tdf        ;
; lpm_decode.tdf                   ; yes             ; Megafunction                       ; c:/altera/quartus51/libraries/megafunctions/lpm_decode.tdf          ;
; declut.inc                       ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/declut.inc              ;
; altshift.inc                     ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/altshift.inc            ;
; db/decode_rpe.tdf                ; yes             ; Auto-Generated Megafunction        ; C:/DE2/DE2_Board/system/db/decode_rpe.tdf                           ;
; sld_dffex.vhd                    ; yes             ; Encrypted Megafunction             ; c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd           ;
; sld_rom_sr.vhd                   ; yes             ; Encrypted Megafunction             ; c:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd          ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+


+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary            ;
+---------------------------------------------+----------+
; Resource                                    ; Usage    ;
+---------------------------------------------+----------+
; Total combinational functions               ; 1419     ;
; Logic element usage by number of LUT inputs ;          ;
;     -- 4 input functions                    ; 703      ;
;     -- 3 input functions                    ; 494      ;
;     -- <=2 input functions                  ; 222      ;
;         -- Combinational cells for routing  ; 0        ;
; Logic elements by mode                      ;          ;
;     -- normal mode                          ; 1246     ;
;     -- arithmetic mode                      ; 173      ;
; Total registers                             ; 812      ;
; I/O pins                                    ; 36       ;
; Total memory bits                           ; 177152   ;
; Maximum fan-out node                        ; CLOCK_50 ;
; Maximum fan-out                             ; 859      ;
; Total fan-out                               ; 10018    ;
; Average fan-out                             ; 4.14     ;
+---------------------------------------------+----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                               ;
+----------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                                                             ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                          ;
+----------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |DE2_Board_top                                                                         ; 1419 (52)         ; 812 (0)      ; 177152      ; 0            ; 0       ; 0         ; 36   ; 0            ; |DE2_Board_top                                                                                                                                                                                                                               ;
;    |DE2_Board:inst|                                                                    ; 1279 (0)          ; 741 (0)      ; 177152      ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst                                                                                                                                                                                                                ;
;       |DE2_Board_reset_clk_domain_synch_module:DE2_Board_reset_clk_domain_synch|       ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|DE2_Board_reset_clk_domain_synch_module:DE2_Board_reset_clk_domain_synch                                                                                                                                       ;
;       |asmi:the_asmi|                                                                  ; 102 (0)           ; 115 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|asmi:the_asmi                                                                                                                                                                                                  ;
;          |asmi_sub:the_asmi_sub|                                                       ; 102 (102)         ; 115 (115)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub                                                                                                                                                                            ;
;          |tornado_asmi_atom:the_tornado_asmi_atom|                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|asmi:the_asmi|tornado_asmi_atom:the_tornado_asmi_atom                                                                                                                                                          ;
;       |asmi_asmi_control_port_arbitrator:the_asmi_asmi_control_port|                   ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|asmi_asmi_control_port_arbitrator:the_asmi_asmi_control_port                                                                                                                                                   ;
;       |cpu_0:the_cpu_0|                                                                ; 647 (647)         ; 309 (308)    ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0                                                                                                                                                                                                ;
;          |cpu_0_rf_module:cpu_0_rf|                                                    ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf                                                                                                                                                                       ;
;             |altsyncram:the_altsyncram|                                                ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram                                                                                                                                             ;
;                |altsyncram_r0r1:auto_generated|                                        ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated                                                                                                              ;
;          |cpu_0_test_bench:the_cpu_0_test_bench|                                       ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench                                                                                                                                                          ;
;       |cpu_0_data_master_arbitrator:the_cpu_0_data_master|                             ; 150 (150)         ; 70 (70)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master                                                                                                                                                             ;
;       |cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|               ; 12 (12)           ; 42 (42)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master                                                                                                                                               ;
;       |data_RAM:the_data_RAM|                                                          ; 1 (1)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|data_RAM:the_data_RAM                                                                                                                                                                                          ;
;          |altsyncram:the_altsyncram|                                                   ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram                                                                                                                                                                ;
;             |altsyncram_8c21:auto_generated|                                           ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated                                                                                                                                 ;
;       |data_RAM_s1_arbitrator:the_data_RAM_s1|                                         ; 23 (23)           ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1                                                                                                                                                                         ;
;       |firmware_ROM:the_firmware_ROM|                                                  ; 0 (0)             ; 0 (0)        ; 28672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|firmware_ROM:the_firmware_ROM                                                                                                                                                                                  ;
;          |altsyncram:the_altsyncram|                                                   ; 0 (0)             ; 0 (0)        ; 28672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram                                                                                                                                                        ;
;             |altsyncram_cs21:auto_generated|                                           ; 0 (0)             ; 0 (0)        ; 28672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated                                                                                                                         ;
;       |firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|                                 ; 29 (29)           ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1                                                                                                                                                                 ;
;       |jtag_uart_0:the_jtag_uart_0|                                                    ; 170 (52)          ; 124 (13)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0                                                                                                                                                                                    ;
;          |alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|                             ; 47 (47)           ; 53 (53)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic                                                                                                                                    ;
;          |jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|                               ; 36 (0)            ; 29 (0)       ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r                                                                                                                                      ;
;             |scfifo:rfifo|                                                             ; 36 (0)            ; 29 (0)       ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo                                                                                                                         ;
;                |scfifo_46p:auto_generated|                                             ; 36 (0)            ; 29 (0)       ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated                                                                                               ;
;                   |a_dpfifo_bcp:dpfifo|                                                ; 36 (0)            ; 29 (0)       ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo                                                                           ;
;                      |a_fefifo_odf:fifo_state|                                         ; 18 (9)            ; 11 (2)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state                                                   ;
;                         |cntr_uj7:count_usedw|                                         ; 9 (9)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw                              ;
;                      |cntr_gl8:rd_ptr_count|                                           ; 9 (9)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count                                                     ;
;                      |cntr_gl8:wr_ptr|                                                 ; 9 (9)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr                                                           ;
;                      |dpram_scp:FIFOram|                                               ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram                                                         ;
;                         |altsyncram_3pc1:altsyncram2|                                  ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2                             ;
;                            |altsyncram_0431:altsyncram3|                               ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3 ;
;          |jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|                               ; 35 (0)            ; 29 (0)       ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w                                                                                                                                      ;
;             |scfifo:wfifo|                                                             ; 35 (0)            ; 29 (0)       ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo                                                                                                                         ;
;                |scfifo_46p:auto_generated|                                             ; 35 (0)            ; 29 (0)       ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated                                                                                               ;
;                   |a_dpfifo_bcp:dpfifo|                                                ; 35 (0)            ; 29 (0)       ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo                                                                           ;
;                      |a_fefifo_odf:fifo_state|                                         ; 17 (8)            ; 11 (2)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state                                                   ;
;                         |cntr_uj7:count_usedw|                                         ; 9 (9)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw                              ;
;                      |cntr_gl8:rd_ptr_count|                                           ; 9 (9)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count                                                     ;
;                      |cntr_gl8:wr_ptr|                                                 ; 9 (9)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr                                                           ;
;                      |dpram_scp:FIFOram|                                               ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram                                                         ;
;                         |altsyncram_3pc1:altsyncram2|                                  ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2                             ;
;                            |altsyncram_0431:altsyncram3|                               ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3 ;
;       |jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|     ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave                                                                                                                                     ;
;       |payload_buffer:the_payload_buffer|                                              ; 18 (0)            ; 1 (0)        ; 131072      ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|payload_buffer:the_payload_buffer                                                                                                                                                                              ;
;          |altsyncram:the_altsyncram|                                                   ; 18 (0)            ; 1 (0)        ; 131072      ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram                                                                                                                                                    ;
;             |altsyncram_l331:auto_generated|                                           ; 18 (0)            ; 1 (1)        ; 131072      ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated                                                                                                                     ;
;                |decode_1oa:decode3|                                                    ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|decode_1oa:decode3                                                                                                  ;
;                |mux_0kb:mux2|                                                          ; 16 (16)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2                                                                                                        ;
;       |payload_buffer_s1_arbitrator:the_payload_buffer_s1|                             ; 49 (49)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1                                                                                                                                                             ;
;       |sysid_control_slave_arbitrator:the_sysid_control_slave|                         ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|sysid_control_slave_arbitrator:the_sysid_control_slave                                                                                                                                                         ;
;       |tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave| ; 75 (75)           ; 61 (61)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave                                                                                                                                 ;
;    |delay_reset_block:inst3|                                                           ; 12 (1)            ; 10 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|delay_reset_block:inst3                                                                                                                                                                                                       ;
;       |reset_counter:inst|                                                             ; 11 (0)            ; 10 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|delay_reset_block:inst3|reset_counter:inst                                                                                                                                                                                    ;
;          |lpm_counter:lpm_counter_component|                                           ; 11 (0)            ; 10 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component                                                                                                                                                  ;
;             |cntr_8bc:auto_generated|                                                  ; 11 (11)           ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated                                                                                                                          ;
;    |sld_hub:sld_hub_inst|                                                              ; 76 (26)           ; 61 (7)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|sld_hub:sld_hub_inst                                                                                                                                                                                                          ;
;       |lpm_decode:instruction_decoder|                                                 ; 5 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder                                                                                                                                                                           ;
;          |decode_rpe:auto_generated|                                                   ; 5 (5)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated                                                                                                                                                 ;
;       |lpm_shiftreg:jtag_ir_register|                                                  ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register                                                                                                                                                                            ;
;       |sld_dffex:BROADCAST|                                                            ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_dffex:BROADCAST                                                                                                                                                                                      ;
;       |sld_dffex:IRF_ENA_0|                                                            ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0                                                                                                                                                                                      ;
;       |sld_dffex:IRF_ENA|                                                              ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA                                                                                                                                                                                        ;
;       |sld_dffex:IRSR|                                                                 ; 1 (1)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_dffex:IRSR                                                                                                                                                                                           ;
;       |sld_dffex:RESET|                                                                ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_dffex:RESET                                                                                                                                                                                          ;
;       |sld_dffex:\GEN_IRF:1:IRF|                                                       ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF                                                                                                                                                                                 ;
;       |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|                                              ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF                                                                                                                                                                        ;
;       |sld_jtag_state_machine:jtag_state_machine|                                      ; 19 (19)           ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine                                                                                                                                                                ;
;       |sld_rom_sr:HUB_INFO_REG|                                                        ; 19 (19)           ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG                                                                                                                                                                                  ;
+----------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+--------------------+
; Name                                                                                                                                                                                                                                     ; Type ; Mode           ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF                ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+--------------------+
; DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|ALTSYNCRAM                                                                                                              ; AUTO ; True Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024   ; rf_ram.mif         ;
; DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|ALTSYNCRAM                                                                                                                                 ; M4K  ; Single Port    ; 256          ; 32           ; --           ; --           ; 8192   ; data_RAM.hex       ;
; DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|ALTSYNCRAM                                                                                                                         ; M4K  ; Single Port    ; 896          ; 32           ; --           ; --           ; 28672  ; firmware_ROM.hex   ;
; DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|ALTSYNCRAM ; AUTO ; True Dual Port ; 512          ; 8            ; 512          ; 8            ; 4096   ; None               ;
; DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|ALTSYNCRAM ; AUTO ; True Dual Port ; 512          ; 8            ; 512          ; 8            ; 4096   ; None               ;
; DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ALTSYNCRAM                                                                                                                     ; M4K  ; Single Port    ; 8192         ; 16           ; --           ; --           ; 131072 ; payload_buffer.hex ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by SYN_PRESERVE, DONT_TOUCH                                                                                                                             ;
+----------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------+
; Register Name                                                                                      ; Protected by SYN_PRESERVE ; Not to be Touched by Netlist Optimizations ;
+----------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------+
; DE2_Board:inst|DE2_Board_reset_clk_domain_synch_module:DE2_Board_reset_clk_domain_synch|data_out   ; yes                       ; yes                                        ;
; DE2_Board:inst|DE2_Board_reset_clk_domain_synch_module:DE2_Board_reset_clk_domain_synch|data_in_d1 ; yes                       ; yes                                        ;
+----------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 812   ;
; Number of registers using Synchronous Clear  ; 73    ;
; Number of registers using Synchronous Load   ; 139   ;
; Number of registers using Asynchronous Clear ; 721   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 397   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                          ;
+---------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                           ; Fan out ;
+---------------------------------------------------------------------------------------------------------------------------------------------+---------+
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|select_n_to_the_cfi_flash_0                   ; 1       ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn                      ; 1       ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|write_n_to_the_cfi_flash_0                    ; 1       ;
; DE2_Board:inst|cpu_0:the_cpu_0|i_read                                                                                                       ; 28      ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0] ; 5       ;
; sld_hub:sld_hub_inst|hub_tdo                                                                                                                ; 2       ;
; DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest                                             ; 15      ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle                           ; 8       ;
; DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|av_waitrequest                                                                                   ; 1       ;
; DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|t_dav                                                                                            ; 3       ;
; DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[9]                                         ; 11      ;
; DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[0]                                                                 ; 2       ;
; DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[0]                                                         ; 1       ;
; DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|stateZero                                                                                ; 1       ;
; Total number of inverted registers = 14                                                                                                     ;         ;
+---------------------------------------------------------------------------------------------------------------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3]                                                                                                                      ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data[2]                                                                                                            ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[6]                                                                                                            ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|E_src2[12]                                                                                                                     ;
; 3:1                ; 21 bits   ; 42 LEs        ; 42 LEs               ; 0 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|E_src1[20]                                                                                                                     ;
; 3:1                ; 11 bits   ; 22 LEs        ; 11 LEs               ; 11 LEs                 ; Yes        ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|E_src1[23]                                                                                                                     ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[7]                                                                                                          ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[21]                                                                                                                ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[27]                                                                                                                ;
; 4:1                ; 20 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|F_pc[19]                                                                                                                       ;
; 4:1                ; 23 bits   ; 46 LEs        ; 46 LEs               ; 0 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[5]                                                                                                                ;
; 4:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|E_src2[27]                                                                                                                     ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg[7]                                                                                               ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[0]                                  ;
; 5:1                ; 9 bits    ; 27 LEs        ; 27 LEs               ; 0 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[26]                                                                                                               ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|d_byteenable[2]                                                                                                                ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; Yes        ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]                                                                                                  ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[8]                                                                                             ;
; 5:1                ; 4 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[3]                                                                                             ;
; 5:1                ; 5 bits    ; 15 LEs        ; 10 LEs               ; 5 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[15]                                                                                            ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[0]                                                                                             ;
; 20:1               ; 4 bits    ; 52 LEs        ; 32 LEs               ; 20 LEs                 ; Yes        ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[2]                                                                                                       ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7]                          ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; No         ; |DE2_Board_top|DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter_next_value[1] ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; No         ; |DE2_Board_top|DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_arb_share_counter_next_value[2]                                           ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; No         ; |DE2_Board_top|DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_arb_share_counter_next_value[2]                                                 ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; No         ; |DE2_Board_top|DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_arb_share_counter_next_value[0]                                                             ;
; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; No         ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[5]                                                                                                              ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |DE2_Board_top|DE2_Board:inst|cpu_0:the_cpu_0|D_dst_regnum[3]                                                                                                                ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; No         ; |DE2_Board_top|DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~0                                                           ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; No         ; |DE2_Board_top|DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|add~0                                                                                       ;
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[6]                                                           ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[9]                                                        ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[5]                                                        ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; Yes        ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[4]                                                        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------+
; Assignment                      ; Value              ; from ; to                                                                        ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                         ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Source assignments for DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------+
; Assignment                      ; Value              ; from ; to                                                     ;
+---------------------------------+--------------------+------+--------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                      ;
+---------------------------------+--------------------+------+--------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------------+
; Assignment                      ; Value              ; from ; to                                                             ;
+---------------------------------+--------------------+------+----------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                              ;
+---------------------------------+--------------------+------+----------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; from ; to                                                                                                                                                         ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                          ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3 ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; from ; to                                                                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; from ; to                                                                                                                                                         ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                          ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3 ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; from ; to                                                                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------+
; Assignment                      ; Value              ; from ; to                                                                 ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                  ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Source assignments for DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave ;
+-----------------------------+-------+------+-------------------------------------------------------------------------+
; Assignment                  ; Value ; from ; to                                                                      ;
+-----------------------------+-------+------+-------------------------------------------------------------------------+
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[7]                                     ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[6]                                     ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[5]                                     ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[4]                                     ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[3]                                     ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[2]                                     ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[1]                                     ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[0]                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; select_n_to_the_cfi_flash_0                                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[21]                                          ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[20]                                          ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[19]                                          ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[18]                                          ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[17]                                          ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[16]                                          ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[15]                                          ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[14]                                          ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[13]                                          ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[12]                                          ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[11]                                          ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[10]                                          ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[9]                                           ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[8]                                           ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[7]                                           ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[6]                                           ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[5]                                           ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[4]                                           ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[3]                                           ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[2]                                           ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[1]                                           ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[0]                                           ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_readn                                                ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; write_n_to_the_cfi_flash_0                                              ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[7]~reg0                                ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[6]~reg0                                ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[5]~reg0                                ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[4]~reg0                                ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[3]~reg0                                ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[2]~reg0                                ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[1]~reg0                                ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[0]~reg0                                ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[7]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[6]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[5]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[4]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[3]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[2]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[1]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[0]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[21]~reg0                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[20]~reg0                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[19]~reg0                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[18]~reg0                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[17]~reg0                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[16]~reg0                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[15]~reg0                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[14]~reg0                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[13]~reg0                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[12]~reg0                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[11]~reg0                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[10]~reg0                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[9]~reg0                                      ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[8]~reg0                                      ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[7]~reg0                                      ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[6]~reg0                                      ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[5]~reg0                                      ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[4]~reg0                                      ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[3]~reg0                                      ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[2]~reg0                                      ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[1]~reg0                                      ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[0]~reg0                                      ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; select_n_to_the_cfi_flash_0~reg0                                        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; d1_in_a_write_cycle                                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_readn~reg0                                           ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; write_n_to_the_cfi_flash_0~reg0                                         ;
+-----------------------------+-------+------+-------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Source assignments for DE2_Board:inst|DE2_Board_reset_clk_domain_synch_module:DE2_Board_reset_clk_domain_synch ;
+-------------------+-------+------+-----------------------------------------------------------------------------+
; Assignment        ; Value ; from ; to                                                                          ;
+-------------------+-------+------+-----------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                    ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                               ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                  ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                  ;
+-------------------+-------+------+-----------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf ;
+----------------+------------+------------------------------------------------------------------------+
; Parameter Name ; Value      ; Type                                                                   ;
+----------------+------------+------------------------------------------------------------------------+
; lpm_file       ; rf_ram.mif ; String                                                                 ;
+----------------+------------+------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram ;
+------------------------------------+-----------------+-------------------------------------------------------------------------+
; Parameter Name                     ; Value           ; Type                                                                    ;
+------------------------------------+-----------------+-------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                                 ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                              ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                            ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                            ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                          ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                                 ;
; WIDTH_A                            ; 32              ; Integer                                                                 ;
; WIDTHAD_A                          ; 5               ; Integer                                                                 ;
; NUMWORDS_A                         ; 32              ; Integer                                                                 ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                                                                 ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                                 ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                                 ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                                 ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                                                 ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                                 ;
; WIDTH_B                            ; 32              ; Integer                                                                 ;
; WIDTHAD_B                          ; 5               ; Integer                                                                 ;
; NUMWORDS_B                         ; 32              ; Integer                                                                 ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                                 ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                                 ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                                 ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                                 ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                                                                 ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                                 ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                                                 ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                 ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                                 ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                                 ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                 ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                                 ;
; WIDTH_BYTEENA_A                    ; 1               ; Untyped                                                                 ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                                                                 ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                                 ;
; BYTE_SIZE                          ; 8               ; Untyped                                                                 ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA        ; Untyped                                                                 ;
; INIT_FILE                          ; rf_ram.mif      ; Untyped                                                                 ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                                 ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                                 ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                                                                 ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                                                 ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                                                 ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                                                 ;
; DEVICE_FAMILY                      ; Cyclone II      ; Untyped                                                                 ;
; CBXI_PARAMETER                     ; altsyncram_r0r1 ; Untyped                                                                 ;
+------------------------------------+-----------------+-------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram ;
+------------------------------------+-----------------+------------------------------------------------------+
; Parameter Name                     ; Value           ; Type                                                 ;
+------------------------------------+-----------------+------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                              ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                         ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                       ;
; OPERATION_MODE                     ; SINGLE_PORT     ; Untyped                                              ;
; WIDTH_A                            ; 32              ; Integer                                              ;
; WIDTHAD_A                          ; 8               ; Integer                                              ;
; NUMWORDS_A                         ; 256             ; Integer                                              ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                                              ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                              ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                              ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                              ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                              ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                              ;
; WIDTH_B                            ; 1               ; Untyped                                              ;
; WIDTHAD_B                          ; 1               ; Untyped                                              ;
; NUMWORDS_B                         ; 1               ; Untyped                                              ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                              ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                              ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                                              ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                              ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                              ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                              ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                              ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                              ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                              ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                              ;
; WIDTH_BYTEENA_A                    ; 4               ; Integer                                              ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                                              ;
; RAM_BLOCK_TYPE                     ; M4K             ; Untyped                                              ;
; BYTE_SIZE                          ; 8               ; Integer                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                              ;
; INIT_FILE                          ; data_RAM.hex    ; Untyped                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                              ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                                              ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                              ;
; DEVICE_FAMILY                      ; Cyclone II      ; Untyped                                              ;
; CBXI_PARAMETER                     ; altsyncram_8c21 ; Untyped                                              ;
+------------------------------------+-----------------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram ;
+------------------------------------+------------------+-------------------------------------------------------------+
; Parameter Name                     ; Value            ; Type                                                        ;
+------------------------------------+------------------+-------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                ; Untyped                                                     ;
; AUTO_CARRY_CHAINS                  ; ON               ; AUTO_CARRY                                                  ;
; IGNORE_CARRY_BUFFERS               ; OFF              ; IGNORE_CARRY                                                ;
; AUTO_CASCADE_CHAINS                ; ON               ; AUTO_CASCADE                                                ;
; IGNORE_CASCADE_BUFFERS             ; OFF              ; IGNORE_CASCADE                                              ;
; OPERATION_MODE                     ; SINGLE_PORT      ; Untyped                                                     ;
; WIDTH_A                            ; 32               ; Integer                                                     ;
; WIDTHAD_A                          ; 10               ; Integer                                                     ;
; NUMWORDS_A                         ; 896              ; Integer                                                     ;
; OUTDATA_REG_A                      ; UNREGISTERED     ; Untyped                                                     ;
; ADDRESS_ACLR_A                     ; NONE             ; Untyped                                                     ;
; OUTDATA_ACLR_A                     ; NONE             ; Untyped                                                     ;
; WRCONTROL_ACLR_A                   ; NONE             ; Untyped                                                     ;
; INDATA_ACLR_A                      ; NONE             ; Untyped                                                     ;
; BYTEENA_ACLR_A                     ; NONE             ; Untyped                                                     ;
; WIDTH_B                            ; 1                ; Untyped                                                     ;
; WIDTHAD_B                          ; 1                ; Untyped                                                     ;
; NUMWORDS_B                         ; 1                ; Untyped                                                     ;
; INDATA_REG_B                       ; CLOCK1           ; Untyped                                                     ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1           ; Untyped                                                     ;
; RDCONTROL_REG_B                    ; CLOCK1           ; Untyped                                                     ;
; ADDRESS_REG_B                      ; CLOCK1           ; Untyped                                                     ;
; OUTDATA_REG_B                      ; UNREGISTERED     ; Untyped                                                     ;
; BYTEENA_REG_B                      ; CLOCK1           ; Untyped                                                     ;
; INDATA_ACLR_B                      ; NONE             ; Untyped                                                     ;
; WRCONTROL_ACLR_B                   ; NONE             ; Untyped                                                     ;
; ADDRESS_ACLR_B                     ; NONE             ; Untyped                                                     ;
; OUTDATA_ACLR_B                     ; NONE             ; Untyped                                                     ;
; RDCONTROL_ACLR_B                   ; NONE             ; Untyped                                                     ;
; BYTEENA_ACLR_B                     ; NONE             ; Untyped                                                     ;
; WIDTH_BYTEENA_A                    ; 4                ; Integer                                                     ;
; WIDTH_BYTEENA_B                    ; 1                ; Untyped                                                     ;
; RAM_BLOCK_TYPE                     ; M4K              ; Untyped                                                     ;
; BYTE_SIZE                          ; 8                ; Integer                                                     ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE        ; Untyped                                                     ;
; INIT_FILE                          ; firmware_ROM.hex ; Untyped                                                     ;
; INIT_FILE_LAYOUT                   ; PORT_A           ; Untyped                                                     ;
; MAXIMUM_DEPTH                      ; 0                ; Untyped                                                     ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL           ; Untyped                                                     ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL           ; Untyped                                                     ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL           ; Untyped                                                     ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL           ; Untyped                                                     ;
; DEVICE_FAMILY                      ; Cyclone II       ; Untyped                                                     ;
; CBXI_PARAMETER                     ; altsyncram_cs21  ; Untyped                                                     ;
+------------------------------------+------------------+-------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo ;
+-------------------------+------------+-------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value      ; Type                                                                                                        ;
+-------------------------+------------+-------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON         ; AUTO_CARRY                                                                                                  ;
; IGNORE_CARRY_BUFFERS    ; OFF        ; IGNORE_CARRY                                                                                                ;
; AUTO_CASCADE_CHAINS     ; ON         ; AUTO_CASCADE                                                                                                ;
; IGNORE_CASCADE_BUFFERS  ; OFF        ; IGNORE_CASCADE                                                                                              ;
; lpm_width               ; 8          ; Integer                                                                                                     ;
; LPM_NUMWORDS            ; 512        ; Integer                                                                                                     ;
; LPM_WIDTHU              ; 9          ; Integer                                                                                                     ;
; LPM_SHOWAHEAD           ; OFF        ; Untyped                                                                                                     ;
; UNDERFLOW_CHECKING      ; OFF        ; Untyped                                                                                                     ;
; OVERFLOW_CHECKING       ; OFF        ; Untyped                                                                                                     ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF        ; Untyped                                                                                                     ;
; ADD_RAM_OUTPUT_REGISTER ; OFF        ; Untyped                                                                                                     ;
; ALMOST_FULL_VALUE       ; 0          ; Untyped                                                                                                     ;
; ALMOST_EMPTY_VALUE      ; 0          ; Untyped                                                                                                     ;
; USE_EAB                 ; ON         ; Untyped                                                                                                     ;
; MAXIMIZE_SPEED          ; 5          ; Untyped                                                                                                     ;
; DEVICE_FAMILY           ; Cyclone II ; Untyped                                                                                                     ;
; OPTIMIZE_FOR_SPEED      ; 5          ; Untyped                                                                                                     ;
; CBXI_PARAMETER          ; scfifo_46p ; Untyped                                                                                                     ;
+-------------------------+------------+-------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo ;
+-------------------------+------------+-------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value      ; Type                                                                                                        ;
+-------------------------+------------+-------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON         ; AUTO_CARRY                                                                                                  ;
; IGNORE_CARRY_BUFFERS    ; OFF        ; IGNORE_CARRY                                                                                                ;
; AUTO_CASCADE_CHAINS     ; ON         ; AUTO_CASCADE                                                                                                ;
; IGNORE_CASCADE_BUFFERS  ; OFF        ; IGNORE_CASCADE                                                                                              ;
; lpm_width               ; 8          ; Integer                                                                                                     ;
; LPM_NUMWORDS            ; 512        ; Integer                                                                                                     ;
; LPM_WIDTHU              ; 9          ; Integer                                                                                                     ;
; LPM_SHOWAHEAD           ; OFF        ; Untyped                                                                                                     ;
; UNDERFLOW_CHECKING      ; OFF        ; Untyped                                                                                                     ;
; OVERFLOW_CHECKING       ; OFF        ; Untyped                                                                                                     ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF        ; Untyped                                                                                                     ;
; ADD_RAM_OUTPUT_REGISTER ; OFF        ; Untyped                                                                                                     ;
; ALMOST_FULL_VALUE       ; 0          ; Untyped                                                                                                     ;
; ALMOST_EMPTY_VALUE      ; 0          ; Untyped                                                                                                     ;
; USE_EAB                 ; ON         ; Untyped                                                                                                     ;
; MAXIMIZE_SPEED          ; 5          ; Untyped                                                                                                     ;
; DEVICE_FAMILY           ; Cyclone II ; Untyped                                                                                                     ;
; OPTIMIZE_FOR_SPEED      ; 5          ; Untyped                                                                                                     ;
; CBXI_PARAMETER          ; scfifo_46p ; Untyped                                                                                                     ;
+-------------------------+------------+-------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic ;
+-------------------+----------------------------------+----------------------------------------------------------------------------------+
; Parameter Name    ; Value                            ; Type                                                                             ;
+-------------------+----------------------------------+----------------------------------------------------------------------------------+
; INSTANCE_ID       ; 0                                ; Integer                                                                          ;
; SLD_NODE_INFO     ; 00001100000000000110111000000000 ; Binary                                                                           ;
; LOG2_TXFIFO_DEPTH ; 9                                ; Integer                                                                          ;
; LOG2_RXFIFO_DEPTH ; 9                                ; Integer                                                                          ;
; RESERVED          ; 0                                ; Integer                                                                          ;
; DATA_WIDTH        ; 8                                ; Integer                                                                          ;
; NODE_IR_WIDTH     ; 1                                ; Integer                                                                          ;
; SCAN_LENGTH       ; 11                               ; Integer                                                                          ;
+-------------------+----------------------------------+----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram ;
+------------------------------------+--------------------+---------------------------------------------------------------+
; Parameter Name                     ; Value              ; Type                                                          ;
+------------------------------------+--------------------+---------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                  ; Untyped                                                       ;
; AUTO_CARRY_CHAINS                  ; ON                 ; AUTO_CARRY                                                    ;
; IGNORE_CARRY_BUFFERS               ; OFF                ; IGNORE_CARRY                                                  ;
; AUTO_CASCADE_CHAINS                ; ON                 ; AUTO_CASCADE                                                  ;
; IGNORE_CASCADE_BUFFERS             ; OFF                ; IGNORE_CASCADE                                                ;
; OPERATION_MODE                     ; SINGLE_PORT        ; Untyped                                                       ;
; WIDTH_A                            ; 16                 ; Integer                                                       ;
; WIDTHAD_A                          ; 13                 ; Integer                                                       ;
; NUMWORDS_A                         ; 8192               ; Integer                                                       ;
; OUTDATA_REG_A                      ; UNREGISTERED       ; Untyped                                                       ;
; ADDRESS_ACLR_A                     ; NONE               ; Untyped                                                       ;
; OUTDATA_ACLR_A                     ; NONE               ; Untyped                                                       ;
; WRCONTROL_ACLR_A                   ; NONE               ; Untyped                                                       ;
; INDATA_ACLR_A                      ; NONE               ; Untyped                                                       ;
; BYTEENA_ACLR_A                     ; NONE               ; Untyped                                                       ;
; WIDTH_B                            ; 1                  ; Untyped                                                       ;
; WIDTHAD_B                          ; 1                  ; Untyped                                                       ;
; NUMWORDS_B                         ; 1                  ; Untyped                                                       ;
; INDATA_REG_B                       ; CLOCK1             ; Untyped                                                       ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1             ; Untyped                                                       ;
; RDCONTROL_REG_B                    ; CLOCK1             ; Untyped                                                       ;
; ADDRESS_REG_B                      ; CLOCK1             ; Untyped                                                       ;
; OUTDATA_REG_B                      ; UNREGISTERED       ; Untyped                                                       ;
; BYTEENA_REG_B                      ; CLOCK1             ; Untyped                                                       ;
; INDATA_ACLR_B                      ; NONE               ; Untyped                                                       ;
; WRCONTROL_ACLR_B                   ; NONE               ; Untyped                                                       ;
; ADDRESS_ACLR_B                     ; NONE               ; Untyped                                                       ;
; OUTDATA_ACLR_B                     ; NONE               ; Untyped                                                       ;
; RDCONTROL_ACLR_B                   ; NONE               ; Untyped                                                       ;
; BYTEENA_ACLR_B                     ; NONE               ; Untyped                                                       ;
; WIDTH_BYTEENA_A                    ; 2                  ; Integer                                                       ;
; WIDTH_BYTEENA_B                    ; 1                  ; Untyped                                                       ;
; RAM_BLOCK_TYPE                     ; M4K                ; Untyped                                                       ;
; BYTE_SIZE                          ; 8                  ; Integer                                                       ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE          ; Untyped                                                       ;
; INIT_FILE                          ; payload_buffer.hex ; Untyped                                                       ;
; INIT_FILE_LAYOUT                   ; PORT_A             ; Untyped                                                       ;
; MAXIMUM_DEPTH                      ; 0                  ; Untyped                                                       ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL             ; Untyped                                                       ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL             ; Untyped                                                       ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL             ; Untyped                                                       ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL             ; Untyped                                                       ;
; DEVICE_FAMILY                      ; Cyclone II         ; Untyped                                                       ;
; CBXI_PARAMETER                     ; altsyncram_l331    ; Untyped                                                       ;
+------------------------------------+--------------------+---------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component ;
+------------------------+-------------------+------------------------------------------------------------------------------+
; Parameter Name         ; Value             ; Type                                                                         ;
+------------------------+-------------------+------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                                                                   ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                                                                 ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                                                                 ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                                                               ;
; LPM_WIDTH              ; 10                ; Integer                                                                      ;
; LPM_DIRECTION          ; UP                ; Untyped                                                                      ;
; LPM_MODULUS            ; 0                 ; Untyped                                                                      ;
; LPM_AVALUE             ; UNUSED            ; Untyped                                                                      ;
; LPM_SVALUE             ; UNUSED            ; Untyped                                                                      ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                                                                      ;
; DEVICE_FAMILY          ; Cyclone II        ; Untyped                                                                      ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                                                                      ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH                                                           ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK                                                           ;
; CARRY_CNT_EN           ; SMART             ; Untyped                                                                      ;
; LABWIDE_SCLR           ; ON                ; Untyped                                                                      ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                                                                      ;
; CBXI_PARAMETER         ; cntr_8bc          ; Untyped                                                                      ;
+------------------------+-------------------+------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst ;
+--------------------------+----------------------------------+---------+
; Parameter Name           ; Value                            ; Type    ;
+--------------------------+----------------------------------+---------+
; sld_hub_ip_version       ; 1                                ; Untyped ;
; sld_hub_ip_minor_version ; 2                                ; Untyped ;
; sld_common_ip_version    ; 0                                ; Untyped ;
; device_family            ; Cyclone II                       ; Untyped ;
; n_nodes                  ; 1                                ; Untyped ;
; n_sel_bits               ; 1                                ; Untyped ;
; n_node_ir_bits           ; 4                                ; Untyped ;
; node_info                ; 00001100000000000110111000000000 ; Binary  ;
+--------------------------+----------------------------------+---------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------+
; scfifo Parameter Settings by Entity Instance                                                                                       ;
+----------------------------+-------------------------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                                 ;
+----------------------------+-------------------------------------------------------------------------------------------------------+
; Number of entity instances ; 2                                                                                                     ;
; Entity Instance            ; DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo ;
;     -- FIFO Type           ; Single Clock                                                                                          ;
;     -- lpm_width           ; 8                                                                                                     ;
;     -- LPM_NUMWORDS        ; 512                                                                                                   ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                   ;
;     -- USE_EAB             ; ON                                                                                                    ;
; Entity Instance            ; DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo ;
;     -- FIFO Type           ; Single Clock                                                                                          ;
;     -- lpm_width           ; 8                                                                                                     ;
;     -- LPM_NUMWORDS        ; 512                                                                                                   ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                   ;
;     -- USE_EAB             ; ON                                                                                                    ;
+----------------------------+-------------------------------------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/DE2/DE2_Board/system/DE2_Board.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Nov 17 16:22:57 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_Board -c DE2_Board
Info: Found 1 design units, including 1 entities, in source file DE2_Board_top.bdf
    Info: Found entity 1: DE2_Board_top
Warning: Can't analyze file -- file C:/DE2/DE2_Board/system/BT_SWAP.v is missing
Info: Elaborating entity "DE2_Board_top" for the top level hierarchy
Warning: Using design file DE2_Board.v, which is not specified as a design file for the current project, but contains definitions for 14 design units and 14 entities in project
    Info: Found entity 1: asmi_asmi_control_port_arbitrator
    Info: Found entity 2: cpu_0_data_master_arbitrator
    Info: Found entity 3: cpu_0_instruction_master_arbitrator
    Info: Found entity 4: data_RAM_s1_arbitrator
    Info: Found entity 5: firmware_ROM_s1_arbitrator
    Info: Found entity 6: jtag_uart_0_avalon_jtag_slave_arbitrator
    Info: Found entity 7: payload_buffer_s1_arbitrator
    Info: Found entity 8: sysid_control_slave_arbitrator
    Info: Found entity 9: tri_state_bridge_0_avalon_slave_arbitrator
    Info: Found entity 10: tri_state_bridge_0_bridge_arbitrator
    Info: Found entity 11: DE2_Board_reset_clk_domain_synch_module
    Info: Found entity 12: DE2_Board
    Info: Found entity 13: cfi_flash_0_lane0_module
    Info: Found entity 14: cfi_flash_0
Info: Elaborating entity "DE2_Board" for hierarchy "DE2_Board:inst"
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(3795): truncated value with size 32 to match size of target (1)
Info: Elaborating entity "asmi_asmi_control_port_arbitrator" for hierarchy "DE2_Board:inst|asmi_asmi_control_port_arbitrator:the_asmi_asmi_control_port"
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(68): object "cpu_0_data_master_read_data_valid_asmi_asmi_control_port" declared but not used
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(85): object "asmi_asmi_control_port_allow_new_arb_cycle" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(91): object "asmi_asmi_control_port_beginbursttransfer_internal" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(112): object "cpu_0_data_master_arbiterlock" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(118): object "cpu_0_data_master_saved_grant_asmi_asmi_control_port" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(121): object "in_a_read_cycle" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(122): object "in_a_write_cycle" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(123): object "wait_for_asmi_asmi_control_port_counter" assigned a value but never read
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(128): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(148): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(190): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(227): truncated value with size 23 to match size of target (3)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(234): conditional expression evaluates to a constant
Warning (10034): Output port "cpu_0_data_master_read_data_valid_asmi_asmi_control_port" at DE2_Board.v(68) has no driver
Warning: Using design file asmi.v, which is not specified as a design file for the current project, but contains definitions for 3 design units and 3 entities in project
    Info: Found entity 1: asmi_sub
    Info: Found entity 2: tornado_asmi_atom
    Info: Found entity 3: asmi
Info: Elaborating entity "asmi" for hierarchy "DE2_Board:inst|asmi:the_asmi"
Info: Elaborating entity "asmi_sub" for hierarchy "DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub"
Warning (10036): Verilog HDL or VHDL warning at asmi.v(106): object "iTMT_reg" assigned a value but never read
Warning (10037): Verilog HDL or VHDL warning at asmi.v(140): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at asmi.v(150): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at asmi.v(161): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at asmi.v(171): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at asmi.v(225): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at asmi.v(254): truncated value with size 32 to match size of target (2)
Warning (10037): Verilog HDL or VHDL warning at asmi.v(262): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at asmi.v(308): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at asmi.v(315): truncated value with size 16 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at asmi.v(347): truncated value with size 16 to match size of target (8)
Warning (10037): Verilog HDL or VHDL warning at asmi.v(395): conditional expression evaluates to a constant
Info: Elaborating entity "tornado_asmi_atom" for hierarchy "DE2_Board:inst|asmi:the_asmi|tornado_asmi_atom:the_tornado_asmi_atom"
Info: Elaborating entity "cpu_0_data_master_arbitrator" for hierarchy "DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master"
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(355): object "cpu_0_data_master_granted_asmi_asmi_control_port" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(359): object "cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(361): object "cpu_0_data_master_granted_sysid_control_slave" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(370): object "cpu_0_data_master_read_data_valid_asmi_asmi_control_port" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(372): object "cpu_0_data_master_read_data_valid_data_RAM_s1" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(373): object "cpu_0_data_master_read_data_valid_firmware_ROM_s1" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(374): object "cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(376): object "cpu_0_data_master_read_data_valid_sysid_control_slave" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(386): object "d1_asmi_asmi_control_port_end_xfer" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(387): object "d1_data_RAM_s1_end_xfer" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(388): object "d1_firmware_ROM_s1_end_xfer" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(389): object "d1_jtag_uart_0_avalon_jtag_slave_end_xfer" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(390): object "d1_payload_buffer_s1_end_xfer" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(391): object "d1_sysid_control_slave_end_xfer" declared but not used
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(422): object "dbs_counter_overflow" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(435): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(441): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(463): truncated value with size 32 to match size of target (1)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(464): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(465): truncated value with size 32 to match size of target (1)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(508): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(521): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(531): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(556): truncated value with size 32 to match size of target (2)
Info: Elaborating entity "cpu_0_instruction_master_arbitrator" for hierarchy "DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master"
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(676): object "cfi_flash_0_s1_wait_counter_eq_0" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(677): object "cfi_flash_0_s1_wait_counter_eq_1" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(697): object "d1_data_RAM_s1_end_xfer" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(698): object "d1_firmware_ROM_s1_end_xfer" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(699): object "d1_payload_buffer_s1_end_xfer" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(700): object "d1_tri_state_bridge_0_avalon_slave_end_xfer" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(707): object "active_and_waiting_last_time" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(708): object "cpu_0_instruction_master_address_last_time" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(712): object "cpu_0_instruction_master_read_last_time" declared but not used
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(722): object "dbs_counter_overflow" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(732): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(738): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(773): truncated value with size 32 to match size of target (2)
Warning: Using design file cpu_0.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project
    Info: Found entity 1: cpu_0_rf_module
    Info: Found entity 2: cpu_0
Info: Elaborating entity "cpu_0" for hierarchy "DE2_Board:inst|cpu_0:the_cpu_0"
Warning: Using design file cpu_0_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_0_test_bench
Info: Elaborating entity "cpu_0_test_bench" for hierarchy "DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench"
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(46): object "D_iw" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(49): object "D_valid" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(50): object "E_alu_result" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(51): object "E_mem_byte_en" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(52): object "E_st_data" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(53): object "E_valid" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(54): object "F_pcb" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(55): object "F_valid" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(57): object "R_ctrl_ld_non_io" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(58): object "R_dst_regnum" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(60): object "W_alu_result" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(61): object "W_bstatus_reg" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(62): object "W_cmp_result" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(63): object "W_estatus_reg" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(64): object "W_ienable_reg" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(65): object "W_ipending_reg" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(66): object "W_status_reg" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(67): object "W_valid" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(71): object "d_address" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(72): object "d_byteenable" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(73): object "d_read" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(75): object "i_address" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(76): object "i_read" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(77): object "i_readdata" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(78): object "i_waitrequest" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(81): object "D_inst" declared but not used
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(82): object "D_op_add" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(83): object "D_op_addi" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(84): object "D_op_and" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(85): object "D_op_andhi" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(86): object "D_op_andi" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(87): object "D_op_beq" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(88): object "D_op_bge" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(89): object "D_op_bgeu" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(90): object "D_op_blt" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(91): object "D_op_bltu" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(92): object "D_op_bne" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(93): object "D_op_br" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(94): object "D_op_break" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(95): object "D_op_bret" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(96): object "D_op_call" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(97): object "D_op_callr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(98): object "D_op_cmpeq" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(99): object "D_op_cmpeqi" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(100): object "D_op_cmpge" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(101): object "D_op_cmpgei" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(102): object "D_op_cmpgeu" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(103): object "D_op_cmpgeui" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(104): object "D_op_cmplt" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(105): object "D_op_cmplti" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(106): object "D_op_cmpltu" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(107): object "D_op_cmpltui" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(108): object "D_op_cmpne" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(109): object "D_op_cmpnei" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(110): object "D_op_custom" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(111): object "D_op_div" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(112): object "D_op_divu" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(113): object "D_op_eret" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(114): object "D_op_flushd" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(115): object "D_op_flushda" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(116): object "D_op_flushi" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(117): object "D_op_flushp" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(118): object "D_op_hbreak" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(119): object "D_op_initd" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(120): object "D_op_initi" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(121): object "D_op_intr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(122): object "D_op_jmp" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(123): object "D_op_ldb" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(124): object "D_op_ldbio" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(125): object "D_op_ldbu" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(126): object "D_op_ldbuio" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(127): object "D_op_ldh" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(128): object "D_op_ldhio" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(129): object "D_op_ldhu" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(130): object "D_op_ldhuio" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(131): object "D_op_ldw" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(132): object "D_op_ldwio" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(133): object "D_op_mul" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(134): object "D_op_muli" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(135): object "D_op_mulxss" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(136): object "D_op_mulxsu" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(137): object "D_op_mulxuu" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(138): object "D_op_nextpc" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(139): object "D_op_nor" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(141): object "D_op_or" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(142): object "D_op_orhi" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(143): object "D_op_ori" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(144): object "D_op_rdctl" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(145): object "D_op_ret" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(146): object "D_op_rol" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(147): object "D_op_roli" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(148): object "D_op_ror" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(149): object "D_op_rsv01" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(150): object "D_op_rsv02" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(151): object "D_op_rsv09" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(152): object "D_op_rsv10" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(153): object "D_op_rsv17" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(154): object "D_op_rsv18" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(155): object "D_op_rsv19" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(156): object "D_op_rsv25" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(157): object "D_op_rsv26" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(158): object "D_op_rsv29" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(159): object "D_op_rsv31" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(160): object "D_op_rsv33" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(161): object "D_op_rsv34" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(162): object "D_op_rsv41" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(163): object "D_op_rsv42" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(164): object "D_op_rsv49" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(165): object "D_op_rsv56" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(166): object "D_op_rsv57" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(167): object "D_op_rsv61" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(168): object "D_op_rsv62" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(169): object "D_op_rsv63" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(170): object "D_op_rsvx00" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(171): object "D_op_rsvx10" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(172): object "D_op_rsvx15" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(173): object "D_op_rsvx17" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(174): object "D_op_rsvx20" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(175): object "D_op_rsvx21" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(176): object "D_op_rsvx25" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(177): object "D_op_rsvx33" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(178): object "D_op_rsvx34" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(179): object "D_op_rsvx35" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(180): object "D_op_rsvx42" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(181): object "D_op_rsvx43" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(182): object "D_op_rsvx44" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(183): object "D_op_rsvx47" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(184): object "D_op_rsvx50" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(185): object "D_op_rsvx51" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(186): object "D_op_rsvx55" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(187): object "D_op_rsvx56" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(188): object "D_op_rsvx60" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(189): object "D_op_rsvx62" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(190): object "D_op_rsvx63" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(191): object "D_op_sll" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(192): object "D_op_slli" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(193): object "D_op_sra" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(194): object "D_op_srai" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(195): object "D_op_srl" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(196): object "D_op_srli" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(197): object "D_op_stb" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(198): object "D_op_stbio" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(199): object "D_op_sth" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(200): object "D_op_sthio" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(201): object "D_op_stw" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(202): object "D_op_stwio" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(203): object "D_op_sub" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(204): object "D_op_sync" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(205): object "D_op_trap" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(206): object "D_op_wrctl" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(207): object "D_op_xor" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(208): object "D_op_xorhi" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(209): object "D_op_xori" assigned a value but never read
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(210): object "W_vinst" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(212): object "av_ld_data_aligned_unfiltered_0_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(213): object "av_ld_data_aligned_unfiltered_10_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(214): object "av_ld_data_aligned_unfiltered_11_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(215): object "av_ld_data_aligned_unfiltered_12_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(216): object "av_ld_data_aligned_unfiltered_13_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(217): object "av_ld_data_aligned_unfiltered_14_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(218): object "av_ld_data_aligned_unfiltered_15_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(219): object "av_ld_data_aligned_unfiltered_16_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(220): object "av_ld_data_aligned_unfiltered_17_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(221): object "av_ld_data_aligned_unfiltered_18_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(222): object "av_ld_data_aligned_unfiltered_19_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(223): object "av_ld_data_aligned_unfiltered_1_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(224): object "av_ld_data_aligned_unfiltered_20_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(225): object "av_ld_data_aligned_unfiltered_21_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(226): object "av_ld_data_aligned_unfiltered_22_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(227): object "av_ld_data_aligned_unfiltered_23_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(228): object "av_ld_data_aligned_unfiltered_24_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(229): object "av_ld_data_aligned_unfiltered_25_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(230): object "av_ld_data_aligned_unfiltered_26_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(231): object "av_ld_data_aligned_unfiltered_27_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(232): object "av_ld_data_aligned_unfiltered_28_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(233): object "av_ld_data_aligned_unfiltered_29_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(234): object "av_ld_data_aligned_unfiltered_2_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(235): object "av_ld_data_aligned_unfiltered_30_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(236): object "av_ld_data_aligned_unfiltered_31_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(237): object "av_ld_data_aligned_unfiltered_3_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(238): object "av_ld_data_aligned_unfiltered_4_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(239): object "av_ld_data_aligned_unfiltered_5_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(240): object "av_ld_data_aligned_unfiltered_6_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(241): object "av_ld_data_aligned_unfiltered_7_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(242): object "av_ld_data_aligned_unfiltered_8_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(243): object "av_ld_data_aligned_unfiltered_9_is_x" declared but not used
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(245): object "rf_wr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(246): object "rf_wr_data" assigned a value but never read
Warning (10037): Verilog HDL or VHDL warning at cpu_0_test_bench.v(251): conditional expression evaluates to a constant
Info: Elaborating entity "cpu_0_rf_module" for hierarchy "DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus51/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_r0r1.tdf
    Info: Found entity 1: altsyncram_r0r1
Info: Elaborating entity "altsyncram_r0r1" for hierarchy "DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated"
Info: Elaborating entity "data_RAM_s1_arbitrator" for hierarchy "DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1"
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(997): object "data_RAM_s1_beginbursttransfer_internal" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(1017): object "in_a_read_cycle" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(1018): object "in_a_write_cycle" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(1024): object "wait_for_data_RAM_s1_counter" assigned a value but never read
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(1029): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1046): truncated value with size 32 to match size of target (3)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(1091): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1092): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1108): truncated value with size 2 to match size of target (1)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(1115): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(1135): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1136): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1148): truncated value with size 2 to match size of target (1)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(1155): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1205): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1231): truncated value with size 23 to match size of target (8)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(1239): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1245): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1254): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1264): truncated value with size 32 to match size of target (4)
Warning: Using design file data_RAM.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: data_RAM
Info: Elaborating entity "data_RAM" for hierarchy "DE2_Board:inst|data_RAM:the_data_RAM"
Info: Elaborating entity "altsyncram" for hierarchy "DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_8c21.tdf
    Info: Found entity 1: altsyncram_8c21
Info: Elaborating entity "altsyncram_8c21" for hierarchy "DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated"
Warning: Memory depth value (256) in design file differs from memory depth value (1) in Memory Initialization File -- setting initial value for remaining addresses to 0
Info: Elaborating entity "firmware_ROM_s1_arbitrator" for hierarchy "DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1"
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(1395): object "firmware_ROM_s1_beginbursttransfer_internal" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(1415): object "in_a_read_cycle" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(1416): object "in_a_write_cycle" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(1422): object "wait_for_firmware_ROM_s1_counter" assigned a value but never read
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(1427): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1444): truncated value with size 32 to match size of target (3)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(1489): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1490): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1506): truncated value with size 2 to match size of target (1)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(1513): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(1533): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1534): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1546): truncated value with size 2 to match size of target (1)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(1553): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1603): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1629): truncated value with size 23 to match size of target (10)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(1637): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1643): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1652): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1662): truncated value with size 32 to match size of target (4)
Warning: Using design file firmware_ROM.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: firmware_ROM
Info: Elaborating entity "firmware_ROM" for hierarchy "DE2_Board:inst|firmware_ROM:the_firmware_ROM"
Info: Elaborating entity "altsyncram" for hierarchy "DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_cs21.tdf
    Info: Found entity 1: altsyncram_cs21
Info: Elaborating entity "altsyncram_cs21" for hierarchy "DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated"
Info: Elaborating entity "jtag_uart_0_avalon_jtag_slave_arbitrator" for hierarchy "DE2_Board:inst|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave"
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(1735): object "cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave" declared but not used
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(1762): object "cpu_0_data_master_arbiterlock" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(1768): object "cpu_0_data_master_saved_grant_jtag_uart_0_avalon_jtag_slave" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(1771): object "in_a_read_cycle" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(1772): object "in_a_write_cycle" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(1775): object "jtag_uart_0_avalon_jtag_slave_allow_new_arb_cycle" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(1781): object "jtag_uart_0_avalon_jtag_slave_beginbursttransfer_internal" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(1802): object "wait_for_jtag_uart_0_avalon_jtag_slave_counter" assigned a value but never read
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(1807): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1830): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(1906): truncated value with size 23 to match size of target (1)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(1913): conditional expression evaluates to a constant
Warning (10034): Output port "cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave" at DE2_Board.v(1735) has no driver
Warning: Using design file jtag_uart_0.v, which is not specified as a design file for the current project, but contains definitions for 7 design units and 7 entities in project
    Info: Found entity 1: jtag_uart_0_log_module
    Info: Found entity 2: jtag_uart_0_sim_scfifo_w
    Info: Found entity 3: jtag_uart_0_scfifo_w
    Info: Found entity 4: jtag_uart_0_drom_module
    Info: Found entity 5: jtag_uart_0_sim_scfifo_r
    Info: Found entity 6: jtag_uart_0_scfifo_r
    Info: Found entity 7: jtag_uart_0
Info: Elaborating entity "jtag_uart_0" for hierarchy "DE2_Board:inst|jtag_uart_0:the_jtag_uart_0"
Info (10035): Verilog HDL or VHDL information at jtag_uart_0.v(539): object "sim_r_ena" declared but not used
Info (10035): Verilog HDL or VHDL information at jtag_uart_0.v(540): object "sim_t_dat" declared but not used
Info (10035): Verilog HDL or VHDL information at jtag_uart_0.v(541): object "sim_t_ena" declared but not used
Info (10035): Verilog HDL or VHDL information at jtag_uart_0.v(542): object "sim_t_pause" declared but not used
Warning (10037): Verilog HDL or VHDL warning at jtag_uart_0.v(668): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at jtag_uart_0.v(723): conditional expression evaluates to a constant
Info: Elaborating entity "jtag_uart_0_scfifo_w" for hierarchy "DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus51/libraries/megafunctions/scfifo.tdf
    Info: Found entity 1: scfifo
Info: Elaborating entity "scfifo" for hierarchy "DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_46p.tdf
    Info: Found entity 1: scfifo_46p
Info: Elaborating entity "scfifo_46p" for hierarchy "DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_bcp.tdf
    Info: Found entity 1: a_dpfifo_bcp
Info: Elaborating entity "a_dpfifo_bcp" for hierarchy "DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_odf.tdf
    Info: Found entity 1: a_fefifo_odf
Info: Elaborating entity "a_fefifo_odf" for hierarchy "DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state"
Info: Found 1 design units, including 1 entities, in source file db/cntr_uj7.tdf
    Info: Found entity 1: cntr_uj7
Info: Elaborating entity "cntr_uj7" for hierarchy "DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw"
Info: Found 1 design units, including 1 entities, in source file db/dpram_scp.tdf
    Info: Found entity 1: dpram_scp
Info: Elaborating entity "dpram_scp" for hierarchy "DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3pc1.tdf
    Info: Found entity 1: altsyncram_3pc1
Info: Elaborating entity "altsyncram_3pc1" for hierarchy "DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_0431.tdf
    Info: Found entity 1: altsyncram_0431
Info: Elaborating entity "altsyncram_0431" for hierarchy "DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3"
Info: Found 1 design units, including 1 entities, in source file db/cntr_gl8.tdf
    Info: Found entity 1: cntr_gl8
Info: Elaborating entity "cntr_gl8" for hierarchy "DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count"
Info: Elaborating entity "jtag_uart_0_scfifo_r" for hierarchy "DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r"
Info (10035): Verilog HDL or VHDL information at jtag_uart_0.v(425): object "rst_n" declared but not used
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus51/libraries/megafunctions/alt_jtag_atlantic.v
    Info: Found entity 1: alt_jtag_atlantic
Info: Elaborating entity "alt_jtag_atlantic" for hierarchy "DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic"
Info: Elaborating entity "payload_buffer_s1_arbitrator" for hierarchy "DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1"
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(2039): object "in_a_read_cycle" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(2040): object "in_a_write_cycle" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(2056): object "payload_buffer_s1_beginbursttransfer_internal" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(2077): object "wait_for_payload_buffer_s1_counter" assigned a value but never read
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2082): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2096): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2103): truncated value with size 32 to match size of target (3)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2148): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2149): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2165): truncated value with size 2 to match size of target (1)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2172): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2192): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2193): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2205): truncated value with size 2 to match size of target (1)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2212): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2262): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2288): truncated value with size 24 to match size of target (13)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2298): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2304): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2313): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2323): truncated value with size 32 to match size of target (2)
Warning: Using design file payload_buffer.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: payload_buffer
Info: Elaborating entity "payload_buffer" for hierarchy "DE2_Board:inst|payload_buffer:the_payload_buffer"
Info: Elaborating entity "altsyncram" for hierarchy "DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_l331.tdf
    Info: Found entity 1: altsyncram_l331
Info: Elaborating entity "altsyncram_l331" for hierarchy "DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated"
Warning: Memory depth value (8192) in design file differs from memory depth value (1) in Memory Initialization File -- setting initial value for remaining addresses to 0
Info: Found 1 design units, including 1 entities, in source file db/decode_1oa.tdf
    Info: Found entity 1: decode_1oa
Info: Elaborating entity "decode_1oa" for hierarchy "DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|decode_1oa:decode3"
Info: Found 1 design units, including 1 entities, in source file db/mux_0kb.tdf
    Info: Found entity 1: mux_0kb
Info: Elaborating entity "mux_0kb" for hierarchy "DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2"
Info: Elaborating entity "sysid_control_slave_arbitrator" for hierarchy "DE2_Board:inst|sysid_control_slave_arbitrator:the_sysid_control_slave"
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(2386): object "cpu_0_data_master_read_data_valid_sysid_control_slave" declared but not used
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(2398): object "cpu_0_data_master_arbiterlock" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(2404): object "cpu_0_data_master_saved_grant_sysid_control_slave" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(2407): object "in_a_read_cycle" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(2408): object "in_a_write_cycle" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(2411): object "sysid_control_slave_allow_new_arb_cycle" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(2417): object "sysid_control_slave_beginbursttransfer_internal" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(2429): object "wait_for_sysid_control_slave_counter" assigned a value but never read
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2434): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2448): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2511): truncated value with size 23 to match size of target (1)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2518): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2533): truncated value with size 32 to match size of target (1)
Warning (10034): Output port "cpu_0_data_master_read_data_valid_sysid_control_slave" at DE2_Board.v(2386) has no driver
Warning: Using design file sysid.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sysid
Info: Elaborating entity "sysid" for hierarchy "DE2_Board:inst|sysid:the_sysid"
Info: Elaborating entity "tri_state_bridge_0_avalon_slave_arbitrator" for hierarchy "DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave"
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(2655): object "in_a_read_cycle" assigned a value but never read
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(2658): object "incoming_tri_state_bridge_0_data_bit_0_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(2659): object "incoming_tri_state_bridge_0_data_bit_1_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(2660): object "incoming_tri_state_bridge_0_data_bit_2_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(2661): object "incoming_tri_state_bridge_0_data_bit_3_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(2662): object "incoming_tri_state_bridge_0_data_bit_4_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(2663): object "incoming_tri_state_bridge_0_data_bit_5_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(2664): object "incoming_tri_state_bridge_0_data_bit_6_is_x" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Board.v(2665): object "incoming_tri_state_bridge_0_data_bit_7_is_x" declared but not used
Warning (10036): Verilog HDL or VHDL warning at DE2_Board.v(2690): object "tri_state_bridge_0_avalon_slave_beginbursttransfer_internal" assigned a value but never read
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2710): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2721): truncated value with size 32 to match size of target (1)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2722): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2735): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2742): truncated value with size 32 to match size of target (3)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2787): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2788): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2804): truncated value with size 3 to match size of target (2)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2811): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2824): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2833): truncated value with size 32 to match size of target (1)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2841): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2851): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2868): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2869): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2881): truncated value with size 3 to match size of target (2)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2888): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2938): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2964): truncated value with size 32 to match size of target (1)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2965): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2974): truncated value with size 32 to match size of target (1)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2975): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(2991): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(2997): truncated value with size 25 to match size of target (22)
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(3007): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(3038): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(3043): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at DE2_Board.v(3050): truncated value with size 32 to match size of target (1)
Info: Elaborating entity "DE2_Board_reset_clk_domain_synch_module" for hierarchy "DE2_Board:inst|DE2_Board_reset_clk_domain_synch_module:DE2_Board_reset_clk_domain_synch"
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(3178): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at DE2_Board.v(3187): conditional expression evaluates to a constant
Warning: Using design file delay_reset_block.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: delay_reset_block
Info: Elaborating entity "delay_reset_block" for hierarchy "delay_reset_block:inst3"
Warning: Using design file reset_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: reset_counter
Info: Elaborating entity "reset_counter" for hierarchy "delay_reset_block:inst3|reset_counter:inst"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus51/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_8bc.tdf
    Info: Found entity 1: cntr_8bc
Info: Elaborating entity "cntr_8bc" for hierarchy "delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated"
Info: Found 6 design units, including 2 entities, in source file ../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd
    Info: Found design unit 1: HUB_PACK
    Info: Found design unit 2: JTAG_PACK
    Info: Found design unit 3: sld_hub-rtl
    Info: Found design unit 4: sld_jtag_state_machine-rtl
    Info: Found entity 1: sld_hub
    Info: Found entity 2: sld_jtag_state_machine
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus51/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus51/libraries/megafunctions/lpm_decode.tdf
    Info: Found entity 1: lpm_decode
Info: Found 1 design units, including 1 entities, in source file db/decode_rpe.tdf
    Info: Found entity 1: decode_rpe
Info: Found 2 design units, including 1 entities, in source file ../../../altera/quartus51/libraries/megafunctions/sld_dffex.vhd
    Info: Found design unit 1: sld_dffex-DFFEX
    Info: Found entity 1: sld_dffex
Info: Found 2 design units, including 1 entities, in source file ../../../altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd
    Info: Found design unit 1: sld_rom_sr-INFO_REG
    Info: Found entity 1: sld_rom_sr
Warning: Reduced register "DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|d1_reasons_to_wait" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|d1_reasons_to_wait" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|d1_reasons_to_wait" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[31]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[30]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[29]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[28]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[27]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[26]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[25]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[24]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[22]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[21]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[20]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[19]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[18]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[2]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_tri_state_bridge_0_avalon_slave_end_xfer" merged to single register "DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[11]" merged to single register "DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[31]"
    Info: Duplicate register "DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[26]" merged to single register "DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[31]"
    Info: Duplicate register "DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[27]" merged to single register "DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[31]"
    Info: Duplicate register "DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[28]" merged to single register "DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[31]"
    Info: Duplicate register "DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[29]" merged to single register "DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[31]"
    Info: Duplicate register "DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[30]" merged to single register "DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[31]"
Warning: Reduced register "DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_arb_share_counter[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_arb_share_counter[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|slowcount[1]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_arb_addend[0]" merged to single register "DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_arb_addend[1]", power-up level changed
    Info: Duplicate register "DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_arb_addend[0]" merged to single register "DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_arb_addend[1]", power-up level changed
    Info: Duplicate register "DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_arb_addend[0]" merged to single register "DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_arb_addend[1]", power-up level changed
Warning: Reduced register "DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_slavearbiterlockenable" with stuck data_in port to stuck value GND
Warning: Reduced register "DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_slavearbiterlockenable" with stuck data_in port to stuck value GND
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 1867 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 27 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 1681 logic cells
    Info: Implemented 144 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 342 warnings
    Info: Processing ended: Thu Nov 17 16:23:49 2005
    Info: Elapsed time: 00:00:52


