Quartus II
Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition
14
1046
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
Reset_Delay
# storage
db|DE2_SD_Card_Audio.(1).cnf
db|DE2_SD_Card_Audio.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Reset_Delay.v
7478b5712772431a3d07e9d65faf3
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
Reset_Delay:delay1
}
# macro_sequence

# end
# entity
altpll
# storage
db|DE2_SD_Card_Audio.(3).cnf
db|DE2_SD_Card_Audio.(3).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altpll.tdf
2edfab7fd52cb567d9dca9f62da13c
7
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
FAST
PARAMETER_UNKNOWN
USR
LPM_HINT
UNUSED
PARAMETER_UNKNOWN
DEF
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
20000
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_SIGNED_DEC
USR
CLK1_MULTIPLY_BY
2
PARAMETER_SIGNED_DEC
USR
CLK0_MULTIPLY_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
2
PARAMETER_SIGNED_DEC
USR
CLK1_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK0_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK0_PHASE_SHIFT
-3000
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK1_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_LOW_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_HIGH_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
DPA_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
DPA_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
DPA_DIVIDER
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C6_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C7_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C8_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C9_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
C6_PH
0
PARAMETER_UNKNOWN
DEF
C7_PH
0
PARAMETER_UNKNOWN
DEF
C8_PH
0
PARAMETER_UNKNOWN
DEF
C9_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C6_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C7_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C8_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C9_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK6_COUNTER
E0
PARAMETER_UNKNOWN
DEF
CLK7_COUNTER
E1
PARAMETER_UNKNOWN
DEF
CLK8_COUNTER
E2
PARAMETER_UNKNOWN
DEF
CLK9_COUNTER
E3
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C_BITS
9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASESTEP
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEUPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLKENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASECOUNTERSELECT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
SIM_GATE_LOCK_DEVICE_BEHAVIOR
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
clkswitch
-1
1
areset
-1
1
pllena
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# macro_sequence

# end
# entity
altpll
# storage
db|DE2_SD_Card_Audio.(5).cnf
db|DE2_SD_Card_Audio.(5).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altpll.tdf
2edfab7fd52cb567d9dca9f62da13c
7
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
FAST
PARAMETER_UNKNOWN
USR
LPM_HINT
UNUSED
PARAMETER_UNKNOWN
DEF
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
37037
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_MULTIPLY_BY
92
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_DIVIDE_BY
135
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_LOW_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_HIGH_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
DPA_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
DPA_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
DPA_DIVIDER
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C6_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C7_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C8_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C9_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
C6_PH
0
PARAMETER_UNKNOWN
DEF
C7_PH
0
PARAMETER_UNKNOWN
DEF
C8_PH
0
PARAMETER_UNKNOWN
DEF
C9_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C6_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C7_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C8_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C9_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK6_COUNTER
E0
PARAMETER_UNKNOWN
DEF
CLK7_COUNTER
E1
PARAMETER_UNKNOWN
DEF
CLK8_COUNTER
E2
PARAMETER_UNKNOWN
DEF
CLK9_COUNTER
E3
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C_BITS
9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASESTEP
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEUPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLKENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASECOUNTERSELECT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
SIM_GATE_LOCK_DEVICE_BEHAVIOR
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
areset
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
clkswitch
-1
1
pllena
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# hierarchies {
Audio_PLL:PLL2|altpll:altpll_component
}
# macro_sequence

# end
# entity
FIFO_16_256
# storage
db|DE2_SD_Card_Audio.(10).cnf
db|DE2_SD_Card_Audio.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
FIFO_16_256.v
75c891157aba16bfb8e20e5c3ff1f19
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0
}
# macro_sequence

# end
# entity
dcfifo
# storage
db|DE2_SD_Card_Audio.(11).cnf
db|DE2_SD_Card_Audio.(11).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|dcfifo.tdf
f882cb97b06cc9eb9a184517332d777
7
# user_parameter {
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
16
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
256
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
8
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
DEF
DELAY_RDUSEDW
1
PARAMETER_UNKNOWN
DEF
DELAY_WRUSEDW
1
PARAMETER_UNKNOWN
DEF
RDSYNC_DELAYPIPE
4
PARAMETER_SIGNED_DEC
USR
WRSYNC_DELAYPIPE
4
PARAMETER_SIGNED_DEC
USR
CLOCKS_ARE_SYNCHRONIZED
FALSE
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
ADD_USEDW_MSB_BIT
OFF
PARAMETER_UNKNOWN
DEF
WRITE_ACLR_SYNCH
OFF
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
dcfifo_hlj1
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdreq
-1
3
rdclk
-1
3
q
-1
3
data
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component
}
# macro_sequence

# end
# entity
dcfifo_hlj1
# storage
db|DE2_SD_Card_Audio.(12).cnf
db|DE2_SD_Card_Audio.(12).cnf
# case_insensitive
# source_file
db|dcfifo_hlj1.tdf
935fdb2e731e716d839d8cd64128b98
7
# used_port {
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdreq
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_hlj1:auto_generated
}
# macro_sequence

# end
# entity
a_graycounter_g86
# storage
db|DE2_SD_Card_Audio.(13).cnf
db|DE2_SD_Card_Audio.(13).cnf
# case_insensitive
# source_file
db|a_graycounter_g86.tdf
dd92ebb332ede64e3d6253c9bca390aa
7
# used_port {
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_hlj1:auto_generated|a_graycounter_g86:rdptr_g1p
}
# macro_sequence

# end
# entity
a_graycounter_7fc
# storage
db|DE2_SD_Card_Audio.(14).cnf
db|DE2_SD_Card_Audio.(14).cnf
# case_insensitive
# source_file
db|a_graycounter_7fc.tdf
437e2d5f3255c71fbe4aa94b802ce582
7
# used_port {
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_hlj1:auto_generated|a_graycounter_7fc:wrptr_g1p
}
# macro_sequence

# end
# entity
a_graycounter_6fc
# storage
db|DE2_SD_Card_Audio.(15).cnf
db|DE2_SD_Card_Audio.(15).cnf
# case_insensitive
# source_file
db|a_graycounter_6fc.tdf
a311d180471170f0db51f8d96decb79c
7
# used_port {
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_hlj1:auto_generated|a_graycounter_6fc:wrptr_gp
}
# macro_sequence

# end
# entity
altsyncram_vk81
# storage
db|DE2_SD_Card_Audio.(16).cnf
db|DE2_SD_Card_Audio.(16).cnf
# case_insensitive
# source_file
db|altsyncram_vk81.tdf
a88e1b8f8a77a4926273cf21df79983e
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
addressstall_b
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
aclr1
-1
3
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_hlj1:auto_generated|altsyncram_vk81:fifo_ram
}
# macro_sequence

# end
# entity
altsyncram_brg1
# storage
db|DE2_SD_Card_Audio.(17).cnf
db|DE2_SD_Card_Audio.(17).cnf
# case_insensitive
# source_file
db|altsyncram_brg1.tdf
e4a7a62c6a87257f1b9c889c25f9cf71
7
# used_port {
wren_b
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b3
-1
3
data_b2
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
addressstall_a
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
aclr1
-1
3
wren_a
-1
1
data_a9
-1
2
data_a8
-1
2
data_a7
-1
2
data_a6
-1
2
data_a5
-1
2
data_a4
-1
2
data_a3
-1
2
data_a2
-1
2
data_a15
-1
2
data_a14
-1
2
data_a13
-1
2
data_a12
-1
2
data_a11
-1
2
data_a10
-1
2
data_a1
-1
2
data_a0
-1
2
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_hlj1:auto_generated|altsyncram_vk81:fifo_ram|altsyncram_brg1:altsyncram14
}
# macro_sequence

# end
# entity
dffpipe_ngh
# storage
db|DE2_SD_Card_Audio.(18).cnf
db|DE2_SD_Card_Audio.(18).cnf
# case_insensitive
# source_file
db|dffpipe_ngh.tdf
be34cc12b65f0bfa289bbf576ff7d7
7
# used_port {
q0
-1
3
clrn
-1
3
clock
-1
3
d0
-1
2
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_hlj1:auto_generated|dffpipe_ngh:rdaclr
}
# macro_sequence

# end
# entity
alt_synch_pipe_jcb
# storage
db|DE2_SD_Card_Audio.(19).cnf
db|DE2_SD_Card_Audio.(19).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_jcb.tdf
708af26e9f8eecea474163422157a1c
7
# used_port {
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clrn
-1
3
clock
-1
3
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_hlj1:auto_generated|alt_synch_pipe_jcb:rs_dgwp
}
# macro_sequence

# end
# entity
dffpipe_hd9
# storage
db|DE2_SD_Card_Audio.(20).cnf
db|DE2_SD_Card_Audio.(20).cnf
# case_insensitive
# source_file
db|dffpipe_hd9.tdf
6051e7de3d662853e9450b82b1c6699
7
# used_port {
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clrn
-1
3
clock
-1
3
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_hlj1:auto_generated|alt_synch_pipe_jcb:rs_dgwp|dffpipe_hd9:dffpipe17
}
# macro_sequence

# end
# entity
alt_synch_pipe_nc8
# storage
db|DE2_SD_Card_Audio.(21).cnf
db|DE2_SD_Card_Audio.(21).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_nc8.tdf
8b231d47b889a0d3c1967162309f4f20
7
# used_port {
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clrn
-1
3
clock
-1
3
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_hlj1:auto_generated|alt_synch_pipe_nc8:ws_dgrp
}
# macro_sequence

# end
# entity
dffpipe_id9
# storage
db|DE2_SD_Card_Audio.(22).cnf
db|DE2_SD_Card_Audio.(22).cnf
# case_insensitive
# source_file
db|dffpipe_id9.tdf
b76513294f69a9195f8b6f25345759a
7
# used_port {
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clrn
-1
3
clock
-1
3
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_hlj1:auto_generated|alt_synch_pipe_nc8:ws_dgrp|dffpipe_id9:dffpipe20
}
# macro_sequence

# end
# entity
cmpr_t16
# storage
db|DE2_SD_Card_Audio.(23).cnf
db|DE2_SD_Card_Audio.(23).cnf
# case_insensitive
# source_file
db|cmpr_t16.tdf
32f06c71834a8b8f6a7232f973635ca8
7
# used_port {
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_hlj1:auto_generated|cmpr_t16:rdempty_eq_comp
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_hlj1:auto_generated|cmpr_t16:wrfull_eq_comp
}
# macro_sequence

# end
# entity
SD_CLK
# storage
db|DE2_SD_Card_Audio.(31).cnf
db|DE2_SD_Card_Audio.(31).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SD_CLK.v
c775283e58a08896748da27b528d2639
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|SD_CLK:the_SD_CLK
}
# macro_sequence

# end
# entity
SD_CMD
# storage
db|DE2_SD_Card_Audio.(33).cnf
db|DE2_SD_Card_Audio.(33).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SD_CMD.v
16b64c122e1fd698b7c0f94088cebeda
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|SD_CMD:the_SD_CMD
}
# macro_sequence

# end
# entity
SD_DAT
# storage
db|DE2_SD_Card_Audio.(35).cnf
db|DE2_SD_Card_Audio.(35).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SD_DAT.v
ff9e323887c921a529ee96497519f4
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|SD_DAT:the_SD_DAT
}
# macro_sequence

# end
# entity
SEG7_Display
# storage
db|DE2_SD_Card_Audio.(37).cnf
db|DE2_SD_Card_Audio.(37).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SEG7_Display.v
6937b7f632d51bbe29f2c5e8cb8156
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|SEG7_Display:the_SEG7_Display
}
# macro_sequence

# end
# entity
SEG7_LUT_8
# storage
db|DE2_SD_Card_Audio.(38).cnf
db|DE2_SD_Card_Audio.(38).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SEG7_LUT_8.v
d64b2439fc458122ff5c412095d9699e
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8
}
# macro_sequence

# end
# entity
SEG7_LUT
# storage
db|DE2_SD_Card_Audio.(39).cnf
db|DE2_SD_Card_Audio.(39).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SEG7_LUT.v
2ab9a3d025ae9ad40f9aa264d22326f
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u0
system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u1
system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u2
system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u3
system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u4
system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u5
system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u6
system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u7
}
# macro_sequence

# end
# entity
Img_RAM
# storage
db|DE2_SD_Card_Audio.(45).cnf
db|DE2_SD_Card_Audio.(45).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Img_RAM.v
13664eb9305fc6198935403670f4a97
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(46).cnf
db|DE2_SD_Card_Audio.(46).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
1
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
19
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
307200
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
16
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
38400
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
M4K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
Img_DATA.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_B
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_q7o1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# macro_sequence

# end
# entity
altsyncram_q7o1
# storage
db|DE2_SD_Card_Audio.(47).cnf
db|DE2_SD_Card_Audio.(47).cnf
# case_insensitive
# source_file
db|altsyncram_q7o1.tdf
5708090b2ce6cd7c1adefbf12e31638
7
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b15
-1
3
address_b14
-1
3
address_b13
-1
3
address_b12
-1
3
address_b11
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a18
-1
3
address_a17
-1
3
address_a16
-1
3
address_a15
-1
3
address_a14
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_p132
# storage
db|DE2_SD_Card_Audio.(48).cnf
db|DE2_SD_Card_Audio.(48).cnf
# case_insensitive
# source_file
db|altsyncram_p132.tdf
ce58c020127f201e42aa41544c371d
7
# used_port {
wren_b
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
data_b0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b18
-1
3
address_b17
-1
3
address_b16
-1
3
address_b15
-1
3
address_b14
-1
3
address_b13
-1
3
address_b12
-1
3
address_b11
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a15
-1
3
address_a14
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
wren_a
-1
1
data_a7
-1
2
data_a6
-1
2
data_a5
-1
2
data_a4
-1
2
data_a3
-1
2
data_a2
-1
2
data_a1
-1
2
data_a0
-1
2
}
# memory_file {
Img_DATA.hex
47202b227d14bedb6328ac62948702f
}
# macro_sequence

# end
# entity
decode_1qa
# storage
db|DE2_SD_Card_Audio.(49).cnf
db|DE2_SD_Card_Audio.(49).cnf
# case_insensitive
# source_file
db|decode_1qa.tdf
87b41a455d48f0eba79129b03027488c
7
# used_port {
eq9
-1
3
eq8
-1
3
eq74
-1
3
eq73
-1
3
eq72
-1
3
eq71
-1
3
eq70
-1
3
eq7
-1
3
eq69
-1
3
eq68
-1
3
eq67
-1
3
eq66
-1
3
eq65
-1
3
eq64
-1
3
eq63
-1
3
eq62
-1
3
eq61
-1
3
eq60
-1
3
eq6
-1
3
eq59
-1
3
eq58
-1
3
eq57
-1
3
eq56
-1
3
eq55
-1
3
eq54
-1
3
eq53
-1
3
eq52
-1
3
eq51
-1
3
eq50
-1
3
eq5
-1
3
eq49
-1
3
eq48
-1
3
eq47
-1
3
eq46
-1
3
eq45
-1
3
eq44
-1
3
eq43
-1
3
eq42
-1
3
eq41
-1
3
eq40
-1
3
eq4
-1
3
eq39
-1
3
eq38
-1
3
eq37
-1
3
eq36
-1
3
eq35
-1
3
eq34
-1
3
eq33
-1
3
eq32
-1
3
eq31
-1
3
eq30
-1
3
eq3
-1
3
eq29
-1
3
eq28
-1
3
eq27
-1
3
eq26
-1
3
eq25
-1
3
eq24
-1
3
eq23
-1
3
eq22
-1
3
eq21
-1
3
eq20
-1
3
eq2
-1
3
eq19
-1
3
eq18
-1
3
eq17
-1
3
eq16
-1
3
eq15
-1
3
eq14
-1
3
eq13
-1
3
eq12
-1
3
eq11
-1
3
eq10
-1
3
eq1
-1
3
eq0
-1
3
enable
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
decode_1qa
# storage
db|DE2_SD_Card_Audio.(50).cnf
db|DE2_SD_Card_Audio.(50).cnf
# case_insensitive
# source_file
db|decode_1qa.tdf
87b41a455d48f0eba79129b03027488c
7
# used_port {
eq9
-1
3
eq8
-1
3
eq74
-1
3
eq73
-1
3
eq72
-1
3
eq71
-1
3
eq70
-1
3
eq7
-1
3
eq69
-1
3
eq68
-1
3
eq67
-1
3
eq66
-1
3
eq65
-1
3
eq64
-1
3
eq63
-1
3
eq62
-1
3
eq61
-1
3
eq60
-1
3
eq6
-1
3
eq59
-1
3
eq58
-1
3
eq57
-1
3
eq56
-1
3
eq55
-1
3
eq54
-1
3
eq53
-1
3
eq52
-1
3
eq51
-1
3
eq50
-1
3
eq5
-1
3
eq49
-1
3
eq48
-1
3
eq47
-1
3
eq46
-1
3
eq45
-1
3
eq44
-1
3
eq43
-1
3
eq42
-1
3
eq41
-1
3
eq40
-1
3
eq4
-1
3
eq39
-1
3
eq38
-1
3
eq37
-1
3
eq36
-1
3
eq35
-1
3
eq34
-1
3
eq33
-1
3
eq32
-1
3
eq31
-1
3
eq30
-1
3
eq3
-1
3
eq29
-1
3
eq28
-1
3
eq27
-1
3
eq26
-1
3
eq25
-1
3
eq24
-1
3
eq23
-1
3
eq22
-1
3
eq21
-1
3
eq20
-1
3
eq2
-1
3
eq19
-1
3
eq18
-1
3
eq17
-1
3
eq16
-1
3
eq15
-1
3
eq14
-1
3
eq13
-1
3
eq12
-1
3
eq11
-1
3
eq10
-1
3
eq1
-1
3
eq0
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
enable
-1
2
}
# macro_sequence

# end
# entity
mux_hkb
# storage
db|DE2_SD_Card_Audio.(51).cnf
db|DE2_SD_Card_Audio.(51).cnf
# case_insensitive
# source_file
db|mux_hkb.tdf
b39ed9a87c1341cc6a2c5c2c2ae1336
7
# used_port {
sel6
-1
3
sel5
-1
3
sel4
-1
3
sel3
-1
3
sel2
-1
3
sel1
-1
3
sel0
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
data99
-1
3
data98
-1
3
data97
-1
3
data96
-1
3
data95
-1
3
data94
-1
3
data93
-1
3
data92
-1
3
data91
-1
3
data90
-1
3
data9
-1
3
data89
-1
3
data88
-1
3
data87
-1
3
data86
-1
3
data85
-1
3
data84
-1
3
data83
-1
3
data82
-1
3
data81
-1
3
data80
-1
3
data8
-1
3
data79
-1
3
data78
-1
3
data77
-1
3
data76
-1
3
data75
-1
3
data74
-1
3
data73
-1
3
data72
-1
3
data71
-1
3
data70
-1
3
data7
-1
3
data69
-1
3
data68
-1
3
data67
-1
3
data66
-1
3
data65
-1
3
data64
-1
3
data63
-1
3
data62
-1
3
data61
-1
3
data60
-1
3
data6
-1
3
data599
-1
3
data598
-1
3
data597
-1
3
data596
-1
3
data595
-1
3
data594
-1
3
data593
-1
3
data592
-1
3
data591
-1
3
data590
-1
3
data59
-1
3
data589
-1
3
data588
-1
3
data587
-1
3
data586
-1
3
data585
-1
3
data584
-1
3
data583
-1
3
data582
-1
3
data581
-1
3
data580
-1
3
data58
-1
3
data579
-1
3
data578
-1
3
data577
-1
3
data576
-1
3
data575
-1
3
data574
-1
3
data573
-1
3
data572
-1
3
data571
-1
3
data570
-1
3
data57
-1
3
data569
-1
3
data568
-1
3
data567
-1
3
data566
-1
3
data565
-1
3
data564
-1
3
data563
-1
3
data562
-1
3
data561
-1
3
data560
-1
3
data56
-1
3
data559
-1
3
data558
-1
3
data557
-1
3
data556
-1
3
data555
-1
3
data554
-1
3
data553
-1
3
data552
-1
3
data551
-1
3
data550
-1
3
data55
-1
3
data549
-1
3
data548
-1
3
data547
-1
3
data546
-1
3
data545
-1
3
data544
-1
3
data543
-1
3
data542
-1
3
data541
-1
3
data540
-1
3
data54
-1
3
data539
-1
3
data538
-1
3
data537
-1
3
data536
-1
3
data535
-1
3
data534
-1
3
data533
-1
3
data532
-1
3
data531
-1
3
data530
-1
3
data53
-1
3
data529
-1
3
data528
-1
3
data527
-1
3
data526
-1
3
data525
-1
3
data524
-1
3
data523
-1
3
data522
-1
3
data521
-1
3
data520
-1
3
data52
-1
3
data519
-1
3
data518
-1
3
data517
-1
3
data516
-1
3
data515
-1
3
data514
-1
3
data513
-1
3
data512
-1
3
data511
-1
3
data510
-1
3
data51
-1
3
data509
-1
3
data508
-1
3
data507
-1
3
data506
-1
3
data505
-1
3
data504
-1
3
data503
-1
3
data502
-1
3
data501
-1
3
data500
-1
3
data50
-1
3
data5
-1
3
data499
-1
3
data498
-1
3
data497
-1
3
data496
-1
3
data495
-1
3
data494
-1
3
data493
-1
3
data492
-1
3
data491
-1
3
data490
-1
3
data49
-1
3
data489
-1
3
data488
-1
3
data487
-1
3
data486
-1
3
data485
-1
3
data484
-1
3
data483
-1
3
data482
-1
3
data481
-1
3
data480
-1
3
data48
-1
3
data479
-1
3
data478
-1
3
data477
-1
3
data476
-1
3
data475
-1
3
data474
-1
3
data473
-1
3
data472
-1
3
data471
-1
3
data470
-1
3
data47
-1
3
data469
-1
3
data468
-1
3
data467
-1
3
data466
-1
3
data465
-1
3
data464
-1
3
data463
-1
3
data462
-1
3
data461
-1
3
data460
-1
3
data46
-1
3
data459
-1
3
data458
-1
3
data457
-1
3
data456
-1
3
data455
-1
3
data454
-1
3
data453
-1
3
data452
-1
3
data451
-1
3
data450
-1
3
data45
-1
3
data449
-1
3
data448
-1
3
data447
-1
3
data446
-1
3
data445
-1
3
data444
-1
3
data443
-1
3
data442
-1
3
data441
-1
3
data440
-1
3
data44
-1
3
data439
-1
3
data438
-1
3
data437
-1
3
data436
-1
3
data435
-1
3
data434
-1
3
data433
-1
3
data432
-1
3
data431
-1
3
data430
-1
3
data43
-1
3
data429
-1
3
data428
-1
3
data427
-1
3
data426
-1
3
data425
-1
3
data424
-1
3
data423
-1
3
data422
-1
3
data421
-1
3
data420
-1
3
data42
-1
3
data419
-1
3
data418
-1
3
data417
-1
3
data416
-1
3
data415
-1
3
data414
-1
3
data413
-1
3
data412
-1
3
data411
-1
3
data410
-1
3
data41
-1
3
data409
-1
3
data408
-1
3
data407
-1
3
data406
-1
3
data405
-1
3
data404
-1
3
data403
-1
3
data402
-1
3
data401
-1
3
data400
-1
3
data40
-1
3
data4
-1
3
data399
-1
3
data398
-1
3
data397
-1
3
data396
-1
3
data395
-1
3
data394
-1
3
data393
-1
3
data392
-1
3
data391
-1
3
data390
-1
3
data39
-1
3
data389
-1
3
data388
-1
3
data387
-1
3
data386
-1
3
data385
-1
3
data384
-1
3
data383
-1
3
data382
-1
3
data381
-1
3
data380
-1
3
data38
-1
3
data379
-1
3
data378
-1
3
data377
-1
3
data376
-1
3
data375
-1
3
data374
-1
3
data373
-1
3
data372
-1
3
data371
-1
3
data370
-1
3
data37
-1
3
data369
-1
3
data368
-1
3
data367
-1
3
data366
-1
3
data365
-1
3
data364
-1
3
data363
-1
3
data362
-1
3
data361
-1
3
data360
-1
3
data36
-1
3
data359
-1
3
data358
-1
3
data357
-1
3
data356
-1
3
data355
-1
3
data354
-1
3
data353
-1
3
data352
-1
3
data351
-1
3
data350
-1
3
data35
-1
3
data349
-1
3
data348
-1
3
data347
-1
3
data346
-1
3
data345
-1
3
data344
-1
3
data343
-1
3
data342
-1
3
data341
-1
3
data340
-1
3
data34
-1
3
data339
-1
3
data338
-1
3
data337
-1
3
data336
-1
3
data335
-1
3
data334
-1
3
data333
-1
3
data332
-1
3
data331
-1
3
data330
-1
3
data33
-1
3
data329
-1
3
data328
-1
3
data327
-1
3
data326
-1
3
data325
-1
3
data324
-1
3
data323
-1
3
data322
-1
3
data321
-1
3
data320
-1
3
data32
-1
3
data319
-1
3
data318
-1
3
data317
-1
3
data316
-1
3
data315
-1
3
data314
-1
3
data313
-1
3
data312
-1
3
data311
-1
3
data310
-1
3
data31
-1
3
data309
-1
3
data308
-1
3
data307
-1
3
data306
-1
3
data305
-1
3
data304
-1
3
data303
-1
3
data302
-1
3
data301
-1
3
data300
-1
3
data30
-1
3
data3
-1
3
data299
-1
3
data298
-1
3
data297
-1
3
data296
-1
3
data295
-1
3
data294
-1
3
data293
-1
3
data292
-1
3
data291
-1
3
data290
-1
3
data29
-1
3
data289
-1
3
data288
-1
3
data287
-1
3
data286
-1
3
data285
-1
3
data284
-1
3
data283
-1
3
data282
-1
3
data281
-1
3
data280
-1
3
data28
-1
3
data279
-1
3
data278
-1
3
data277
-1
3
data276
-1
3
data275
-1
3
data274
-1
3
data273
-1
3
data272
-1
3
data271
-1
3
data270
-1
3
data27
-1
3
data269
-1
3
data268
-1
3
data267
-1
3
data266
-1
3
data265
-1
3
data264
-1
3
data263
-1
3
data262
-1
3
data261
-1
3
data260
-1
3
data26
-1
3
data259
-1
3
data258
-1
3
data257
-1
3
data256
-1
3
data255
-1
3
data254
-1
3
data253
-1
3
data252
-1
3
data251
-1
3
data250
-1
3
data25
-1
3
data249
-1
3
data248
-1
3
data247
-1
3
data246
-1
3
data245
-1
3
data244
-1
3
data243
-1
3
data242
-1
3
data241
-1
3
data240
-1
3
data24
-1
3
data239
-1
3
data238
-1
3
data237
-1
3
data236
-1
3
data235
-1
3
data234
-1
3
data233
-1
3
data232
-1
3
data231
-1
3
data230
-1
3
data23
-1
3
data229
-1
3
data228
-1
3
data227
-1
3
data226
-1
3
data225
-1
3
data224
-1
3
data223
-1
3
data222
-1
3
data221
-1
3
data220
-1
3
data22
-1
3
data219
-1
3
data218
-1
3
data217
-1
3
data216
-1
3
data215
-1
3
data214
-1
3
data213
-1
3
data212
-1
3
data211
-1
3
data210
-1
3
data21
-1
3
data209
-1
3
data208
-1
3
data207
-1
3
data206
-1
3
data205
-1
3
data204
-1
3
data203
-1
3
data202
-1
3
data201
-1
3
data200
-1
3
data20
-1
3
data2
-1
3
data199
-1
3
data198
-1
3
data197
-1
3
data196
-1
3
data195
-1
3
data194
-1
3
data193
-1
3
data192
-1
3
data191
-1
3
data190
-1
3
data19
-1
3
data189
-1
3
data188
-1
3
data187
-1
3
data186
-1
3
data185
-1
3
data184
-1
3
data183
-1
3
data182
-1
3
data181
-1
3
data180
-1
3
data18
-1
3
data179
-1
3
data178
-1
3
data177
-1
3
data176
-1
3
data175
-1
3
data174
-1
3
data173
-1
3
data172
-1
3
data171
-1
3
data170
-1
3
data17
-1
3
data169
-1
3
data168
-1
3
data167
-1
3
data166
-1
3
data165
-1
3
data164
-1
3
data163
-1
3
data162
-1
3
data161
-1
3
data160
-1
3
data16
-1
3
data159
-1
3
data158
-1
3
data157
-1
3
data156
-1
3
data155
-1
3
data154
-1
3
data153
-1
3
data152
-1
3
data151
-1
3
data150
-1
3
data15
-1
3
data149
-1
3
data148
-1
3
data147
-1
3
data146
-1
3
data145
-1
3
data144
-1
3
data143
-1
3
data142
-1
3
data141
-1
3
data140
-1
3
data14
-1
3
data139
-1
3
data138
-1
3
data137
-1
3
data136
-1
3
data135
-1
3
data134
-1
3
data133
-1
3
data132
-1
3
data131
-1
3
data130
-1
3
data13
-1
3
data129
-1
3
data128
-1
3
data127
-1
3
data126
-1
3
data125
-1
3
data124
-1
3
data123
-1
3
data122
-1
3
data121
-1
3
data120
-1
3
data12
-1
3
data119
-1
3
data118
-1
3
data117
-1
3
data116
-1
3
data115
-1
3
data114
-1
3
data113
-1
3
data112
-1
3
data111
-1
3
data110
-1
3
data11
-1
3
data109
-1
3
data108
-1
3
data107
-1
3
data106
-1
3
data105
-1
3
data104
-1
3
data103
-1
3
data102
-1
3
data101
-1
3
data100
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
mux_akb
# storage
db|DE2_SD_Card_Audio.(52).cnf
db|DE2_SD_Card_Audio.(52).cnf
# case_insensitive
# source_file
db|mux_akb.tdf
1fb6f23cb34c77c2c1941659dc4df36f
7
# used_port {
sel6
-1
3
sel5
-1
3
sel4
-1
3
sel3
-1
3
sel2
-1
3
sel1
-1
3
sel0
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data74
-1
3
data73
-1
3
data72
-1
3
data71
-1
3
data70
-1
3
data7
-1
3
data69
-1
3
data68
-1
3
data67
-1
3
data66
-1
3
data65
-1
3
data64
-1
3
data63
-1
3
data62
-1
3
data61
-1
3
data60
-1
3
data6
-1
3
data59
-1
3
data58
-1
3
data57
-1
3
data56
-1
3
data55
-1
3
data54
-1
3
data53
-1
3
data52
-1
3
data51
-1
3
data50
-1
3
data5
-1
3
data49
-1
3
data48
-1
3
data47
-1
3
data46
-1
3
data45
-1
3
data44
-1
3
data43
-1
3
data42
-1
3
data41
-1
3
data40
-1
3
data4
-1
3
data39
-1
3
data38
-1
3
data37
-1
3
data36
-1
3
data35
-1
3
data34
-1
3
data33
-1
3
data32
-1
3
data31
-1
3
data30
-1
3
data3
-1
3
data29
-1
3
data28
-1
3
data27
-1
3
data26
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(61).cnf
db|DE2_SD_Card_Audio.(61).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
10
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
1024
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
10
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
1024
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_qed1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# macro_sequence

# end
# entity
altsyncram_qed1
# storage
db|DE2_SD_Card_Audio.(62).cnf
db|DE2_SD_Card_Audio.(62).cnf
# case_insensitive
# source_file
db|altsyncram_qed1.tdf
e6f413728a6535e6de8bd1964dfb93
7
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(64).cnf
db|DE2_SD_Card_Audio.(64).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
21
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
7
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
128
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
21
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
7
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
128
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_0_ic_tag_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_d5g1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(67).cnf
db|DE2_SD_Card_Audio.(67).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
2
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
256
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
2
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
256
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_0_bht_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_8pf1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(70).cnf
db|DE2_SD_Card_Audio.(70).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
32
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
32
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_0_rf_ram_a.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_87f1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altsyncram_87f1
# storage
db|DE2_SD_Card_Audio.(71).cnf
db|DE2_SD_Card_Audio.(71).cnf
# case_insensitive
# source_file
db|altsyncram_87f1.tdf
de7f579478471b751809237352abd4a
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_0_rf_ram_a.mif
55d713de4db17accc269d4dfa42c9c44
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_87f1:auto_generated
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(73).cnf
db|DE2_SD_Card_Audio.(73).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
32
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
32
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_0_rf_ram_b.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_97f1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altsyncram_97f1
# storage
db|DE2_SD_Card_Audio.(74).cnf
db|DE2_SD_Card_Audio.(74).cnf
# case_insensitive
# source_file
db|altsyncram_97f1.tdf
c9c6a876d3566c76a93e6f42e8341da2
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_0_rf_ram_b.mif
55d713de4db17accc269d4dfa42c9c44
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_97f1:auto_generated
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(76).cnf
db|DE2_SD_Card_Audio.(76).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
9
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
512
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
16
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
9
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
512
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_0_dc_tag_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_1g22
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
q_b
-1
3
q_a
-1
3
data_b
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
wren_a
-1
1
data_a
-1
1
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(79).cnf
db|DE2_SD_Card_Audio.(79).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
9
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
512
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
9
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
512
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
4
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_a422
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
q_b
-1
3
q_a
-1
3
data_b
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
byteena_b
-1
3
address_b
-1
3
address_a
-1
3
wren_a
-1
1
data_a
-1
1
}
# macro_sequence

# end
# entity
altsyncram_a422
# storage
db|DE2_SD_Card_Audio.(80).cnf
db|DE2_SD_Card_Audio.(80).cnf
# case_insensitive
# source_file
db|altsyncram_a422.tdf
465753e088d941a139d1268560c5c484
7
# used_port {
wren_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b31
-1
3
data_b30
-1
3
data_b3
-1
3
data_b29
-1
3
data_b28
-1
3
data_b27
-1
3
data_b26
-1
3
data_b25
-1
3
data_b24
-1
3
data_b23
-1
3
data_b22
-1
3
data_b21
-1
3
data_b20
-1
3
data_b2
-1
3
data_b19
-1
3
data_b18
-1
3
data_b17
-1
3
data_b16
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
byteena_b3
-1
3
byteena_b2
-1
3
byteena_b1
-1
3
byteena_b0
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altmult_add
# storage
db|DE2_SD_Card_Audio.(82).cnf
db|DE2_SD_Card_Audio.(82).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altmult_add.tdf
73bd75fad5a4f124a3816832830fc9
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
ACCUM_DIRECTION
ADD
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ACCUMULATOR
NO
PARAMETER_UNKNOWN
DEF
ADDER1_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDER3_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1
ACLR0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_REGISTER1
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ADDER
NO
PARAMETER_UNKNOWN
DEF
CHAINOUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATION
NO
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_CIRCUITRY
YES
PARAMETER_UNKNOWN
USR
DSP_BLOCK_BALANCING
AUTO
PARAMETER_UNKNOWN
USR
EXTRA_LATENCY
0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_A1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_B1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A0
DATAA
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_A1
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A2
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A3
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B0
DATAB
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_B1
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B2
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B3
DATAB
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_ACLR
ACLR2
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER1_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
MULTIPLIER23_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER23_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER3_DIRECTION
ADD
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR0
ACLR0
PARAMETER_UNKNOWN
USR
MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR2
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER0
CLOCK0
PARAMETER_UNKNOWN
USR
MULTIPLIER_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER2
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
NUMBER_OF_MULTIPLIERS
1
PARAMETER_SIGNED_DEC
USR
OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
USR
OUTPUT_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_TYPE
NEAREST_INTEGER
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_TYPE
ASYMMETRIC
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATION
NO
PARAMETER_UNKNOWN
DEF
port_addnsub1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
port_addnsub3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CHAINOUT_SAT_IS_OVERFLOW
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT0_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT1_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT2_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT3_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_OUTPUT_IS_OVERFLOW
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
port_signa
PORT_UNUSED
PARAMETER_UNKNOWN
USR
port_signb
PORT_UNUSED
PARAMETER_UNKNOWN
USR
REPRESENTATION_A
UNSIGNED
PARAMETER_UNKNOWN
USR
REPRESENTATION_B
UNSIGNED
PARAMETER_UNKNOWN
USR
ROTATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ROTATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ROTATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
WIDTH_MSB
17
PARAMETER_UNKNOWN
DEF
WIDTH_SATURATE_SIGN
1
PARAMETER_UNKNOWN
DEF
SCANOUTA_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SCANOUTA_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
DEF
SHIFT_MODE
NO
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SIGNED_ACLR_A
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_ACLR_B
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_PIPELINE_ACLR_A
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_ACLR_B
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_REGISTER_A
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_REGISTER_B
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_SIGNED_DEC
USR
WIDTH_B
16
PARAMETER_SIGNED_DEC
USR
WIDTH_CHAININ
1
PARAMETER_UNKNOWN
DEF
WIDTH_RESULT
32
PARAMETER_SIGNED_DEC
USR
ZERO_CHAINOUT_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_CHAINOUT_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mult_add_4cr2
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
WIDTH_C
22
PARAMETER_UNKNOWN
DEF
LOADCONST_VALUE
64
PARAMETER_UNKNOWN
DEF
PREADDER_MODE
SIMPLE
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_0
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_1
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_2
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_3
ADD
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_C0
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_C0
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL0_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL1_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL2_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL3_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL0_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL1_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL2_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL3_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_DELAY1
CLOCK0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_DELAY3
CLOCK0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_ACLR1
ACLR0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_ACLR3
ACLR0
PARAMETER_UNKNOWN
DEF
COEF0_0
0
PARAMETER_UNKNOWN
DEF
COEF0_1
0
PARAMETER_UNKNOWN
DEF
COEF0_2
0
PARAMETER_UNKNOWN
DEF
COEF0_3
0
PARAMETER_UNKNOWN
DEF
COEF0_4
0
PARAMETER_UNKNOWN
DEF
COEF0_5
0
PARAMETER_UNKNOWN
DEF
COEF0_6
0
PARAMETER_UNKNOWN
DEF
COEF0_7
0
PARAMETER_UNKNOWN
DEF
COEF1_0
0
PARAMETER_UNKNOWN
DEF
COEF1_1
0
PARAMETER_UNKNOWN
DEF
COEF1_2
0
PARAMETER_UNKNOWN
DEF
COEF1_3
0
PARAMETER_UNKNOWN
DEF
COEF1_4
0
PARAMETER_UNKNOWN
DEF
COEF1_5
0
PARAMETER_UNKNOWN
DEF
COEF1_6
0
PARAMETER_UNKNOWN
DEF
COEF1_7
0
PARAMETER_UNKNOWN
DEF
COEF2_0
0
PARAMETER_UNKNOWN
DEF
COEF2_1
0
PARAMETER_UNKNOWN
DEF
COEF2_2
0
PARAMETER_UNKNOWN
DEF
COEF2_3
0
PARAMETER_UNKNOWN
DEF
COEF2_4
0
PARAMETER_UNKNOWN
DEF
COEF2_5
0
PARAMETER_UNKNOWN
DEF
COEF2_6
0
PARAMETER_UNKNOWN
DEF
COEF2_7
0
PARAMETER_UNKNOWN
DEF
COEF3_0
0
PARAMETER_UNKNOWN
DEF
COEF3_1
0
PARAMETER_UNKNOWN
DEF
COEF3_2
0
PARAMETER_UNKNOWN
DEF
COEF3_3
0
PARAMETER_UNKNOWN
DEF
COEF3_4
0
PARAMETER_UNKNOWN
DEF
COEF3_5
0
PARAMETER_UNKNOWN
DEF
COEF3_6
0
PARAMETER_UNKNOWN
DEF
COEF3_7
0
PARAMETER_UNKNOWN
DEF
WIDTH_COEF
18
PARAMETER_UNKNOWN
DEF
}
# used_port {
result
-1
3
datab
-1
3
dataa
-1
3
clock0
-1
3
aclr0
-1
3
ena0
-1
2
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1
}
# macro_sequence

# end
# entity
mult_add_4cr2
# storage
db|DE2_SD_Card_Audio.(83).cnf
db|DE2_SD_Card_Audio.(83).cnf
# case_insensitive
# source_file
db|mult_add_4cr2.tdf
b8eb5d1d22f6a26fccb1bdd8cedd71c4
7
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result31
-1
3
result30
-1
3
result3
-1
3
result29
-1
3
result28
-1
3
result27
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock0
-1
3
aclr0
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated
}
# macro_sequence

# end
# entity
ded_mult_2o81
# storage
db|DE2_SD_Card_Audio.(84).cnf
db|DE2_SD_Card_Audio.(84).cnf
# case_insensitive
# source_file
db|ded_mult_2o81.tdf
72a5219f1f4ed3ef411f76e395dc1e
7
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result31
-1
3
result30
-1
3
result3
-1
3
result29
-1
3
result28
-1
3
result27
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
ena0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock0
-1
3
aclr0
-1
3
aclr3
-1
1
aclr2
-1
1
aclr1
-1
1
ena3
-1
2
ena2
-1
2
ena1
-1
2
clock3
-1
2
clock2
-1
2
clock1
-1
2
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1
}
# macro_sequence

# end
# entity
dffpipe_93c
# storage
db|DE2_SD_Card_Audio.(85).cnf
db|DE2_SD_Card_Audio.(85).cnf
# case_insensitive
# source_file
db|dffpipe_93c.tdf
e1907047f7f19bdc22551276fecfef3
7
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q31
-1
3
q30
-1
3
q3
-1
3
q29
-1
3
q28
-1
3
q27
-1
3
q26
-1
3
q25
-1
3
q24
-1
3
q23
-1
3
q22
-1
3
q21
-1
3
q20
-1
3
q2
-1
3
q19
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
d9
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d31
-1
3
d30
-1
3
d3
-1
3
d29
-1
3
d28
-1
3
d27
-1
3
d26
-1
3
d25
-1
3
d24
-1
3
d23
-1
3
d22
-1
3
d21
-1
3
d20
-1
3
d2
-1
3
d19
-1
3
d18
-1
3
d17
-1
3
d16
-1
3
d15
-1
3
d14
-1
3
d13
-1
3
d12
-1
3
d11
-1
3
d10
-1
3
d1
-1
3
d0
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result
}
# macro_sequence

# end
# entity
altmult_add
# storage
db|DE2_SD_Card_Audio.(86).cnf
db|DE2_SD_Card_Audio.(86).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altmult_add.tdf
73bd75fad5a4f124a3816832830fc9
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
ACCUM_DIRECTION
ADD
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ACCUMULATOR
NO
PARAMETER_UNKNOWN
DEF
ADDER1_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDER3_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1
ACLR0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_REGISTER1
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ADDER
NO
PARAMETER_UNKNOWN
DEF
CHAINOUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATION
NO
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_CIRCUITRY
YES
PARAMETER_UNKNOWN
USR
DSP_BLOCK_BALANCING
AUTO
PARAMETER_UNKNOWN
USR
EXTRA_LATENCY
0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_A1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_B1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A0
DATAA
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_A1
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A2
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A3
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B0
DATAB
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_B1
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B2
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B3
DATAB
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_ACLR
ACLR2
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER1_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
MULTIPLIER23_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER23_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER3_DIRECTION
ADD
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR0
ACLR0
PARAMETER_UNKNOWN
USR
MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR2
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER0
CLOCK0
PARAMETER_UNKNOWN
USR
MULTIPLIER_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER2
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
NUMBER_OF_MULTIPLIERS
1
PARAMETER_SIGNED_DEC
USR
OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
USR
OUTPUT_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_TYPE
NEAREST_INTEGER
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_TYPE
ASYMMETRIC
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATION
NO
PARAMETER_UNKNOWN
DEF
port_addnsub1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
port_addnsub3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CHAINOUT_SAT_IS_OVERFLOW
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT0_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT1_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT2_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT3_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_OUTPUT_IS_OVERFLOW
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
port_signa
PORT_UNUSED
PARAMETER_UNKNOWN
USR
port_signb
PORT_UNUSED
PARAMETER_UNKNOWN
USR
REPRESENTATION_A
UNSIGNED
PARAMETER_UNKNOWN
USR
REPRESENTATION_B
UNSIGNED
PARAMETER_UNKNOWN
USR
ROTATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ROTATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ROTATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
WIDTH_MSB
17
PARAMETER_UNKNOWN
DEF
WIDTH_SATURATE_SIGN
1
PARAMETER_UNKNOWN
DEF
SCANOUTA_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SCANOUTA_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
DEF
SHIFT_MODE
NO
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SIGNED_ACLR_A
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_ACLR_B
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_PIPELINE_ACLR_A
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_ACLR_B
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_REGISTER_A
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_REGISTER_B
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_SIGNED_DEC
USR
WIDTH_B
16
PARAMETER_SIGNED_DEC
USR
WIDTH_CHAININ
1
PARAMETER_UNKNOWN
DEF
WIDTH_RESULT
16
PARAMETER_SIGNED_DEC
USR
ZERO_CHAINOUT_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_CHAINOUT_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mult_add_6cr2
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
WIDTH_C
22
PARAMETER_UNKNOWN
DEF
LOADCONST_VALUE
64
PARAMETER_UNKNOWN
DEF
PREADDER_MODE
SIMPLE
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_0
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_1
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_2
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_3
ADD
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_C0
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_C0
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL0_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL1_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL2_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL3_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL0_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL1_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL2_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL3_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_DELAY1
CLOCK0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_DELAY3
CLOCK0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_ACLR1
ACLR0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_ACLR3
ACLR0
PARAMETER_UNKNOWN
DEF
COEF0_0
0
PARAMETER_UNKNOWN
DEF
COEF0_1
0
PARAMETER_UNKNOWN
DEF
COEF0_2
0
PARAMETER_UNKNOWN
DEF
COEF0_3
0
PARAMETER_UNKNOWN
DEF
COEF0_4
0
PARAMETER_UNKNOWN
DEF
COEF0_5
0
PARAMETER_UNKNOWN
DEF
COEF0_6
0
PARAMETER_UNKNOWN
DEF
COEF0_7
0
PARAMETER_UNKNOWN
DEF
COEF1_0
0
PARAMETER_UNKNOWN
DEF
COEF1_1
0
PARAMETER_UNKNOWN
DEF
COEF1_2
0
PARAMETER_UNKNOWN
DEF
COEF1_3
0
PARAMETER_UNKNOWN
DEF
COEF1_4
0
PARAMETER_UNKNOWN
DEF
COEF1_5
0
PARAMETER_UNKNOWN
DEF
COEF1_6
0
PARAMETER_UNKNOWN
DEF
COEF1_7
0
PARAMETER_UNKNOWN
DEF
COEF2_0
0
PARAMETER_UNKNOWN
DEF
COEF2_1
0
PARAMETER_UNKNOWN
DEF
COEF2_2
0
PARAMETER_UNKNOWN
DEF
COEF2_3
0
PARAMETER_UNKNOWN
DEF
COEF2_4
0
PARAMETER_UNKNOWN
DEF
COEF2_5
0
PARAMETER_UNKNOWN
DEF
COEF2_6
0
PARAMETER_UNKNOWN
DEF
COEF2_7
0
PARAMETER_UNKNOWN
DEF
COEF3_0
0
PARAMETER_UNKNOWN
DEF
COEF3_1
0
PARAMETER_UNKNOWN
DEF
COEF3_2
0
PARAMETER_UNKNOWN
DEF
COEF3_3
0
PARAMETER_UNKNOWN
DEF
COEF3_4
0
PARAMETER_UNKNOWN
DEF
COEF3_5
0
PARAMETER_UNKNOWN
DEF
COEF3_6
0
PARAMETER_UNKNOWN
DEF
COEF3_7
0
PARAMETER_UNKNOWN
DEF
WIDTH_COEF
18
PARAMETER_UNKNOWN
DEF
}
# used_port {
result
-1
3
datab
-1
3
dataa
-1
3
clock0
-1
3
aclr0
-1
3
ena0
-1
2
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2
}
# macro_sequence

# end
# entity
mult_add_6cr2
# storage
db|DE2_SD_Card_Audio.(87).cnf
db|DE2_SD_Card_Audio.(87).cnf
# case_insensitive
# source_file
db|mult_add_6cr2.tdf
ad4e12a197b017d44458a0f62bf23510
7
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock0
-1
3
aclr0
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(92).cnf
db|DE2_SD_Card_Audio.(92).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
256
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
256
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
4
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_0_ociram_default_contents.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_c572
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b
-1
3
q_a
-1
3
data_b
-1
3
data_a
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
byteena_a
-1
3
address_b
-1
3
address_a
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
cpu_0_oci_test_bench
# storage
db|DE2_SD_Card_Audio.(105).cnf
db|DE2_SD_Card_Audio.(105).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0_oci_test_bench.v
fca913b896f99c817797c066a827d2bf
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_oci_test_bench:the_cpu_0_oci_test_bench
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(109).cnf
db|DE2_SD_Card_Audio.(109).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
36
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
7
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
128
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
36
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
7
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
128
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_e502
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b
-1
3
q_a
-1
3
data_b
-1
3
data_a
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altsyncram_e502
# storage
db|DE2_SD_Card_Audio.(110).cnf
db|DE2_SD_Card_Audio.(110).cnf
# case_insensitive
# source_file
db|altsyncram_e502.tdf
217292c7e6c17b7a6bb3301381a27d17
7
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a35
-1
3
q_a34
-1
3
q_a33
-1
3
q_a32
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b35
-1
3
data_b34
-1
3
data_b33
-1
3
data_b32
-1
3
data_b31
-1
3
data_b30
-1
3
data_b3
-1
3
data_b29
-1
3
data_b28
-1
3
data_b27
-1
3
data_b26
-1
3
data_b25
-1
3
data_b24
-1
3
data_b23
-1
3
data_b22
-1
3
data_b21
-1
3
data_b20
-1
3
data_b2
-1
3
data_b19
-1
3
data_b18
-1
3
data_b17
-1
3
data_b16
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated
}
# macro_sequence

# end
# entity
cpu_0_jtag_debug_module_wrapper
# storage
db|DE2_SD_Card_Audio.(111).cnf
db|DE2_SD_Card_Audio.(111).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0_jtag_debug_module_wrapper.v
e6425ce1be773fba13e1fba1708320fb
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper
}
# macro_sequence

# end
# entity
cpu_0_jtag_debug_module_tck
# storage
db|DE2_SD_Card_Audio.(112).cnf
db|DE2_SD_Card_Audio.(112).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0_jtag_debug_module_tck.v
3c662ef1472f8344fd1845f12649c780
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck
}
# macro_sequence

# end
# entity
altera_std_synchronizer
# storage
db|DE2_SD_Card_Audio.(113).cnf
db|DE2_SD_Card_Audio.(113).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altera_std_synchronizer.v
d77aac9f8f4ad0b3b3f1ef8b7ca34f8a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
depth
2
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3
system_0:u0|system_0_clock_0:the_system_0_clock_0|altera_std_synchronizer:the_altera_std_synchronizer
system_0:u0|system_0_clock_0:the_system_0_clock_0|altera_std_synchronizer:the_altera_std_synchronizer1
system_0:u0|system_0_clock_0:the_system_0_clock_0|altera_std_synchronizer:the_altera_std_synchronizer2
system_0:u0|system_0_clock_0:the_system_0_clock_0|altera_std_synchronizer:the_altera_std_synchronizer3
system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer
}
# macro_sequence

# end
# entity
cpu_0_jtag_debug_module_sysclk
# storage
db|DE2_SD_Card_Audio.(114).cnf
db|DE2_SD_Card_Audio.(114).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0_jtag_debug_module_sysclk.v
e3f5fbcb65faf65bb6b87b3ba8e68cd
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk
}
# macro_sequence

# end
# entity
sld_virtual_jtag_basic
# storage
db|DE2_SD_Card_Audio.(115).cnf
db|DE2_SD_Card_Audio.(115).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|sld_virtual_jtag_basic.v
a594e070231d4480d281add39f7efa5f
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
sld_mfg_id
70
PARAMETER_SIGNED_DEC
USR
sld_type_id
34
PARAMETER_SIGNED_DEC
USR
sld_version
3
PARAMETER_SIGNED_DEC
USR
sld_instance_index
0
PARAMETER_SIGNED_DEC
USR
sld_auto_instance_index
YES
PARAMETER_STRING
USR
sld_ir_width
2
PARAMETER_SIGNED_DEC
USR
sld_sim_n_scan
0
PARAMETER_SIGNED_DEC
USR
sld_sim_action

PARAMETER_STRING
USR
sld_sim_total_length
0
PARAMETER_SIGNED_DEC
USR
lpm_type
sld_virtual_jtag_basic
PARAMETER_STRING
DEF
lpm_hint
UNUSED
PARAMETER_STRING
DEF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy
}
# macro_sequence

# end
# entity
sld_virtual_jtag_impl
# storage
db|DE2_SD_Card_Audio.(116).cnf
db|DE2_SD_Card_Audio.(116).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|sld_virtual_jtag_basic.v
a594e070231d4480d281add39f7efa5f
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
sld_mfg_id
70
PARAMETER_SIGNED_DEC
USR
sld_type_id
34
PARAMETER_SIGNED_DEC
USR
sld_version
3
PARAMETER_SIGNED_DEC
USR
sld_instance_index
0
PARAMETER_SIGNED_DEC
USR
sld_auto_instance_index
YES
PARAMETER_STRING
USR
sld_ir_width
2
PARAMETER_SIGNED_DEC
USR
SLD_NODE_INFO
420496896
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst
}
# macro_sequence
MASK_8_BITS255INST_BIT_INDEX0MASK_11_BITS2047MFG_BIT_INDEX8MASK_8_BITS255TYPE_BIT_INDEX19MASK_5_BITS31VERION_BIT_INDEX27
# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(121).cnf
db|DE2_SD_Card_Audio.(121).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
7
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
128
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
epcs_controller_boot_rom_synth.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_ad41
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a
-1
3
clock0
-1
3
address_a
-1
3
}
# hierarchies {
system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom
}
# macro_sequence

# end
# entity
altsyncram_ad41
# storage
db|DE2_SD_Card_Audio.(122).cnf
db|DE2_SD_Card_Audio.(122).cnf
# case_insensitive
# source_file
db|altsyncram_ad41.tdf
7c7c5e5a99a6b91342914f722af840b
7
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
epcs_controller_boot_rom_synth.hex
d86d17f199903c5cf264c7b2416f745
}
# hierarchies {
system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_ad41:auto_generated
}
# macro_sequence

# end
# entity
jtag_uart_0
# storage
db|DE2_SD_Card_Audio.(124).cnf
db|DE2_SD_Card_Audio.(124).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart_0.v
f6745217d120712b1f9b8cd5fa7664e
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0
}
# macro_sequence

# end
# entity
jtag_uart_0_scfifo_w
# storage
db|DE2_SD_Card_Audio.(125).cnf
db|DE2_SD_Card_Audio.(125).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart_0.v
f6745217d120712b1f9b8cd5fa7664e
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w
}
# macro_sequence

# end
# entity
scfifo
# storage
db|DE2_SD_Card_Audio.(126).cnf
db|DE2_SD_Card_Audio.(126).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|scfifo.tdf
38d2ef3d596cd2c32ff7173349fd89ee
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
8
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
64
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
6
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
DEF
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_1n21
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw
-1
3
rdreq
-1
3
q
-1
3
full
-1
3
empty
-1
3
data
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo
}
# macro_sequence

# end
# entity
scfifo_1n21
# storage
db|DE2_SD_Card_Audio.(127).cnf
db|DE2_SD_Card_Audio.(127).cnf
# case_insensitive
# source_file
db|scfifo_1n21.tdf
88d4456827a3c2d44d430a057d2ef30
7
# used_port {
wrreq
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated
}
# macro_sequence

# end
# entity
a_dpfifo_8t21
# storage
db|DE2_SD_Card_Audio.(128).cnf
db|DE2_SD_Card_Audio.(128).cnf
# case_insensitive
# source_file
db|a_dpfifo_8t21.tdf
fdd1682bdde46f9ab46558f268a66caf
7
# used_port {
wreq
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo
}
# macro_sequence

# end
# entity
a_fefifo_7cf
# storage
db|DE2_SD_Card_Audio.(129).cnf
db|DE2_SD_Card_Audio.(129).cnf
# case_insensitive
# source_file
db|a_fefifo_7cf.tdf
ed78757424b9fbf8dcb540fb78c9c9b
7
# used_port {
wreq
-1
3
usedw_out5
-1
3
usedw_out4
-1
3
usedw_out3
-1
3
usedw_out2
-1
3
usedw_out1
-1
3
usedw_out0
-1
3
sclr
-1
3
rreq
-1
3
full
-1
3
empty
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state
}
# macro_sequence

# end
# entity
cntr_rj7
# storage
db|DE2_SD_Card_Audio.(130).cnf
db|DE2_SD_Card_Audio.(130).cnf
# case_insensitive
# source_file
db|cntr_rj7.tdf
738a54762eeff7911036eabe438c59e3
7
# used_port {
updown
-1
3
sclr
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw
}
# macro_sequence

# end
# entity
dpram_5h21
# storage
db|DE2_SD_Card_Audio.(131).cnf
db|DE2_SD_Card_Audio.(131).cnf
# case_insensitive
# source_file
db|dpram_5h21.tdf
2c8261da11bc706c87c1b1afe4824833
7
# used_port {
wren
-1
3
wraddress5
-1
3
wraddress4
-1
3
wraddress3
-1
3
wraddress2
-1
3
wraddress1
-1
3
wraddress0
-1
3
rdaddress5
-1
3
rdaddress4
-1
3
rdaddress3
-1
3
rdaddress2
-1
3
rdaddress1
-1
3
rdaddress0
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclock
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram
}
# macro_sequence

# end
# entity
altsyncram_9tl1
# storage
db|DE2_SD_Card_Audio.(132).cnf
db|DE2_SD_Card_Audio.(132).cnf
# case_insensitive
# source_file
db|altsyncram_9tl1.tdf
6b1cad82d88da2ad5df021b571ff32
7
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2
}
# macro_sequence

# end
# entity
cntr_fjb
# storage
db|DE2_SD_Card_Audio.(133).cnf
db|DE2_SD_Card_Audio.(133).cnf
# case_insensitive
# source_file
db|cntr_fjb.tdf
59eba190849130db9f76d8022202978
7
# used_port {
sclr
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:rd_ptr_count
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:wr_ptr
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:rd_ptr_count
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:wr_ptr
}
# macro_sequence

# end
# entity
jtag_uart_0_scfifo_r
# storage
db|DE2_SD_Card_Audio.(134).cnf
db|DE2_SD_Card_Audio.(134).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart_0.v
f6745217d120712b1f9b8cd5fa7664e
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r
}
# macro_sequence

# end
# entity
alt_jtag_atlantic
# storage
db|DE2_SD_Card_Audio.(135).cnf
db|DE2_SD_Card_Audio.(135).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|alt_jtag_atlantic.v
d86551e05817d27f31e31fe2c53f393e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
INSTANCE_ID
0
PARAMETER_SIGNED_DEC
USR
SLD_NODE_INFO
00001100000000000110111000000000
PARAMETER_UNSIGNED_BIN
DEF
SLD_AUTO_INSTANCE_INDEX
YES
PARAMETER_STRING
USR
LOG2_TXFIFO_DEPTH
6
PARAMETER_SIGNED_DEC
USR
LOG2_RXFIFO_DEPTH
6
PARAMETER_SIGNED_DEC
USR
RESERVED
0
PARAMETER_SIGNED_DEC
DEF
DATA_WIDTH
8
PARAMETER_SIGNED_DEC
DEF
NODE_IR_WIDTH
1
PARAMETER_SIGNED_DEC
DEF
SCAN_LENGTH
11
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic
}
# macro_sequence

# end
# entity
lcd_16207_0
# storage
db|DE2_SD_Card_Audio.(137).cnf
db|DE2_SD_Card_Audio.(137).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lcd_16207_0.v
ac97dd4535fb4296f2b4b9c84fed39
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|lcd_16207_0:the_lcd_16207_0
}
# macro_sequence

# end
# entity
sram_0
# storage
db|DE2_SD_Card_Audio.(148).cnf
db|DE2_SD_Card_Audio.(148).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sram_0.v
fb1ca8c16ac47e2a680aed21f51dce8
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|sram_0:the_sram_0
}
# macro_sequence

# end
# entity
SRAM_16Bit_512K
# storage
db|DE2_SD_Card_Audio.(149).cnf
db|DE2_SD_Card_Audio.(149).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SRAM_16Bit_512K.v
151414e61658497f7ad546d5079e13
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K
}
# macro_sequence

# end
# entity
sld_hub
# storage
db|DE2_SD_Card_Audio.(181).cnf
db|DE2_SD_Card_Audio.(181).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|sld_hub.vhd
7a79487a6e8170b43b1767a2ea68
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
4
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone II
PARAMETER_UNKNOWN
USR
n_nodes
2
PARAMETER_UNKNOWN
USR
n_sel_bits
2
PARAMETER_UNKNOWN
USR
n_node_ir_bits
5
PARAMETER_UNKNOWN
USR
node_info
0000110000000000011011100000000000011001000100000100011000000000
PARAMETER_UNSIGNED_BIN
USR
compilation_mode
1
PARAMETER_UNKNOWN
USR
BROADCAST_FEATURE
1
PARAMETER_SIGNED_DEC
DEF
FORCE_IR_CAPTURE_FEATURE
1
PARAMETER_SIGNED_DEC
DEF
}
# lmf
|opt|altera|10.1sp1|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_shadow_jsm
# storage
db|DE2_SD_Card_Audio.(182).cnf
db|DE2_SD_Card_Audio.(182).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|sld_hub.vhd
7a79487a6e8170b43b1767a2ea68
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
1
PARAMETER_SIGNED_DEC
USR
ip_minor_version
4
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
 constraint(jtag_state)
15 downto 0
PARAMETER_STRING
USR
}
# lmf
|opt|altera|10.1sp1|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_rom_sr
# storage
db|DE2_SD_Card_Audio.(183).cnf
db|DE2_SD_Card_Audio.(183).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|sld_rom_sr.vhd
c8a299171b404a8be9d59988f836b14
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
n_bits
96
PARAMETER_SIGNED_DEC
USR
word_size
4
PARAMETER_SIGNED_DEC
USR
 constraint(rom_data)
95 downto 0
PARAMETER_STRING
USR
}
# lmf
|opt|altera|10.1sp1|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
noteA
# storage
db|DE2_SD_Card_Audio.(144).cnf
db|DE2_SD_Card_Audio.(144).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
noteA.v
b2d22c5ce4ca6f10b039ede8ce6e1a77
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|noteA:the_noteA
}
# macro_sequence

# end
# entity
Audio_0
# storage
db|DE2_SD_Card_Audio.(8).cnf
db|DE2_SD_Card_Audio.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Audio_0.v
2c1ff2f28fbf14f6f6429d5b6ed95731
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0
}
# macro_sequence

# end
# entity
AUDIO_DAC_FIFO
# storage
db|DE2_SD_Card_Audio.(9).cnf
db|DE2_SD_Card_Audio.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
AUDIO_DAC_FIFO.v
82d22de8b3de13d2b4b2c97d64ac435
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
REF_CLK
18432000
PARAMETER_SIGNED_DEC
USR
SAMPLE_RATE
48000
PARAMETER_SIGNED_DEC
USR
DATA_WIDTH
16
PARAMETER_SIGNED_DEC
USR
CHANNEL_NUM
2
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO
}
# macro_sequence

# end
# entity
altpll
# storage
db|DE2_SD_Card_Audio.(189).cnf
db|DE2_SD_Card_Audio.(189).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altpll.tdf
2edfab7fd52cb567d9dca9f62da13c
7
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
FAST
PARAMETER_UNKNOWN
USR
LPM_HINT
UNUSED
PARAMETER_UNKNOWN
DEF
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
10000
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_SIGNED_DEC
USR
CLK1_MULTIPLY_BY
2
PARAMETER_SIGNED_DEC
USR
CLK0_MULTIPLY_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
2
PARAMETER_SIGNED_DEC
USR
CLK1_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK0_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK0_PHASE_SHIFT
-3000
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK1_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_LOW_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_HIGH_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
DPA_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
DPA_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
DPA_DIVIDER
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C6_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C7_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C8_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C9_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
C6_PH
0
PARAMETER_UNKNOWN
DEF
C7_PH
0
PARAMETER_UNKNOWN
DEF
C8_PH
0
PARAMETER_UNKNOWN
DEF
C9_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C6_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C7_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C8_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C9_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK6_COUNTER
E0
PARAMETER_UNKNOWN
DEF
CLK7_COUNTER
E1
PARAMETER_UNKNOWN
DEF
CLK8_COUNTER
E2
PARAMETER_UNKNOWN
DEF
CLK9_COUNTER
E3
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C_BITS
9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASESTEP
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEUPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLKENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASECOUNTERSELECT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
SIM_GATE_LOCK_DEVICE_BEHAVIOR
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
clkswitch
-1
1
areset
-1
1
pllena
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# macro_sequence

# end
# entity
noteB
# storage
db|DE2_SD_Card_Audio.(171).cnf
db|DE2_SD_Card_Audio.(171).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
noteB.v
53f5c25feb16edf46ad58c6ea3c99b6
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|noteB:the_noteB
}
# macro_sequence

# end
# entity
noteC
# storage
db|DE2_SD_Card_Audio.(175).cnf
db|DE2_SD_Card_Audio.(175).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
noteC.v
a49bddfa20bf4867c67ea2cce58125
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|noteC:the_noteC
}
# macro_sequence

# end
# entity
noteD
# storage
db|DE2_SD_Card_Audio.(187).cnf
db|DE2_SD_Card_Audio.(187).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
noteD.v
28406636675a6ef03f95efe36dbbe7a9
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|noteD:the_noteD
}
# macro_sequence

# end
# entity
noteE
# storage
db|DE2_SD_Card_Audio.(190).cnf
db|DE2_SD_Card_Audio.(190).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
noteE.v
b5f164bd70f0c044d030ea6280e6add4
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|noteE:the_noteE
}
# macro_sequence

# end
# entity
noteF
# storage
db|DE2_SD_Card_Audio.(192).cnf
db|DE2_SD_Card_Audio.(192).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
noteF.v
3483571d1abb7d9efb5a8c1952e464
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|noteF:the_noteF
}
# macro_sequence

# end
# entity
noteG
# storage
db|DE2_SD_Card_Audio.(194).cnf
db|DE2_SD_Card_Audio.(194).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
noteG.v
7fca0e0ab2ecce12228f3e8bf149bc
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|noteG:the_noteG
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(97).cnf
db|DE2_SD_Card_Audio.(97).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
22
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
7
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
128
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
22
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
7
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
128
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_0_ic_tag_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_f5g1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(103).cnf
db|DE2_SD_Card_Audio.(103).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
17
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
9
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
512
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
17
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
9
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
512
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_0_dc_tag_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_3g22
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
q_b
-1
3
q_a
-1
3
data_b
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
wren_a
-1
1
data_a
-1
1
}
# macro_sequence

# end
# entity
system_0_clock_1
# storage
db|DE2_SD_Card_Audio.(202).cnf
db|DE2_SD_Card_Audio.(202).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_clock_1.v
149460a04839cc5cbb976cf1cda8f4c
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
system_0_clock_1_edge_to_pulse
# storage
db|DE2_SD_Card_Audio.(203).cnf
db|DE2_SD_Card_Audio.(203).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_clock_1.v
149460a04839cc5cbb976cf1cda8f4c
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
system_0_clock_1_slave_FSM
# storage
db|DE2_SD_Card_Audio.(204).cnf
db|DE2_SD_Card_Audio.(204).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_clock_1.v
149460a04839cc5cbb976cf1cda8f4c
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
system_0_clock_1_master_FSM
# storage
db|DE2_SD_Card_Audio.(205).cnf
db|DE2_SD_Card_Audio.(205).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_clock_1.v
149460a04839cc5cbb976cf1cda8f4c
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
system_0_clock_1_bit_pipe
# storage
db|DE2_SD_Card_Audio.(206).cnf
db|DE2_SD_Card_Audio.(206).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_clock_1.v
149460a04839cc5cbb976cf1cda8f4c
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
MReset
# storage
db|DE2_SD_Card_Audio.(34).cnf
db|DE2_SD_Card_Audio.(34).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
MReset.v
e8dc44eb912f518acaea90d0dc7adc11
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
MS
# storage
db|DE2_SD_Card_Audio.(40).cnf
db|DE2_SD_Card_Audio.(40).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
MS.v
9ae9972981e07b7abd1462482609b74
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|MS:the_MS
}
# macro_sequence

# end
# entity
Oct_DOWN
# storage
db|DE2_SD_Card_Audio.(56).cnf
db|DE2_SD_Card_Audio.(56).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Oct_DOWN.v
99741221d1829fbba9376a1d21c09487
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|Oct_DOWN:the_Oct_DOWN
}
# macro_sequence

# end
# entity
Oct_UP
# storage
db|DE2_SD_Card_Audio.(59).cnf
db|DE2_SD_Card_Audio.(59).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Oct_UP.v
baca48e9bbbb879adb1f7571b592b43
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|Oct_UP:the_Oct_UP
}
# macro_sequence

# end
# entity
RST
# storage
db|DE2_SD_Card_Audio.(63).cnf
db|DE2_SD_Card_Audio.(63).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RST.v
2bbf2dbb3efc9f7f14485f77c9ed1a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|RST:the_RST
}
# macro_sequence

# end
# entity
dist_sensor
# storage
db|DE2_SD_Card_Audio.(123).cnf
db|DE2_SD_Card_Audio.(123).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dist_sensor.v
aa4bb390b4757e3ccb947423b5bc13
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|dist_sensor:the_dist_sensor
}
# macro_sequence

# end
# entity
altpll
# storage
db|DE2_SD_Card_Audio.(165).cnf
db|DE2_SD_Card_Audio.(165).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altpll.tdf
2edfab7fd52cb567d9dca9f62da13c
7
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
FAST
PARAMETER_UNKNOWN
USR
LPM_HINT
UNUSED
PARAMETER_UNKNOWN
DEF
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
37037
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_MULTIPLY_BY
37
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_DIVIDE_BY
100
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_LOW_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_HIGH_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
DPA_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
DPA_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
DPA_DIVIDER
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C6_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C7_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C8_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C9_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
C6_PH
0
PARAMETER_UNKNOWN
DEF
C7_PH
0
PARAMETER_UNKNOWN
DEF
C8_PH
0
PARAMETER_UNKNOWN
DEF
C9_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C6_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C7_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C8_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C9_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK6_COUNTER
E0
PARAMETER_UNKNOWN
DEF
CLK7_COUNTER
E1
PARAMETER_UNKNOWN
DEF
CLK8_COUNTER
E2
PARAMETER_UNKNOWN
DEF
CLK9_COUNTER
E3
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C_BITS
9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASESTEP
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEUPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLKENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASECOUNTERSELECT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
SIM_GATE_LOCK_DEVICE_BEHAVIOR
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
areset
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
clkswitch
-1
1
pllena
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# macro_sequence

# end
# entity
altpll
# storage
db|DE2_SD_Card_Audio.(6).cnf
db|DE2_SD_Card_Audio.(6).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altpll.tdf
2edfab7fd52cb567d9dca9f62da13c
7
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
FAST
PARAMETER_UNKNOWN
USR
LPM_HINT
UNUSED
PARAMETER_UNKNOWN
DEF
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
37037
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_MULTIPLY_BY
2
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_DIVIDE_BY
3
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_LOW_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_HIGH_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
DPA_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
DPA_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
DPA_DIVIDER
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C6_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C7_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C8_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C9_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
C6_PH
0
PARAMETER_UNKNOWN
DEF
C7_PH
0
PARAMETER_UNKNOWN
DEF
C8_PH
0
PARAMETER_UNKNOWN
DEF
C9_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C6_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C7_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C8_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C9_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK6_COUNTER
E0
PARAMETER_UNKNOWN
DEF
CLK7_COUNTER
E1
PARAMETER_UNKNOWN
DEF
CLK8_COUNTER
E2
PARAMETER_UNKNOWN
DEF
CLK9_COUNTER
E3
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C_BITS
9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASESTEP
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEUPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLKENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASECOUNTERSELECT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
SIM_GATE_LOCK_DEVICE_BEHAVIOR
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
areset
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
clkswitch
-1
1
pllena
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(55).cnf
db|DE2_SD_Card_Audio.(55).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
32
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
32
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_0_rf_ram_a.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_vaf1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# macro_sequence

# end
# entity
altsyncram_vaf1
# storage
db|DE2_SD_Card_Audio.(57).cnf
db|DE2_SD_Card_Audio.(57).cnf
# case_insensitive
# source_file
db|altsyncram_vaf1.tdf
f8e5b6d9c1b591e644263cf15a5c1df8
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_0_rf_ram_a.mif
55d713de4db17accc269d4dfa42c9c44
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(60).cnf
db|DE2_SD_Card_Audio.(60).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
32
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
32
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_0_rf_ram_b.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_0bf1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# macro_sequence

# end
# entity
altsyncram_0bf1
# storage
db|DE2_SD_Card_Audio.(65).cnf
db|DE2_SD_Card_Audio.(65).cnf
# case_insensitive
# source_file
db|altsyncram_0bf1.tdf
4461cb151214aa10db6f382696e38199
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_0_rf_ram_b.mif
55d713de4db17accc269d4dfa42c9c44
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(72).cnf
db|DE2_SD_Card_Audio.(72).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
32
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
32
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_0_rf_ram_a.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_irf1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# macro_sequence

# end
# entity
altsyncram_irf1
# storage
db|DE2_SD_Card_Audio.(75).cnf
db|DE2_SD_Card_Audio.(75).cnf
# case_insensitive
# source_file
db|altsyncram_irf1.tdf
5629d084944c6df50c8fde8f54ecc
7
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_0_rf_ram_a.mif
55d713de4db17accc269d4dfa42c9c44
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(78).cnf
db|DE2_SD_Card_Audio.(78).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
32
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
32
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_0_rf_ram_b.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_jrf1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# macro_sequence

# end
# entity
altsyncram_jrf1
# storage
db|DE2_SD_Card_Audio.(81).cnf
db|DE2_SD_Card_Audio.(81).cnf
# case_insensitive
# source_file
db|altsyncram_jrf1.tdf
69fcac9ba67a5db746f2c9872127f1ce
7
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_0_rf_ram_b.mif
55d713de4db17accc269d4dfa42c9c44
}
# macro_sequence

# end
# entity
altshift_taps
# storage
db|DE2_SD_Card_Audio.(188).cnf
db|DE2_SD_Card_Audio.(188).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altshift_taps.tdf
6b68dac2c783fe96bd138c297a7a5f2f
7
# user_parameter {
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
NUMBER_OF_TAPS
1
PARAMETER_UNKNOWN
USR
TAP_DISTANCE
4
PARAMETER_UNKNOWN
USR
WIDTH
8
PARAMETER_UNKNOWN
USR
POWER_UP_STATE
CLEARED
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
shift_taps_rvm
PARAMETER_UNKNOWN
USR
}
# used_port {
taps7
-1
3
taps6
-1
3
taps5
-1
3
taps4
-1
3
taps3
-1
3
taps2
-1
3
taps1
-1
3
taps0
-1
3
shiftin7
-1
3
shiftin6
-1
3
shiftin5
-1
3
shiftin4
-1
3
shiftin3
-1
3
shiftin2
-1
3
shiftin1
-1
3
shiftin0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# macro_sequence

# end
# entity
shift_taps_rvm
# storage
db|DE2_SD_Card_Audio.(191).cnf
db|DE2_SD_Card_Audio.(191).cnf
# case_insensitive
# source_file
db|shift_taps_rvm.tdf
3454f820c495efa4531ea49b6dc3240
7
# used_port {
taps7
-1
3
taps6
-1
3
taps5
-1
3
taps4
-1
3
taps3
-1
3
taps2
-1
3
taps1
-1
3
taps0
-1
3
shiftin7
-1
3
shiftin6
-1
3
shiftin5
-1
3
shiftin4
-1
3
shiftin3
-1
3
shiftin2
-1
3
shiftin1
-1
3
shiftin0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# macro_sequence

# end
# entity
altsyncram_cqa1
# storage
db|DE2_SD_Card_Audio.(193).cnf
db|DE2_SD_Card_Audio.(193).cnf
# case_insensitive
# source_file
db|altsyncram_cqa1.tdf
b75d7a8d7d5402b54f3206f37c6b35a
7
# used_port {
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken0
-1
3
clock0
-1
3
address_b0
-1
3
address_a0
-1
3
aclr0
-1
3
wren_a
-1
2
}
# macro_sequence

# end
# entity
cntr_ikf
# storage
db|DE2_SD_Card_Audio.(200).cnf
db|DE2_SD_Card_Audio.(200).cnf
# case_insensitive
# source_file
db|cntr_ikf.tdf
3966672b8642241426e84626f76e7ace
7
# used_port {
q0
-1
3
clock
-1
3
clk_en
-1
3
}
# macro_sequence

# end
# entity
cntr_94h
# storage
db|DE2_SD_Card_Audio.(201).cnf
db|DE2_SD_Card_Audio.(201).cnf
# case_insensitive
# source_file
db|cntr_94h.tdf
764036d912c7623cdf16cf2a9a0437
7
# used_port {
cout
-1
3
cnt_en
-1
3
clock
-1
3
clk_en
-1
3
aset
-1
3
}
# macro_sequence

# end
# entity
cpu_0_test_bench
# storage
db|DE2_SD_Card_Audio.(53).cnf
db|DE2_SD_Card_Audio.(53).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0_test_bench.v
5ccf9925ceaca3098d7b42dba9786f
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench
}
# macro_sequence

# end
# entity
cpu_0_mult_cell
# storage
db|DE2_SD_Card_Audio.(90).cnf
db|DE2_SD_Card_Audio.(90).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0_mult_cell.v
6c6c837874e2661a78a2f531a79aa176
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell
}
# macro_sequence

# end
# entity
I2C_Controller
# storage
db|DE2_SD_Card_Audio.(163).cnf
db|DE2_SD_Card_Audio.(163).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
I2C_Controller.v
17c8bc8fba8c347d7666adffc13e8
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
I2C_AV_Config:u1|I2C_Controller:u0
}
# macro_sequence

# end
# entity
SDRAM_PLL
# storage
db|DE2_SD_Card_Audio.(2).cnf
db|DE2_SD_Card_Audio.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SDRAM_PLL.v
a548aa98add2333d50147de46bd1af2
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
altpll
# storage
db|DE2_SD_Card_Audio.(162).cnf
db|DE2_SD_Card_Audio.(162).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altpll.tdf
2edfab7fd52cb567d9dca9f62da13c
7
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
FAST
PARAMETER_UNKNOWN
USR
LPM_HINT
UNUSED
PARAMETER_UNKNOWN
DEF
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
20000
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_SIGNED_DEC
USR
CLK1_MULTIPLY_BY
2
PARAMETER_SIGNED_DEC
USR
CLK0_MULTIPLY_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
2
PARAMETER_SIGNED_DEC
USR
CLK1_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK0_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK0_PHASE_SHIFT
-3300
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK1_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_LOW_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_HIGH_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
DPA_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
DPA_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
DPA_DIVIDER
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C6_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C7_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C8_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C9_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
C6_PH
0
PARAMETER_UNKNOWN
DEF
C7_PH
0
PARAMETER_UNKNOWN
DEF
C8_PH
0
PARAMETER_UNKNOWN
DEF
C9_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C6_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C7_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C8_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C9_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK6_COUNTER
E0
PARAMETER_UNKNOWN
DEF
CLK7_COUNTER
E1
PARAMETER_UNKNOWN
DEF
CLK8_COUNTER
E2
PARAMETER_UNKNOWN
DEF
CLK9_COUNTER
E3
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C_BITS
9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASESTEP
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEUPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLKENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASECOUNTERSELECT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
SIM_GATE_LOCK_DEVICE_BEHAVIOR
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
clkswitch
-1
1
areset
-1
1
pllena
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# macro_sequence

# end
# entity
I2C_AV_Config
# storage
db|DE2_SD_Card_Audio.(209).cnf
db|DE2_SD_Card_Audio.(209).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
I2C_AV_Config.v
b8467dfba375dcfa2fd133d8bfba5a1
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
CLK_Freq
50000000
PARAMETER_SIGNED_DEC
DEF
I2C_Freq
100000
PARAMETER_SIGNED_DEC
DEF
LUT_SIZE
51
PARAMETER_SIGNED_DEC
DEF
Dummy_DATA
0
PARAMETER_SIGNED_DEC
DEF
SET_LIN_L
1
PARAMETER_SIGNED_DEC
DEF
SET_LIN_R
2
PARAMETER_SIGNED_DEC
DEF
SET_HEAD_L
3
PARAMETER_SIGNED_DEC
DEF
SET_HEAD_R
4
PARAMETER_SIGNED_DEC
DEF
A_PATH_CTRL
5
PARAMETER_SIGNED_DEC
DEF
D_PATH_CTRL
6
PARAMETER_SIGNED_DEC
DEF
POWER_ON
7
PARAMETER_SIGNED_DEC
DEF
SET_FORMAT
8
PARAMETER_SIGNED_DEC
DEF
SAMPLE_CTRL
9
PARAMETER_SIGNED_DEC
DEF
SET_ACTIVE
10
PARAMETER_SIGNED_DEC
DEF
SET_VIDEO
11
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
I2C_AV_Config:u1
}
# macro_sequence

# end
# entity
Audio_PLL
# storage
db|DE2_SD_Card_Audio.(4).cnf
db|DE2_SD_Card_Audio.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Audio_PLL.v
e58c190e9d041876870416c820fc69
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
Audio_PLL:PLL2
}
# macro_sequence

# end
# entity
system_0_clock_2
# storage
db|DE2_SD_Card_Audio.(172).cnf
db|DE2_SD_Card_Audio.(172).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_clock_2.v
427afd312ce3ba60496c49d52f9feb
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
system_0_clock_2_edge_to_pulse
# storage
db|DE2_SD_Card_Audio.(173).cnf
db|DE2_SD_Card_Audio.(173).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_clock_2.v
427afd312ce3ba60496c49d52f9feb
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
system_0_clock_2_slave_FSM
# storage
db|DE2_SD_Card_Audio.(185).cnf
db|DE2_SD_Card_Audio.(185).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_clock_2.v
427afd312ce3ba60496c49d52f9feb
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
system_0_clock_2_master_FSM
# storage
db|DE2_SD_Card_Audio.(186).cnf
db|DE2_SD_Card_Audio.(186).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_clock_2.v
427afd312ce3ba60496c49d52f9feb
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
system_0_clock_2_bit_pipe
# storage
db|DE2_SD_Card_Audio.(210).cnf
db|DE2_SD_Card_Audio.(210).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_clock_2.v
427afd312ce3ba60496c49d52f9feb
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
opencores_i2c_master
# storage
db|DE2_SD_Card_Audio.(150).cnf
db|DE2_SD_Card_Audio.(150).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
altera_avalon_opencores_i2c|opencores_i2c_master.vhd
e033541185d15d803c77d4ff6040c64
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(wb_adr_i)
2 downto 0
PARAMETER_STRING
USR
 constraint(wb_dat_i)
31 downto 0
PARAMETER_STRING
USR
 constraint(wb_dat_o)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master
}
# lmf
|opt|altera|10.1sp1|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
i2c_master_top
# storage
db|DE2_SD_Card_Audio.(151).cnf
db|DE2_SD_Card_Audio.(151).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
altera_avalon_opencores_i2c|i2c_master_top.vhd
b88a5d597431056f24496dd3abe1895
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ARST_LVL
'0'
PARAMETER_ENUM
DEF
Tcq
1000000 fs
PARAMETER_PHYSICAL
DEF
 constraint(wb_adr_i)
2 downto 0
PARAMETER_STRING
USR
 constraint(wb_dat_i)
7 downto 0
PARAMETER_STRING
USR
 constraint(wb_dat_o)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst
}
# lmf
|opt|altera|10.1sp1|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
i2c_master_byte_ctrl
# storage
db|DE2_SD_Card_Audio.(152).cnf
db|DE2_SD_Card_Audio.(152).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
altera_avalon_opencores_i2c|i2c_master_byte_ctrl.vhd
35c999a05adcb9718c66c35c152
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
tcq
1000000 fs
PARAMETER_PHYSICAL
USR
 constraint(clk_cnt)
15 downto 0
PARAMETER_STRING
USR
 constraint(din)
7 downto 0
PARAMETER_STRING
USR
 constraint(dout)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1
}
# lmf
|opt|altera|10.1sp1|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
i2c_master_bit_ctrl
# storage
db|DE2_SD_Card_Audio.(153).cnf
db|DE2_SD_Card_Audio.(153).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
altera_avalon_opencores_i2c|i2c_master_bit_ctrl.vhd
80919453f316a9728f836f12286aa1
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
tcq
1000000 fs
PARAMETER_PHYSICAL
USR
 constraint(clk_cnt)
15 downto 0
PARAMETER_STRING
USR
 constraint(cmd)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|i2c_master_bit_ctrl:u1
}
# lmf
|opt|altera|10.1sp1|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
accelerometer
# storage
db|DE2_SD_Card_Audio.(26).cnf
db|DE2_SD_Card_Audio.(26).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
Accelerometer1|accelerometer.vhd
8abf94c52dc21e1ac5738cc9fa3a9de
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(avalon_slave_address)
2 downto 0
PARAMETER_STRING
USR
 constraint(avalon_slave_readdata)
31 downto 0
PARAMETER_STRING
USR
 constraint(avalon_slave_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(avalon_slave_byteenable)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|Accel_Control:the_Accel_Control|accelerometer:accel_control
}
# lmf
|opt|altera|10.1sp1|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
Accel_Control
# storage
db|DE2_SD_Card_Audio.(25).cnf
db|DE2_SD_Card_Audio.(25).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
Accel_Control.vhd
6ec25a48c6dea6d0226a5d7cdcc0a696
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# hierarchies {
system_0:u0|Accel_Control:the_Accel_Control
}
# lmf
|opt|altera|10.1sp1|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
i2c_master
# storage
db|DE2_SD_Card_Audio.(156).cnf
db|DE2_SD_Card_Audio.(156).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
i2c_master.vhd
b12c815a92929cd8684bb2d7ecf1d56
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# hierarchies {
system_0:u0|i2c_master:the_i2c_master
}
# lmf
|opt|altera|10.1sp1|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
altpll
# storage
db|DE2_SD_Card_Audio.(119).cnf
db|DE2_SD_Card_Audio.(119).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altpll.tdf
2edfab7fd52cb567d9dca9f62da13c
7
# user_parameter {
OPERATION_MODE
normal
PARAMETER_UNKNOWN
USR
PLL_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
LPM_HINT
UNUSED
PARAMETER_UNKNOWN
DEF
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK1
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
20000
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
2
PARAMETER_SIGNED_DEC
USR
CLK0_MULTIPLY_BY
2
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK0_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK0_PHASE_SHIFT
-3000
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_LOW_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_HIGH_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
DPA_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
DPA_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
DPA_DIVIDER
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C6_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C7_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C8_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C9_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
C6_PH
0
PARAMETER_UNKNOWN
DEF
C7_PH
0
PARAMETER_UNKNOWN
DEF
C8_PH
0
PARAMETER_UNKNOWN
DEF
C9_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C6_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C7_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C8_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C9_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK6_COUNTER
E0
PARAMETER_UNKNOWN
DEF
CLK7_COUNTER
E1
PARAMETER_UNKNOWN
DEF
CLK8_COUNTER
E2
PARAMETER_UNKNOWN
DEF
CLK9_COUNTER
E3
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C_BITS
9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA4
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA5
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKBAD1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKLOSS
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBIN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PLLENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKSWITCH
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ARESET
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PFDENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANACLR
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANREAD
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANWRITE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_LOCKED
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CONFIGUPDATE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASESTEP
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEUPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLKENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASECOUNTERSELECT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
SIM_GATE_LOCK_DEVICE_BEHAVIOR
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
locked
-1
3
inclk
-1
3
clk
-1
3
areset
-1
3
}
# hierarchies {
system_0:u0|altpll_0:the_altpll_0|altpll:sd1
}
# macro_sequence

# end
# entity
system_0_clock_0
# storage
db|DE2_SD_Card_Audio.(199).cnf
db|DE2_SD_Card_Audio.(199).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_clock_0.v
895af8bbea57226824263ea28c748d14
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_clock_0:the_system_0_clock_0
}
# macro_sequence

# end
# entity
system_0_clock_0_edge_to_pulse
# storage
db|DE2_SD_Card_Audio.(207).cnf
db|DE2_SD_Card_Audio.(207).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_clock_0.v
895af8bbea57226824263ea28c748d14
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_clock_0:the_system_0_clock_0|system_0_clock_0_edge_to_pulse:read_done_edge_to_pulse
system_0:u0|system_0_clock_0:the_system_0_clock_0|system_0_clock_0_edge_to_pulse:write_done_edge_to_pulse
system_0:u0|system_0_clock_0:the_system_0_clock_0|system_0_clock_0_edge_to_pulse:read_request_edge_to_pulse
system_0:u0|system_0_clock_0:the_system_0_clock_0|system_0_clock_0_edge_to_pulse:write_request_edge_to_pulse
}
# macro_sequence

# end
# entity
system_0_clock_0_slave_FSM
# storage
db|DE2_SD_Card_Audio.(208).cnf
db|DE2_SD_Card_Audio.(208).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_clock_0.v
895af8bbea57226824263ea28c748d14
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_clock_0:the_system_0_clock_0|system_0_clock_0_slave_FSM:slave_FSM
}
# macro_sequence

# end
# entity
system_0_clock_0_master_FSM
# storage
db|DE2_SD_Card_Audio.(212).cnf
db|DE2_SD_Card_Audio.(212).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_clock_0.v
895af8bbea57226824263ea28c748d14
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_clock_0:the_system_0_clock_0|system_0_clock_0_master_FSM:master_FSM
}
# macro_sequence

# end
# entity
system_0_clock_0_bit_pipe
# storage
db|DE2_SD_Card_Audio.(213).cnf
db|DE2_SD_Card_Audio.(213).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_clock_0.v
895af8bbea57226824263ea28c748d14
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_clock_0:the_system_0_clock_0|system_0_clock_0_bit_pipe:endofpacket_bit_pipe
}
# macro_sequence

# end
# entity
altpll
# storage
db|DE2_SD_Card_Audio.(141).cnf
db|DE2_SD_Card_Audio.(141).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altpll.tdf
2edfab7fd52cb567d9dca9f62da13c
7
# user_parameter {
OPERATION_MODE
normal
PARAMETER_UNKNOWN
USR
PLL_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
LPM_HINT
UNUSED
PARAMETER_UNKNOWN
DEF
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK1
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
20000
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
1
PARAMETER_SIGNED_DEC
USR
CLK0_MULTIPLY_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK0_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK0_PHASE_SHIFT
-3000
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_LOW_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_HIGH_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
DPA_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
DPA_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
DPA_DIVIDER
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C6_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C7_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C8_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C9_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
C6_PH
0
PARAMETER_UNKNOWN
DEF
C7_PH
0
PARAMETER_UNKNOWN
DEF
C8_PH
0
PARAMETER_UNKNOWN
DEF
C9_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C6_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C7_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C8_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C9_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK6_COUNTER
E0
PARAMETER_UNKNOWN
DEF
CLK7_COUNTER
E1
PARAMETER_UNKNOWN
DEF
CLK8_COUNTER
E2
PARAMETER_UNKNOWN
DEF
CLK9_COUNTER
E3
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C_BITS
9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA4
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA5
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKBAD1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKLOSS
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBIN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PLLENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKSWITCH
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ARESET
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PFDENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANACLR
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANREAD
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANWRITE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_LOCKED
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CONFIGUPDATE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASESTEP
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEUPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLKENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASECOUNTERSELECT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
SIM_GATE_LOCK_DEVICE_BEHAVIOR
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
locked
-1
3
inclk
-1
3
clk
-1
3
areset
-1
3
}
# macro_sequence

# end
# entity
altpll_0
# storage
db|DE2_SD_Card_Audio.(54).cnf
db|DE2_SD_Card_Audio.(54).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
altpll_0.v
4ae95c86f7c613e328756eb31f7a67cd
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|altpll_0:the_altpll_0
}
# macro_sequence

# end
# entity
altpll_0_stdsync_sv6
# storage
db|DE2_SD_Card_Audio.(58).cnf
db|DE2_SD_Card_Audio.(58).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
altpll_0.v
4ae95c86f7c613e328756eb31f7a67cd
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|altpll_0:the_altpll_0|altpll_0_stdsync_sv6:stdsync2
}
# macro_sequence

# end
# entity
altpll_0_dffpipe_l2c
# storage
db|DE2_SD_Card_Audio.(101).cnf
db|DE2_SD_Card_Audio.(101).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
altpll_0.v
4ae95c86f7c613e328756eb31f7a67cd
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|altpll_0:the_altpll_0|altpll_0_stdsync_sv6:stdsync2|altpll_0_dffpipe_l2c:dffpipe3
}
# macro_sequence
ALTERA_RESERVED_QISALTERA_RESERVED_QIS
# end
# entity
epcs_controller
# storage
db|DE2_SD_Card_Audio.(159).cnf
db|DE2_SD_Card_Audio.(159).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
epcs_controller.v
47a79747405cf7da146328f5eabf94d
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|epcs_controller:the_epcs_controller
}
# macro_sequence

# end
# entity
epcs_controller_sub
# storage
db|DE2_SD_Card_Audio.(160).cnf
db|DE2_SD_Card_Audio.(160).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
epcs_controller.v
47a79747405cf7da146328f5eabf94d
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub
}
# macro_sequence

# end
# entity
tornado_epcs_controller_atom
# storage
db|DE2_SD_Card_Audio.(161).cnf
db|DE2_SD_Card_Audio.(161).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
epcs_controller.v
47a79747405cf7da146328f5eabf94d
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|epcs_controller:the_epcs_controller|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom
}
# macro_sequence

# end
# entity
sdram_0
# storage
db|DE2_SD_Card_Audio.(195).cnf
db|DE2_SD_Card_Audio.(195).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sdram_0.v
ae73ec9462a583fcfe926c2c447ee4
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|sdram_0:the_sdram_0
}
# macro_sequence

# end
# entity
sdram_0_input_efifo_module
# storage
db|DE2_SD_Card_Audio.(196).cnf
db|DE2_SD_Card_Audio.(196).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sdram_0.v
ae73ec9462a583fcfe926c2c447ee4
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module
}
# macro_sequence

# end
# entity
timer_0
# storage
db|DE2_SD_Card_Audio.(216).cnf
db|DE2_SD_Card_Audio.(216).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
timer_0.v
16dd8a4f8926184d2048fea3fdd668
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|timer_0:the_timer_0
}
# macro_sequence

# end
# entity
timer_1
# storage
db|DE2_SD_Card_Audio.(218).cnf
db|DE2_SD_Card_Audio.(218).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
timer_1.v
68e5db1465b3c7e1838a06bef3d9345
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|timer_1:the_timer_1
}
# macro_sequence

# end
# entity
uart_0
# storage
db|DE2_SD_Card_Audio.(221).cnf
db|DE2_SD_Card_Audio.(221).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_0.v
cf5c3c42b0fce411bfdf53b4713348e8
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|uart_0:the_uart_0
}
# macro_sequence

# end
# entity
uart_0_tx
# storage
db|DE2_SD_Card_Audio.(222).cnf
db|DE2_SD_Card_Audio.(222).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_0.v
cf5c3c42b0fce411bfdf53b4713348e8
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx
}
# macro_sequence

# end
# entity
uart_0_rx
# storage
db|DE2_SD_Card_Audio.(223).cnf
db|DE2_SD_Card_Audio.(223).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_0.v
cf5c3c42b0fce411bfdf53b4713348e8
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx
}
# macro_sequence

# end
# entity
uart_0_rx_stimulus_source
# storage
db|DE2_SD_Card_Audio.(224).cnf
db|DE2_SD_Card_Audio.(224).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_0.v
cf5c3c42b0fce411bfdf53b4713348e8
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|uart_0_rx_stimulus_source:the_uart_0_rx_stimulus_source
}
# macro_sequence

# end
# entity
uart_0_regs
# storage
db|DE2_SD_Card_Audio.(225).cnf
db|DE2_SD_Card_Audio.(225).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_0.v
cf5c3c42b0fce411bfdf53b4713348e8
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs
}
# macro_sequence

# end
# entity
DE2_SD_Card_Audio
# storage
db|DE2_SD_Card_Audio.(0).cnf
db|DE2_SD_Card_Audio.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
DE2_SD_Card_Audio.v
4519fafc79964640d25d4da985345d9
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
|
}
# macro_sequence

# end
# entity
onchip_memory2_0
# storage
db|DE2_SD_Card_Audio.(180).cnf
db|DE2_SD_Card_Audio.(180).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
onchip_memory2_0.v
6f71deb34af31aa27633a65a892dbca
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(184).cnf
db|DE2_SD_Card_Audio.(184).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
SINGLE_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
12
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
4096
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
4
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
onchip_memory2_0.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
4096
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_94c1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_a
-1
3
data_a
-1
3
clocken0
-1
3
clock0
-1
3
byteena_a
-1
3
address_a
-1
3
}
# macro_sequence

# end
# entity
system_0
# storage
db|DE2_SD_Card_Audio.(7).cnf
db|DE2_SD_Card_Audio.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0
}
# macro_sequence

# end
# entity
Accel_Control_avalon_slave_arbitrator
# storage
db|DE2_SD_Card_Audio.(24).cnf
db|DE2_SD_Card_Audio.(24).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|Accel_Control_avalon_slave_arbitrator:the_Accel_Control_avalon_slave
}
# macro_sequence

# end
# entity
Audio_0_avalon_slave_0_arbitrator
# storage
db|DE2_SD_Card_Audio.(27).cnf
db|DE2_SD_Card_Audio.(27).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|Audio_0_avalon_slave_0_arbitrator:the_Audio_0_avalon_slave_0
}
# macro_sequence

# end
# entity
MS_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(28).cnf
db|DE2_SD_Card_Audio.(28).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|MS_s1_arbitrator:the_MS_s1
}
# macro_sequence

# end
# entity
Oct_DOWN_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(29).cnf
db|DE2_SD_Card_Audio.(29).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|Oct_DOWN_s1_arbitrator:the_Oct_DOWN_s1
}
# macro_sequence

# end
# entity
Oct_UP_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(30).cnf
db|DE2_SD_Card_Audio.(30).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|Oct_UP_s1_arbitrator:the_Oct_UP_s1
}
# macro_sequence

# end
# entity
RST_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(32).cnf
db|DE2_SD_Card_Audio.(32).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|RST_s1_arbitrator:the_RST_s1
}
# macro_sequence

# end
# entity
SD_CLK_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(36).cnf
db|DE2_SD_Card_Audio.(36).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|SD_CLK_s1_arbitrator:the_SD_CLK_s1
}
# macro_sequence

# end
# entity
SD_CMD_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(41).cnf
db|DE2_SD_Card_Audio.(41).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|SD_CMD_s1_arbitrator:the_SD_CMD_s1
}
# macro_sequence

# end
# entity
SD_DAT_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(42).cnf
db|DE2_SD_Card_Audio.(42).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|SD_DAT_s1_arbitrator:the_SD_DAT_s1
}
# macro_sequence

# end
# entity
SEG7_Display_avalon_slave_0_arbitrator
# storage
db|DE2_SD_Card_Audio.(43).cnf
db|DE2_SD_Card_Audio.(43).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|SEG7_Display_avalon_slave_0_arbitrator:the_SEG7_Display_avalon_slave_0
}
# macro_sequence

# end
# entity
altpll_0_pll_slave_arbitrator
# storage
db|DE2_SD_Card_Audio.(44).cnf
db|DE2_SD_Card_Audio.(44).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|altpll_0_pll_slave_arbitrator:the_altpll_0_pll_slave
}
# macro_sequence

# end
# entity
cpu_0_jtag_debug_module_arbitrator
# storage
db|DE2_SD_Card_Audio.(66).cnf
db|DE2_SD_Card_Audio.(66).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module
}
# macro_sequence

# end
# entity
cpu_0_data_master_arbitrator
# storage
db|DE2_SD_Card_Audio.(68).cnf
db|DE2_SD_Card_Audio.(68).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master
}
# macro_sequence

# end
# entity
cpu_0_instruction_master_arbitrator
# storage
db|DE2_SD_Card_Audio.(69).cnf
db|DE2_SD_Card_Audio.(69).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master
}
# macro_sequence

# end
# entity
cpu_0
# storage
db|DE2_SD_Card_Audio.(77).cnf
db|DE2_SD_Card_Audio.(77).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0
}
# macro_sequence

# end
# entity
cpu_0_ic_data_module
# storage
db|DE2_SD_Card_Audio.(88).cnf
db|DE2_SD_Card_Audio.(88).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
UNUSED
PARAMETER_STRING
DEF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(89).cnf
db|DE2_SD_Card_Audio.(89).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
2048
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
2048
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_afd1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altsyncram_afd1
# storage
db|DE2_SD_Card_Audio.(91).cnf
db|DE2_SD_Card_Audio.(91).cnf
# case_insensitive
# source_file
db|altsyncram_afd1.tdf
1e5d426917df791170eea2b2adcde945
7
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_afd1:auto_generated
}
# macro_sequence

# end
# entity
cpu_0_ic_tag_module
# storage
db|DE2_SD_Card_Audio.(93).cnf
db|DE2_SD_Card_Audio.(93).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
cpu_0_ic_tag_ram.mif
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(94).cnf
db|DE2_SD_Card_Audio.(94).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
20
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
256
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
20
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
256
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_0_ic_tag_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_h5g1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altsyncram_h5g1
# storage
db|DE2_SD_Card_Audio.(95).cnf
db|DE2_SD_Card_Audio.(95).cnf
# case_insensitive
# source_file
db|altsyncram_h5g1.tdf
bf3121241e1e9934741374b29d84d9
7
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_0_ic_tag_ram.mif
d0fc2d3669ba59a040ff1d14e63ffae9
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_h5g1:auto_generated
}
# macro_sequence

# end
# entity
cpu_0_bht_module
# storage
db|DE2_SD_Card_Audio.(96).cnf
db|DE2_SD_Card_Audio.(96).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
cpu_0_bht_ram.mif
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht
}
# macro_sequence

# end
# entity
altsyncram_8pf1
# storage
db|DE2_SD_Card_Audio.(98).cnf
db|DE2_SD_Card_Audio.(98).cnf
# case_insensitive
# source_file
db|altsyncram_8pf1.tdf
b854a4f214be22a568740e986bea11
7
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b1
-1
3
q_b0
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_0_bht_ram.mif
ef25a26cde16463e81aa89d3967e6a75
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_8pf1:auto_generated
}
# macro_sequence

# end
# entity
cpu_0_register_bank_a_module
# storage
db|DE2_SD_Card_Audio.(99).cnf
db|DE2_SD_Card_Audio.(99).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
cpu_0_rf_ram_a.mif
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a
}
# macro_sequence

# end
# entity
cpu_0_register_bank_b_module
# storage
db|DE2_SD_Card_Audio.(100).cnf
db|DE2_SD_Card_Audio.(100).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
cpu_0_rf_ram_b.mif
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b
}
# macro_sequence

# end
# entity
cpu_0_dc_tag_module
# storage
db|DE2_SD_Card_Audio.(102).cnf
db|DE2_SD_Card_Audio.(102).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
cpu_0_dc_tag_ram.mif
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(104).cnf
db|DE2_SD_Card_Audio.(104).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
14
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
256
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
14
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
256
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_0_dc_tag_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_8hf1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altsyncram_8hf1
# storage
db|DE2_SD_Card_Audio.(106).cnf
db|DE2_SD_Card_Audio.(106).cnf
# case_insensitive
# source_file
db|altsyncram_8hf1.tdf
1c4013eee4d61acb7d9a9cfe866214de
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_0_dc_tag_ram.mif
cabb9e31f1cf39f2c91e848b88e711fc
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_8hf1:auto_generated
}
# macro_sequence

# end
# entity
cpu_0_dc_data_module
# storage
db|DE2_SD_Card_Audio.(107).cnf
db|DE2_SD_Card_Audio.(107).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
UNUSED
PARAMETER_STRING
DEF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(108).cnf
db|DE2_SD_Card_Audio.(108).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
2048
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
2048
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
4
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_0ff1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
byteena_a
-1
3
address_b
-1
3
address_a
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altsyncram_0ff1
# storage
db|DE2_SD_Card_Audio.(117).cnf
db|DE2_SD_Card_Audio.(117).cnf
# case_insensitive
# source_file
db|altsyncram_0ff1.tdf
d12cb552f63524a55c9687e5b76f4d
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
byteena_a3
-1
3
byteena_a2
-1
3
byteena_a1
-1
3
byteena_a0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_0ff1:auto_generated
}
# macro_sequence

# end
# entity
cpu_0_dc_victim_module
# storage
db|DE2_SD_Card_Audio.(118).cnf
db|DE2_SD_Card_Audio.(118).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
UNUSED
PARAMETER_STRING
DEF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_victim_module:cpu_0_dc_victim
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_SD_Card_Audio.(120).cnf
db|DE2_SD_Card_Audio.(120).cnf
# case_insensitive
# source_file
|opt|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
16d928f7e81377a1ba693df1a44d2a83
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
3
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
8
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
3
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
8
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_9vc1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_victim_module:cpu_0_dc_victim|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altsyncram_9vc1
# storage
db|DE2_SD_Card_Audio.(136).cnf
db|DE2_SD_Card_Audio.(136).cnf
# case_insensitive
# source_file
db|altsyncram_9vc1.tdf
e61e1dfa479861efb56504214debe1
7
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_victim_module:cpu_0_dc_victim|altsyncram:the_altsyncram|altsyncram_9vc1:auto_generated
}
# macro_sequence

# end
# entity
cpu_0_nios2_oci
# storage
db|DE2_SD_Card_Audio.(138).cnf
db|DE2_SD_Card_Audio.(138).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci
}
# macro_sequence

# end
# entity
cpu_0_nios2_oci_debug
# storage
db|DE2_SD_Card_Audio.(139).cnf
db|DE2_SD_Card_Audio.(139).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug
}
# macro_sequence

# end
# entity
cpu_0_nios2_ocimem
# storage
db|DE2_SD_Card_Audio.(140).cnf
db|DE2_SD_Card_Audio.(140).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem
}
# macro_sequence

# end
# entity
cpu_0_ociram_lpm_dram_bdp_component_module
# storage
db|DE2_SD_Card_Audio.(142).cnf
db|DE2_SD_Card_Audio.(142).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
cpu_0_ociram_default_contents.mif
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component
}
# macro_sequence

# end
# entity
altsyncram_c572
# storage
db|DE2_SD_Card_Audio.(143).cnf
db|DE2_SD_Card_Audio.(143).cnf
# case_insensitive
# source_file
db|altsyncram_c572.tdf
c14676c529d45f29be971aaa248c96
7
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b31
-1
3
data_b30
-1
3
data_b3
-1
3
data_b29
-1
3
data_b28
-1
3
data_b27
-1
3
data_b26
-1
3
data_b25
-1
3
data_b24
-1
3
data_b23
-1
3
data_b22
-1
3
data_b21
-1
3
data_b20
-1
3
data_b2
-1
3
data_b19
-1
3
data_b18
-1
3
data_b17
-1
3
data_b16
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
byteena_a3
-1
3
byteena_a2
-1
3
byteena_a1
-1
3
byteena_a0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_0_ociram_default_contents.mif
6f607c68f279d63090991fe91eedc171
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated
}
# macro_sequence

# end
# entity
cpu_0_nios2_avalon_reg
# storage
db|DE2_SD_Card_Audio.(145).cnf
db|DE2_SD_Card_Audio.(145).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg
}
# macro_sequence

# end
# entity
cpu_0_nios2_oci_break
# storage
db|DE2_SD_Card_Audio.(146).cnf
db|DE2_SD_Card_Audio.(146).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break
}
# macro_sequence

# end
# entity
cpu_0_nios2_oci_xbrk
# storage
db|DE2_SD_Card_Audio.(147).cnf
db|DE2_SD_Card_Audio.(147).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk
}
# macro_sequence

# end
# entity
cpu_0_nios2_oci_dbrk
# storage
db|DE2_SD_Card_Audio.(154).cnf
db|DE2_SD_Card_Audio.(154).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk
}
# macro_sequence

# end
# entity
cpu_0_nios2_oci_itrace
# storage
db|DE2_SD_Card_Audio.(155).cnf
db|DE2_SD_Card_Audio.(155).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace
}
# macro_sequence

# end
# entity
cpu_0_nios2_oci_dtrace
# storage
db|DE2_SD_Card_Audio.(157).cnf
db|DE2_SD_Card_Audio.(157).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace
}
# macro_sequence

# end
# entity
cpu_0_nios2_oci_td_mode
# storage
db|DE2_SD_Card_Audio.(158).cnf
db|DE2_SD_Card_Audio.(158).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace|cpu_0_nios2_oci_td_mode:cpu_0_nios2_oci_trc_ctrl_td_mode
}
# macro_sequence

# end
# entity
cpu_0_nios2_oci_fifo
# storage
db|DE2_SD_Card_Audio.(164).cnf
db|DE2_SD_Card_Audio.(164).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo
}
# macro_sequence

# end
# entity
cpu_0_nios2_oci_compute_tm_count
# storage
db|DE2_SD_Card_Audio.(166).cnf
db|DE2_SD_Card_Audio.(166).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_compute_tm_count:cpu_0_nios2_oci_compute_tm_count_tm_count
}
# macro_sequence

# end
# entity
cpu_0_nios2_oci_fifowp_inc
# storage
db|DE2_SD_Card_Audio.(167).cnf
db|DE2_SD_Card_Audio.(167).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifowp_inc:cpu_0_nios2_oci_fifowp_inc_fifowp
}
# macro_sequence

# end
# entity
cpu_0_nios2_oci_fifocount_inc
# storage
db|DE2_SD_Card_Audio.(168).cnf
db|DE2_SD_Card_Audio.(168).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifocount_inc:cpu_0_nios2_oci_fifocount_inc_fifocount
}
# macro_sequence

# end
# entity
cpu_0_nios2_oci_pib
# storage
db|DE2_SD_Card_Audio.(169).cnf
db|DE2_SD_Card_Audio.(169).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_pib:the_cpu_0_nios2_oci_pib
}
# macro_sequence

# end
# entity
cpu_0_nios2_oci_im
# storage
db|DE2_SD_Card_Audio.(170).cnf
db|DE2_SD_Card_Audio.(170).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im
}
# macro_sequence

# end
# entity
cpu_0_traceram_lpm_dram_bdp_component_module
# storage
db|DE2_SD_Card_Audio.(174).cnf
db|DE2_SD_Card_Audio.(174).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
508d91961273bb01363a9afde7ee80
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
UNUSED
PARAMETER_STRING
DEF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component
}
# macro_sequence

# end
# entity
dist_sensor_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(176).cnf
db|DE2_SD_Card_Audio.(176).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|dist_sensor_s1_arbitrator:the_dist_sensor_s1
}
# macro_sequence

# end
# entity
epcs_controller_epcs_control_port_arbitrator
# storage
db|DE2_SD_Card_Audio.(177).cnf
db|DE2_SD_Card_Audio.(177).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port
}
# macro_sequence

# end
# entity
i2c_master_avalon_slave_0_arbitrator
# storage
db|DE2_SD_Card_Audio.(178).cnf
db|DE2_SD_Card_Audio.(178).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|i2c_master_avalon_slave_0_arbitrator:the_i2c_master_avalon_slave_0
}
# macro_sequence

# end
# entity
jtag_uart_0_avalon_jtag_slave_arbitrator
# storage
db|DE2_SD_Card_Audio.(179).cnf
db|DE2_SD_Card_Audio.(179).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave
}
# macro_sequence

# end
# entity
lcd_16207_0_control_slave_arbitrator
# storage
db|DE2_SD_Card_Audio.(197).cnf
db|DE2_SD_Card_Audio.(197).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|lcd_16207_0_control_slave_arbitrator:the_lcd_16207_0_control_slave
}
# macro_sequence

# end
# entity
noteA_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(198).cnf
db|DE2_SD_Card_Audio.(198).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|noteA_s1_arbitrator:the_noteA_s1
}
# macro_sequence

# end
# entity
noteB_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(214).cnf
db|DE2_SD_Card_Audio.(214).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|noteB_s1_arbitrator:the_noteB_s1
}
# macro_sequence

# end
# entity
noteC_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(215).cnf
db|DE2_SD_Card_Audio.(215).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|noteC_s1_arbitrator:the_noteC_s1
}
# macro_sequence

# end
# entity
noteD_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(217).cnf
db|DE2_SD_Card_Audio.(217).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|noteD_s1_arbitrator:the_noteD_s1
}
# macro_sequence

# end
# entity
noteE_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(219).cnf
db|DE2_SD_Card_Audio.(219).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|noteE_s1_arbitrator:the_noteE_s1
}
# macro_sequence

# end
# entity
noteF_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(220).cnf
db|DE2_SD_Card_Audio.(220).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|noteF_s1_arbitrator:the_noteF_s1
}
# macro_sequence

# end
# entity
noteG_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(226).cnf
db|DE2_SD_Card_Audio.(226).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|noteG_s1_arbitrator:the_noteG_s1
}
# macro_sequence

# end
# entity
sdram_0_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(227).cnf
db|DE2_SD_Card_Audio.(227).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1
}
# macro_sequence

# end
# entity
rdv_fifo_for_system_0_burst_4_downstream_to_sdram_0_s1_module
# storage
db|DE2_SD_Card_Audio.(228).cnf
db|DE2_SD_Card_Audio.(228).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_system_0_burst_4_downstream_to_sdram_0_s1_module:rdv_fifo_for_system_0_burst_4_downstream_to_sdram_0_s1
}
# macro_sequence

# end
# entity
rdv_fifo_for_system_0_burst_5_downstream_to_sdram_0_s1_module
# storage
db|DE2_SD_Card_Audio.(229).cnf
db|DE2_SD_Card_Audio.(229).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_system_0_burst_5_downstream_to_sdram_0_s1_module:rdv_fifo_for_system_0_burst_5_downstream_to_sdram_0_s1
}
# macro_sequence

# end
# entity
sram_0_avalon_slave_0_arbitrator
# storage
db|DE2_SD_Card_Audio.(230).cnf
db|DE2_SD_Card_Audio.(230).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0
}
# macro_sequence

# end
# entity
system_0_burst_0_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(231).cnf
db|DE2_SD_Card_Audio.(231).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_0_upstream_arbitrator:the_system_0_burst_0_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_0_upstream_module
# storage
db|DE2_SD_Card_Audio.(232).cnf
db|DE2_SD_Card_Audio.(232).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_0_upstream_arbitrator:the_system_0_burst_0_upstream|burstcount_fifo_for_system_0_burst_0_upstream_module:burstcount_fifo_for_system_0_burst_0_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_0_upstream_module
# storage
db|DE2_SD_Card_Audio.(233).cnf
db|DE2_SD_Card_Audio.(233).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_0_upstream_arbitrator:the_system_0_burst_0_upstream|rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_0_upstream_module:rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_0_upstream
}
# macro_sequence

# end
# entity
system_0_burst_0_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(234).cnf
db|DE2_SD_Card_Audio.(234).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_0_downstream_arbitrator:the_system_0_burst_0_downstream
}
# macro_sequence

# end
# entity
system_0_burst_0
# storage
db|DE2_SD_Card_Audio.(235).cnf
db|DE2_SD_Card_Audio.(235).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_0.v
9c40fddb294da3d9a81fd5c15d5dbb7
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_0:the_system_0_burst_0
}
# macro_sequence

# end
# entity
system_0_burst_1_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(236).cnf
db|DE2_SD_Card_Audio.(236).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_1_upstream_arbitrator:the_system_0_burst_1_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_1_upstream_module
# storage
db|DE2_SD_Card_Audio.(237).cnf
db|DE2_SD_Card_Audio.(237).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_1_upstream_arbitrator:the_system_0_burst_1_upstream|burstcount_fifo_for_system_0_burst_1_upstream_module:burstcount_fifo_for_system_0_burst_1_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_1_upstream_module
# storage
db|DE2_SD_Card_Audio.(238).cnf
db|DE2_SD_Card_Audio.(238).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_1_upstream_arbitrator:the_system_0_burst_1_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_1_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_1_upstream
}
# macro_sequence

# end
# entity
system_0_burst_1_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(239).cnf
db|DE2_SD_Card_Audio.(239).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_1_downstream_arbitrator:the_system_0_burst_1_downstream
}
# macro_sequence

# end
# entity
system_0_burst_1
# storage
db|DE2_SD_Card_Audio.(240).cnf
db|DE2_SD_Card_Audio.(240).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_1.v
9ab65ce2be6abc41aab39fc1db0c552
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_1:the_system_0_burst_1
}
# macro_sequence

# end
# entity
system_0_burst_10_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(241).cnf
db|DE2_SD_Card_Audio.(241).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_10_upstream_arbitrator:the_system_0_burst_10_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_10_upstream_module
# storage
db|DE2_SD_Card_Audio.(242).cnf
db|DE2_SD_Card_Audio.(242).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_10_upstream_arbitrator:the_system_0_burst_10_upstream|burstcount_fifo_for_system_0_burst_10_upstream_module:burstcount_fifo_for_system_0_burst_10_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_10_upstream_module
# storage
db|DE2_SD_Card_Audio.(243).cnf
db|DE2_SD_Card_Audio.(243).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_10_upstream_arbitrator:the_system_0_burst_10_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_10_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_10_upstream
}
# macro_sequence

# end
# entity
system_0_burst_10_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(244).cnf
db|DE2_SD_Card_Audio.(244).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_10_downstream_arbitrator:the_system_0_burst_10_downstream
}
# macro_sequence

# end
# entity
system_0_burst_10
# storage
db|DE2_SD_Card_Audio.(245).cnf
db|DE2_SD_Card_Audio.(245).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_10.v
714675c9b9b3c3af9962ac3b017e2ef
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_10:the_system_0_burst_10
}
# macro_sequence

# end
# entity
system_0_burst_11_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(246).cnf
db|DE2_SD_Card_Audio.(246).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_11_upstream_arbitrator:the_system_0_burst_11_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_11_upstream_module
# storage
db|DE2_SD_Card_Audio.(247).cnf
db|DE2_SD_Card_Audio.(247).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_11_upstream_arbitrator:the_system_0_burst_11_upstream|burstcount_fifo_for_system_0_burst_11_upstream_module:burstcount_fifo_for_system_0_burst_11_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_11_upstream_module
# storage
db|DE2_SD_Card_Audio.(248).cnf
db|DE2_SD_Card_Audio.(248).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_11_upstream_arbitrator:the_system_0_burst_11_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_11_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_11_upstream
}
# macro_sequence

# end
# entity
system_0_burst_11_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(249).cnf
db|DE2_SD_Card_Audio.(249).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_11_downstream_arbitrator:the_system_0_burst_11_downstream
}
# macro_sequence

# end
# entity
system_0_burst_11
# storage
db|DE2_SD_Card_Audio.(250).cnf
db|DE2_SD_Card_Audio.(250).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_11.v
fd1e2c6e1c235a85557674165074d07d
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_11:the_system_0_burst_11
}
# macro_sequence

# end
# entity
system_0_burst_12_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(251).cnf
db|DE2_SD_Card_Audio.(251).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_12_upstream_arbitrator:the_system_0_burst_12_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_12_upstream_module
# storage
db|DE2_SD_Card_Audio.(252).cnf
db|DE2_SD_Card_Audio.(252).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_12_upstream_arbitrator:the_system_0_burst_12_upstream|burstcount_fifo_for_system_0_burst_12_upstream_module:burstcount_fifo_for_system_0_burst_12_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_12_upstream_module
# storage
db|DE2_SD_Card_Audio.(253).cnf
db|DE2_SD_Card_Audio.(253).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_12_upstream_arbitrator:the_system_0_burst_12_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_12_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_12_upstream
}
# macro_sequence

# end
# entity
system_0_burst_12_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(254).cnf
db|DE2_SD_Card_Audio.(254).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_12_downstream_arbitrator:the_system_0_burst_12_downstream
}
# macro_sequence

# end
# entity
system_0_burst_12
# storage
db|DE2_SD_Card_Audio.(255).cnf
db|DE2_SD_Card_Audio.(255).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_12.v
608f625dd1fe2ac57775711bc1a50
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_12:the_system_0_burst_12
}
# macro_sequence

# end
# entity
system_0_burst_13_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(256).cnf
db|DE2_SD_Card_Audio.(256).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_13_upstream_arbitrator:the_system_0_burst_13_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_13_upstream_module
# storage
db|DE2_SD_Card_Audio.(257).cnf
db|DE2_SD_Card_Audio.(257).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_13_upstream_arbitrator:the_system_0_burst_13_upstream|burstcount_fifo_for_system_0_burst_13_upstream_module:burstcount_fifo_for_system_0_burst_13_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_13_upstream_module
# storage
db|DE2_SD_Card_Audio.(258).cnf
db|DE2_SD_Card_Audio.(258).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_13_upstream_arbitrator:the_system_0_burst_13_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_13_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_13_upstream
}
# macro_sequence

# end
# entity
system_0_burst_13_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(259).cnf
db|DE2_SD_Card_Audio.(259).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_13_downstream_arbitrator:the_system_0_burst_13_downstream
}
# macro_sequence

# end
# entity
system_0_burst_13
# storage
db|DE2_SD_Card_Audio.(260).cnf
db|DE2_SD_Card_Audio.(260).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_13.v
7e71fa4a934361e3f167a4ae35b459fd
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_13:the_system_0_burst_13
}
# macro_sequence

# end
# entity
system_0_burst_14_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(261).cnf
db|DE2_SD_Card_Audio.(261).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_14_upstream_arbitrator:the_system_0_burst_14_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_14_upstream_module
# storage
db|DE2_SD_Card_Audio.(262).cnf
db|DE2_SD_Card_Audio.(262).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_14_upstream_arbitrator:the_system_0_burst_14_upstream|burstcount_fifo_for_system_0_burst_14_upstream_module:burstcount_fifo_for_system_0_burst_14_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_14_upstream_module
# storage
db|DE2_SD_Card_Audio.(263).cnf
db|DE2_SD_Card_Audio.(263).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_14_upstream_arbitrator:the_system_0_burst_14_upstream|rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_14_upstream_module:rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_14_upstream
}
# macro_sequence

# end
# entity
system_0_burst_14_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(264).cnf
db|DE2_SD_Card_Audio.(264).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_14_downstream_arbitrator:the_system_0_burst_14_downstream
}
# macro_sequence

# end
# entity
system_0_burst_14
# storage
db|DE2_SD_Card_Audio.(265).cnf
db|DE2_SD_Card_Audio.(265).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_14.v
82dae8f6b13778ffac85c4b4a91c4
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_14:the_system_0_burst_14
}
# macro_sequence

# end
# entity
system_0_burst_15_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(266).cnf
db|DE2_SD_Card_Audio.(266).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_15_upstream_arbitrator:the_system_0_burst_15_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_15_upstream_module
# storage
db|DE2_SD_Card_Audio.(267).cnf
db|DE2_SD_Card_Audio.(267).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_15_upstream_arbitrator:the_system_0_burst_15_upstream|burstcount_fifo_for_system_0_burst_15_upstream_module:burstcount_fifo_for_system_0_burst_15_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_15_upstream_module
# storage
db|DE2_SD_Card_Audio.(268).cnf
db|DE2_SD_Card_Audio.(268).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_15_upstream_arbitrator:the_system_0_burst_15_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_15_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_15_upstream
}
# macro_sequence

# end
# entity
system_0_burst_15_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(269).cnf
db|DE2_SD_Card_Audio.(269).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_15_downstream_arbitrator:the_system_0_burst_15_downstream
}
# macro_sequence

# end
# entity
system_0_burst_15
# storage
db|DE2_SD_Card_Audio.(270).cnf
db|DE2_SD_Card_Audio.(270).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_15.v
3eefd726cefe82cd9768ecf7dbd67f4
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_15:the_system_0_burst_15
}
# macro_sequence

# end
# entity
system_0_burst_16_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(271).cnf
db|DE2_SD_Card_Audio.(271).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_16_upstream_arbitrator:the_system_0_burst_16_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_16_upstream_module
# storage
db|DE2_SD_Card_Audio.(272).cnf
db|DE2_SD_Card_Audio.(272).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_16_upstream_arbitrator:the_system_0_burst_16_upstream|burstcount_fifo_for_system_0_burst_16_upstream_module:burstcount_fifo_for_system_0_burst_16_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_16_upstream_module
# storage
db|DE2_SD_Card_Audio.(273).cnf
db|DE2_SD_Card_Audio.(273).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_16_upstream_arbitrator:the_system_0_burst_16_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_16_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_16_upstream
}
# macro_sequence

# end
# entity
system_0_burst_16_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(274).cnf
db|DE2_SD_Card_Audio.(274).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_16_downstream_arbitrator:the_system_0_burst_16_downstream
}
# macro_sequence

# end
# entity
system_0_burst_16
# storage
db|DE2_SD_Card_Audio.(275).cnf
db|DE2_SD_Card_Audio.(275).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_16.v
419447c28fa8ab5f43bebdfae2b997b8
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_16:the_system_0_burst_16
}
# macro_sequence

# end
# entity
system_0_burst_17_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(276).cnf
db|DE2_SD_Card_Audio.(276).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_17_upstream_arbitrator:the_system_0_burst_17_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_17_upstream_module
# storage
db|DE2_SD_Card_Audio.(277).cnf
db|DE2_SD_Card_Audio.(277).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_17_upstream_arbitrator:the_system_0_burst_17_upstream|burstcount_fifo_for_system_0_burst_17_upstream_module:burstcount_fifo_for_system_0_burst_17_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_17_upstream_module
# storage
db|DE2_SD_Card_Audio.(278).cnf
db|DE2_SD_Card_Audio.(278).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_17_upstream_arbitrator:the_system_0_burst_17_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_17_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_17_upstream
}
# macro_sequence

# end
# entity
system_0_burst_17_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(279).cnf
db|DE2_SD_Card_Audio.(279).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_17_downstream_arbitrator:the_system_0_burst_17_downstream
}
# macro_sequence

# end
# entity
system_0_burst_17
# storage
db|DE2_SD_Card_Audio.(280).cnf
db|DE2_SD_Card_Audio.(280).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_17.v
abf8be685c774e2d3aa9b6b154293
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_17:the_system_0_burst_17
}
# macro_sequence

# end
# entity
system_0_burst_18_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(281).cnf
db|DE2_SD_Card_Audio.(281).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_18_upstream_arbitrator:the_system_0_burst_18_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_18_upstream_module
# storage
db|DE2_SD_Card_Audio.(282).cnf
db|DE2_SD_Card_Audio.(282).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_18_upstream_arbitrator:the_system_0_burst_18_upstream|burstcount_fifo_for_system_0_burst_18_upstream_module:burstcount_fifo_for_system_0_burst_18_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_18_upstream_module
# storage
db|DE2_SD_Card_Audio.(283).cnf
db|DE2_SD_Card_Audio.(283).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_18_upstream_arbitrator:the_system_0_burst_18_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_18_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_18_upstream
}
# macro_sequence

# end
# entity
system_0_burst_18_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(284).cnf
db|DE2_SD_Card_Audio.(284).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_18_downstream_arbitrator:the_system_0_burst_18_downstream
}
# macro_sequence

# end
# entity
system_0_burst_18
# storage
db|DE2_SD_Card_Audio.(285).cnf
db|DE2_SD_Card_Audio.(285).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_18.v
786f64f432fcc2058cc671c86873984
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_18:the_system_0_burst_18
}
# macro_sequence

# end
# entity
system_0_burst_19_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(286).cnf
db|DE2_SD_Card_Audio.(286).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_19_upstream_arbitrator:the_system_0_burst_19_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_19_upstream_module
# storage
db|DE2_SD_Card_Audio.(287).cnf
db|DE2_SD_Card_Audio.(287).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_19_upstream_arbitrator:the_system_0_burst_19_upstream|burstcount_fifo_for_system_0_burst_19_upstream_module:burstcount_fifo_for_system_0_burst_19_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_19_upstream_module
# storage
db|DE2_SD_Card_Audio.(288).cnf
db|DE2_SD_Card_Audio.(288).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_19_upstream_arbitrator:the_system_0_burst_19_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_19_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_19_upstream
}
# macro_sequence

# end
# entity
system_0_burst_19_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(289).cnf
db|DE2_SD_Card_Audio.(289).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_19_downstream_arbitrator:the_system_0_burst_19_downstream
}
# macro_sequence

# end
# entity
system_0_burst_19
# storage
db|DE2_SD_Card_Audio.(290).cnf
db|DE2_SD_Card_Audio.(290).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_19.v
9aa834dccdf2a8472ebb5f6e871923f5
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_19:the_system_0_burst_19
}
# macro_sequence

# end
# entity
system_0_burst_2_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(291).cnf
db|DE2_SD_Card_Audio.(291).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_2_upstream_arbitrator:the_system_0_burst_2_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_2_upstream_module
# storage
db|DE2_SD_Card_Audio.(292).cnf
db|DE2_SD_Card_Audio.(292).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_2_upstream_arbitrator:the_system_0_burst_2_upstream|burstcount_fifo_for_system_0_burst_2_upstream_module:burstcount_fifo_for_system_0_burst_2_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_2_upstream_module
# storage
db|DE2_SD_Card_Audio.(293).cnf
db|DE2_SD_Card_Audio.(293).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_2_upstream_arbitrator:the_system_0_burst_2_upstream|rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_2_upstream_module:rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_2_upstream
}
# macro_sequence

# end
# entity
system_0_burst_2_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(294).cnf
db|DE2_SD_Card_Audio.(294).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_2_downstream_arbitrator:the_system_0_burst_2_downstream
}
# macro_sequence

# end
# entity
system_0_burst_2
# storage
db|DE2_SD_Card_Audio.(295).cnf
db|DE2_SD_Card_Audio.(295).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_2.v
b8a45eb881dddf252228cf9d5aadbacb
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_2:the_system_0_burst_2
}
# macro_sequence

# end
# entity
system_0_burst_20_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(296).cnf
db|DE2_SD_Card_Audio.(296).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_20_upstream_arbitrator:the_system_0_burst_20_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_20_upstream_module
# storage
db|DE2_SD_Card_Audio.(297).cnf
db|DE2_SD_Card_Audio.(297).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_20_upstream_arbitrator:the_system_0_burst_20_upstream|burstcount_fifo_for_system_0_burst_20_upstream_module:burstcount_fifo_for_system_0_burst_20_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_20_upstream_module
# storage
db|DE2_SD_Card_Audio.(298).cnf
db|DE2_SD_Card_Audio.(298).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_20_upstream_arbitrator:the_system_0_burst_20_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_20_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_20_upstream
}
# macro_sequence

# end
# entity
system_0_burst_20_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(299).cnf
db|DE2_SD_Card_Audio.(299).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_20_downstream_arbitrator:the_system_0_burst_20_downstream
}
# macro_sequence

# end
# entity
system_0_burst_20
# storage
db|DE2_SD_Card_Audio.(300).cnf
db|DE2_SD_Card_Audio.(300).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_20.v
e072c79531c8552d6c86a7fae3f9a46b
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_20:the_system_0_burst_20
}
# macro_sequence

# end
# entity
system_0_burst_21_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(301).cnf
db|DE2_SD_Card_Audio.(301).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_21_upstream_arbitrator:the_system_0_burst_21_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_21_upstream_module
# storage
db|DE2_SD_Card_Audio.(302).cnf
db|DE2_SD_Card_Audio.(302).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_21_upstream_arbitrator:the_system_0_burst_21_upstream|burstcount_fifo_for_system_0_burst_21_upstream_module:burstcount_fifo_for_system_0_burst_21_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_21_upstream_module
# storage
db|DE2_SD_Card_Audio.(303).cnf
db|DE2_SD_Card_Audio.(303).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_21_upstream_arbitrator:the_system_0_burst_21_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_21_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_21_upstream
}
# macro_sequence

# end
# entity
system_0_burst_21_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(304).cnf
db|DE2_SD_Card_Audio.(304).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_21_downstream_arbitrator:the_system_0_burst_21_downstream
}
# macro_sequence

# end
# entity
system_0_burst_21
# storage
db|DE2_SD_Card_Audio.(305).cnf
db|DE2_SD_Card_Audio.(305).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_21.v
dbd6b968a6bc8b0dd76dbad59125eb9
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_21:the_system_0_burst_21
}
# macro_sequence

# end
# entity
system_0_burst_22_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(306).cnf
db|DE2_SD_Card_Audio.(306).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_22_upstream_arbitrator:the_system_0_burst_22_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_22_upstream_module
# storage
db|DE2_SD_Card_Audio.(307).cnf
db|DE2_SD_Card_Audio.(307).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_22_upstream_arbitrator:the_system_0_burst_22_upstream|burstcount_fifo_for_system_0_burst_22_upstream_module:burstcount_fifo_for_system_0_burst_22_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_22_upstream_module
# storage
db|DE2_SD_Card_Audio.(308).cnf
db|DE2_SD_Card_Audio.(308).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_22_upstream_arbitrator:the_system_0_burst_22_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_22_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_22_upstream
}
# macro_sequence

# end
# entity
system_0_burst_22_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(309).cnf
db|DE2_SD_Card_Audio.(309).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_22_downstream_arbitrator:the_system_0_burst_22_downstream
}
# macro_sequence

# end
# entity
system_0_burst_22
# storage
db|DE2_SD_Card_Audio.(310).cnf
db|DE2_SD_Card_Audio.(310).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_22.v
a9ec6e365ab7557853e9230f22a16b0
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_22:the_system_0_burst_22
}
# macro_sequence

# end
# entity
system_0_burst_23_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(311).cnf
db|DE2_SD_Card_Audio.(311).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_23_upstream_arbitrator:the_system_0_burst_23_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_23_upstream_module
# storage
db|DE2_SD_Card_Audio.(312).cnf
db|DE2_SD_Card_Audio.(312).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_23_upstream_arbitrator:the_system_0_burst_23_upstream|burstcount_fifo_for_system_0_burst_23_upstream_module:burstcount_fifo_for_system_0_burst_23_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_23_upstream_module
# storage
db|DE2_SD_Card_Audio.(313).cnf
db|DE2_SD_Card_Audio.(313).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_23_upstream_arbitrator:the_system_0_burst_23_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_23_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_23_upstream
}
# macro_sequence

# end
# entity
system_0_burst_23_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(314).cnf
db|DE2_SD_Card_Audio.(314).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_23_downstream_arbitrator:the_system_0_burst_23_downstream
}
# macro_sequence

# end
# entity
system_0_burst_23
# storage
db|DE2_SD_Card_Audio.(315).cnf
db|DE2_SD_Card_Audio.(315).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_23.v
3097d650eeea699ccf75f38e5d40a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_23:the_system_0_burst_23
}
# macro_sequence

# end
# entity
system_0_burst_24_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(316).cnf
db|DE2_SD_Card_Audio.(316).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_24_upstream_arbitrator:the_system_0_burst_24_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_24_upstream_module
# storage
db|DE2_SD_Card_Audio.(317).cnf
db|DE2_SD_Card_Audio.(317).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_24_upstream_arbitrator:the_system_0_burst_24_upstream|burstcount_fifo_for_system_0_burst_24_upstream_module:burstcount_fifo_for_system_0_burst_24_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_24_upstream_module
# storage
db|DE2_SD_Card_Audio.(318).cnf
db|DE2_SD_Card_Audio.(318).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_24_upstream_arbitrator:the_system_0_burst_24_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_24_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_24_upstream
}
# macro_sequence

# end
# entity
system_0_burst_24_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(319).cnf
db|DE2_SD_Card_Audio.(319).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_24_downstream_arbitrator:the_system_0_burst_24_downstream
}
# macro_sequence

# end
# entity
system_0_burst_24
# storage
db|DE2_SD_Card_Audio.(320).cnf
db|DE2_SD_Card_Audio.(320).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_24.v
88eef5a44e88c19db73663eb14ee669
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_24:the_system_0_burst_24
}
# macro_sequence

# end
# entity
system_0_burst_25_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(321).cnf
db|DE2_SD_Card_Audio.(321).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_25_upstream_arbitrator:the_system_0_burst_25_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_25_upstream_module
# storage
db|DE2_SD_Card_Audio.(322).cnf
db|DE2_SD_Card_Audio.(322).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_25_upstream_arbitrator:the_system_0_burst_25_upstream|burstcount_fifo_for_system_0_burst_25_upstream_module:burstcount_fifo_for_system_0_burst_25_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_25_upstream_module
# storage
db|DE2_SD_Card_Audio.(323).cnf
db|DE2_SD_Card_Audio.(323).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_25_upstream_arbitrator:the_system_0_burst_25_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_25_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_25_upstream
}
# macro_sequence

# end
# entity
system_0_burst_25_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(324).cnf
db|DE2_SD_Card_Audio.(324).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_25_downstream_arbitrator:the_system_0_burst_25_downstream
}
# macro_sequence

# end
# entity
system_0_burst_25
# storage
db|DE2_SD_Card_Audio.(325).cnf
db|DE2_SD_Card_Audio.(325).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_25.v
3375c47977752fe11af9c395a4ae6
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_25:the_system_0_burst_25
}
# macro_sequence

# end
# entity
system_0_burst_26_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(326).cnf
db|DE2_SD_Card_Audio.(326).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_26_upstream_arbitrator:the_system_0_burst_26_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_26_upstream_module
# storage
db|DE2_SD_Card_Audio.(327).cnf
db|DE2_SD_Card_Audio.(327).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_26_upstream_arbitrator:the_system_0_burst_26_upstream|burstcount_fifo_for_system_0_burst_26_upstream_module:burstcount_fifo_for_system_0_burst_26_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_26_upstream_module
# storage
db|DE2_SD_Card_Audio.(328).cnf
db|DE2_SD_Card_Audio.(328).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_26_upstream_arbitrator:the_system_0_burst_26_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_26_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_26_upstream
}
# macro_sequence

# end
# entity
system_0_burst_26_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(329).cnf
db|DE2_SD_Card_Audio.(329).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_26_downstream_arbitrator:the_system_0_burst_26_downstream
}
# macro_sequence

# end
# entity
system_0_burst_26
# storage
db|DE2_SD_Card_Audio.(330).cnf
db|DE2_SD_Card_Audio.(330).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_26.v
45ef0ab263bd8821478546b7589ffb
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_26:the_system_0_burst_26
}
# macro_sequence

# end
# entity
system_0_burst_27_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(331).cnf
db|DE2_SD_Card_Audio.(331).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_27_upstream_arbitrator:the_system_0_burst_27_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_27_upstream_module
# storage
db|DE2_SD_Card_Audio.(332).cnf
db|DE2_SD_Card_Audio.(332).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_27_upstream_arbitrator:the_system_0_burst_27_upstream|burstcount_fifo_for_system_0_burst_27_upstream_module:burstcount_fifo_for_system_0_burst_27_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_27_upstream_module
# storage
db|DE2_SD_Card_Audio.(333).cnf
db|DE2_SD_Card_Audio.(333).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_27_upstream_arbitrator:the_system_0_burst_27_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_27_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_27_upstream
}
# macro_sequence

# end
# entity
system_0_burst_27_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(334).cnf
db|DE2_SD_Card_Audio.(334).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_27_downstream_arbitrator:the_system_0_burst_27_downstream
}
# macro_sequence

# end
# entity
system_0_burst_27
# storage
db|DE2_SD_Card_Audio.(335).cnf
db|DE2_SD_Card_Audio.(335).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_27.v
acc3928b5d81876b13418de9bea04355
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_27:the_system_0_burst_27
}
# macro_sequence

# end
# entity
system_0_burst_28_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(336).cnf
db|DE2_SD_Card_Audio.(336).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_28_upstream_arbitrator:the_system_0_burst_28_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_28_upstream_module
# storage
db|DE2_SD_Card_Audio.(337).cnf
db|DE2_SD_Card_Audio.(337).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_28_upstream_arbitrator:the_system_0_burst_28_upstream|burstcount_fifo_for_system_0_burst_28_upstream_module:burstcount_fifo_for_system_0_burst_28_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_28_upstream_module
# storage
db|DE2_SD_Card_Audio.(338).cnf
db|DE2_SD_Card_Audio.(338).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_28_upstream_arbitrator:the_system_0_burst_28_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_28_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_28_upstream
}
# macro_sequence

# end
# entity
system_0_burst_28_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(339).cnf
db|DE2_SD_Card_Audio.(339).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_28_downstream_arbitrator:the_system_0_burst_28_downstream
}
# macro_sequence

# end
# entity
system_0_burst_28
# storage
db|DE2_SD_Card_Audio.(340).cnf
db|DE2_SD_Card_Audio.(340).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_28.v
fbf0367ee027dd209c67561012d6efdf
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_28:the_system_0_burst_28
}
# macro_sequence

# end
# entity
system_0_burst_29_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(341).cnf
db|DE2_SD_Card_Audio.(341).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_29_upstream_arbitrator:the_system_0_burst_29_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_29_upstream_module
# storage
db|DE2_SD_Card_Audio.(342).cnf
db|DE2_SD_Card_Audio.(342).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_29_upstream_arbitrator:the_system_0_burst_29_upstream|burstcount_fifo_for_system_0_burst_29_upstream_module:burstcount_fifo_for_system_0_burst_29_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_29_upstream_module
# storage
db|DE2_SD_Card_Audio.(343).cnf
db|DE2_SD_Card_Audio.(343).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_29_upstream_arbitrator:the_system_0_burst_29_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_29_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_29_upstream
}
# macro_sequence

# end
# entity
system_0_burst_29_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(344).cnf
db|DE2_SD_Card_Audio.(344).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_29_downstream_arbitrator:the_system_0_burst_29_downstream
}
# macro_sequence

# end
# entity
system_0_burst_29
# storage
db|DE2_SD_Card_Audio.(345).cnf
db|DE2_SD_Card_Audio.(345).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_29.v
5cb42d1b4604cea6149da736239bcf2
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_29:the_system_0_burst_29
}
# macro_sequence

# end
# entity
system_0_burst_3_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(346).cnf
db|DE2_SD_Card_Audio.(346).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_3_upstream_arbitrator:the_system_0_burst_3_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_3_upstream_module
# storage
db|DE2_SD_Card_Audio.(347).cnf
db|DE2_SD_Card_Audio.(347).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_3_upstream_arbitrator:the_system_0_burst_3_upstream|burstcount_fifo_for_system_0_burst_3_upstream_module:burstcount_fifo_for_system_0_burst_3_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_3_upstream_module
# storage
db|DE2_SD_Card_Audio.(348).cnf
db|DE2_SD_Card_Audio.(348).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_3_upstream_arbitrator:the_system_0_burst_3_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_3_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_3_upstream
}
# macro_sequence

# end
# entity
system_0_burst_3_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(349).cnf
db|DE2_SD_Card_Audio.(349).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_3_downstream_arbitrator:the_system_0_burst_3_downstream
}
# macro_sequence

# end
# entity
system_0_burst_3
# storage
db|DE2_SD_Card_Audio.(350).cnf
db|DE2_SD_Card_Audio.(350).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_3.v
89646f2ff9641e99dc74d93da286f39
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_3:the_system_0_burst_3
}
# macro_sequence

# end
# entity
system_0_burst_30_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(351).cnf
db|DE2_SD_Card_Audio.(351).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_30_upstream_arbitrator:the_system_0_burst_30_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_30_upstream_module
# storage
db|DE2_SD_Card_Audio.(352).cnf
db|DE2_SD_Card_Audio.(352).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_30_upstream_arbitrator:the_system_0_burst_30_upstream|burstcount_fifo_for_system_0_burst_30_upstream_module:burstcount_fifo_for_system_0_burst_30_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_30_upstream_module
# storage
db|DE2_SD_Card_Audio.(353).cnf
db|DE2_SD_Card_Audio.(353).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_30_upstream_arbitrator:the_system_0_burst_30_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_30_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_30_upstream
}
# macro_sequence

# end
# entity
system_0_burst_30_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(354).cnf
db|DE2_SD_Card_Audio.(354).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_30_downstream_arbitrator:the_system_0_burst_30_downstream
}
# macro_sequence

# end
# entity
system_0_burst_30
# storage
db|DE2_SD_Card_Audio.(355).cnf
db|DE2_SD_Card_Audio.(355).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_30.v
9a235cba23d25dafc6f37d2baf6a81
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_30:the_system_0_burst_30
}
# macro_sequence

# end
# entity
system_0_burst_31_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(356).cnf
db|DE2_SD_Card_Audio.(356).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_31_upstream_arbitrator:the_system_0_burst_31_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_31_upstream_module
# storage
db|DE2_SD_Card_Audio.(357).cnf
db|DE2_SD_Card_Audio.(357).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_31_upstream_arbitrator:the_system_0_burst_31_upstream|burstcount_fifo_for_system_0_burst_31_upstream_module:burstcount_fifo_for_system_0_burst_31_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_31_upstream_module
# storage
db|DE2_SD_Card_Audio.(358).cnf
db|DE2_SD_Card_Audio.(358).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_31_upstream_arbitrator:the_system_0_burst_31_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_31_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_31_upstream
}
# macro_sequence

# end
# entity
system_0_burst_31_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(359).cnf
db|DE2_SD_Card_Audio.(359).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_31_downstream_arbitrator:the_system_0_burst_31_downstream
}
# macro_sequence

# end
# entity
system_0_burst_31
# storage
db|DE2_SD_Card_Audio.(360).cnf
db|DE2_SD_Card_Audio.(360).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_31.v
e8a015be29f3eccd4368a917b45f7bd
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_31:the_system_0_burst_31
}
# macro_sequence

# end
# entity
system_0_burst_32_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(361).cnf
db|DE2_SD_Card_Audio.(361).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_32_upstream_arbitrator:the_system_0_burst_32_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_32_upstream_module
# storage
db|DE2_SD_Card_Audio.(362).cnf
db|DE2_SD_Card_Audio.(362).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_32_upstream_arbitrator:the_system_0_burst_32_upstream|burstcount_fifo_for_system_0_burst_32_upstream_module:burstcount_fifo_for_system_0_burst_32_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_32_upstream_module
# storage
db|DE2_SD_Card_Audio.(363).cnf
db|DE2_SD_Card_Audio.(363).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_32_upstream_arbitrator:the_system_0_burst_32_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_32_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_32_upstream
}
# macro_sequence

# end
# entity
system_0_burst_32_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(364).cnf
db|DE2_SD_Card_Audio.(364).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_32_downstream_arbitrator:the_system_0_burst_32_downstream
}
# macro_sequence

# end
# entity
system_0_burst_32
# storage
db|DE2_SD_Card_Audio.(365).cnf
db|DE2_SD_Card_Audio.(365).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_32.v
87e2caf3b2a726a6dc79ae12a1768589
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_32:the_system_0_burst_32
}
# macro_sequence

# end
# entity
system_0_burst_33_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(366).cnf
db|DE2_SD_Card_Audio.(366).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_33_upstream_arbitrator:the_system_0_burst_33_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_33_upstream_module
# storage
db|DE2_SD_Card_Audio.(367).cnf
db|DE2_SD_Card_Audio.(367).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_33_upstream_arbitrator:the_system_0_burst_33_upstream|burstcount_fifo_for_system_0_burst_33_upstream_module:burstcount_fifo_for_system_0_burst_33_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_33_upstream_module
# storage
db|DE2_SD_Card_Audio.(368).cnf
db|DE2_SD_Card_Audio.(368).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_33_upstream_arbitrator:the_system_0_burst_33_upstream|rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_33_upstream_module:rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_33_upstream
}
# macro_sequence

# end
# entity
system_0_burst_33_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(369).cnf
db|DE2_SD_Card_Audio.(369).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_33_downstream_arbitrator:the_system_0_burst_33_downstream
}
# macro_sequence

# end
# entity
system_0_burst_33
# storage
db|DE2_SD_Card_Audio.(370).cnf
db|DE2_SD_Card_Audio.(370).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_33.v
4a3a41fbec809f99e98a2358fd6948f1
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_33:the_system_0_burst_33
}
# macro_sequence

# end
# entity
system_0_burst_34_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(371).cnf
db|DE2_SD_Card_Audio.(371).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_34_upstream_arbitrator:the_system_0_burst_34_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_34_upstream_module
# storage
db|DE2_SD_Card_Audio.(372).cnf
db|DE2_SD_Card_Audio.(372).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_34_upstream_arbitrator:the_system_0_burst_34_upstream|burstcount_fifo_for_system_0_burst_34_upstream_module:burstcount_fifo_for_system_0_burst_34_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_34_upstream_module
# storage
db|DE2_SD_Card_Audio.(373).cnf
db|DE2_SD_Card_Audio.(373).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_34_upstream_arbitrator:the_system_0_burst_34_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_34_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_34_upstream
}
# macro_sequence

# end
# entity
system_0_burst_34_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(374).cnf
db|DE2_SD_Card_Audio.(374).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_34_downstream_arbitrator:the_system_0_burst_34_downstream
}
# macro_sequence

# end
# entity
system_0_burst_34
# storage
db|DE2_SD_Card_Audio.(375).cnf
db|DE2_SD_Card_Audio.(375).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_34.v
f35ee1050effae1d42222f2387d979b
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_34:the_system_0_burst_34
}
# macro_sequence

# end
# entity
system_0_burst_35_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(376).cnf
db|DE2_SD_Card_Audio.(376).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_35_upstream_arbitrator:the_system_0_burst_35_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_35_upstream_module
# storage
db|DE2_SD_Card_Audio.(377).cnf
db|DE2_SD_Card_Audio.(377).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_35_upstream_arbitrator:the_system_0_burst_35_upstream|burstcount_fifo_for_system_0_burst_35_upstream_module:burstcount_fifo_for_system_0_burst_35_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_35_upstream_module
# storage
db|DE2_SD_Card_Audio.(378).cnf
db|DE2_SD_Card_Audio.(378).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_35_upstream_arbitrator:the_system_0_burst_35_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_35_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_35_upstream
}
# macro_sequence

# end
# entity
system_0_burst_35_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(379).cnf
db|DE2_SD_Card_Audio.(379).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_35_downstream_arbitrator:the_system_0_burst_35_downstream
}
# macro_sequence

# end
# entity
system_0_burst_35
# storage
db|DE2_SD_Card_Audio.(380).cnf
db|DE2_SD_Card_Audio.(380).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_35.v
da1ac6aa58d1a71f71e67a8ead099c6
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_35:the_system_0_burst_35
}
# macro_sequence

# end
# entity
system_0_burst_4_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(381).cnf
db|DE2_SD_Card_Audio.(381).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_4_upstream_arbitrator:the_system_0_burst_4_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_4_upstream_module
# storage
db|DE2_SD_Card_Audio.(382).cnf
db|DE2_SD_Card_Audio.(382).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_4_upstream_arbitrator:the_system_0_burst_4_upstream|burstcount_fifo_for_system_0_burst_4_upstream_module:burstcount_fifo_for_system_0_burst_4_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_4_upstream_module
# storage
db|DE2_SD_Card_Audio.(383).cnf
db|DE2_SD_Card_Audio.(383).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_4_upstream_arbitrator:the_system_0_burst_4_upstream|rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_4_upstream_module:rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_4_upstream
}
# macro_sequence

# end
# entity
system_0_burst_4_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(384).cnf
db|DE2_SD_Card_Audio.(384).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_4_downstream_arbitrator:the_system_0_burst_4_downstream
}
# macro_sequence

# end
# entity
system_0_burst_4
# storage
db|DE2_SD_Card_Audio.(385).cnf
db|DE2_SD_Card_Audio.(385).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_4.v
e8ffe82420409e57c3321e40a7516454
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_4:the_system_0_burst_4
}
# macro_sequence

# end
# entity
system_0_burst_5_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(386).cnf
db|DE2_SD_Card_Audio.(386).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_5_upstream_arbitrator:the_system_0_burst_5_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_5_upstream_module
# storage
db|DE2_SD_Card_Audio.(387).cnf
db|DE2_SD_Card_Audio.(387).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_5_upstream_arbitrator:the_system_0_burst_5_upstream|burstcount_fifo_for_system_0_burst_5_upstream_module:burstcount_fifo_for_system_0_burst_5_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_5_upstream_module
# storage
db|DE2_SD_Card_Audio.(388).cnf
db|DE2_SD_Card_Audio.(388).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_5_upstream_arbitrator:the_system_0_burst_5_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_5_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_5_upstream
}
# macro_sequence

# end
# entity
system_0_burst_5_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(389).cnf
db|DE2_SD_Card_Audio.(389).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_5_downstream_arbitrator:the_system_0_burst_5_downstream
}
# macro_sequence

# end
# entity
system_0_burst_5
# storage
db|DE2_SD_Card_Audio.(390).cnf
db|DE2_SD_Card_Audio.(390).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_5.v
929322948d05aec5e463bfe1197c8ba
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_5:the_system_0_burst_5
}
# macro_sequence

# end
# entity
system_0_burst_6_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(391).cnf
db|DE2_SD_Card_Audio.(391).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_6_upstream_arbitrator:the_system_0_burst_6_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_6_upstream_module
# storage
db|DE2_SD_Card_Audio.(392).cnf
db|DE2_SD_Card_Audio.(392).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_6_upstream_arbitrator:the_system_0_burst_6_upstream|burstcount_fifo_for_system_0_burst_6_upstream_module:burstcount_fifo_for_system_0_burst_6_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_6_upstream_module
# storage
db|DE2_SD_Card_Audio.(393).cnf
db|DE2_SD_Card_Audio.(393).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_6_upstream_arbitrator:the_system_0_burst_6_upstream|rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_6_upstream_module:rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_6_upstream
}
# macro_sequence

# end
# entity
system_0_burst_6_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(394).cnf
db|DE2_SD_Card_Audio.(394).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_6_downstream_arbitrator:the_system_0_burst_6_downstream
}
# macro_sequence

# end
# entity
system_0_burst_6
# storage
db|DE2_SD_Card_Audio.(395).cnf
db|DE2_SD_Card_Audio.(395).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_6.v
b1d5f9d9bbd9d07ce3e5e78481b79e
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_6:the_system_0_burst_6
}
# macro_sequence

# end
# entity
system_0_burst_7_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(396).cnf
db|DE2_SD_Card_Audio.(396).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_7_upstream_arbitrator:the_system_0_burst_7_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_7_upstream_module
# storage
db|DE2_SD_Card_Audio.(397).cnf
db|DE2_SD_Card_Audio.(397).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_7_upstream_arbitrator:the_system_0_burst_7_upstream|burstcount_fifo_for_system_0_burst_7_upstream_module:burstcount_fifo_for_system_0_burst_7_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_7_upstream_module
# storage
db|DE2_SD_Card_Audio.(398).cnf
db|DE2_SD_Card_Audio.(398).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_7_upstream_arbitrator:the_system_0_burst_7_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_7_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_7_upstream
}
# macro_sequence

# end
# entity
system_0_burst_7_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(399).cnf
db|DE2_SD_Card_Audio.(399).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_7_downstream_arbitrator:the_system_0_burst_7_downstream
}
# macro_sequence

# end
# entity
system_0_burst_7
# storage
db|DE2_SD_Card_Audio.(400).cnf
db|DE2_SD_Card_Audio.(400).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_7.v
ae52aaa4a35e034a63d43c424bf895
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_7:the_system_0_burst_7
}
# macro_sequence

# end
# entity
system_0_burst_8_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(401).cnf
db|DE2_SD_Card_Audio.(401).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_8_upstream_arbitrator:the_system_0_burst_8_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_8_upstream_module
# storage
db|DE2_SD_Card_Audio.(402).cnf
db|DE2_SD_Card_Audio.(402).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_8_upstream_arbitrator:the_system_0_burst_8_upstream|burstcount_fifo_for_system_0_burst_8_upstream_module:burstcount_fifo_for_system_0_burst_8_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_8_upstream_module
# storage
db|DE2_SD_Card_Audio.(403).cnf
db|DE2_SD_Card_Audio.(403).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_8_upstream_arbitrator:the_system_0_burst_8_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_8_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_8_upstream
}
# macro_sequence

# end
# entity
system_0_burst_8_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(404).cnf
db|DE2_SD_Card_Audio.(404).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_8_downstream_arbitrator:the_system_0_burst_8_downstream
}
# macro_sequence

# end
# entity
system_0_burst_8
# storage
db|DE2_SD_Card_Audio.(405).cnf
db|DE2_SD_Card_Audio.(405).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_8.v
29fe543abbd94d48df291c21f46d766
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_8:the_system_0_burst_8
}
# macro_sequence

# end
# entity
system_0_burst_9_upstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(406).cnf
db|DE2_SD_Card_Audio.(406).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_9_upstream_arbitrator:the_system_0_burst_9_upstream
}
# macro_sequence

# end
# entity
burstcount_fifo_for_system_0_burst_9_upstream_module
# storage
db|DE2_SD_Card_Audio.(407).cnf
db|DE2_SD_Card_Audio.(407).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_9_upstream_arbitrator:the_system_0_burst_9_upstream|burstcount_fifo_for_system_0_burst_9_upstream_module:burstcount_fifo_for_system_0_burst_9_upstream
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_0_data_master_to_system_0_burst_9_upstream_module
# storage
db|DE2_SD_Card_Audio.(408).cnf
db|DE2_SD_Card_Audio.(408).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_9_upstream_arbitrator:the_system_0_burst_9_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_9_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_9_upstream
}
# macro_sequence

# end
# entity
system_0_burst_9_downstream_arbitrator
# storage
db|DE2_SD_Card_Audio.(409).cnf
db|DE2_SD_Card_Audio.(409).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_9_downstream_arbitrator:the_system_0_burst_9_downstream
}
# macro_sequence

# end
# entity
system_0_burst_9
# storage
db|DE2_SD_Card_Audio.(410).cnf
db|DE2_SD_Card_Audio.(410).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0_burst_9.v
293ac1aa1c77923db1f18e0e3c5f7dc
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_burst_9:the_system_0_burst_9
}
# macro_sequence

# end
# entity
system_0_clock_0_in_arbitrator
# storage
db|DE2_SD_Card_Audio.(411).cnf
db|DE2_SD_Card_Audio.(411).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_clock_0_in_arbitrator:the_system_0_clock_0_in
}
# macro_sequence

# end
# entity
system_0_clock_0_out_arbitrator
# storage
db|DE2_SD_Card_Audio.(412).cnf
db|DE2_SD_Card_Audio.(412).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_clock_0_out_arbitrator:the_system_0_clock_0_out
}
# macro_sequence

# end
# entity
timer_0_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(413).cnf
db|DE2_SD_Card_Audio.(413).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|timer_0_s1_arbitrator:the_timer_0_s1
}
# macro_sequence

# end
# entity
timer_1_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(414).cnf
db|DE2_SD_Card_Audio.(414).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|timer_1_s1_arbitrator:the_timer_1_s1
}
# macro_sequence

# end
# entity
tri_state_bridge_0_avalon_slave_arbitrator
# storage
db|DE2_SD_Card_Audio.(415).cnf
db|DE2_SD_Card_Audio.(415).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave
}
# macro_sequence

# end
# entity
uart_0_s1_arbitrator
# storage
db|DE2_SD_Card_Audio.(416).cnf
db|DE2_SD_Card_Audio.(416).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|uart_0_s1_arbitrator:the_uart_0_s1
}
# macro_sequence

# end
# entity
system_0_reset_altpll_0_c1_out_domain_synch_module
# storage
db|DE2_SD_Card_Audio.(417).cnf
db|DE2_SD_Card_Audio.(417).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_reset_altpll_0_c1_out_domain_synch_module:system_0_reset_altpll_0_c1_out_domain_synch
}
# macro_sequence

# end
# entity
system_0_reset_clk_domain_synch_module
# storage
db|DE2_SD_Card_Audio.(418).cnf
db|DE2_SD_Card_Audio.(418).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
3171e6506adf61508b2eddb97578923a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch
}
# macro_sequence

# end
# complete

