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//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
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// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module I2C_Core (
                  // inputs:
                   wb_adr_i,
                   wb_clk_i,
                   wb_cyc_i,
                   wb_dat_i,
                   wb_rst_i,
                   wb_stb_i,
                   wb_we_i,

                  // outputs:
                   scl_pad_io,
                   sda_pad_io,
                   wb_ack_o,
                   wb_dat_o,
                   wb_err_o,
                   wb_inta_o
                )
;

  inout            scl_pad_io;
  inout            sda_pad_io;
  output           wb_ack_o;
  output  [ 31: 0] wb_dat_o;
  output           wb_err_o;
  output           wb_inta_o;
  input   [  2: 0] wb_adr_i;
  input            wb_clk_i;
  input            wb_cyc_i;
  input   [ 31: 0] wb_dat_i;
  input            wb_rst_i;
  input            wb_stb_i;
  input            wb_we_i;

  wire             scl_pad_io;
  wire             sda_pad_io;
  wire             wb_ack_o;
  wire    [ 31: 0] wb_dat_o;
  wire             wb_err_o;
  wire             wb_inta_o;
  oc_i2c_master the_oc_i2c_master
    (
      .scl_pad_io (scl_pad_io),
      .sda_pad_io (sda_pad_io),
      .wb_ack_o   (wb_ack_o),
      .wb_adr_i   (wb_adr_i),
      .wb_clk_i   (wb_clk_i),
      .wb_cyc_i   (wb_cyc_i),
      .wb_dat_i   (wb_dat_i),
      .wb_dat_o   (wb_dat_o),
      .wb_err_o   (wb_err_o),
      .wb_inta_o  (wb_inta_o),
      .wb_rst_i   (wb_rst_i),
      .wb_stb_i   (wb_stb_i),
      .wb_we_i    (wb_we_i)
    );


endmodule

