{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition " "Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 12 14:05:42 2013 " "Info: Processing started: Fri Apr 12 14:05:42 2013" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DE2_SD_Card_Audio -c DE2_SD_Card_Audio " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_SD_Card_Audio -c DE2_SD_Card_Audio" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WIDU_QIC_OFF_NOT_SUPPORTED" "" "Critical Warning: Setting INCREMENTAL_COMPILATION to \"OFF\" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to \"ON\" instead." {  } {  } 1 0 "Setting INCREMENTAL_COMPILATION to \"OFF\" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to \"ON\" instead." 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "onchip_memory2_0.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file onchip_memory2_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 onchip_memory2_0 " "Info: Found entity 1: onchip_memory2_0" {  } { { "onchip_memory2_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/onchip_memory2_0.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system_0_clock_2.v 5 5 " "Info: Found 5 design units, including 5 entities, in source file system_0_clock_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_0_clock_2_edge_to_pulse " "Info: Found entity 1: system_0_clock_2_edge_to_pulse" {  } { { "system_0_clock_2.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_2.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 system_0_clock_2_slave_FSM " "Info: Found entity 2: system_0_clock_2_slave_FSM" {  } { { "system_0_clock_2.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_2.v" 58 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 system_0_clock_2_master_FSM " "Info: Found entity 3: system_0_clock_2_master_FSM" {  } { { "system_0_clock_2.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_2.v" 199 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "4 system_0_clock_2_bit_pipe " "Info: Found entity 4: system_0_clock_2_bit_pipe" {  } { { "system_0_clock_2.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_2.v" 365 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "5 system_0_clock_2 " "Info: Found entity 5: system_0_clock_2" {  } { { "system_0_clock_2.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_2.v" 417 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "I2C_Controller.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file I2C_Controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_Controller " "Info: Found entity 1: I2C_Controller" {  } { { "I2C_Controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_Controller.v" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "I2C_AV_Config.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file I2C_AV_Config.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_AV_Config " "Info: Found entity 1: I2C_AV_Config" {  } { { "I2C_AV_Config.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_AV_Config.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Oct_DOWN.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Oct_DOWN.v" { { "Info" "ISGN_ENTITY_NAME" "1 Oct_DOWN " "Info: Found entity 1: Oct_DOWN" {  } { { "Oct_DOWN.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Oct_DOWN.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Oct_UP.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Oct_UP.v" { { "Info" "ISGN_ENTITY_NAME" "1 Oct_UP " "Info: Found entity 1: Oct_UP" {  } { { "Oct_UP.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Oct_UP.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RST.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file RST.v" { { "Info" "ISGN_ENTITY_NAME" "1 RST " "Info: Found entity 1: RST" {  } { { "RST.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/RST.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dist_sensor.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dist_sensor.v" { { "Info" "ISGN_ENTITY_NAME" "1 dist_sensor " "Info: Found entity 1: dist_sensor" {  } { { "dist_sensor.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/dist_sensor.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "noteG.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file noteG.v" { { "Info" "ISGN_ENTITY_NAME" "1 noteG " "Info: Found entity 1: noteG" {  } { { "noteG.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/noteG.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "noteF.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file noteF.v" { { "Info" "ISGN_ENTITY_NAME" "1 noteF " "Info: Found entity 1: noteF" {  } { { "noteF.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/noteF.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "noteE.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file noteE.v" { { "Info" "ISGN_ENTITY_NAME" "1 noteE " "Info: Found entity 1: noteE" {  } { { "noteE.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/noteE.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "noteD.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file noteD.v" { { "Info" "ISGN_ENTITY_NAME" "1 noteD " "Info: Found entity 1: noteD" {  } { { "noteD.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/noteD.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "noteC.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file noteC.v" { { "Info" "ISGN_ENTITY_NAME" "1 noteC " "Info: Found entity 1: noteC" {  } { { "noteC.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/noteC.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "noteB.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file noteB.v" { { "Info" "ISGN_ENTITY_NAME" "1 noteB " "Info: Found entity 1: noteB" {  } { { "noteB.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/noteB.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MS.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MS.v" { { "Info" "ISGN_ENTITY_NAME" "1 MS " "Info: Found entity 1: MS" {  } { { "MS.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/MS.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MReset.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MReset.v" { { "Info" "ISGN_ENTITY_NAME" "1 MReset " "Info: Found entity 1: MReset" {  } { { "MReset.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/MReset.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "noteA.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file noteA.v" { { "Info" "ISGN_ENTITY_NAME" "1 noteA " "Info: Found entity 1: noteA" {  } { { "noteA.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/noteA.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu_0_oci_test_bench.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cpu_0_oci_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_oci_test_bench " "Info: Found entity 1: cpu_0_oci_test_bench" {  } { { "cpu_0_oci_test_bench.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_oci_test_bench.v" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu_0_jtag_debug_module_tck.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cpu_0_jtag_debug_module_tck.v" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_jtag_debug_module_tck " "Info: Found entity 1: cpu_0_jtag_debug_module_tck" {  } { { "cpu_0_jtag_debug_module_tck.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_jtag_debug_module_tck.v" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system_0_clock_1.v 5 5 " "Info: Found 5 design units, including 5 entities, in source file system_0_clock_1.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_0_clock_1_edge_to_pulse " "Info: Found entity 1: system_0_clock_1_edge_to_pulse" {  } { { "system_0_clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_1.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 system_0_clock_1_slave_FSM " "Info: Found entity 2: system_0_clock_1_slave_FSM" {  } { { "system_0_clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_1.v" 58 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 system_0_clock_1_master_FSM " "Info: Found entity 3: system_0_clock_1_master_FSM" {  } { { "system_0_clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_1.v" 199 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "4 system_0_clock_1_bit_pipe " "Info: Found entity 4: system_0_clock_1_bit_pipe" {  } { { "system_0_clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_1.v" 365 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "5 system_0_clock_1 " "Info: Found entity 5: system_0_clock_1" {  } { { "system_0_clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_1.v" 417 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system_0_clock_0.v 5 5 " "Info: Found 5 design units, including 5 entities, in source file system_0_clock_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_0_clock_0_edge_to_pulse " "Info: Found entity 1: system_0_clock_0_edge_to_pulse" {  } { { "system_0_clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 system_0_clock_0_slave_FSM " "Info: Found entity 2: system_0_clock_0_slave_FSM" {  } { { "system_0_clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 58 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 system_0_clock_0_master_FSM " "Info: Found entity 3: system_0_clock_0_master_FSM" {  } { { "system_0_clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 199 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "4 system_0_clock_0_bit_pipe " "Info: Found entity 4: system_0_clock_0_bit_pipe" {  } { { "system_0_clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 365 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "5 system_0_clock_0 " "Info: Found entity 5: system_0_clock_0" {  } { { "system_0_clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 417 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu_0_jtag_debug_module_sysclk.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cpu_0_jtag_debug_module_sysclk.v" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_jtag_debug_module_sysclk " "Info: Found entity 1: cpu_0_jtag_debug_module_sysclk" {  } { { "cpu_0_jtag_debug_module_sysclk.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_jtag_debug_module_sysclk.v" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock_1.v 9 9 " "Info: Found 9 design units, including 9 entities, in source file clock_1.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_1_master_read_done_sync_module " "Info: Found entity 1: clock_1_master_read_done_sync_module" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 clock_1_master_write_done_sync_module " "Info: Found entity 2: clock_1_master_write_done_sync_module" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 66 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 clock_1_edge_to_pulse " "Info: Found entity 3: clock_1_edge_to_pulse" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 111 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "4 clock_1_slave_FSM " "Info: Found entity 4: clock_1_slave_FSM" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 148 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "5 clock_1_slave_read_request_sync_module " "Info: Found entity 5: clock_1_slave_read_request_sync_module" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 289 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "6 clock_1_slave_write_request_sync_module " "Info: Found entity 6: clock_1_slave_write_request_sync_module" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 334 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "7 clock_1_master_FSM " "Info: Found entity 7: clock_1_master_FSM" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 379 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "8 clock_1_bit_pipe " "Info: Found entity 8: clock_1_bit_pipe" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 545 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "9 clock_1 " "Info: Found entity 9: clock_1" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 597 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock_0.v 9 9 " "Info: Found 9 design units, including 9 entities, in source file clock_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_0_master_read_done_sync_module " "Info: Found entity 1: clock_0_master_read_done_sync_module" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 clock_0_master_write_done_sync_module " "Info: Found entity 2: clock_0_master_write_done_sync_module" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 66 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 clock_0_edge_to_pulse " "Info: Found entity 3: clock_0_edge_to_pulse" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 111 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "4 clock_0_slave_FSM " "Info: Found entity 4: clock_0_slave_FSM" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 148 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "5 clock_0_slave_read_request_sync_module " "Info: Found entity 5: clock_0_slave_read_request_sync_module" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 289 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "6 clock_0_slave_write_request_sync_module " "Info: Found entity 6: clock_0_slave_write_request_sync_module" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 334 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "7 clock_0_master_FSM " "Info: Found entity 7: clock_0_master_FSM" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 379 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "8 clock_0_bit_pipe " "Info: Found entity 8: clock_0_bit_pipe" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 545 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "9 clock_0 " "Info: Found entity 9: clock_0" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 597 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Audio_0.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Audio_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 Audio_0 " "Info: Found entity 1: Audio_0" {  } { { "Audio_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Audio_0.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AUDIO_DAC_FIFO.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file AUDIO_DAC_FIFO.v" { { "Info" "ISGN_ENTITY_NAME" "1 AUDIO_DAC_FIFO " "Info: Found entity 1: AUDIO_DAC_FIFO" {  } { { "AUDIO_DAC_FIFO.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/AUDIO_DAC_FIFO.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Audio_PLL.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Audio_PLL.v" { { "Info" "ISGN_ENTITY_NAME" "1 Audio_PLL " "Info: Found entity 1: Audio_PLL" {  } { { "Audio_PLL.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Audio_PLL.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu_0.v 27 27 " "Info: Found 27 design units, including 27 entities, in source file cpu_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_ic_data_module " "Info: Found entity 1: cpu_0_ic_data_module" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 cpu_0_ic_tag_module " "Info: Found entity 2: cpu_0_ic_tag_module" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 83 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 cpu_0_bht_module " "Info: Found entity 3: cpu_0_bht_module" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 146 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "4 cpu_0_register_bank_a_module " "Info: Found entity 4: cpu_0_register_bank_a_module" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 209 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "5 cpu_0_register_bank_b_module " "Info: Found entity 5: cpu_0_register_bank_b_module" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 269 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "6 cpu_0_dc_tag_module " "Info: Found entity 6: cpu_0_dc_tag_module" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 329 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "7 cpu_0_dc_data_module " "Info: Found entity 7: cpu_0_dc_data_module" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 415 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "8 cpu_0_nios2_oci_debug " "Info: Found entity 8: cpu_0_nios2_oci_debug" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 505 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "9 cpu_0_ociram_lpm_dram_bdp_component_module " "Info: Found entity 9: cpu_0_ociram_lpm_dram_bdp_component_module" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 630 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "10 cpu_0_nios2_ocimem " "Info: Found entity 10: cpu_0_nios2_ocimem" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 720 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "11 cpu_0_nios2_avalon_reg " "Info: Found entity 11: cpu_0_nios2_avalon_reg" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 863 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "12 cpu_0_nios2_oci_break " "Info: Found entity 12: cpu_0_nios2_oci_break" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 954 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "13 cpu_0_nios2_oci_xbrk " "Info: Found entity 13: cpu_0_nios2_oci_xbrk" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 1245 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "14 cpu_0_nios2_oci_dbrk " "Info: Found entity 14: cpu_0_nios2_oci_dbrk" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 1502 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "15 cpu_0_nios2_oci_itrace " "Info: Found entity 15: cpu_0_nios2_oci_itrace" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 1687 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "16 cpu_0_nios2_oci_td_mode " "Info: Found entity 16: cpu_0_nios2_oci_td_mode" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 1983 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "17 cpu_0_nios2_oci_dtrace " "Info: Found entity 17: cpu_0_nios2_oci_dtrace" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2047 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "18 cpu_0_nios2_oci_compute_tm_count " "Info: Found entity 18: cpu_0_nios2_oci_compute_tm_count" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2138 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "19 cpu_0_nios2_oci_fifowp_inc " "Info: Found entity 19: cpu_0_nios2_oci_fifowp_inc" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2206 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "20 cpu_0_nios2_oci_fifocount_inc " "Info: Found entity 20: cpu_0_nios2_oci_fifocount_inc" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2245 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "21 cpu_0_nios2_oci_fifo " "Info: Found entity 21: cpu_0_nios2_oci_fifo" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2288 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "22 cpu_0_nios2_oci_pib " "Info: Found entity 22: cpu_0_nios2_oci_pib" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2790 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "23 cpu_0_traceram_lpm_dram_bdp_component_module " "Info: Found entity 23: cpu_0_traceram_lpm_dram_bdp_component_module" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2855 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "24 cpu_0_nios2_oci_im " "Info: Found entity 24: cpu_0_nios2_oci_im" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2941 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "25 cpu_0_nios2_performance_monitors " "Info: Found entity 25: cpu_0_nios2_performance_monitors" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3075 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "26 cpu_0_nios2_oci " "Info: Found entity 26: cpu_0_nios2_oci" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3088 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "27 cpu_0 " "Info: Found entity 27: cpu_0" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3588 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu_0_jtag_debug_module.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cpu_0_jtag_debug_module.v" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_jtag_debug_module " "Info: Found entity 1: cpu_0_jtag_debug_module" {  } { { "cpu_0_jtag_debug_module.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_jtag_debug_module.v" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu_0_jtag_debug_module_wrapper.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cpu_0_jtag_debug_module_wrapper.v" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_jtag_debug_module_wrapper " "Info: Found entity 1: cpu_0_jtag_debug_module_wrapper" {  } { { "cpu_0_jtag_debug_module_wrapper.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_jtag_debug_module_wrapper.v" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu_0_mult_cell.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cpu_0_mult_cell.v" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_mult_cell " "Info: Found entity 1: cpu_0_mult_cell" {  } { { "cpu_0_mult_cell.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_mult_cell.v" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu_0_test_bench.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cpu_0_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_test_bench " "Info: Found entity 1: cpu_0_test_bench" {  } { { "cpu_0_test_bench.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_test_bench.v" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DE2_SD_Card_Audio.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DE2_SD_Card_Audio.v" { { "Info" "ISGN_ENTITY_NAME" "1 DE2_SD_Card_Audio " "Info: Found entity 1: DE2_SD_Card_Audio" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "epcs_controller.v 3 3 " "Info: Found 3 design units, including 3 entities, in source file epcs_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 epcs_controller_sub " "Info: Found entity 1: epcs_controller_sub" {  } { { "epcs_controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/epcs_controller.v" 41 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 tornado_epcs_controller_atom " "Info: Found entity 2: tornado_epcs_controller_atom" {  } { { "epcs_controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/epcs_controller.v" 421 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 epcs_controller " "Info: Found entity 3: epcs_controller" {  } { { "epcs_controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/epcs_controller.v" 469 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FIFO_16_256.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file FIFO_16_256.v" { { "Info" "ISGN_ENTITY_NAME" "1 FIFO_16_256 " "Info: Found entity 1: FIFO_16_256" {  } { { "FIFO_16_256.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/FIFO_16_256.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Img_RAM.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Img_RAM.v" { { "Info" "ISGN_ENTITY_NAME" "1 Img_RAM " "Info: Found entity 1: Img_RAM" {  } { { "Img_RAM.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Img_RAM.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_uart_0.v 7 7 " "Info: Found 7 design units, including 7 entities, in source file jtag_uart_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 jtag_uart_0_log_module " "Info: Found entity 1: jtag_uart_0_log_module" {  } { { "jtag_uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 jtag_uart_0_sim_scfifo_w " "Info: Found entity 2: jtag_uart_0_sim_scfifo_w" {  } { { "jtag_uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 65 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 jtag_uart_0_scfifo_w " "Info: Found entity 3: jtag_uart_0_scfifo_w" {  } { { "jtag_uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 120 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "4 jtag_uart_0_drom_module " "Info: Found entity 4: jtag_uart_0_drom_module" {  } { { "jtag_uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 202 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "5 jtag_uart_0_sim_scfifo_r " "Info: Found entity 5: jtag_uart_0_sim_scfifo_r" {  } { { "jtag_uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 351 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "6 jtag_uart_0_scfifo_r " "Info: Found entity 6: jtag_uart_0_scfifo_r" {  } { { "jtag_uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 436 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "7 jtag_uart_0 " "Info: Found entity 7: jtag_uart_0" {  } { { "jtag_uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 520 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_16207_0.v(57) " "Warning (10273): Verilog HDL warning at lcd_16207_0.v(57): extended using \"x\" or \"z\"" {  } { { "lcd_16207_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/lcd_16207_0.v" 57 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd_16207_0.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd_16207_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_16207_0 " "Info: Found entity 1: lcd_16207_0" {  } { { "lcd_16207_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/lcd_16207_0.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Reset_Delay.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Reset_Delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 Reset_Delay " "Info: Found entity 1: Reset_Delay" {  } { { "Reset_Delay.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Reset_Delay.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SD_CLK.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SD_CLK.v" { { "Info" "ISGN_ENTITY_NAME" "1 SD_CLK " "Info: Found entity 1: SD_CLK" {  } { { "SD_CLK.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/SD_CLK.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SD_CMD.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SD_CMD.v" { { "Info" "ISGN_ENTITY_NAME" "1 SD_CMD " "Info: Found entity 1: SD_CMD" {  } { { "SD_CMD.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/SD_CMD.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SD_DAT.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SD_DAT.v" { { "Info" "ISGN_ENTITY_NAME" "1 SD_DAT " "Info: Found entity 1: SD_DAT" {  } { { "SD_DAT.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/SD_DAT.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_0.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file sdram_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_0_input_efifo_module " "Info: Found entity 1: sdram_0_input_efifo_module" {  } { { "sdram_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sdram_0.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 sdram_0 " "Info: Found entity 2: sdram_0" {  } { { "sdram_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sdram_0.v" 155 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "sdram_0_test_component.v(231) " "Warning (10273): Verilog HDL warning at sdram_0_test_component.v(231): extended using \"x\" or \"z\"" {  } { { "sdram_0_test_component.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sdram_0_test_component.v" 231 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 -1}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "sdram_0_test_component.v(232) " "Warning (10273): Verilog HDL warning at sdram_0_test_component.v(232): extended using \"x\" or \"z\"" {  } { { "sdram_0_test_component.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sdram_0_test_component.v" 232 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_0_test_component.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file sdram_0_test_component.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_0_test_component_ram_module " "Info: Found entity 1: sdram_0_test_component_ram_module" {  } { { "sdram_0_test_component.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sdram_0_test_component.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 sdram_0_test_component " "Info: Found entity 2: sdram_0_test_component" {  } { { "sdram_0_test_component.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sdram_0_test_component.v" 110 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SDRAM_PLL.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SDRAM_PLL.v" { { "Info" "ISGN_ENTITY_NAME" "1 SDRAM_PLL " "Info: Found entity 1: SDRAM_PLL" {  } { { "SDRAM_PLL.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/SDRAM_PLL.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SEG7_Display.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SEG7_Display.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_Display " "Info: Found entity 1: SEG7_Display" {  } { { "SEG7_Display.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/SEG7_Display.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SEG7_LUT.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SEG7_LUT.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT " "Info: Found entity 1: SEG7_LUT" {  } { { "SEG7_LUT.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/SEG7_LUT.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SEG7_LUT_8.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SEG7_LUT_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT_8 " "Info: Found entity 1: SEG7_LUT_8" {  } { { "SEG7_LUT_8.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/SEG7_LUT_8.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sram_0.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sram_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 sram_0 " "Info: Found entity 1: sram_0" {  } { { "sram_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sram_0.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SRAM_16Bit_512K.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SRAM_16Bit_512K.v" { { "Info" "ISGN_ENTITY_NAME" "1 SRAM_16Bit_512K " "Info: Found entity 1: SRAM_16Bit_512K" {  } { { "SRAM_16Bit_512K.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/SRAM_16Bit_512K.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system_0.v 43 43 " "Info: Found 43 design units, including 43 entities, in source file system_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 Accel_Control_avalon_slave_arbitrator " "Info: Found entity 1: Accel_Control_avalon_slave_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 Audio_0_avalon_slave_0_arbitrator " "Info: Found entity 2: Audio_0_avalon_slave_0_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 309 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 MS_s1_arbitrator " "Info: Found entity 3: MS_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 567 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "4 Oct_DOWN_s1_arbitrator " "Info: Found entity 4: Oct_DOWN_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 843 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "5 Oct_UP_s1_arbitrator " "Info: Found entity 5: Oct_UP_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 1119 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "6 RST_s1_arbitrator " "Info: Found entity 6: RST_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 1395 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "7 SD_CLK_s1_arbitrator " "Info: Found entity 7: SD_CLK_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 1671 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "8 SD_CMD_s1_arbitrator " "Info: Found entity 8: SD_CMD_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 1939 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "9 SD_DAT_s1_arbitrator " "Info: Found entity 9: SD_DAT_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 2207 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "10 SEG7_Display_avalon_slave_0_arbitrator " "Info: Found entity 10: SEG7_Display_avalon_slave_0_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 2475 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "11 altpll_0_pll_slave_arbitrator " "Info: Found entity 11: altpll_0_pll_slave_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 2723 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "12 cpu_0_jtag_debug_module_arbitrator " "Info: Found entity 12: cpu_0_jtag_debug_module_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 2991 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "13 cpu_0_data_master_arbitrator " "Info: Found entity 13: cpu_0_data_master_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 3429 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "14 cpu_0_instruction_master_arbitrator " "Info: Found entity 14: cpu_0_instruction_master_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 4172 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "15 dist_sensor_s1_arbitrator " "Info: Found entity 15: dist_sensor_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 4618 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "16 epcs_controller_epcs_control_port_arbitrator " "Info: Found entity 16: epcs_controller_epcs_control_port_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 4894 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "17 i2c_master_avalon_slave_0_arbitrator " "Info: Found entity 17: i2c_master_avalon_slave_0_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 5338 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "18 jtag_uart_0_avalon_jtag_slave_arbitrator " "Info: Found entity 18: jtag_uart_0_avalon_jtag_slave_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 5762 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "19 lcd_16207_0_control_slave_arbitrator " "Info: Found entity 19: lcd_16207_0_control_slave_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 6068 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "20 noteA_s1_arbitrator " "Info: Found entity 20: noteA_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 6367 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "21 noteB_s1_arbitrator " "Info: Found entity 21: noteB_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 6615 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "22 noteC_s1_arbitrator " "Info: Found entity 22: noteC_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 6863 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "23 noteD_s1_arbitrator " "Info: Found entity 23: noteD_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 7111 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "24 noteE_s1_arbitrator " "Info: Found entity 24: noteE_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 7359 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "25 noteF_s1_arbitrator " "Info: Found entity 25: noteF_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 7607 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "26 noteG_s1_arbitrator " "Info: Found entity 26: noteG_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 7855 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "27 onchip_memory2_0_s1_arbitrator " "Info: Found entity 27: onchip_memory2_0_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 8103 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "28 rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module " "Info: Found entity 28: rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 8573 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "29 rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module " "Info: Found entity 29: rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 8921 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "30 sdram_0_s1_arbitrator " "Info: Found entity 30: sdram_0_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 9269 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "31 sram_0_avalon_slave_0_arbitrator " "Info: Found entity 31: sram_0_avalon_slave_0_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 9781 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "32 system_0_clock_0_in_arbitrator " "Info: Found entity 32: system_0_clock_0_in_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 10248 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "33 system_0_clock_0_out_arbitrator " "Info: Found entity 33: system_0_clock_0_out_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 10547 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "34 timer_0_s1_arbitrator " "Info: Found entity 34: timer_0_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 10750 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "35 timer_1_s1_arbitrator " "Info: Found entity 35: timer_1_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 11026 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "36 tri_state_bridge_0_avalon_slave_arbitrator " "Info: Found entity 36: tri_state_bridge_0_avalon_slave_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 11302 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "37 tri_state_bridge_0_bridge_arbitrator " "Info: Found entity 37: tri_state_bridge_0_bridge_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 11966 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "38 uart_0_s1_arbitrator " "Info: Found entity 38: uart_0_s1_arbitrator" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 11979 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "39 system_0_reset_altpll_0_c1_out_domain_synch_module " "Info: Found entity 39: system_0_reset_altpll_0_c1_out_domain_synch_module" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 12279 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "40 system_0_reset_clk_domain_synch_module " "Info: Found entity 40: system_0_reset_clk_domain_synch_module" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 12324 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "41 system_0 " "Info: Found entity 41: system_0" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 12369 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "42 cfi_flash_0_lane0_module " "Info: Found entity 42: cfi_flash_0_lane0_module" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14755 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "43 cfi_flash_0 " "Info: Found entity 43: cfi_flash_0" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14844 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "timer_0.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file timer_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 timer_0 " "Info: Found entity 1: timer_0" {  } { { "timer_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/timer_0.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "timer_1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file timer_1.v" { { "Info" "ISGN_ENTITY_NAME" "1 timer_1 " "Info: Found entity 1: timer_1" {  } { { "timer_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/timer_1.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_0.v 7 7 " "Info: Found 7 design units, including 7 entities, in source file uart_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_0_log_module " "Info: Found entity 1: uart_0_log_module" {  } { { "uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/uart_0.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 uart_0_tx " "Info: Found entity 2: uart_0_tx" {  } { { "uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/uart_0.v" 63 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 uart_0_rx_stimulus_source_character_source_rom_module " "Info: Found entity 3: uart_0_rx_stimulus_source_character_source_rom_module" {  } { { "uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/uart_0.v" 232 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "4 uart_0_rx_stimulus_source " "Info: Found entity 4: uart_0_rx_stimulus_source" {  } { { "uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/uart_0.v" 376 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "5 uart_0_rx " "Info: Found entity 5: uart_0_rx" {  } { { "uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/uart_0.v" 478 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "6 uart_0_regs " "Info: Found entity 6: uart_0_regs" {  } { { "uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/uart_0.v" 733 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "7 uart_0 " "Info: Found entity 7: uart_0" {  } { { "uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/uart_0.v" 975 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Accelerometer1/accelerometer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Accelerometer1/accelerometer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 accelerometer-rtl " "Info: Found design unit 1: accelerometer-rtl" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 37 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 accelerometer " "Info: Found entity 1: accelerometer" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 17 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Accel_Control.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Accel_Control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Accel_Control-rtl " "Info: Found design unit 1: Accel_Control-rtl" {  } { { "Accel_Control.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accel_Control.vhd" 30 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 Accel_Control " "Info: Found entity 1: Accel_Control" {  } { { "Accel_Control.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accel_Control.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altera_avalon_opencores_i2c/opencores_i2c_master.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file altera_avalon_opencores_i2c/opencores_i2c_master.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 opencores_i2c_master-behavior " "Info: Found design unit 1: opencores_i2c_master-behavior" {  } { { "altera_avalon_opencores_i2c/opencores_i2c_master.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/opencores_i2c_master.vhd" 28 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 opencores_i2c_master " "Info: Found entity 1: opencores_i2c_master" {  } { { "altera_avalon_opencores_i2c/opencores_i2c_master.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/opencores_i2c_master.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altera_avalon_opencores_i2c/i2c_master_top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file altera_avalon_opencores_i2c/i2c_master_top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_master_top-structural " "Info: Found design unit 1: i2c_master_top-structural" {  } { { "altera_avalon_opencores_i2c/i2c_master_top.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_top.vhd" 95 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 i2c_master_top " "Info: Found entity 1: i2c_master_top" {  } { { "altera_avalon_opencores_i2c/i2c_master_top.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_top.vhd" 62 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_master_byte_ctrl-structural " "Info: Found design unit 1: i2c_master_byte_ctrl-structural" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 107 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 i2c_master_byte_ctrl " "Info: Found entity 1: i2c_master_byte_ctrl" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 71 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altera_avalon_opencores_i2c/i2c_master_bit_ctrl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file altera_avalon_opencores_i2c/i2c_master_bit_ctrl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_master_bit_ctrl-structural " "Info: Found design unit 1: i2c_master_bit_ctrl-structural" {  } { { "altera_avalon_opencores_i2c/i2c_master_bit_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_bit_ctrl.vhd" 138 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 i2c_master_bit_ctrl " "Info: Found entity 1: i2c_master_bit_ctrl" {  } { { "altera_avalon_opencores_i2c/i2c_master_bit_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_bit_ctrl.vhd" 109 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c_master.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file i2c_master.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_master-rtl " "Info: Found design unit 1: i2c_master-rtl" {  } { { "i2c_master.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/i2c_master.vhd" 28 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 i2c_master " "Info: Found entity 1: i2c_master" {  } { { "i2c_master.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/i2c_master.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altpll_0.v 3 3 " "Info: Found 3 design units, including 3 entities, in source file altpll_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 altpll_0_dffpipe_l2c " "Info: Found entity 1: altpll_0_dffpipe_l2c" {  } { { "altpll_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altpll_0.v" 37 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 altpll_0_stdsync_sv6 " "Info: Found entity 2: altpll_0_stdsync_sv6" {  } { { "altpll_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altpll_0.v" 98 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 altpll_0 " "Info: Found entity 3: altpll_0" {  } { { "altpll_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altpll_0.v" 129 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_2.v(95) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_2.v(95): conditional expression evaluates to a constant" {  } { { "system_0_clock_2.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_2.v" 95 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_2.v(104) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_2.v(104): conditional expression evaluates to a constant" {  } { { "system_0_clock_2.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_2.v" 104 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_2.v(113) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_2.v(113): conditional expression evaluates to a constant" {  } { { "system_0_clock_2.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_2.v" 113 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_2.v(239) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_2.v(239): conditional expression evaluates to a constant" {  } { { "system_0_clock_2.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_2.v" 239 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_2.v(248) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_2.v(248): conditional expression evaluates to a constant" {  } { { "system_0_clock_2.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_2.v" 248 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_2.v(257) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_2.v(257): conditional expression evaluates to a constant" {  } { { "system_0_clock_2.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_2.v" 257 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_2.v(266) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_2.v(266): conditional expression evaluates to a constant" {  } { { "system_0_clock_2.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_2.v" 266 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_2.v(275) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_2.v(275): conditional expression evaluates to a constant" {  } { { "system_0_clock_2.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_2.v" 275 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_1.v(95) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_1.v(95): conditional expression evaluates to a constant" {  } { { "system_0_clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_1.v" 95 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_1.v(104) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_1.v(104): conditional expression evaluates to a constant" {  } { { "system_0_clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_1.v" 104 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_1.v(113) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_1.v(113): conditional expression evaluates to a constant" {  } { { "system_0_clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_1.v" 113 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_1.v(239) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_1.v(239): conditional expression evaluates to a constant" {  } { { "system_0_clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_1.v" 239 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_1.v(248) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_1.v(248): conditional expression evaluates to a constant" {  } { { "system_0_clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_1.v" 248 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_1.v(257) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_1.v(257): conditional expression evaluates to a constant" {  } { { "system_0_clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_1.v" 257 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_1.v(266) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_1.v(266): conditional expression evaluates to a constant" {  } { { "system_0_clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_1.v" 266 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_1.v(275) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_1.v(275): conditional expression evaluates to a constant" {  } { { "system_0_clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_1.v" 275 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_0.v(95) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_0.v(95): conditional expression evaluates to a constant" {  } { { "system_0_clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 95 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_0.v(104) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_0.v(104): conditional expression evaluates to a constant" {  } { { "system_0_clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 104 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_0.v(113) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_0.v(113): conditional expression evaluates to a constant" {  } { { "system_0_clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 113 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_0.v(239) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_0.v(239): conditional expression evaluates to a constant" {  } { { "system_0_clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 239 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_0.v(248) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_0.v(248): conditional expression evaluates to a constant" {  } { { "system_0_clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 248 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_0.v(257) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_0.v(257): conditional expression evaluates to a constant" {  } { { "system_0_clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 257 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_0.v(266) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_0.v(266): conditional expression evaluates to a constant" {  } { { "system_0_clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 266 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_0_clock_0.v(275) " "Warning (10037): Verilog HDL or VHDL warning at system_0_clock_0.v(275): conditional expression evaluates to a constant" {  } { { "system_0_clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 275 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(43) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(43): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 43 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(52) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(52): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 52 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(88) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(88): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 88 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(97) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(97): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 97 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(133) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(133): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 133 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(185) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(185): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 185 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(194) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(194): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 194 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(203) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(203): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 203 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(311) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(311): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 311 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(320) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(320): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 320 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(356) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(356): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 356 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(365) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(365): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 365 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(419) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(419): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 419 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(428) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(428): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 428 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(437) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(437): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 437 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(446) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(446): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 446 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(455) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(455): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 455 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(571) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(571): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 571 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(580) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(580): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 580 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(801) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(801): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 801 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(810) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(810): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 810 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(819) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(819): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 819 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(828) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(828): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 828 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(837) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(837): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 837 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(846) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(846): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 846 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(855) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(855): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 855 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(864) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(864): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 864 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_1.v(873) " "Warning (10037): Verilog HDL or VHDL warning at clock_1.v(873): conditional expression evaluates to a constant" {  } { { "clock_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_1.v" 873 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(43) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(43): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 43 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(52) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(52): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 52 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(88) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(88): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 88 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(97) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(97): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 97 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(133) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(133): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 133 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(185) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(185): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 185 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(194) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(194): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 194 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(203) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(203): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 203 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(311) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(311): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 311 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(320) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(320): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 320 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(356) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(356): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 356 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(365) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(365): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 365 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(419) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(419): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 419 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(428) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(428): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 428 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(437) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(437): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 437 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(446) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(446): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 446 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(455) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(455): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 455 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(571) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(571): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 571 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(580) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(580): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 580 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(801) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(801): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 801 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(810) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(810): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 810 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(819) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(819): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 819 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(828) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(828): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 828 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(837) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(837): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 837 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(846) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(846): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 846 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(855) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(855): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 855 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(864) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(864): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 864 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "clock_0.v(873) " "Warning (10037): Verilog HDL or VHDL warning at clock_0.v(873): conditional expression evaluates to a constant" {  } { { "clock_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/clock_0.v" 873 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "cpu_0.v(1954) " "Warning (10037): Verilog HDL or VHDL warning at cpu_0.v(1954): conditional expression evaluates to a constant" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 1954 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "cpu_0.v(1956) " "Warning (10037): Verilog HDL or VHDL warning at cpu_0.v(1956): conditional expression evaluates to a constant" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 1956 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "cpu_0.v(2106) " "Warning (10037): Verilog HDL or VHDL warning at cpu_0.v(2106): conditional expression evaluates to a constant" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2106 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "cpu_0.v(3004) " "Warning (10037): Verilog HDL or VHDL warning at cpu_0.v(3004): conditional expression evaluates to a constant" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3004 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "epcs_controller.v(401) " "Warning (10037): Verilog HDL or VHDL warning at epcs_controller.v(401): conditional expression evaluates to a constant" {  } { { "epcs_controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/epcs_controller.v" 401 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "sdram_0.v(313) " "Warning (10037): Verilog HDL or VHDL warning at sdram_0.v(313): conditional expression evaluates to a constant" {  } { { "sdram_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sdram_0.v" 313 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "sdram_0.v(323) " "Warning (10037): Verilog HDL or VHDL warning at sdram_0.v(323): conditional expression evaluates to a constant" {  } { { "sdram_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sdram_0.v" 323 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "sdram_0.v(333) " "Warning (10037): Verilog HDL or VHDL warning at sdram_0.v(333): conditional expression evaluates to a constant" {  } { { "sdram_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sdram_0.v" 333 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "sdram_0.v(677) " "Warning (10037): Verilog HDL or VHDL warning at sdram_0.v(677): conditional expression evaluates to a constant" {  } { { "sdram_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sdram_0.v" 677 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "DE2_SD_Card_Audio " "Info: Elaborating entity \"DE2_SD_Card_Audio\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "IRDA_TXD DE2_SD_Card_Audio.v(145) " "Warning (10034): Output port \"IRDA_TXD\" at DE2_SD_Card_Audio.v(145) has no driver" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 145 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VDB_ONEWAY_BIDIR_CONNECTION" "AUD_ADCLRCK AUD_DACLRCK DE2_SD_Card_Audio.v(193) " "Warning (10665): Bidirectional port \"AUD_DACLRCK\" at DE2_SD_Card_Audio.v(193) has a one-way connection to bidirectional port \"AUD_ADCLRCK\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 193 0 0 } }  } 0 10665 "Bidirectional port \"%2!s!\" at %3!s! has a one-way connection to bidirectional port \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reset_Delay Reset_Delay:delay1 " "Info: Elaborating entity \"Reset_Delay\" for hierarchy \"Reset_Delay:delay1\"" {  } { { "DE2_SD_Card_Audio.v" "delay1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 233 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 Reset_Delay.v(18) " "Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(18): truncated value with size 32 to match size of target (24)" {  } { { "Reset_Delay.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Reset_Delay.v" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Audio_PLL Audio_PLL:PLL2 " "Info: Elaborating entity \"Audio_PLL\" for hierarchy \"Audio_PLL:PLL2\"" {  } { { "DE2_SD_Card_Audio.v" "PLL2" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 236 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll Audio_PLL:PLL2\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"Audio_PLL:PLL2\|altpll:altpll_component\"" {  } { { "Audio_PLL.v" "altpll_component" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Audio_PLL.v" 77 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "Audio_PLL:PLL2\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"Audio_PLL:PLL2\|altpll:altpll_component\"" {  } { { "Audio_PLL.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Audio_PLL.v" 77 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Audio_PLL:PLL2\|altpll:altpll_component " "Info: Instantiated megafunction \"Audio_PLL:PLL2\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 135 " "Info: Parameter \"clk0_divide_by\" = \"135\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Info: Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 92 " "Info: Parameter \"clk0_multiply_by\" = \"92\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Info: Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Info: Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 37037 " "Info: Parameter \"inclk0_input_frequency\" = \"37037\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone II " "Info: Parameter \"intended_device_family\" = \"Cyclone II\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Info: Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Info: Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type FAST " "Info: Parameter \"pll_type\" = \"FAST\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Info: Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_USED " "Info: Parameter \"port_areset\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Info: Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Info: Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Info: Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Info: Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Info: Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Info: Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Info: Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Info: Parameter \"port_locked\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Info: Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Info: Parameter \"port_pllena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Info: Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Info: Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Info: Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Info: Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Info: Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Info: Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Info: Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Info: Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_UNUSED " "Info: Parameter \"port_clk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Info: Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Info: Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Info: Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Info: Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Info: Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Info: Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Info: Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Info: Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Info: Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Info: Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_enable0 PORT_UNUSED " "Info: Parameter \"port_enable0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_enable1 PORT_UNUSED " "Info: Parameter \"port_enable1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Info: Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Info: Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Info: Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Info: Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclkena0 PORT_UNUSED " "Info: Parameter \"port_extclkena0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclkena1 PORT_UNUSED " "Info: Parameter \"port_extclkena1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclkena2 PORT_UNUSED " "Info: Parameter \"port_extclkena2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclkena3 PORT_UNUSED " "Info: Parameter \"port_extclkena3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_sclkout0 PORT_UNUSED " "Info: Parameter \"port_sclkout0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_sclkout1 PORT_UNUSED " "Info: Parameter \"port_sclkout1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "Audio_PLL.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Audio_PLL.v" 77 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_0 system_0:u0 " "Info: Elaborating entity \"system_0\" for hierarchy \"system_0:u0\"" {  } { { "DE2_SD_Card_Audio.v" "u0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Accel_Control_avalon_slave_arbitrator system_0:u0\|Accel_Control_avalon_slave_arbitrator:the_Accel_Control_avalon_slave " "Info: Elaborating entity \"Accel_Control_avalon_slave_arbitrator\" for hierarchy \"system_0:u0\|Accel_Control_avalon_slave_arbitrator:the_Accel_Control_avalon_slave\"" {  } { { "system_0.v" "the_Accel_Control_avalon_slave" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13139 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Accel_Control system_0:u0\|Accel_Control:the_Accel_Control " "Info: Elaborating entity \"Accel_Control\" for hierarchy \"system_0:u0\|Accel_Control:the_Accel_Control\"" {  } { { "system_0.v" "the_Accel_Control" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13158 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "accelerometer system_0:u0\|Accel_Control:the_Accel_Control\|accelerometer:accel_control " "Info: Elaborating entity \"accelerometer\" for hierarchy \"system_0:u0\|Accel_Control:the_Accel_Control\|accelerometer:accel_control\"" {  } { { "Accel_Control.vhd" "accel_control" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accel_Control.vhd" 53 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sda_padoen_o accelerometer.vhd(50) " "Warning (10492): VHDL Process Statement warning at accelerometer.vhd(50): signal \"sda_padoen_o\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 50 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sda_i2c_to_bus accelerometer.vhd(51) " "Warning (10492): VHDL Process Statement warning at accelerometer.vhd(51): signal \"sda_i2c_to_bus\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 51 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sda_i2c_to_bus accelerometer.vhd(54) " "Warning (10492): VHDL Process Statement warning at accelerometer.vhd(54): signal \"sda_i2c_to_bus\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 54 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sda_padoen_o accelerometer.vhd(60) " "Warning (10492): VHDL Process Statement warning at accelerometer.vhd(60): signal \"sda_padoen_o\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 60 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sda_i2c_to_accel accelerometer.vhd(61) " "Warning (10492): VHDL Process Statement warning at accelerometer.vhd(61): signal \"sda_i2c_to_accel\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 61 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sda_i2c_to_accel accelerometer.vhd(64) " "Warning (10492): VHDL Process Statement warning at accelerometer.vhd(64): signal \"sda_i2c_to_accel\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 64 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "sda_i2c_to_accel accelerometer.vhd(47) " "Warning (10631): VHDL Process Statement warning at accelerometer.vhd(47): inferring latch(es) for signal or variable \"sda_i2c_to_accel\", which holds its previous value in one or more paths through the process" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 47 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "sda_i2c_to_bus accelerometer.vhd(47) " "Warning (10631): VHDL Process Statement warning at accelerometer.vhd(47): inferring latch(es) for signal or variable \"sda_i2c_to_bus\", which holds its previous value in one or more paths through the process" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 47 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "avalon_slave_read accelerometer.vhd(101) " "Warning (10492): VHDL Process Statement warning at accelerometer.vhd(101): signal \"avalon_slave_read\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 101 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data_out accelerometer.vhd(102) " "Warning (10492): VHDL Process Statement warning at accelerometer.vhd(102): signal \"data_out\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 102 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "avalon_slave_readdata accelerometer.vhd(93) " "Warning (10631): VHDL Process Statement warning at accelerometer.vhd(93): inferring latch(es) for signal or variable \"avalon_slave_readdata\", which holds its previous value in one or more paths through the process" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[0\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[0\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[1\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[1\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[2\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[2\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[3\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[3\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[4\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[4\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[5\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[5\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[6\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[6\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[7\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[7\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[8\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[8\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[9\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[9\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[10\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[10\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[11\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[11\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[12\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[12\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[13\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[13\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[14\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[14\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[15\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[15\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[16\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[16\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[17\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[17\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[18\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[18\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[19\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[19\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[20\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[20\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[21\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[21\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[22\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[22\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[23\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[23\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[24\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[24\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[25\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[25\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[26\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[26\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[27\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[27\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[28\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[28\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[29\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[29\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[30\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[30\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "avalon_slave_readdata\[31\] accelerometer.vhd(93) " "Info (10041): Inferred latch for \"avalon_slave_readdata\[31\]\" at accelerometer.vhd(93)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "sda_i2c_to_bus accelerometer.vhd(47) " "Info (10041): Inferred latch for \"sda_i2c_to_bus\" at accelerometer.vhd(47)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 47 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "sda_i2c_to_accel accelerometer.vhd(47) " "Info (10041): Inferred latch for \"sda_i2c_to_accel\" at accelerometer.vhd(47)" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 47 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Audio_0_avalon_slave_0_arbitrator system_0:u0\|Audio_0_avalon_slave_0_arbitrator:the_Audio_0_avalon_slave_0 " "Info: Elaborating entity \"Audio_0_avalon_slave_0_arbitrator\" for hierarchy \"system_0:u0\|Audio_0_avalon_slave_0_arbitrator:the_Audio_0_avalon_slave_0\"" {  } { { "system_0.v" "the_Audio_0_avalon_slave_0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13179 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Audio_0 system_0:u0\|Audio_0:the_Audio_0 " "Info: Elaborating entity \"Audio_0\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\"" {  } { { "system_0.v" "the_Audio_0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13193 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AUDIO_DAC_FIFO system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO " "Info: Elaborating entity \"AUDIO_DAC_FIFO\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\"" {  } { { "Audio_0.v" "the_AUDIO_DAC_FIFO" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Audio_0.v" 66 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 AUDIO_DAC_FIFO.v(67) " "Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_FIFO.v(67): truncated value with size 32 to match size of target (4)" {  } { { "AUDIO_DAC_FIFO.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/AUDIO_DAC_FIFO.v" 67 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 AUDIO_DAC_FIFO.v(90) " "Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_FIFO.v(90): truncated value with size 32 to match size of target (9)" {  } { { "AUDIO_DAC_FIFO.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/AUDIO_DAC_FIFO.v" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 AUDIO_DAC_FIFO.v(98) " "Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_FIFO.v(98): truncated value with size 32 to match size of target (8)" {  } { { "AUDIO_DAC_FIFO.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/AUDIO_DAC_FIFO.v" 98 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 AUDIO_DAC_FIFO.v(147) " "Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_FIFO.v(147): truncated value with size 32 to match size of target (4)" {  } { { "AUDIO_DAC_FIFO.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/AUDIO_DAC_FIFO.v" 147 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "oDATA\[15..1\] AUDIO_DAC_FIFO.v(22) " "Warning (10034): Output port \"oDATA\[15..1\]\" at AUDIO_DAC_FIFO.v(22) has no driver" {  } { { "AUDIO_DAC_FIFO.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/AUDIO_DAC_FIFO.v" 22 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FIFO_16_256 system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0 " "Info: Elaborating entity \"FIFO_16_256\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\"" {  } { { "AUDIO_DAC_FIFO.v" "u0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/AUDIO_DAC_FIFO.v" 48 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component " "Info: Elaborating entity \"dcfifo\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\"" {  } { { "FIFO_16_256.v" "dcfifo_component" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/FIFO_16_256.v" 77 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component " "Info: Elaborated megafunction instantiation \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\"" {  } { { "FIFO_16_256.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/FIFO_16_256.v" 77 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component " "Info: Instantiated megafunction \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone II " "Info: Parameter \"intended_device_family\" = \"Cyclone II\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=M4K " "Info: Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=M4K\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 256 " "Info: Parameter \"lpm_numwords\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Info: Parameter \"lpm_showahead\" = \"OFF\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type dcfifo " "Info: Parameter \"lpm_type\" = \"dcfifo\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 16 " "Info: Parameter \"lpm_width\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 8 " "Info: Parameter \"lpm_widthu\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Info: Parameter \"overflow_checking\" = \"ON\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdsync_delaypipe 4 " "Info: Parameter \"rdsync_delaypipe\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Info: Parameter \"underflow_checking\" = \"ON\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Info: Parameter \"use_eab\" = \"ON\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrsync_delaypipe 4 " "Info: Parameter \"wrsync_delaypipe\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "FIFO_16_256.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/FIFO_16_256.v" 77 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dcfifo_hlj1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dcfifo_hlj1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dcfifo_hlj1 " "Info: Found entity 1: dcfifo_hlj1" {  } { { "db/dcfifo_hlj1.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dcfifo_hlj1.tdf" 40 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo_hlj1 system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated " "Info: Elaborating entity \"dcfifo_hlj1\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\"" {  } { { "dcfifo.tdf" "auto_generated" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/dcfifo.tdf" 187 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_g86.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_g86.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_g86 " "Info: Found entity 1: a_graycounter_g86" {  } { { "db/a_graycounter_g86.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/a_graycounter_g86.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_g86 system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|a_graycounter_g86:rdptr_g1p " "Info: Elaborating entity \"a_graycounter_g86\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|a_graycounter_g86:rdptr_g1p\"" {  } { { "db/dcfifo_hlj1.tdf" "rdptr_g1p" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dcfifo_hlj1.tdf" 52 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_7fc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_7fc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_7fc " "Info: Found entity 1: a_graycounter_7fc" {  } { { "db/a_graycounter_7fc.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/a_graycounter_7fc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_7fc system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|a_graycounter_7fc:wrptr_g1p " "Info: Elaborating entity \"a_graycounter_7fc\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|a_graycounter_7fc:wrptr_g1p\"" {  } { { "db/dcfifo_hlj1.tdf" "wrptr_g1p" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dcfifo_hlj1.tdf" 53 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_6fc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_6fc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_6fc " "Info: Found entity 1: a_graycounter_6fc" {  } { { "db/a_graycounter_6fc.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/a_graycounter_6fc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_6fc system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|a_graycounter_6fc:wrptr_gp " "Info: Elaborating entity \"a_graycounter_6fc\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|a_graycounter_6fc:wrptr_gp\"" {  } { { "db/dcfifo_hlj1.tdf" "wrptr_gp" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dcfifo_hlj1.tdf" 54 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_vk81.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_vk81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_vk81 " "Info: Found entity 1: altsyncram_vk81" {  } { { "db/altsyncram_vk81.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_vk81.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_vk81 system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|altsyncram_vk81:fifo_ram " "Info: Elaborating entity \"altsyncram_vk81\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|altsyncram_vk81:fifo_ram\"" {  } { { "db/dcfifo_hlj1.tdf" "fifo_ram" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dcfifo_hlj1.tdf" 55 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_brg1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_brg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_brg1 " "Info: Found entity 1: altsyncram_brg1" {  } { { "db/altsyncram_brg1.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_brg1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_brg1 system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|altsyncram_vk81:fifo_ram\|altsyncram_brg1:altsyncram14 " "Info: Elaborating entity \"altsyncram_brg1\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|altsyncram_vk81:fifo_ram\|altsyncram_brg1:altsyncram14\"" {  } { { "db/altsyncram_vk81.tdf" "altsyncram14" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_vk81.tdf" 40 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_ngh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dffpipe_ngh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_ngh " "Info: Found entity 1: dffpipe_ngh" {  } { { "db/dffpipe_ngh.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dffpipe_ngh.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_ngh system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|dffpipe_ngh:rdaclr " "Info: Elaborating entity \"dffpipe_ngh\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|dffpipe_ngh:rdaclr\"" {  } { { "db/dcfifo_hlj1.tdf" "rdaclr" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dcfifo_hlj1.tdf" 62 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_jcb.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_jcb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_jcb " "Info: Found entity 1: alt_synch_pipe_jcb" {  } { { "db/alt_synch_pipe_jcb.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/alt_synch_pipe_jcb.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_synch_pipe_jcb system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|alt_synch_pipe_jcb:rs_dgwp " "Info: Elaborating entity \"alt_synch_pipe_jcb\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|alt_synch_pipe_jcb:rs_dgwp\"" {  } { { "db/dcfifo_hlj1.tdf" "rs_dgwp" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dcfifo_hlj1.tdf" 63 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_hd9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dffpipe_hd9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_hd9 " "Info: Found entity 1: dffpipe_hd9" {  } { { "db/dffpipe_hd9.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dffpipe_hd9.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_hd9 system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|alt_synch_pipe_jcb:rs_dgwp\|dffpipe_hd9:dffpipe17 " "Info: Elaborating entity \"dffpipe_hd9\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|alt_synch_pipe_jcb:rs_dgwp\|dffpipe_hd9:dffpipe17\"" {  } { { "db/alt_synch_pipe_jcb.tdf" "dffpipe17" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/alt_synch_pipe_jcb.tdf" 34 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_nc8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_nc8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_nc8 " "Info: Found entity 1: alt_synch_pipe_nc8" {  } { { "db/alt_synch_pipe_nc8.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/alt_synch_pipe_nc8.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_synch_pipe_nc8 system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|alt_synch_pipe_nc8:ws_dgrp " "Info: Elaborating entity \"alt_synch_pipe_nc8\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|alt_synch_pipe_nc8:ws_dgrp\"" {  } { { "db/dcfifo_hlj1.tdf" "ws_dgrp" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dcfifo_hlj1.tdf" 64 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_id9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dffpipe_id9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_id9 " "Info: Found entity 1: dffpipe_id9" {  } { { "db/dffpipe_id9.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dffpipe_id9.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_id9 system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|alt_synch_pipe_nc8:ws_dgrp\|dffpipe_id9:dffpipe20 " "Info: Elaborating entity \"dffpipe_id9\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|alt_synch_pipe_nc8:ws_dgrp\|dffpipe_id9:dffpipe20\"" {  } { { "db/alt_synch_pipe_nc8.tdf" "dffpipe20" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/alt_synch_pipe_nc8.tdf" 34 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_t16.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_t16.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_t16 " "Info: Found entity 1: cmpr_t16" {  } { { "db/cmpr_t16.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/cmpr_t16.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_t16 system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|cmpr_t16:rdempty_eq_comp " "Info: Elaborating entity \"cmpr_t16\" for hierarchy \"system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|cmpr_t16:rdempty_eq_comp\"" {  } { { "db/dcfifo_hlj1.tdf" "rdempty_eq_comp" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dcfifo_hlj1.tdf" 65 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MS_s1_arbitrator system_0:u0\|MS_s1_arbitrator:the_MS_s1 " "Info: Elaborating entity \"MS_s1_arbitrator\" for hierarchy \"system_0:u0\|MS_s1_arbitrator:the_MS_s1\"" {  } { { "system_0.v" "the_MS_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13218 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MS system_0:u0\|MS:the_MS " "Info: Elaborating entity \"MS\" for hierarchy \"system_0:u0\|MS:the_MS\"" {  } { { "system_0.v" "the_MS" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13231 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Oct_DOWN_s1_arbitrator system_0:u0\|Oct_DOWN_s1_arbitrator:the_Oct_DOWN_s1 " "Info: Elaborating entity \"Oct_DOWN_s1_arbitrator\" for hierarchy \"system_0:u0\|Oct_DOWN_s1_arbitrator:the_Oct_DOWN_s1\"" {  } { { "system_0.v" "the_Oct_DOWN_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13256 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Oct_DOWN system_0:u0\|Oct_DOWN:the_Oct_DOWN " "Info: Elaborating entity \"Oct_DOWN\" for hierarchy \"system_0:u0\|Oct_DOWN:the_Oct_DOWN\"" {  } { { "system_0.v" "the_Oct_DOWN" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13269 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Oct_UP_s1_arbitrator system_0:u0\|Oct_UP_s1_arbitrator:the_Oct_UP_s1 " "Info: Elaborating entity \"Oct_UP_s1_arbitrator\" for hierarchy \"system_0:u0\|Oct_UP_s1_arbitrator:the_Oct_UP_s1\"" {  } { { "system_0.v" "the_Oct_UP_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13294 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Oct_UP system_0:u0\|Oct_UP:the_Oct_UP " "Info: Elaborating entity \"Oct_UP\" for hierarchy \"system_0:u0\|Oct_UP:the_Oct_UP\"" {  } { { "system_0.v" "the_Oct_UP" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13307 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RST_s1_arbitrator system_0:u0\|RST_s1_arbitrator:the_RST_s1 " "Info: Elaborating entity \"RST_s1_arbitrator\" for hierarchy \"system_0:u0\|RST_s1_arbitrator:the_RST_s1\"" {  } { { "system_0.v" "the_RST_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13332 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RST system_0:u0\|RST:the_RST " "Info: Elaborating entity \"RST\" for hierarchy \"system_0:u0\|RST:the_RST\"" {  } { { "system_0.v" "the_RST" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13345 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SD_CLK_s1_arbitrator system_0:u0\|SD_CLK_s1_arbitrator:the_SD_CLK_s1 " "Info: Elaborating entity \"SD_CLK_s1_arbitrator\" for hierarchy \"system_0:u0\|SD_CLK_s1_arbitrator:the_SD_CLK_s1\"" {  } { { "system_0.v" "the_SD_CLK_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13368 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SD_CLK system_0:u0\|SD_CLK:the_SD_CLK " "Info: Elaborating entity \"SD_CLK\" for hierarchy \"system_0:u0\|SD_CLK:the_SD_CLK\"" {  } { { "system_0.v" "the_SD_CLK" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13380 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SD_CMD_s1_arbitrator system_0:u0\|SD_CMD_s1_arbitrator:the_SD_CMD_s1 " "Info: Elaborating entity \"SD_CMD_s1_arbitrator\" for hierarchy \"system_0:u0\|SD_CMD_s1_arbitrator:the_SD_CMD_s1\"" {  } { { "system_0.v" "the_SD_CMD_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13403 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SD_CMD system_0:u0\|SD_CMD:the_SD_CMD " "Info: Elaborating entity \"SD_CMD\" for hierarchy \"system_0:u0\|SD_CMD:the_SD_CMD\"" {  } { { "system_0.v" "the_SD_CMD" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13415 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SD_DAT_s1_arbitrator system_0:u0\|SD_DAT_s1_arbitrator:the_SD_DAT_s1 " "Info: Elaborating entity \"SD_DAT_s1_arbitrator\" for hierarchy \"system_0:u0\|SD_DAT_s1_arbitrator:the_SD_DAT_s1\"" {  } { { "system_0.v" "the_SD_DAT_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13438 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SD_DAT system_0:u0\|SD_DAT:the_SD_DAT " "Info: Elaborating entity \"SD_DAT\" for hierarchy \"system_0:u0\|SD_DAT:the_SD_DAT\"" {  } { { "system_0.v" "the_SD_DAT" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13450 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_Display_avalon_slave_0_arbitrator system_0:u0\|SEG7_Display_avalon_slave_0_arbitrator:the_SEG7_Display_avalon_slave_0 " "Info: Elaborating entity \"SEG7_Display_avalon_slave_0_arbitrator\" for hierarchy \"system_0:u0\|SEG7_Display_avalon_slave_0_arbitrator:the_SEG7_Display_avalon_slave_0\"" {  } { { "system_0.v" "the_SEG7_Display_avalon_slave_0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13468 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_Display system_0:u0\|SEG7_Display:the_SEG7_Display " "Info: Elaborating entity \"SEG7_Display\" for hierarchy \"system_0:u0\|SEG7_Display:the_SEG7_Display\"" {  } { { "system_0.v" "the_SEG7_Display" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13484 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT_8 system_0:u0\|SEG7_Display:the_SEG7_Display\|SEG7_LUT_8:the_SEG7_LUT_8 " "Info: Elaborating entity \"SEG7_LUT_8\" for hierarchy \"system_0:u0\|SEG7_Display:the_SEG7_Display\|SEG7_LUT_8:the_SEG7_LUT_8\"" {  } { { "SEG7_Display.v" "the_SEG7_LUT_8" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/SEG7_Display.v" 75 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT system_0:u0\|SEG7_Display:the_SEG7_Display\|SEG7_LUT_8:the_SEG7_LUT_8\|SEG7_LUT:u0 " "Info: Elaborating entity \"SEG7_LUT\" for hierarchy \"system_0:u0\|SEG7_Display:the_SEG7_Display\|SEG7_LUT_8:the_SEG7_LUT_8\|SEG7_LUT:u0\"" {  } { { "SEG7_LUT_8.v" "u0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/SEG7_LUT_8.v" 19 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_0_pll_slave_arbitrator system_0:u0\|altpll_0_pll_slave_arbitrator:the_altpll_0_pll_slave " "Info: Elaborating entity \"altpll_0_pll_slave_arbitrator\" for hierarchy \"system_0:u0\|altpll_0_pll_slave_arbitrator:the_altpll_0_pll_slave\"" {  } { { "system_0.v" "the_altpll_0_pll_slave" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13506 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_0 system_0:u0\|altpll_0:the_altpll_0 " "Info: Elaborating entity \"altpll_0\" for hierarchy \"system_0:u0\|altpll_0:the_altpll_0\"" {  } { { "system_0.v" "the_altpll_0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13527 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_0_stdsync_sv6 system_0:u0\|altpll_0:the_altpll_0\|altpll_0_stdsync_sv6:stdsync2 " "Info: Elaborating entity \"altpll_0_stdsync_sv6\" for hierarchy \"system_0:u0\|altpll_0:the_altpll_0\|altpll_0_stdsync_sv6:stdsync2\"" {  } { { "altpll_0.v" "stdsync2" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altpll_0.v" 174 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_0_dffpipe_l2c system_0:u0\|altpll_0:the_altpll_0\|altpll_0_stdsync_sv6:stdsync2\|altpll_0_dffpipe_l2c:dffpipe3 " "Info: Elaborating entity \"altpll_0_dffpipe_l2c\" for hierarchy \"system_0:u0\|altpll_0:the_altpll_0\|altpll_0_stdsync_sv6:stdsync2\|altpll_0_dffpipe_l2c:dffpipe3\"" {  } { { "altpll_0.v" "dffpipe3" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altpll_0.v" 116 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1 " "Info: Elaborating entity \"altpll\" for hierarchy \"system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\"" {  } { { "altpll_0.v" "sd1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altpll_0.v" 220 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1 " "Info: Elaborated megafunction instantiation \"system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\"" {  } { { "altpll_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altpll_0.v" 220 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1 " "Info: Instantiated megafunction \"system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Info: Parameter \"clk0_divide_by\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Info: Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 2 " "Info: Parameter \"clk0_multiply_by\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift -3000 " "Info: Parameter \"clk0_phase_shift\" = \"-3000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Info: Parameter \"clk1_divide_by\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Info: Parameter \"clk1_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 2 " "Info: Parameter \"clk1_multiply_by\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Info: Parameter \"clk1_phase_shift\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK1 " "Info: Parameter \"compensate_clock\" = \"CLK1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Info: Parameter \"inclk0_input_frequency\" = \"20000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode normal " "Info: Parameter \"operation_mode\" = \"normal\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Info: Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Info: Parameter \"port_clk1\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Info: Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Info: Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Info: Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Info: Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Info: Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Info: Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Info: Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Info: Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Info: Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Info: Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Info: Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Info: Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Info: Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone II " "Info: Parameter \"intended_device_family\" = \"Cyclone II\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Info: Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "altpll_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altpll_0.v" 220 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_jtag_debug_module_arbitrator system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module " "Info: Elaborating entity \"cpu_0_jtag_debug_module_arbitrator\" for hierarchy \"system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\"" {  } { { "system_0.v" "the_cpu_0_jtag_debug_module" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13565 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_data_master_arbitrator system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master " "Info: Elaborating entity \"cpu_0_data_master_arbitrator\" for hierarchy \"system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\"" {  } { { "system_0.v" "the_cpu_0_data_master" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13795 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_instruction_master_arbitrator system_0:u0\|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master " "Info: Elaborating entity \"cpu_0_instruction_master_arbitrator\" for hierarchy \"system_0:u0\|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master\"" {  } { { "system_0.v" "the_cpu_0_instruction_master" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13858 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0 system_0:u0\|cpu_0:the_cpu_0 " "Info: Elaborating entity \"cpu_0\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\"" {  } { { "system_0.v" "the_cpu_0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_test_bench system_0:u0\|cpu_0:the_cpu_0\|cpu_0_test_bench:the_cpu_0_test_bench " "Info: Elaborating entity \"cpu_0_test_bench\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_test_bench:the_cpu_0_test_bench\"" {  } { { "cpu_0.v" "the_cpu_0_test_bench" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 5821 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_ic_data_module system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_data_module:cpu_0_ic_data " "Info: Elaborating entity \"cpu_0_ic_data_module\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_data_module:cpu_0_ic_data\"" {  } { { "cpu_0.v" "cpu_0_ic_data" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 6846 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_data_module:cpu_0_ic_data\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_data_module:cpu_0_ic_data\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "the_altsyncram" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 58 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_data_module:cpu_0_ic_data\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_data_module:cpu_0_ic_data\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 58 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_data_module:cpu_0_ic_data\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_data_module:cpu_0_ic_data\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Info: Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Info: Parameter \"maximum_depth\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Info: Parameter \"numwords_a\" = \"1024\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 1024 " "Info: Parameter \"numwords_b\" = \"1024\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Info: Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Info: Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Info: Parameter \"width_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Info: Parameter \"width_b\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Info: Parameter \"widthad_a\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 10 " "Info: Parameter \"widthad_b\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 58 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qed1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_qed1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qed1 " "Info: Found entity 1: altsyncram_qed1" {  } { { "db/altsyncram_qed1.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_qed1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qed1 system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_data_module:cpu_0_ic_data\|altsyncram:the_altsyncram\|altsyncram_qed1:auto_generated " "Info: Elaborating entity \"altsyncram_qed1\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_data_module:cpu_0_ic_data\|altsyncram:the_altsyncram\|altsyncram_qed1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_ic_tag_module system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_tag_module:cpu_0_ic_tag " "Info: Elaborating entity \"cpu_0_ic_tag_module\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_tag_module:cpu_0_ic_tag\"" {  } { { "cpu_0.v" "cpu_0_ic_tag" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 6912 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_tag_module:cpu_0_ic_tag\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_tag_module:cpu_0_ic_tag\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "the_altsyncram" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 120 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_tag_module:cpu_0_ic_tag\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_tag_module:cpu_0_ic_tag\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 120 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_tag_module:cpu_0_ic_tag\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_tag_module:cpu_0_ic_tag\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Info: Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file cpu_0_ic_tag_ram.mif " "Info: Parameter \"init_file\" = \"cpu_0_ic_tag_ram.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Info: Parameter \"maximum_depth\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Info: Parameter \"numwords_a\" = \"128\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Info: Parameter \"numwords_b\" = \"128\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Info: Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Info: Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 21 " "Info: Parameter \"width_a\" = \"21\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 21 " "Info: Parameter \"width_b\" = \"21\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Info: Parameter \"widthad_a\" = \"7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Info: Parameter \"widthad_b\" = \"7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 120 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_d5g1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_d5g1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_d5g1 " "Info: Found entity 1: altsyncram_d5g1" {  } { { "db/altsyncram_d5g1.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_d5g1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_d5g1 system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_tag_module:cpu_0_ic_tag\|altsyncram:the_altsyncram\|altsyncram_d5g1:auto_generated " "Info: Elaborating entity \"altsyncram_d5g1\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_ic_tag_module:cpu_0_ic_tag\|altsyncram:the_altsyncram\|altsyncram_d5g1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_bht_module system_0:u0\|cpu_0:the_cpu_0\|cpu_0_bht_module:cpu_0_bht " "Info: Elaborating entity \"cpu_0_bht_module\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_bht_module:cpu_0_bht\"" {  } { { "cpu_0.v" "cpu_0_bht" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 7116 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system_0:u0\|cpu_0:the_cpu_0\|cpu_0_bht_module:cpu_0_bht\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_bht_module:cpu_0_bht\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "the_altsyncram" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 183 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_bht_module:cpu_0_bht\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_bht_module:cpu_0_bht\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 183 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_bht_module:cpu_0_bht\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_bht_module:cpu_0_bht\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Info: Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file cpu_0_bht_ram.mif " "Info: Parameter \"init_file\" = \"cpu_0_bht_ram.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Info: Parameter \"maximum_depth\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Info: Parameter \"numwords_a\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Info: Parameter \"numwords_b\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Info: Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Info: Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 2 " "Info: Parameter \"width_a\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 2 " "Info: Parameter \"width_b\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Info: Parameter \"widthad_a\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Info: Parameter \"widthad_b\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 183 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_8pf1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_8pf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_8pf1 " "Info: Found entity 1: altsyncram_8pf1" {  } { { "db/altsyncram_8pf1.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_8pf1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_8pf1 system_0:u0\|cpu_0:the_cpu_0\|cpu_0_bht_module:cpu_0_bht\|altsyncram:the_altsyncram\|altsyncram_8pf1:auto_generated " "Info: Elaborating entity \"altsyncram_8pf1\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_bht_module:cpu_0_bht\|altsyncram:the_altsyncram\|altsyncram_8pf1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_register_bank_a_module system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_a_module:cpu_0_register_bank_a " "Info: Elaborating entity \"cpu_0_register_bank_a_module\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_a_module:cpu_0_register_bank_a\"" {  } { { "cpu_0.v" "cpu_0_register_bank_a" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 7262 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_a_module:cpu_0_register_bank_a\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_a_module:cpu_0_register_bank_a\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "the_altsyncram" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 243 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_a_module:cpu_0_register_bank_a\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_a_module:cpu_0_register_bank_a\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 243 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_a_module:cpu_0_register_bank_a\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_a_module:cpu_0_register_bank_a\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Info: Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file cpu_0_rf_ram_a.mif " "Info: Parameter \"init_file\" = \"cpu_0_rf_ram_a.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Info: Parameter \"maximum_depth\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Info: Parameter \"numwords_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Info: Parameter \"numwords_b\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Info: Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Info: Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Info: Parameter \"width_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Info: Parameter \"width_b\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Info: Parameter \"widthad_a\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Info: Parameter \"widthad_b\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 243 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_87f1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_87f1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_87f1 " "Info: Found entity 1: altsyncram_87f1" {  } { { "db/altsyncram_87f1.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_87f1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_87f1 system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_a_module:cpu_0_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_87f1:auto_generated " "Info: Elaborating entity \"altsyncram_87f1\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_a_module:cpu_0_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_87f1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_register_bank_b_module system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_b_module:cpu_0_register_bank_b " "Info: Elaborating entity \"cpu_0_register_bank_b_module\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_b_module:cpu_0_register_bank_b\"" {  } { { "cpu_0.v" "cpu_0_register_bank_b" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 7283 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_b_module:cpu_0_register_bank_b\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_b_module:cpu_0_register_bank_b\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "the_altsyncram" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 303 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_b_module:cpu_0_register_bank_b\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_b_module:cpu_0_register_bank_b\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 303 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_b_module:cpu_0_register_bank_b\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_b_module:cpu_0_register_bank_b\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Info: Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file cpu_0_rf_ram_b.mif " "Info: Parameter \"init_file\" = \"cpu_0_rf_ram_b.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Info: Parameter \"maximum_depth\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Info: Parameter \"numwords_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Info: Parameter \"numwords_b\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Info: Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Info: Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Info: Parameter \"width_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Info: Parameter \"width_b\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Info: Parameter \"widthad_a\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Info: Parameter \"widthad_b\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 303 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_97f1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_97f1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_97f1 " "Info: Found entity 1: altsyncram_97f1" {  } { { "db/altsyncram_97f1.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_97f1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_97f1 system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_b_module:cpu_0_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_97f1:auto_generated " "Info: Elaborating entity \"altsyncram_97f1\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_register_bank_b_module:cpu_0_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_97f1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_dc_tag_module system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_tag_module:cpu_0_dc_tag " "Info: Elaborating entity \"cpu_0_dc_tag_module\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_tag_module:cpu_0_dc_tag\"" {  } { { "cpu_0.v" "cpu_0_dc_tag" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 7766 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_tag_module:cpu_0_dc_tag\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_tag_module:cpu_0_dc_tag\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "the_altsyncram" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 380 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_tag_module:cpu_0_dc_tag\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_tag_module:cpu_0_dc_tag\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 380 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_tag_module:cpu_0_dc_tag\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_tag_module:cpu_0_dc_tag\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Info: Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Info: Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Info: Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Info: Parameter \"indata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Info: Parameter \"indata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file cpu_0_dc_tag_ram.mif " "Info: Parameter \"init_file\" = \"cpu_0_dc_tag_ram.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEII " "Info: Parameter \"intended_device_family\" = \"CYCLONEII\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Info: Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 512 " "Info: Parameter \"numwords_a\" = \"512\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 512 " "Info: Parameter \"numwords_b\" = \"512\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Info: Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Info: Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Info: Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Info: Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Info: Parameter \"width_a\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Info: Parameter \"width_b\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 9 " "Info: Parameter \"widthad_a\" = \"9\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 9 " "Info: Parameter \"widthad_b\" = \"9\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Info: Parameter \"wrcontrol_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Info: Parameter \"wrcontrol_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 380 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_1g22.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_1g22.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_1g22 " "Info: Found entity 1: altsyncram_1g22" {  } { { "db/altsyncram_1g22.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_1g22.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_1g22 system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_tag_module:cpu_0_dc_tag\|altsyncram:the_altsyncram\|altsyncram_1g22:auto_generated " "Info: Elaborating entity \"altsyncram_1g22\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_tag_module:cpu_0_dc_tag\|altsyncram:the_altsyncram\|altsyncram_1g22:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_dc_data_module system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_data_module:cpu_0_dc_data " "Info: Elaborating entity \"cpu_0_dc_data_module\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_data_module:cpu_0_dc_data\"" {  } { { "cpu_0.v" "cpu_0_dc_data" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 7800 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_data_module:cpu_0_dc_data\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_data_module:cpu_0_dc_data\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "the_altsyncram" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 469 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_data_module:cpu_0_dc_data\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_data_module:cpu_0_dc_data\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 469 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_data_module:cpu_0_dc_data\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_data_module:cpu_0_dc_data\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Info: Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Info: Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Info: Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Info: Parameter \"indata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Info: Parameter \"indata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file UNUSED " "Info: Parameter \"init_file\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEII " "Info: Parameter \"intended_device_family\" = \"CYCLONEII\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Info: Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 512 " "Info: Parameter \"numwords_a\" = \"512\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 512 " "Info: Parameter \"numwords_b\" = \"512\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Info: Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Info: Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Info: Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Info: Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Info: Parameter \"width_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Info: Parameter \"width_b\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 4 " "Info: Parameter \"width_byteena_b\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 9 " "Info: Parameter \"widthad_a\" = \"9\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 9 " "Info: Parameter \"widthad_b\" = \"9\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Info: Parameter \"wrcontrol_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Info: Parameter \"wrcontrol_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 469 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_a422.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_a422.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_a422 " "Info: Found entity 1: altsyncram_a422" {  } { { "db/altsyncram_a422.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_a422.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_a422 system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_data_module:cpu_0_dc_data\|altsyncram:the_altsyncram\|altsyncram_a422:auto_generated " "Info: Elaborating entity \"altsyncram_a422\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_dc_data_module:cpu_0_dc_data\|altsyncram:the_altsyncram\|altsyncram_a422:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_mult_cell system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell " "Info: Elaborating entity \"cpu_0_mult_cell\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\"" {  } { { "cpu_0.v" "the_cpu_0_mult_cell" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9353 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_1 " "Info: Elaborating entity \"altmult_add\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_1\"" {  } { { "cpu_0_mult_cell.v" "the_altmult_add_part_1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_mult_cell.v" 49 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_1 " "Info: Elaborated megafunction instantiation \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_1\"" {  } { { "cpu_0_mult_cell.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_mult_cell.v" 49 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_1 " "Info: Instantiated megafunction \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Info: Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Info: Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Info: Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Info: Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Info: Parameter \"input_register_a0\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Info: Parameter \"input_register_b0\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Info: Parameter \"input_source_a0\" = \"DATAA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Info: Parameter \"input_source_b0\" = \"DATAB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEII " "Info: Parameter \"intended_device_family\" = \"CYCLONEII\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Info: Parameter \"lpm_type\" = \"altmult_add\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Info: Parameter \"multiplier1_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Info: Parameter \"multiplier_aclr0\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Info: Parameter \"multiplier_register0\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Info: Parameter \"number_of_multipliers\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Info: Parameter \"output_register\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Info: Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Info: Parameter \"port_signa\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Info: Parameter \"port_signb\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Info: Parameter \"representation_a\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Info: Parameter \"representation_b\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Info: Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Info: Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Info: Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Info: Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Info: Parameter \"signed_register_a\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Info: Parameter \"signed_register_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Info: Parameter \"width_a\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Info: Parameter \"width_b\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 32 " "Info: Parameter \"width_result\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_0_mult_cell.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_mult_cell.v" 49 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_4cr2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_add_4cr2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_4cr2 " "Info: Found entity 1: mult_add_4cr2" {  } { { "db/mult_add_4cr2.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/mult_add_4cr2.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_4cr2 system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_4cr2:auto_generated " "Info: Elaborating entity \"mult_add_4cr2\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_4cr2:auto_generated\"" {  } { { "altmult_add.tdf" "auto_generated" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ded_mult_2o81.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/ded_mult_2o81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ded_mult_2o81 " "Info: Found entity 1: ded_mult_2o81" {  } { { "db/ded_mult_2o81.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/ded_mult_2o81.tdf" 30 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ded_mult_2o81 system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_4cr2:auto_generated\|ded_mult_2o81:ded_mult1 " "Info: Elaborating entity \"ded_mult_2o81\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_4cr2:auto_generated\|ded_mult_2o81:ded_mult1\"" {  } { { "db/mult_add_4cr2.tdf" "ded_mult1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/mult_add_4cr2.tdf" 33 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_93c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dffpipe_93c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_93c " "Info: Found entity 1: dffpipe_93c" {  } { { "db/dffpipe_93c.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dffpipe_93c.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_93c system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_4cr2:auto_generated\|ded_mult_2o81:ded_mult1\|dffpipe_93c:pre_result " "Info: Elaborating entity \"dffpipe_93c\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_4cr2:auto_generated\|ded_mult_2o81:ded_mult1\|dffpipe_93c:pre_result\"" {  } { { "db/ded_mult_2o81.tdf" "pre_result" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/ded_mult_2o81.tdf" 50 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_2 " "Info: Elaborating entity \"altmult_add\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_2\"" {  } { { "cpu_0_mult_cell.v" "the_altmult_add_part_2" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_mult_cell.v" 89 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_2 " "Info: Elaborated megafunction instantiation \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_2\"" {  } { { "cpu_0_mult_cell.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_mult_cell.v" 89 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_2 " "Info: Instantiated megafunction \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Info: Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Info: Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Info: Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Info: Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Info: Parameter \"input_register_a0\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Info: Parameter \"input_register_b0\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Info: Parameter \"input_source_a0\" = \"DATAA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Info: Parameter \"input_source_b0\" = \"DATAB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEII " "Info: Parameter \"intended_device_family\" = \"CYCLONEII\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Info: Parameter \"lpm_type\" = \"altmult_add\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Info: Parameter \"multiplier1_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Info: Parameter \"multiplier_aclr0\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Info: Parameter \"multiplier_register0\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Info: Parameter \"number_of_multipliers\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Info: Parameter \"output_register\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Info: Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Info: Parameter \"port_signa\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Info: Parameter \"port_signb\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Info: Parameter \"representation_a\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Info: Parameter \"representation_b\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Info: Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Info: Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Info: Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Info: Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Info: Parameter \"signed_register_a\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Info: Parameter \"signed_register_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Info: Parameter \"width_a\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Info: Parameter \"width_b\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 16 " "Info: Parameter \"width_result\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_0_mult_cell.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_mult_cell.v" 89 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_6cr2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_add_6cr2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_6cr2 " "Info: Found entity 1: mult_add_6cr2" {  } { { "db/mult_add_6cr2.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/mult_add_6cr2.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_6cr2 system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_6cr2:auto_generated " "Info: Elaborating entity \"mult_add_6cr2\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_mult_cell:the_cpu_0_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_6cr2:auto_generated\"" {  } { { "altmult_add.tdf" "auto_generated" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_oci system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci " "Info: Elaborating entity \"cpu_0_nios2_oci\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\"" {  } { { "cpu_0.v" "the_cpu_0_nios2_oci" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_oci_debug system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug " "Info: Elaborating entity \"cpu_0_nios2_oci_debug\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\"" {  } { { "cpu_0.v" "the_cpu_0_nios2_oci_debug" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3299 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_ocimem system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem " "Info: Elaborating entity \"cpu_0_nios2_ocimem\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem\"" {  } { { "cpu_0.v" "the_cpu_0_nios2_ocimem" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3319 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_ociram_lpm_dram_bdp_component_module system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem\|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component " "Info: Elaborating entity \"cpu_0_ociram_lpm_dram_bdp_component_module\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem\|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component\"" {  } { { "cpu_0.v" "cpu_0_ociram_lpm_dram_bdp_component" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 833 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem\|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem\|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "the_altsyncram" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 684 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem\|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem\|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 684 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem\|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem\|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Info: Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Info: Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Info: Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Info: Parameter \"indata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Info: Parameter \"indata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file cpu_0_ociram_default_contents.mif " "Info: Parameter \"init_file\" = \"cpu_0_ociram_default_contents.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEII " "Info: Parameter \"intended_device_family\" = \"CYCLONEII\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Info: Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Info: Parameter \"numwords_a\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Info: Parameter \"numwords_b\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Info: Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Info: Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Info: Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Info: Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Info: Parameter \"width_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Info: Parameter \"width_b\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Info: Parameter \"width_byteena_a\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Info: Parameter \"widthad_a\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Info: Parameter \"widthad_b\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Info: Parameter \"wrcontrol_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Info: Parameter \"wrcontrol_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 684 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_c572.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_c572.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_c572 " "Info: Found entity 1: altsyncram_c572" {  } { { "db/altsyncram_c572.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_c572.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_c572 system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem\|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_c572:auto_generated " "Info: Elaborating entity \"altsyncram_c572\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem\|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_c572:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_avalon_reg system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg " "Info: Elaborating entity \"cpu_0_nios2_avalon_reg\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg\"" {  } { { "cpu_0.v" "the_cpu_0_nios2_avalon_reg" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3339 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_oci_break system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break " "Info: Elaborating entity \"cpu_0_nios2_oci_break\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break\"" {  } { { "cpu_0.v" "the_cpu_0_nios2_oci_break" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3370 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_oci_xbrk system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk " "Info: Elaborating entity \"cpu_0_nios2_oci_xbrk\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk\"" {  } { { "cpu_0.v" "the_cpu_0_nios2_oci_xbrk" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3393 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_oci_dbrk system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk " "Info: Elaborating entity \"cpu_0_nios2_oci_dbrk\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk\"" {  } { { "cpu_0.v" "the_cpu_0_nios2_oci_dbrk" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3420 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_oci_itrace system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace " "Info: Elaborating entity \"cpu_0_nios2_oci_itrace\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\"" {  } { { "cpu_0.v" "the_cpu_0_nios2_oci_itrace" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3461 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_oci_dtrace system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace " "Info: Elaborating entity \"cpu_0_nios2_oci_dtrace\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace\"" {  } { { "cpu_0.v" "the_cpu_0_nios2_oci_dtrace" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3476 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_oci_td_mode system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace\|cpu_0_nios2_oci_td_mode:cpu_0_nios2_oci_trc_ctrl_td_mode " "Info: Elaborating entity \"cpu_0_nios2_oci_td_mode\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace\|cpu_0_nios2_oci_td_mode:cpu_0_nios2_oci_trc_ctrl_td_mode\"" {  } { { "cpu_0.v" "cpu_0_nios2_oci_trc_ctrl_td_mode" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2095 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_oci_fifo system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo " "Info: Elaborating entity \"cpu_0_nios2_oci_fifo\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo\"" {  } { { "cpu_0.v" "the_cpu_0_nios2_oci_fifo" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3495 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_oci_compute_tm_count system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo\|cpu_0_nios2_oci_compute_tm_count:cpu_0_nios2_oci_compute_tm_count_tm_count " "Info: Elaborating entity \"cpu_0_nios2_oci_compute_tm_count\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo\|cpu_0_nios2_oci_compute_tm_count:cpu_0_nios2_oci_compute_tm_count_tm_count\"" {  } { { "cpu_0.v" "cpu_0_nios2_oci_compute_tm_count_tm_count" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2415 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_oci_fifowp_inc system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo\|cpu_0_nios2_oci_fifowp_inc:cpu_0_nios2_oci_fifowp_inc_fifowp " "Info: Elaborating entity \"cpu_0_nios2_oci_fifowp_inc\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo\|cpu_0_nios2_oci_fifowp_inc:cpu_0_nios2_oci_fifowp_inc_fifowp\"" {  } { { "cpu_0.v" "cpu_0_nios2_oci_fifowp_inc_fifowp" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2425 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_oci_fifocount_inc system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo\|cpu_0_nios2_oci_fifocount_inc:cpu_0_nios2_oci_fifocount_inc_fifocount " "Info: Elaborating entity \"cpu_0_nios2_oci_fifocount_inc\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo\|cpu_0_nios2_oci_fifocount_inc:cpu_0_nios2_oci_fifocount_inc_fifocount\"" {  } { { "cpu_0.v" "cpu_0_nios2_oci_fifocount_inc_fifocount" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2435 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_oci_test_bench system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo\|cpu_0_oci_test_bench:the_cpu_0_oci_test_bench " "Info: Elaborating entity \"cpu_0_oci_test_bench\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo\|cpu_0_oci_test_bench:the_cpu_0_oci_test_bench\"" {  } { { "cpu_0.v" "the_cpu_0_oci_test_bench" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2444 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_oci_pib system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_pib:the_cpu_0_nios2_oci_pib " "Info: Elaborating entity \"cpu_0_nios2_oci_pib\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_pib:the_cpu_0_nios2_oci_pib\"" {  } { { "cpu_0.v" "the_cpu_0_nios2_oci_pib" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3505 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_nios2_oci_im system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im " "Info: Elaborating entity \"cpu_0_nios2_oci_im\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\"" {  } { { "cpu_0.v" "the_cpu_0_nios2_oci_im" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_traceram_lpm_dram_bdp_component_module system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component " "Info: Elaborating entity \"cpu_0_traceram_lpm_dram_bdp_component_module\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\"" {  } { { "cpu_0.v" "cpu_0_traceram_lpm_dram_bdp_component" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "the_altsyncram" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Info: Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Info: Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Info: Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Info: Parameter \"indata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Info: Parameter \"indata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file UNUSED " "Info: Parameter \"init_file\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEII " "Info: Parameter \"intended_device_family\" = \"CYCLONEII\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Info: Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Info: Parameter \"numwords_a\" = \"128\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Info: Parameter \"numwords_b\" = \"128\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Info: Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Info: Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Info: Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Info: Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 36 " "Info: Parameter \"width_a\" = \"36\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 36 " "Info: Parameter \"width_b\" = \"36\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Info: Parameter \"widthad_a\" = \"7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Info: Parameter \"widthad_b\" = \"7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Info: Parameter \"wrcontrol_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Info: Parameter \"wrcontrol_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_e502.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_e502.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_e502 " "Info: Found entity 1: altsyncram_e502" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_e502 system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated " "Info: Elaborating entity \"altsyncram_e502\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_jtag_debug_module_wrapper system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper " "Info: Elaborating entity \"cpu_0_jtag_debug_module_wrapper\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\"" {  } { { "cpu_0.v" "the_cpu_0_jtag_debug_module_wrapper" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3569 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_jtag_debug_module_tck system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck " "Info: Elaborating entity \"cpu_0_jtag_debug_module_tck\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck\"" {  } { { "cpu_0_jtag_debug_module_wrapper.v" "the_cpu_0_jtag_debug_module_tck" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_jtag_debug_module_wrapper.v" 158 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Info: Elaborating entity \"altera_std_synchronizer\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" {  } { { "cpu_0_jtag_debug_module_tck.v" "the_altera_std_synchronizer" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_jtag_debug_module_tck.v" 199 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Info: Elaborated megafunction instantiation \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" {  } { { "cpu_0_jtag_debug_module_tck.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_jtag_debug_module_tck.v" 199 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Info: Instantiated megafunction \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 2 " "Info: Parameter \"depth\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_0_jtag_debug_module_tck.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_jtag_debug_module_tck.v" 199 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_jtag_debug_module_sysclk system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk " "Info: Elaborating entity \"cpu_0_jtag_debug_module_sysclk\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk\"" {  } { { "cpu_0_jtag_debug_module_wrapper.v" "the_cpu_0_jtag_debug_module_sysclk" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_jtag_debug_module_wrapper.v" 181 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy " "Info: Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy\"" {  } { { "cpu_0_jtag_debug_module_wrapper.v" "cpu_0_jtag_debug_module_phy" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_jtag_debug_module_wrapper.v" 211 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy " "Info: Elaborated megafunction instantiation \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy\"" {  } { { "cpu_0_jtag_debug_module_wrapper.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_jtag_debug_module_wrapper.v" 211 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy " "Info: Instantiated megafunction \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Info: Parameter \"sld_auto_instance_index\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Info: Parameter \"sld_instance_index\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 2 " "Info: Parameter \"sld_ir_width\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 70 " "Info: Parameter \"sld_mfg_id\" = \"70\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action  " "Info: Parameter \"sld_sim_action\" = \"\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Info: Parameter \"sld_sim_n_scan\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Info: Parameter \"sld_sim_total_length\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 34 " "Info: Parameter \"sld_type_id\" = \"34\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 3 " "Info: Parameter \"sld_version\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_0_jtag_debug_module_wrapper.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_jtag_debug_module_wrapper.v" 211 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Info: Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" {  } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy " "Info: Elaborated megafunction instantiation \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy\"" {  } { { "sld_virtual_jtag_basic.v" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } { "cpu_0_jtag_debug_module_wrapper.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0_jtag_debug_module_wrapper.v" 211 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dist_sensor_s1_arbitrator system_0:u0\|dist_sensor_s1_arbitrator:the_dist_sensor_s1 " "Info: Elaborating entity \"dist_sensor_s1_arbitrator\" for hierarchy \"system_0:u0\|dist_sensor_s1_arbitrator:the_dist_sensor_s1\"" {  } { { "system_0.v" "the_dist_sensor_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13912 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dist_sensor system_0:u0\|dist_sensor:the_dist_sensor " "Info: Elaborating entity \"dist_sensor\" for hierarchy \"system_0:u0\|dist_sensor:the_dist_sensor\"" {  } { { "system_0.v" "the_dist_sensor" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13925 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "epcs_controller_epcs_control_port_arbitrator system_0:u0\|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port " "Info: Elaborating entity \"epcs_controller_epcs_control_port_arbitrator\" for hierarchy \"system_0:u0\|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port\"" {  } { { "system_0.v" "the_epcs_controller_epcs_control_port" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13964 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "epcs_controller system_0:u0\|epcs_controller:the_epcs_controller " "Info: Elaborating entity \"epcs_controller\" for hierarchy \"system_0:u0\|epcs_controller:the_epcs_controller\"" {  } { { "system_0.v" "the_epcs_controller" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13980 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "epcs_controller_sub system_0:u0\|epcs_controller:the_epcs_controller\|epcs_controller_sub:the_epcs_controller_sub " "Info: Elaborating entity \"epcs_controller_sub\" for hierarchy \"system_0:u0\|epcs_controller:the_epcs_controller\|epcs_controller_sub:the_epcs_controller_sub\"" {  } { { "epcs_controller.v" "the_epcs_controller_sub" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/epcs_controller.v" 533 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tornado_epcs_controller_atom system_0:u0\|epcs_controller:the_epcs_controller\|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom " "Info: Elaborating entity \"tornado_epcs_controller_atom\" for hierarchy \"system_0:u0\|epcs_controller:the_epcs_controller\|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom\"" {  } { { "epcs_controller.v" "the_tornado_epcs_controller_atom" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/epcs_controller.v" 543 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system_0:u0\|epcs_controller:the_epcs_controller\|altsyncram:the_boot_copier_rom " "Info: Elaborating entity \"altsyncram\" for hierarchy \"system_0:u0\|epcs_controller:the_epcs_controller\|altsyncram:the_boot_copier_rom\"" {  } { { "epcs_controller.v" "the_boot_copier_rom" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/epcs_controller.v" 585 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|epcs_controller:the_epcs_controller\|altsyncram:the_boot_copier_rom " "Info: Elaborated megafunction instantiation \"system_0:u0\|epcs_controller:the_epcs_controller\|altsyncram:the_boot_copier_rom\"" {  } { { "epcs_controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/epcs_controller.v" 585 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|epcs_controller:the_epcs_controller\|altsyncram:the_boot_copier_rom " "Info: Instantiated megafunction \"system_0:u0\|epcs_controller:the_epcs_controller\|altsyncram:the_boot_copier_rom\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Info: Parameter \"byte_size\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file epcs_controller_boot_rom_synth.hex " "Info: Parameter \"init_file\" = \"epcs_controller_boot_rom_synth.hex\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Info: Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Info: Parameter \"numwords_a\" = \"128\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Info: Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Info: Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Info: Parameter \"width_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Info: Parameter \"widthad_a\" = \"7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "epcs_controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/epcs_controller.v" 585 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ad41.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ad41.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ad41 " "Info: Found entity 1: altsyncram_ad41" {  } { { "db/altsyncram_ad41.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_ad41.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ad41 system_0:u0\|epcs_controller:the_epcs_controller\|altsyncram:the_boot_copier_rom\|altsyncram_ad41:auto_generated " "Info: Elaborating entity \"altsyncram_ad41\" for hierarchy \"system_0:u0\|epcs_controller:the_epcs_controller\|altsyncram:the_boot_copier_rom\|altsyncram_ad41:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_master_avalon_slave_0_arbitrator system_0:u0\|i2c_master_avalon_slave_0_arbitrator:the_i2c_master_avalon_slave_0 " "Info: Elaborating entity \"i2c_master_avalon_slave_0_arbitrator\" for hierarchy \"system_0:u0\|i2c_master_avalon_slave_0_arbitrator:the_i2c_master_avalon_slave_0\"" {  } { { "system_0.v" "the_i2c_master_avalon_slave_0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14015 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_master system_0:u0\|i2c_master:the_i2c_master " "Info: Elaborating entity \"i2c_master\" for hierarchy \"system_0:u0\|i2c_master:the_i2c_master\"" {  } { { "system_0.v" "the_i2c_master" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14032 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "opencores_i2c_master system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master " "Info: Elaborating entity \"opencores_i2c_master\" for hierarchy \"system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\"" {  } { { "i2c_master.vhd" "i2c_master" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/i2c_master.vhd" 49 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "wb_err_o opencores_i2c_master.vhd(17) " "Warning (10541): VHDL Signal Declaration warning at opencores_i2c_master.vhd(17): used implicit default value for signal \"wb_err_o\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "altera_avalon_opencores_i2c/opencores_i2c_master.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/opencores_i2c_master.vhd" 17 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "wb_dat_o\[31..8\] opencores_i2c_master.vhd(16) " "Warning (10873): Using initial value X (don't care) for net \"wb_dat_o\[31..8\]\" at opencores_i2c_master.vhd(16)" {  } { { "altera_avalon_opencores_i2c/opencores_i2c_master.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/opencores_i2c_master.vhd" 16 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_master_top system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst " "Info: Elaborating entity \"i2c_master_top\" for hierarchy \"system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\"" {  } { { "altera_avalon_opencores_i2c/opencores_i2c_master.vhd" "i2c_top_inst" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/opencores_i2c_master.vhd" 74 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_master_byte_ctrl system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1 " "Info: Elaborating entity \"i2c_master_byte_ctrl\" for hierarchy \"system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\"" {  } { { "altera_avalon_opencores_i2c/i2c_master_top.vhd" "u1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_top.vhd" 269 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_master_bit_ctrl system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|i2c_master_bit_ctrl:u1 " "Info: Elaborating entity \"i2c_master_bit_ctrl\" for hierarchy \"system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|i2c_master_bit_ctrl:u1\"" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "u1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 159 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_uart_0_avalon_jtag_slave_arbitrator system_0:u0\|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave " "Info: Elaborating entity \"jtag_uart_0_avalon_jtag_slave_arbitrator\" for hierarchy \"system_0:u0\|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave\"" {  } { { "system_0.v" "the_jtag_uart_0_avalon_jtag_slave" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14064 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_uart_0 system_0:u0\|jtag_uart_0:the_jtag_uart_0 " "Info: Elaborating entity \"jtag_uart_0\" for hierarchy \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\"" {  } { { "system_0.v" "the_jtag_uart_0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14080 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_uart_0_scfifo_w system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w " "Info: Elaborating entity \"jtag_uart_0_scfifo_w\" for hierarchy \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\"" {  } { { "jtag_uart_0.v" "the_jtag_uart_0_scfifo_w" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 608 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Info: Elaborating entity \"scfifo\" for hierarchy \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\"" {  } { { "jtag_uart_0.v" "wfifo" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 180 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Info: Elaborated megafunction instantiation \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\"" {  } { { "jtag_uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 180 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Info: Instantiated megafunction \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Info: Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 64 " "Info: Parameter \"lpm_numwords\" = \"64\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Info: Parameter \"lpm_showahead\" = \"OFF\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Info: Parameter \"lpm_type\" = \"scfifo\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Info: Parameter \"lpm_width\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 6 " "Info: Parameter \"lpm_widthu\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Info: Parameter \"overflow_checking\" = \"OFF\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Info: Parameter \"underflow_checking\" = \"OFF\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Info: Parameter \"use_eab\" = \"ON\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "jtag_uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 180 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_1n21.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/scfifo_1n21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_1n21 " "Info: Found entity 1: scfifo_1n21" {  } { { "db/scfifo_1n21.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/scfifo_1n21.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_1n21 system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated " "Info: Elaborating entity \"scfifo_1n21\" for hierarchy \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_8t21.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_8t21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_8t21 " "Info: Found entity 1: a_dpfifo_8t21" {  } { { "db/a_dpfifo_8t21.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/a_dpfifo_8t21.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_8t21 system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo " "Info: Elaborating entity \"a_dpfifo_8t21\" for hierarchy \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\"" {  } { { "db/scfifo_1n21.tdf" "dpfifo" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/scfifo_1n21.tdf" 37 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Info: Found entity 1: a_fefifo_7cf" {  } { { "db/a_fefifo_7cf.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/a_fefifo_7cf.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state " "Info: Elaborating entity \"a_fefifo_7cf\" for hierarchy \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\"" {  } { { "db/a_dpfifo_8t21.tdf" "fifo_state" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/a_dpfifo_8t21.tdf" 42 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_rj7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_rj7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_rj7 " "Info: Found entity 1: cntr_rj7" {  } { { "db/cntr_rj7.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/cntr_rj7.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_rj7 system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_rj7:count_usedw " "Info: Elaborating entity \"cntr_rj7\" for hierarchy \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_rj7:count_usedw\"" {  } { { "db/a_fefifo_7cf.tdf" "count_usedw" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/a_fefifo_7cf.tdf" 38 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_5h21.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dpram_5h21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_5h21 " "Info: Found entity 1: dpram_5h21" {  } { { "db/dpram_5h21.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dpram_5h21.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_5h21 system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|dpram_5h21:FIFOram " "Info: Elaborating entity \"dpram_5h21\" for hierarchy \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|dpram_5h21:FIFOram\"" {  } { { "db/a_dpfifo_8t21.tdf" "FIFOram" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/a_dpfifo_8t21.tdf" 43 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_9tl1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_9tl1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_9tl1 " "Info: Found entity 1: altsyncram_9tl1" {  } { { "db/altsyncram_9tl1.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_9tl1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_9tl1 system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|dpram_5h21:FIFOram\|altsyncram_9tl1:altsyncram2 " "Info: Elaborating entity \"altsyncram_9tl1\" for hierarchy \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|dpram_5h21:FIFOram\|altsyncram_9tl1:altsyncram2\"" {  } { { "db/dpram_5h21.tdf" "altsyncram2" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dpram_5h21.tdf" 36 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_fjb.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_fjb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_fjb " "Info: Found entity 1: cntr_fjb" {  } { { "db/cntr_fjb.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/cntr_fjb.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_fjb system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|cntr_fjb:rd_ptr_count " "Info: Elaborating entity \"cntr_fjb\" for hierarchy \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|cntr_fjb:rd_ptr_count\"" {  } { { "db/a_dpfifo_8t21.tdf" "rd_ptr_count" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/a_dpfifo_8t21.tdf" 44 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_uart_0_scfifo_r system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r " "Info: Elaborating entity \"jtag_uart_0_scfifo_r\" for hierarchy \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r\"" {  } { { "jtag_uart_0.v" "the_jtag_uart_0_scfifo_r" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 622 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_jtag_atlantic system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic " "Info: Elaborating entity \"alt_jtag_atlantic\" for hierarchy \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\"" {  } { { "jtag_uart_0.v" "jtag_uart_0_alt_jtag_atlantic" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 757 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic " "Info: Elaborated megafunction instantiation \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\"" {  } { { "jtag_uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 757 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic " "Info: Instantiated megafunction \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_ID 0 " "Info: Parameter \"INSTANCE_ID\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_RXFIFO_DEPTH 6 " "Info: Parameter \"LOG2_RXFIFO_DEPTH\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_TXFIFO_DEPTH 6 " "Info: Parameter \"LOG2_TXFIFO_DEPTH\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_AUTO_INSTANCE_INDEX YES " "Info: Parameter \"SLD_AUTO_INSTANCE_INDEX\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "jtag_uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 757 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd_16207_0_control_slave_arbitrator system_0:u0\|lcd_16207_0_control_slave_arbitrator:the_lcd_16207_0_control_slave " "Info: Elaborating entity \"lcd_16207_0_control_slave_arbitrator\" for hierarchy \"system_0:u0\|lcd_16207_0_control_slave_arbitrator:the_lcd_16207_0_control_slave\"" {  } { { "system_0.v" "the_lcd_16207_0_control_slave" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14105 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd_16207_0 system_0:u0\|lcd_16207_0:the_lcd_16207_0 " "Info: Elaborating entity \"lcd_16207_0\" for hierarchy \"system_0:u0\|lcd_16207_0:the_lcd_16207_0\"" {  } { { "system_0.v" "the_lcd_16207_0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14119 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "noteA_s1_arbitrator system_0:u0\|noteA_s1_arbitrator:the_noteA_s1 " "Info: Elaborating entity \"noteA_s1_arbitrator\" for hierarchy \"system_0:u0\|noteA_s1_arbitrator:the_noteA_s1\"" {  } { { "system_0.v" "the_noteA_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14137 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "noteA system_0:u0\|noteA:the_noteA " "Info: Elaborating entity \"noteA\" for hierarchy \"system_0:u0\|noteA:the_noteA\"" {  } { { "system_0.v" "the_noteA" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14146 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "noteB_s1_arbitrator system_0:u0\|noteB_s1_arbitrator:the_noteB_s1 " "Info: Elaborating entity \"noteB_s1_arbitrator\" for hierarchy \"system_0:u0\|noteB_s1_arbitrator:the_noteB_s1\"" {  } { { "system_0.v" "the_noteB_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14164 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "noteB system_0:u0\|noteB:the_noteB " "Info: Elaborating entity \"noteB\" for hierarchy \"system_0:u0\|noteB:the_noteB\"" {  } { { "system_0.v" "the_noteB" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14173 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "noteC_s1_arbitrator system_0:u0\|noteC_s1_arbitrator:the_noteC_s1 " "Info: Elaborating entity \"noteC_s1_arbitrator\" for hierarchy \"system_0:u0\|noteC_s1_arbitrator:the_noteC_s1\"" {  } { { "system_0.v" "the_noteC_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14191 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "noteC system_0:u0\|noteC:the_noteC " "Info: Elaborating entity \"noteC\" for hierarchy \"system_0:u0\|noteC:the_noteC\"" {  } { { "system_0.v" "the_noteC" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14200 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "noteD_s1_arbitrator system_0:u0\|noteD_s1_arbitrator:the_noteD_s1 " "Info: Elaborating entity \"noteD_s1_arbitrator\" for hierarchy \"system_0:u0\|noteD_s1_arbitrator:the_noteD_s1\"" {  } { { "system_0.v" "the_noteD_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14218 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "noteD system_0:u0\|noteD:the_noteD " "Info: Elaborating entity \"noteD\" for hierarchy \"system_0:u0\|noteD:the_noteD\"" {  } { { "system_0.v" "the_noteD" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14227 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "noteE_s1_arbitrator system_0:u0\|noteE_s1_arbitrator:the_noteE_s1 " "Info: Elaborating entity \"noteE_s1_arbitrator\" for hierarchy \"system_0:u0\|noteE_s1_arbitrator:the_noteE_s1\"" {  } { { "system_0.v" "the_noteE_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14245 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "noteE system_0:u0\|noteE:the_noteE " "Info: Elaborating entity \"noteE\" for hierarchy \"system_0:u0\|noteE:the_noteE\"" {  } { { "system_0.v" "the_noteE" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14254 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "noteF_s1_arbitrator system_0:u0\|noteF_s1_arbitrator:the_noteF_s1 " "Info: Elaborating entity \"noteF_s1_arbitrator\" for hierarchy \"system_0:u0\|noteF_s1_arbitrator:the_noteF_s1\"" {  } { { "system_0.v" "the_noteF_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14272 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "noteF system_0:u0\|noteF:the_noteF " "Info: Elaborating entity \"noteF\" for hierarchy \"system_0:u0\|noteF:the_noteF\"" {  } { { "system_0.v" "the_noteF" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14281 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "noteG_s1_arbitrator system_0:u0\|noteG_s1_arbitrator:the_noteG_s1 " "Info: Elaborating entity \"noteG_s1_arbitrator\" for hierarchy \"system_0:u0\|noteG_s1_arbitrator:the_noteG_s1\"" {  } { { "system_0.v" "the_noteG_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14299 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "noteG system_0:u0\|noteG:the_noteG " "Info: Elaborating entity \"noteG\" for hierarchy \"system_0:u0\|noteG:the_noteG\"" {  } { { "system_0.v" "the_noteG" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14308 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "onchip_memory2_0_s1_arbitrator system_0:u0\|onchip_memory2_0_s1_arbitrator:the_onchip_memory2_0_s1 " "Info: Elaborating entity \"onchip_memory2_0_s1_arbitrator\" for hierarchy \"system_0:u0\|onchip_memory2_0_s1_arbitrator:the_onchip_memory2_0_s1\"" {  } { { "system_0.v" "the_onchip_memory2_0_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14343 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "onchip_memory2_0 system_0:u0\|onchip_memory2_0:the_onchip_memory2_0 " "Info: Elaborating entity \"onchip_memory2_0\" for hierarchy \"system_0:u0\|onchip_memory2_0:the_onchip_memory2_0\"" {  } { { "system_0.v" "the_onchip_memory2_0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14356 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system_0:u0\|onchip_memory2_0:the_onchip_memory2_0\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"system_0:u0\|onchip_memory2_0:the_onchip_memory2_0\|altsyncram:the_altsyncram\"" {  } { { "onchip_memory2_0.v" "the_altsyncram" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/onchip_memory2_0.v" 92 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "system_0:u0\|onchip_memory2_0:the_onchip_memory2_0\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"system_0:u0\|onchip_memory2_0:the_onchip_memory2_0\|altsyncram:the_altsyncram\"" {  } { { "onchip_memory2_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/onchip_memory2_0.v" 92 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system_0:u0\|onchip_memory2_0:the_onchip_memory2_0\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"system_0:u0\|onchip_memory2_0:the_onchip_memory2_0\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Info: Parameter \"byte_size\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file onchip_memory2_0.hex " "Info: Parameter \"init_file\" = \"onchip_memory2_0.hex\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Info: Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 4096 " "Info: Parameter \"maximum_depth\" = \"4096\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 4096 " "Info: Parameter \"numwords_a\" = \"4096\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Info: Parameter \"operation_mode\" = \"SINGLE_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Info: Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Info: Parameter \"width_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Info: Parameter \"width_byteena_a\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 12 " "Info: Parameter \"widthad_a\" = \"12\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "onchip_memory2_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/onchip_memory2_0.v" 92 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_94c1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_94c1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_94c1 " "Info: Found entity 1: altsyncram_94c1" {  } { { "db/altsyncram_94c1.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_94c1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_94c1 system_0:u0\|onchip_memory2_0:the_onchip_memory2_0\|altsyncram:the_altsyncram\|altsyncram_94c1:auto_generated " "Info: Elaborating entity \"altsyncram_94c1\" for hierarchy \"system_0:u0\|onchip_memory2_0:the_onchip_memory2_0\|altsyncram:the_altsyncram\|altsyncram_94c1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_0_s1_arbitrator system_0:u0\|sdram_0_s1_arbitrator:the_sdram_0_s1 " "Info: Elaborating entity \"sdram_0_s1_arbitrator\" for hierarchy \"system_0:u0\|sdram_0_s1_arbitrator:the_sdram_0_s1\"" {  } { { "system_0.v" "the_sdram_0_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14398 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module system_0:u0\|sdram_0_s1_arbitrator:the_sdram_0_s1\|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1 " "Info: Elaborating entity \"rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module\" for hierarchy \"system_0:u0\|sdram_0_s1_arbitrator:the_sdram_0_s1\|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1\"" {  } { { "system_0.v" "rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 9553 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module system_0:u0\|sdram_0_s1_arbitrator:the_sdram_0_s1\|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1 " "Info: Elaborating entity \"rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module\" for hierarchy \"system_0:u0\|sdram_0_s1_arbitrator:the_sdram_0_s1\|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1\"" {  } { { "system_0.v" "rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 9591 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_0 system_0:u0\|sdram_0:the_sdram_0 " "Info: Elaborating entity \"sdram_0\" for hierarchy \"system_0:u0\|sdram_0:the_sdram_0\"" {  } { { "system_0.v" "the_sdram_0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14422 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_0_input_efifo_module system_0:u0\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module " "Info: Elaborating entity \"sdram_0_input_efifo_module\" for hierarchy \"system_0:u0\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\"" {  } { { "sdram_0.v" "the_sdram_0_input_efifo_module" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sdram_0.v" 293 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sram_0_avalon_slave_0_arbitrator system_0:u0\|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0 " "Info: Elaborating entity \"sram_0_avalon_slave_0_arbitrator\" for hierarchy \"system_0:u0\|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0\"" {  } { { "system_0.v" "the_sram_0_avalon_slave_0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14460 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sram_0 system_0:u0\|sram_0:the_sram_0 " "Info: Elaborating entity \"sram_0\" for hierarchy \"system_0:u0\|sram_0:the_sram_0\"" {  } { { "system_0.v" "the_sram_0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14479 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SRAM_16Bit_512K system_0:u0\|sram_0:the_sram_0\|SRAM_16Bit_512K:the_SRAM_16Bit_512K " "Info: Elaborating entity \"SRAM_16Bit_512K\" for hierarchy \"system_0:u0\|sram_0:the_sram_0\|SRAM_16Bit_512K:the_SRAM_16Bit_512K\"" {  } { { "sram_0.v" "the_SRAM_16Bit_512K" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sram_0.v" 84 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_0_clock_0_in_arbitrator system_0:u0\|system_0_clock_0_in_arbitrator:the_system_0_clock_0_in " "Info: Elaborating entity \"system_0_clock_0_in_arbitrator\" for hierarchy \"system_0:u0\|system_0_clock_0_in_arbitrator:the_system_0_clock_0_in\"" {  } { { "system_0.v" "the_system_0_clock_0_in" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14509 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_0_clock_0_out_arbitrator system_0:u0\|system_0_clock_0_out_arbitrator:the_system_0_clock_0_out " "Info: Elaborating entity \"system_0_clock_0_out_arbitrator\" for hierarchy \"system_0:u0\|system_0_clock_0_out_arbitrator:the_system_0_clock_0_out\"" {  } { { "system_0.v" "the_system_0_clock_0_out" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14530 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_0_clock_0 system_0:u0\|system_0_clock_0:the_system_0_clock_0 " "Info: Elaborating entity \"system_0_clock_0\" for hierarchy \"system_0:u0\|system_0_clock_0:the_system_0_clock_0\"" {  } { { "system_0.v" "the_system_0_clock_0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14556 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_0_clock_0_edge_to_pulse system_0:u0\|system_0_clock_0:the_system_0_clock_0\|system_0_clock_0_edge_to_pulse:read_done_edge_to_pulse " "Info: Elaborating entity \"system_0_clock_0_edge_to_pulse\" for hierarchy \"system_0:u0\|system_0_clock_0:the_system_0_clock_0\|system_0_clock_0_edge_to_pulse:read_done_edge_to_pulse\"" {  } { { "system_0_clock_0.v" "read_done_edge_to_pulse" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 524 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_0_clock_0_slave_FSM system_0:u0\|system_0_clock_0:the_system_0_clock_0\|system_0_clock_0_slave_FSM:slave_FSM " "Info: Elaborating entity \"system_0_clock_0_slave_FSM\" for hierarchy \"system_0:u0\|system_0_clock_0:the_system_0_clock_0\|system_0_clock_0_slave_FSM:slave_FSM\"" {  } { { "system_0_clock_0.v" "slave_FSM" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 547 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_0_clock_0_master_FSM system_0:u0\|system_0_clock_0:the_system_0_clock_0\|system_0_clock_0_master_FSM:master_FSM " "Info: Elaborating entity \"system_0_clock_0_master_FSM\" for hierarchy \"system_0:u0\|system_0_clock_0:the_system_0_clock_0\|system_0_clock_0_master_FSM:master_FSM\"" {  } { { "system_0_clock_0.v" "master_FSM" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 599 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_0_clock_0_bit_pipe system_0:u0\|system_0_clock_0:the_system_0_clock_0\|system_0_clock_0_bit_pipe:endofpacket_bit_pipe " "Info: Elaborating entity \"system_0_clock_0_bit_pipe\" for hierarchy \"system_0:u0\|system_0_clock_0:the_system_0_clock_0\|system_0_clock_0_bit_pipe:endofpacket_bit_pipe\"" {  } { { "system_0_clock_0.v" "endofpacket_bit_pipe" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_clock_0.v" 610 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timer_0_s1_arbitrator system_0:u0\|timer_0_s1_arbitrator:the_timer_0_s1 " "Info: Elaborating entity \"timer_0_s1_arbitrator\" for hierarchy \"system_0:u0\|timer_0_s1_arbitrator:the_timer_0_s1\"" {  } { { "system_0.v" "the_timer_0_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14581 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timer_0 system_0:u0\|timer_0:the_timer_0 " "Info: Elaborating entity \"timer_0\" for hierarchy \"system_0:u0\|timer_0:the_timer_0\"" {  } { { "system_0.v" "the_timer_0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14593 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timer_1_s1_arbitrator system_0:u0\|timer_1_s1_arbitrator:the_timer_1_s1 " "Info: Elaborating entity \"timer_1_s1_arbitrator\" for hierarchy \"system_0:u0\|timer_1_s1_arbitrator:the_timer_1_s1\"" {  } { { "system_0.v" "the_timer_1_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14618 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timer_1 system_0:u0\|timer_1:the_timer_1 " "Info: Elaborating entity \"timer_1\" for hierarchy \"system_0:u0\|timer_1:the_timer_1\"" {  } { { "system_0.v" "the_timer_1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14630 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tri_state_bridge_0_avalon_slave_arbitrator system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave " "Info: Elaborating entity \"tri_state_bridge_0_avalon_slave_arbitrator\" for hierarchy \"system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\"" {  } { { "system_0.v" "the_tri_state_bridge_0_avalon_slave" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14668 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_0_s1_arbitrator system_0:u0\|uart_0_s1_arbitrator:the_uart_0_s1 " "Info: Elaborating entity \"uart_0_s1_arbitrator\" for hierarchy \"system_0:u0\|uart_0_s1_arbitrator:the_uart_0_s1\"" {  } { { "system_0.v" "the_uart_0_s1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14698 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_0 system_0:u0\|uart_0:the_uart_0 " "Info: Elaborating entity \"uart_0\" for hierarchy \"system_0:u0\|uart_0:the_uart_0\"" {  } { { "system_0.v" "the_uart_0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14716 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_0_tx system_0:u0\|uart_0:the_uart_0\|uart_0_tx:the_uart_0_tx " "Info: Elaborating entity \"uart_0_tx\" for hierarchy \"system_0:u0\|uart_0:the_uart_0\|uart_0_tx:the_uart_0_tx\"" {  } { { "uart_0.v" "the_uart_0_tx" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/uart_0.v" 1048 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_0_rx system_0:u0\|uart_0:the_uart_0\|uart_0_rx:the_uart_0_rx " "Info: Elaborating entity \"uart_0_rx\" for hierarchy \"system_0:u0\|uart_0:the_uart_0\|uart_0_rx:the_uart_0_rx\"" {  } { { "uart_0.v" "the_uart_0_rx" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/uart_0.v" 1066 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_0_rx_stimulus_source system_0:u0\|uart_0:the_uart_0\|uart_0_rx:the_uart_0_rx\|uart_0_rx_stimulus_source:the_uart_0_rx_stimulus_source " "Info: Elaborating entity \"uart_0_rx_stimulus_source\" for hierarchy \"system_0:u0\|uart_0:the_uart_0\|uart_0_rx:the_uart_0_rx\|uart_0_rx_stimulus_source:the_uart_0_rx_stimulus_source\"" {  } { { "uart_0.v" "the_uart_0_rx_stimulus_source" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/uart_0.v" 555 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_0_regs system_0:u0\|uart_0:the_uart_0\|uart_0_regs:the_uart_0_regs " "Info: Elaborating entity \"uart_0_regs\" for hierarchy \"system_0:u0\|uart_0:the_uart_0\|uart_0_regs:the_uart_0_regs\"" {  } { { "uart_0.v" "the_uart_0_regs" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/uart_0.v" 1097 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_0_reset_altpll_0_c1_out_domain_synch_module system_0:u0\|system_0_reset_altpll_0_c1_out_domain_synch_module:system_0_reset_altpll_0_c1_out_domain_synch " "Info: Elaborating entity \"system_0_reset_altpll_0_c1_out_domain_synch_module\" for hierarchy \"system_0:u0\|system_0_reset_altpll_0_c1_out_domain_synch_module:system_0_reset_altpll_0_c1_out_domain_synch\"" {  } { { "system_0.v" "system_0_reset_altpll_0_c1_out_domain_synch" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14725 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_0_reset_clk_domain_synch_module system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch " "Info: Elaborating entity \"system_0_reset_clk_domain_synch_module\" for hierarchy \"system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\"" {  } { { "system_0.v" "system_0_reset_clk_domain_synch" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 14741 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C_AV_Config I2C_AV_Config:u1 " "Info: Elaborating entity \"I2C_AV_Config\" for hierarchy \"I2C_AV_Config:u1\"" {  } { { "DE2_SD_Card_Audio.v" "u1" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 356 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 I2C_AV_Config.v(55) " "Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(55): truncated value with size 32 to match size of target (16)" {  } { { "I2C_AV_Config.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_AV_Config.v" 55 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 I2C_AV_Config.v(106) " "Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(106): truncated value with size 32 to match size of target (6)" {  } { { "I2C_AV_Config.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_AV_Config.v" 106 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C_Controller I2C_AV_Config:u1\|I2C_Controller:u0 " "Info: Elaborating entity \"I2C_Controller\" for hierarchy \"I2C_AV_Config:u1\|I2C_Controller:u0\"" {  } { { "I2C_AV_Config.v" "u0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_AV_Config.v" 71 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_Controller.v(78) " "Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(78): truncated value with size 32 to match size of target (1)" {  } { { "I2C_Controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_Controller.v" 78 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_Controller.v(77) " "Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(77): truncated value with size 32 to match size of target (1)" {  } { { "I2C_Controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_Controller.v" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 I2C_Controller.v(90) " "Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(90): truncated value with size 32 to match size of target (6)" {  } { { "I2C_Controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_Controller.v" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Warning: Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Warning: Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[0\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[0\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 43 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[1\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[1\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 72 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[2\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[2\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 101 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[3\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[3\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 130 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[4\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[4\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 159 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[5\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[5\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 188 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[6\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[6\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 217 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[7\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[7\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 246 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[8\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[8\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 275 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[9\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[9\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 304 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[10\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[10\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 333 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[11\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[11\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 362 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[12\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[12\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 391 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[13\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[13\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 420 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[14\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[14\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 449 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[15\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[15\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 478 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[16\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[16\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 507 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[17\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[17\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 536 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[18\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[18\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 565 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[19\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[19\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 594 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[20\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[20\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 623 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[21\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[21\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 652 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[22\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[22\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 681 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[23\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[23\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 710 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[24\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[24\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 739 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[25\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[25\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 768 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[26\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[26\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 797 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[27\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[27\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 826 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[28\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[28\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 855 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[29\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[29\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 884 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[30\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[30\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 913 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[31\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[31\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 942 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[32\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[32\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 971 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[33\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[33\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 1000 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[34\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[34\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 1029 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[35\] " "Warning (14320): Synthesized away node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_e502:auto_generated\|q_a\[35\]\"" {  } { { "db/altsyncram_e502.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/altsyncram_e502.tdf" 1058 2 0 } } { "altsyncram.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 2906 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3064 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 3526 0 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 9591 0 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13887 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 350 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Synthesized away the following %1!s! node(s):" 0 0 "" 0 -1}  } {  } 0 0 "Synthesized away the following node(s):" 0 0 "" 0 -1}
{ "Info" "IOPT_UNINFERRED_RAM_SUMMARY" "1 " "Info: Found 1 instances of uninferred RAM logic" { { "Info" "IOPT_READ_LOGIC_IS_ASYNCHRONOUS" "I2C_AV_Config:u1\|Ram0 " "Info: RAM logic \"I2C_AV_Config:u1\|Ram0\" is uninferred due to asynchronous read logic" {  } { { "I2C_AV_Config.v" "Ram0" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_AV_Config.v" 117 -1 0 } }  } 0 0 "RAM logic \"%1!s!\" is uninferred due to asynchronous read logic" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! instances of uninferred RAM logic" 0 0 "" 0 -1}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "Warning: 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 0 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "" 0 -1}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "Warning: The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "AUD_DACLRCK " "Warning: Inserted always-enabled tri-state buffer between \"AUD_DACLRCK\" and its non-tri-state driver." {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 193 -1 0 } }  } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "AUD_BCLK " "Warning: Inserted always-enabled tri-state buffer between \"AUD_BCLK\" and its non-tri-state driver." {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 195 -1 0 } }  } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_0\[13\] " "Warning: Inserted always-enabled tri-state buffer between \"GPIO_0\[13\]\" and its non-tri-state driver." {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 -1 0 } }  } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1}  } {  } 0 0 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "" 0 -1}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI_HDR" "" "Warning: The following tri-state nodes are fed by constants" { { "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "SD_DAT3 VCC pin " "Warning: The pin \"SD_DAT3\" is fed by VCC" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 184 -1 0 } }  } 0 0 "The %3!s! \"%1!s!\" is fed by %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "The following tri-state nodes are fed by constants" 0 0 "" 0 -1}
{ "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS_HDR" "" "Warning: Removed fan-outs from the following always-disabled I/O buffers" { { "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS" "SD_DAT SD_DAT " "Warning: Removed fan-out from the always-disabled I/O buffer \"SD_DAT\" to the node \"SD_DAT\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 183 -1 0 } }  } 0 0 "Removed fan-out from the always-disabled I/O buffer \"%1!s!\" to the node \"%2!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS" "GPIO_0\[11\] GPIO_0\[11\] " "Warning: Removed fan-out from the always-disabled I/O buffer \"GPIO_0\[11\]\" to the node \"GPIO_0\[11\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 -1 0 } }  } 0 0 "Removed fan-out from the always-disabled I/O buffer \"%1!s!\" to the node \"%2!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS" "GPIO_0\[13\] GPIO_0\[13\] " "Warning: Removed fan-out from the always-disabled I/O buffer \"GPIO_0\[13\]\" to the node \"GPIO_0\[13\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 -1 0 } }  } 0 0 "Removed fan-out from the always-disabled I/O buffer \"%1!s!\" to the node \"%2!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Removed fan-outs from the following always-disabled I/O buffers" 0 0 "" 0 -1}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI_HDR" "" "Warning: Always-enabled tri-state buffer(s) removed" { { "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|sda_pad_io system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|i2c_master_bit_ctrl:u1\|sSDA " "Warning: Converted the fanout from the always-enabled tri-state buffer \"system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|sda_pad_io\" to the node \"system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|i2c_master_bit_ctrl:u1\|sSDA\" into a wire" {  } { { "altera_avalon_opencores_i2c/opencores_i2c_master.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/opencores_i2c_master.vhd" 10 -1 0 } }  } 0 0 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "" 0 -1}  } {  } 0 0 "Always-enabled tri-state buffer(s) removed" 0 0 "" 0 -1}
{ "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_HDR" "" "Info: One or more bidirs are fed by always enabled tri-state buffers" { { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "AUD_DACLRCK " "Info: Fan-out of permanently enabled tri-state buffer feeding bidir \"AUD_DACLRCK\" is moved to its source" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 193 -1 0 } }  } 0 0 "Fan-out of permanently enabled tri-state buffer feeding bidir \"%1!s!\" is moved to its source" 0 0 "" 0 -1}  } {  } 0 0 "One or more bidirs are fed by always enabled tri-state buffers" 0 0 "" 0 -1}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/uart_0.v" 86 -1 0 } } { "sdram_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sdram_0.v" 437 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 11362 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 11361 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 11358 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 8941 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 10098 -1 0 } } { "I2C_Controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_Controller.v" 72 -1 0 } } { "uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/uart_0.v" 102 -1 0 } } { "sdram_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sdram_0.v" 351 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 11735 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 9646 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 3669 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 8593 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 9914 -1 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 5322 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 3300 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 5215 -1 0 } } { "jtag_uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 586 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 284 -1 0 } } { "sdram_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/sdram_0.v" 301 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 11465 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 9415 -1 0 } } { "jtag_uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/jtag_uart_0.v" 541 -1 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 5712 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 3111 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 5022 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 5454 -1 0 } } { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 8228 -1 0 } } { "I2C_Controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_Controller.v" 63 -1 0 } } { "I2C_Controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_Controller.v" 68 -1 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 8783 -1 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 5744 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 223 -1 0 } } { "uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/uart_0.v" 84 -1 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 940 -1 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 5682 -1 0 } } { "cpu_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/cpu_0.v" 8932 -1 0 } } { "uart_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/uart_0.v" 85 -1 0 } } { "db/a_graycounter_6fc.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/a_graycounter_6fc.tdf" 37 2 0 } } { "db/a_graycounter_g86.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/a_graycounter_g86.tdf" 37 2 0 } } { "epcs_controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/epcs_controller.v" 242 -1 0 } } { "timer_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/timer_0.v" 166 -1 0 } } { "timer_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/timer_0.v" 175 -1 0 } } { "timer_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/timer_1.v" 166 -1 0 } } { "timer_1.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/timer_1.v" 175 -1 0 } } { "epcs_controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/epcs_controller.v" 252 -1 0 } } { "altpll_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altpll_0.v" 158 -1 0 } } { "epcs_controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/epcs_controller.v" 131 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 -1}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 -1}
{ "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "SD_DAT3~synth " "Warning: Node \"SD_DAT3~synth\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 184 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "AUD_ADCLRCK~synth " "Warning: Node \"AUD_ADCLRCK~synth\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 191 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "AUD_DACLRCK~synth " "Warning: Node \"AUD_DACLRCK~synth\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 193 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "AUD_BCLK~synth " "Warning: Node \"AUD_BCLK~synth\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 195 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "GPIO_0\[13\]~synth " "Warning: Node \"GPIO_0\[13\]~synth\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "TRI or OPNDRN buffers permanently enabled" 0 0 "" 0 -1}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "IRDA_TXD GND " "Warning (13410): Pin \"IRDA_TXD\" is stuck at GND" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 145 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_CKE VCC " "Warning (13410): Pin \"DRAM_CKE\" is stuck at VCC" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 159 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_RST_N VCC " "Warning (13410): Pin \"FL_RST_N\" is stuck at VCC" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 164 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_ON VCC " "Warning (13410): Pin \"LCD_ON\" is stuck at VCC" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 177 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_BLON VCC " "Warning (13410): Pin \"LCD_BLON\" is stuck at VCC" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 178 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "70 70 " "Info: 70 registers lost all their fanouts during netlist optimizations. The first 70 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[0\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[0\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[1\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[1\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[2\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[2\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[3\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[3\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[4\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[4\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[5\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[5\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[6\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[6\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[7\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[7\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[8\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[8\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[9\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[10\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[10\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[11\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[11\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[12\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[12\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[13\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[13\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[14\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[14\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[15\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[16\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[16\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[17\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[17\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[18\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[18\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[19\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[19\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[20\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[20\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[21\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[21\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[22\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[22\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[23\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[23\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[24\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[24\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[25\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[25\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[26\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[26\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[27\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[27\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[28\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[28\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[29\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[29\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[30\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[30\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[31\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[31\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[34\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[33\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[33\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[32\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[32\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[35\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace\|itm\[35\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[0\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[0\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[16\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[16\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[15\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[14\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[14\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[13\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[13\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[12\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[12\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[11\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[11\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[10\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[10\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[9\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[8\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[8\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[7\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[7\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[6\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[6\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[5\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[5\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[4\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[4\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[3\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[3\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[2\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[2\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[1\] " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im\|trc_jtag_addr\[1\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "I2C_AV_Config:u1\|mSetup_ST~9 " "Info: Register \"I2C_AV_Config:u1\|mSetup_ST~9\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "I2C_AV_Config:u1\|mSetup_ST~10 " "Info: Register \"I2C_AV_Config:u1\|mSetup_ST~10\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|sdram_0:the_sdram_0\|m_next~9 " "Info: Register \"system_0:u0\|sdram_0:the_sdram_0\|m_next~9\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|sdram_0:the_sdram_0\|m_next~10 " "Info: Register \"system_0:u0\|sdram_0:the_sdram_0\|m_next~10\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|sdram_0:the_sdram_0\|m_next~13 " "Info: Register \"system_0:u0\|sdram_0:the_sdram_0\|m_next~13\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|sdram_0:the_sdram_0\|m_next~14 " "Info: Register \"system_0:u0\|sdram_0:the_sdram_0\|m_next~14\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|sdram_0:the_sdram_0\|m_next~16 " "Info: Register \"system_0:u0\|sdram_0:the_sdram_0\|m_next~16\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|sdram_0:the_sdram_0\|i_next~4 " "Info: Register \"system_0:u0\|sdram_0:the_sdram_0\|i_next~4\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|sdram_0:the_sdram_0\|i_next~5 " "Info: Register \"system_0:u0\|sdram_0:the_sdram_0\|i_next~5\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|sdram_0:the_sdram_0\|i_next~6 " "Info: Register \"system_0:u0\|sdram_0:the_sdram_0\|i_next~6\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|sdram_0:the_sdram_0\|i_state~14 " "Info: Register \"system_0:u0\|sdram_0:the_sdram_0\|i_state~14\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|sdram_0:the_sdram_0\|i_state~15 " "Info: Register \"system_0:u0\|sdram_0:the_sdram_0\|i_state~15\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|sdram_0:the_sdram_0\|i_state~16 " "Info: Register \"system_0:u0\|sdram_0:the_sdram_0\|i_state~16\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck\|DRsize~3 " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck\|DRsize~3\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck\|DRsize~4 " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck\|DRsize~4\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck\|DRsize~5 " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck\|DRsize~5\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck\|DRsize.101 " "Info: Register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck\|DRsize.101\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.map.smsg " "Info: Generated suppressed messages file /afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WIDU_QIC_OFF_NOT_SUPPORTED" "" "Critical Warning: Setting INCREMENTAL_COMPILATION to \"OFF\" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to \"ON\" instead." {  } {  } 1 0 "Setting INCREMENTAL_COMPILATION to \"OFF\" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to \"ON\" instead." 0 0 "" 0 -1}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Info: Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|pll " "Info: Adding node \"system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|pll\"" {  } {  } 0 0 "Adding node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "Audio_PLL:PLL2\|altpll:altpll_component\|pll " "Info: Adding node \"Audio_PLL:PLL2\|altpll:altpll_component\|pll\"" {  } {  } 0 0 "Adding node \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "24 " "Warning: Design contains 24 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "EXT_CLOCK " "Warning (15610): No output dependent on input pin \"EXT_CLOCK\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 127 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "Warning (15610): No output dependent on input pin \"KEY\[1\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 129 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "Warning (15610): No output dependent on input pin \"KEY\[2\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 129 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[3\] " "Warning (15610): No output dependent on input pin \"KEY\[3\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 129 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "Warning (15610): No output dependent on input pin \"SW\[0\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[1\] " "Warning (15610): No output dependent on input pin \"SW\[1\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[2\] " "Warning (15610): No output dependent on input pin \"SW\[2\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "Warning (15610): No output dependent on input pin \"SW\[3\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "Warning (15610): No output dependent on input pin \"SW\[4\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[5\] " "Warning (15610): No output dependent on input pin \"SW\[5\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[6\] " "Warning (15610): No output dependent on input pin \"SW\[6\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[7\] " "Warning (15610): No output dependent on input pin \"SW\[7\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "Warning (15610): No output dependent on input pin \"SW\[8\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "Warning (15610): No output dependent on input pin \"SW\[9\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[10\] " "Warning (15610): No output dependent on input pin \"SW\[10\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[11\] " "Warning (15610): No output dependent on input pin \"SW\[11\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[12\] " "Warning (15610): No output dependent on input pin \"SW\[12\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[13\] " "Warning (15610): No output dependent on input pin \"SW\[13\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[14\] " "Warning (15610): No output dependent on input pin \"SW\[14\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[15\] " "Warning (15610): No output dependent on input pin \"SW\[15\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[16\] " "Warning (15610): No output dependent on input pin \"SW\[16\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[17\] " "Warning (15610): No output dependent on input pin \"SW\[17\]\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 131 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "IRDA_RXD " "Warning (15610): No output dependent on input pin \"IRDA_RXD\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 146 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "AUD_ADCDAT " "Warning (15610): No output dependent on input pin \"AUD_ADCDAT\"" {  } { { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 192 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "6926 " "Info: Implemented 6926 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "31 " "Info: Implemented 31 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "139 " "Info: Implemented 139 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "127 " "Info: Implemented 127 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "6326 " "Info: Implemented 6326 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "295 " "Info: Implemented 295 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_PLLS" "2 " "Info: Implemented 2 PLLs" {  } {  } 0 0 "Implemented %1!d! PLLs" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_DSP_ELEM" "4 " "Info: Implemented 4 DSP elements" {  } {  } 0 0 "Implemented %1!d! DSP elements" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 205 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 205 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "356 " "Info: Peak virtual memory: 356 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 12 14:06:30 2013 " "Info: Processing ended: Fri Apr 12 14:06:30 2013" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:48 " "Info: Elapsed time: 00:00:48" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:30 " "Info: Total CPU time (on all processors): 00:00:30" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition " "Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 12 14:06:32 2013 " "Info: Processing started: Fri Apr 12 14:06:32 2013" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DE2_SD_Card_Audio -c DE2_SD_Card_Audio " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DE2_SD_Card_Audio -c DE2_SD_Card_Audio" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WIDU_QIC_OFF_NOT_SUPPORTED" "" "Critical Warning: Setting INCREMENTAL_COMPILATION to \"OFF\" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to \"ON\" instead." {  } {  } 1 0 "Setting INCREMENTAL_COMPILATION to \"OFF\" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to \"ON\" instead." 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "DE2_SD_Card_Audio EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"DE2_SD_Card_Audio\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|pll Cyclone II PLL " "Info: Implemented PLL \"system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk0 2 1 -108 -3000 " "Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of -108 degrees (-3000 ps) for system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk0 port" {  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 920 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk1 2 1 0 0 " "Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk1 port" {  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 917 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 539 3 0 } }  } 0 0 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "Audio_PLL:PLL2\|altpll:altpll_component\|pll Cyclone II PLL " "Info: Implemented PLL \"Audio_PLL:PLL2\|altpll:altpll_component\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "Audio_PLL:PLL2\|altpll:altpll_component\|_clk0 15 22 0 0 " "Info: Implementing clock multiplication of 15, clock division of 22, and phase shift of 0 degrees (0 ps) for Audio_PLL:PLL2\|altpll:altpll_component\|_clk0 port" {  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 920 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 539 3 0 } }  } 0 0 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Info: Pin ~ASDO~ is reserved at location E3" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { ~ASDO~ } } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 18874 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Info: Pin ~nCSO~ is reserved at location D3" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { ~nCSO~ } } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 18875 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "TimeQuest " "Info: Timing-driven compilation is using the TimeQuest Timing Analyzer" {  } {  } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[21\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[21\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[1\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[1\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[22\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[22\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[23\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[23\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[26\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[26\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[31\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[31\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[24\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[24\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[10\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[10\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[16\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[16\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[18\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[18\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[17\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[17\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[19\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[19\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[15\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[15\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[20\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[20\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[25\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[25\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[28\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[28\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[30\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[30\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[29\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[29\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[7\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[7\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[27\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[27\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[0\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[0\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[9\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[9\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[12\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[12\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[14\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[14\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[13\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[13\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[3\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[3\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[2\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[2\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[11\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[11\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[4\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[4\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[5\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[5\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[6\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[6\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[8\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[8\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Info: Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\]  " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read_write1*\}\]  " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read_write1*\}\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Info: Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "Info: set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "dcfifo_hlj1 " "Info: Entity dcfifo_hlj1" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_id9:dffpipe20\|dffe21a*  " "Info: set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_id9:dffpipe20\|dffe21a* " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_hd9:dffpipe17\|dffe18a*  " "Info: set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_hd9:dffpipe17\|dffe18a* " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Info: Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "Info: create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "Info: set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_FOUND" "cpu_0.sdc " "Info: Reading SDC File: 'cpu_0.sdc'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_FOUND" "/opt/altera/10.1sp1/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter/altera_avalon_clock_adapter.sdc " "Info: Reading SDC File: '/opt/altera/10.1sp1/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter/altera_avalon_clock_adapter.sdc'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Warning: Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_0\[15\] " "Warning: Node: GPIO_0\[15\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_27 " "Warning: Node: CLOCK_27 was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "I2C_AV_Config:u1\|mI2C_CTRL_CLK " "Warning: Node: I2C_AV_Config:u1\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK " "Warning: Node: system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "system_0:u0\|cpu_0:the_cpu_0\|d_address\[10\] " "Warning: Node: system_0:u0\|cpu_0:the_cpu_0\|d_address\[10\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: u0\|the_altpll_0\|sd1\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: u0\|the_altpll_0\|sd1\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: u0\|the_altpll_0\|sd1\|pll\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: u0\|the_altpll_0\|sd1\|pll\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: PLL2\|altpll_component\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 37.037 " "Warning: Node: PLL2\|altpll_component\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 37.037" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Info: Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Info: Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "Info:   Period   Clock Name" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "Info: ======== ============" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " "Info:  100.000 altera_reserved_tck" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Audio_PLL:PLL2\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_3) " "Info: Automatically promoted node Audio_PLL:PLL2\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_3)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G11 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G11" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 539 3 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Audio_PLL:PLL2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 7602 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50 (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CLOCK_50 (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 126 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 492 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk0 (placed in counter C2 of PLL_1) " "Info: Automatically promoted node system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk0 (placed in counter C2 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations External Clock Output CLKCTRL_X0_Y1_N1 " "Info: Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_X0_Y1_N1" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 539 3 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|altpll_0:the_altpll_0|altpll:sd1|_clk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 7200 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk1 (placed in counter C0 of PLL_1) " "Info: Automatically promoted node system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk1 (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 539 3 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|altpll_0:the_altpll_0|altpll:sd1|_clk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 7200 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "GPIO_0\[15\]~51 (placed in PIN G25 (LVDS112p, CDPCLK5/DQS2R/CQ3R)) " "Info: Automatically promoted node GPIO_0\[15\]~51 (placed in PIN G25 (LVDS112p, CDPCLK5/DQS2R/CQ3R))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G6 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G6" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[15] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 290 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Info: Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 7923 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "I2C_AV_Config:u1\|mI2C_CTRL_CLK  " "Info: Automatically promoted node I2C_AV_Config:u1\|mI2C_CTRL_CLK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~2 " "Info: Destination node I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~2" {  } { { "I2C_Controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_Controller.v" 62 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 8435 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "I2C_AV_Config:u1\|mI2C_CTRL_CLK~0 " "Info: Destination node I2C_AV_Config:u1\|mI2C_CTRL_CLK~0" {  } { { "I2C_AV_Config.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_AV_Config.v" 16 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|mI2C_CTRL_CLK~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 8843 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "I2C_AV_Config.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_AV_Config.v" 16 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|mI2C_CTRL_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 795 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|Accel_Control_avalon_slave_arbitrator:the_Accel_Control_avalon_slave\|Accel_Control_avalon_slave_read~2  " "Info: Automatically promoted node system_0:u0\|Accel_Control_avalon_slave_arbitrator:the_Accel_Control_avalon_slave\|Accel_Control_avalon_slave_read~2 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 58 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|Accel_Control_avalon_slave_arbitrator:the_Accel_Control_avalon_slave|Accel_Control_avalon_slave_read~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 13049 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK  " "Info: Automatically promoted node system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "AUD_BCLK " "Info: Destination node AUD_BCLK" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { AUD_BCLK } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 195 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 530 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK~0 " "Info: Destination node system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK~0" {  } { { "AUDIO_DAC_FIFO.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/AUDIO_DAC_FIFO.v" 28 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|oAUD_BCK~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 9491 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "AUDIO_DAC_FIFO.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/AUDIO_DAC_FIFO.v" 28 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|oAUD_BCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 7522 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|system_0_reset_altpll_0_c1_out_domain_synch_module:system_0_reset_altpll_0_c1_out_domain_synch\|data_out  " "Info: Automatically promoted node system_0:u0\|system_0_reset_altpll_0_c1_out_domain_synch_module:system_0_reset_altpll_0_c1_out_domain_synch\|data_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|host_ack " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|host_ack" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 233 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|host_ack } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 2657 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[3\] " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[3\]" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 233 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|core_cmd[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 2652 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[2\] " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[2\]" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 233 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|core_cmd[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 2653 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[1\] " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[1\]" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 233 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|core_cmd[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 2654 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[0\] " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[0\]" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 233 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|core_cmd[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 2655 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|i2c_master_bit_ctrl:u1\|iscl_oen " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|i2c_master_bit_ctrl:u1\|iscl_oen" {  } { { "altera_avalon_opencores_i2c/i2c_master_bit_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_bit_ctrl.vhd" 443 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|i2c_master_bit_ctrl:u1|iscl_oen } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 2636 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|ld " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|ld" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 150 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|ld } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 2673 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|shift " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|shift" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 150 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|shift } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 2659 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|i2c_master_bit_ctrl:u1\|isda_oen " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|i2c_master_bit_ctrl:u1\|isda_oen" {  } { { "altera_avalon_opencores_i2c/i2c_master_bit_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_bit_ctrl.vhd" 443 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|i2c_master_bit_ctrl:u1|isda_oen } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 2635 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_txd " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_txd" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 146 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|core_txd } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 2660 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" {  } {  } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 12290 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "system_0:u0\|system_0_reset_altpll_0_c1_out_domain_synch_module:system_0_reset_altpll_0_c1_out_domain_synch\|data_out" } } } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_altpll_0_c1_out_domain_synch_module:system_0_reset_altpll_0_c1_out_domain_synch|data_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 810 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|clr_reg  " "Info: Automatically promoted node sld_hub:auto_hub\|clr_reg " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|clr_reg~_wirecell " "Info: Destination node sld_hub:auto_hub\|clr_reg~_wirecell" {  } { { "sld_hub.vhd" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/sld_hub.vhd" 311 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|clr_reg~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 18849 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "sld_hub.vhd" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/sld_hub.vhd" 311 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "sld_hub:auto_hub\|clr_reg" } } } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|clr_reg } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 18685 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|Accel_Control_avalon_slave_arbitrator:the_Accel_Control_avalon_slave\|Accel_Control_avalon_slave_write_n~2  " "Info: Automatically promoted node system_0:u0\|Accel_Control_avalon_slave_arbitrator:the_Accel_Control_avalon_slave\|Accel_Control_avalon_slave_write_n~2 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 61 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|Accel_Control_avalon_slave_arbitrator:the_Accel_Control_avalon_slave|Accel_Control_avalon_slave_write_n~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 13054 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out  " "Info: Automatically promoted node system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 12335 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out" } } } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 807 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|dffpipe_ngh:rdaclr\|dffe16a\[0\]  " "Info: Automatically promoted node system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|dffpipe_ngh:rdaclr\|dffe16a\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "db/dffpipe_ngh.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dffpipe_ngh.tdf" 32 9 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_hlj1:auto_generated|dffpipe_ngh:rdaclr|dffe16a[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 7346 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state\[0\]  " "Info: Automatically promoted node sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state~0 " "Info: Destination node sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state~0" {  } { { "sld_hub.vhd" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/sld_hub.vhd" 1024 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 18764 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state~1 " "Info: Destination node sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state~1" {  } { { "sld_hub.vhd" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/sld_hub.vhd" 1024 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 18765 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell " "Info: Destination node sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell" {  } { { "sld_hub.vhd" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/sld_hub.vhd" 1039 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 18850 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "sld_hub.vhd" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/sld_hub.vhd" 1039 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 18571 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|reset_n_sources~0  " "Info: Automatically promoted node system_0:u0\|reset_n_sources~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 13009 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|reset_n_sources~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 8864 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Warning" "WFSAC_FSAC_IGNORED_FAST_REGISTER_IO_ASSIGNMENTS" "" "Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 0 "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "2 EC " "Extra Info: Packed 2 registers into blocks of type EC" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "117 I/O " "Extra Info: Packed 117 registers into blocks of type I/O" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "64 Embedded multiplier block " "Extra Info: Packed 64 registers into blocks of type Embedded multiplier block" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "73 " "Extra Info: Created 73 register duplicates" {  } {  } 1 0 "Created %1!d! register duplicates" 0 0 "" 0 -1}  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "Audio_PLL:PLL2\|altpll:altpll_component\|pll clk\[0\] AUD_XCK " "Warning: PLL \"Audio_PLL:PLL2\|altpll:altpll_component\|pll\" output port clk\[0\] feeds output pin \"AUD_XCK\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 920 3 0 } } { "Audio_PLL.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Audio_PLL.v" 77 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 236 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 196 0 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Warning: Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET_DATA\[0\] " "Warning: Ignored I/O standard assignment to node \"ENET_DATA\[0\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[0\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[0\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[0\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[1\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[1\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[2\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[2\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[3\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[3\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[4\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[4\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[5\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[5\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[6\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[6\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[7\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[7\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_HS " "Warning: Ignored I/O standard assignment to node \"TD_HS\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_VS " "Warning: Ignored I/O standard assignment to node \"TD_VS\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Ignored I/O standard assignments to the following nodes" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CLK " "Warning: Node \"ENET_CLK\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_CLK" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CMD " "Warning: Node \"ENET_CMD\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_CMD" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CS_N " "Warning: Node \"ENET_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_CS_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[0\] " "Warning: Node \"ENET_DATA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[10\] " "Warning: Node \"ENET_DATA\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[10\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[11\] " "Warning: Node \"ENET_DATA\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[11\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[12\] " "Warning: Node \"ENET_DATA\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[12\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[13\] " "Warning: Node \"ENET_DATA\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[13\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[14\] " "Warning: Node \"ENET_DATA\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[14\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[15\] " "Warning: Node \"ENET_DATA\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[15\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[1\] " "Warning: Node \"ENET_DATA\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[2\] " "Warning: Node \"ENET_DATA\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[3\] " "Warning: Node \"ENET_DATA\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[4\] " "Warning: Node \"ENET_DATA\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[5\] " "Warning: Node \"ENET_DATA\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[6\] " "Warning: Node \"ENET_DATA\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[7\] " "Warning: Node \"ENET_DATA\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[8\] " "Warning: Node \"ENET_DATA\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[9\] " "Warning: Node \"ENET_DATA\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_INT " "Warning: Node \"ENET_INT\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_INT" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_RD_N " "Warning: Node \"ENET_RD_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_RD_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_RST_N " "Warning: Node \"ENET_RST_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_RST_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_WR_N " "Warning: Node \"ENET_WR_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_WR_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Warning: Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Warning: Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Warning: Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Warning: Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Warning: Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Warning: Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Warning: Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Warning: Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Warning: Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Warning: Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Warning: Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Warning: Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Warning: Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Warning: Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Warning: Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Warning: Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Warning: Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Warning: Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Warning: Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Warning: Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Warning: Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Warning: Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Warning: Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Warning: Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Warning: Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Warning: Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Warning: Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Warning: Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Warning: Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Warning: Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK0_N " "Warning: Node \"OTG_DACK0_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DACK0_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK1_N " "Warning: Node \"OTG_DACK1_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DACK1_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Warning: Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Warning: Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Warning: Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Warning: Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Warning: Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Warning: Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Warning: Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Warning: Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Warning: Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Warning: Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Warning: Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Warning: Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Warning: Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Warning: Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Warning: Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Warning: Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ0 " "Warning: Node \"OTG_DREQ0\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DREQ0" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ1 " "Warning: Node \"OTG_DREQ1\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DREQ1" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_FSPEED " "Warning: Node \"OTG_FSPEED\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT0 " "Warning: Node \"OTG_INT0\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_INT0" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT1 " "Warning: Node \"OTG_INT1\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_INT1" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_LSPEED " "Warning: Node \"OTG_LSPEED\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Warning: Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Warning: Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Warning: Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Warning: Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Warning: Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TCK " "Warning: Node \"TCK\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TCK" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TCS " "Warning: Node \"TCS\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TCS" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TDI " "Warning: Node \"TDI\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TDI" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TDO " "Warning: Node \"TDO\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TDO" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Warning: Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Warning: Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Warning: Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Warning: Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Warning: Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Warning: Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Warning: Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Warning: Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Warning: Node \"TD_HS\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET " "Warning: Node \"TD_RESET\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_RESET" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Warning: Node \"TD_VS\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK " "Warning: Node \"VGA_BLANK\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_BLANK" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Warning: Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Warning: Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Warning: Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Warning: Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Warning: Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Warning: Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Warning: Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Warning: Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[8\] " "Warning: Node \"VGA_B\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[9\] " "Warning: Node \"VGA_B\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Warning: Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Warning: Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Warning: Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Warning: Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Warning: Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Warning: Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Warning: Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Warning: Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Warning: Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[8\] " "Warning: Node \"VGA_G\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[9\] " "Warning: Node \"VGA_G\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Warning: Node \"VGA_HS\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Warning: Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Warning: Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Warning: Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Warning: Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Warning: Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Warning: Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Warning: Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Warning: Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[8\] " "Warning: Node \"VGA_R\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[9\] " "Warning: Node \"VGA_R\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC " "Warning: Node \"VGA_SYNC\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_SYNC" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Warning: Node \"VGA_VS\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:07 " "Info: Fitter preparation operations ending: elapsed time is 00:00:07" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Info: Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "9 " "Info: Router estimated average interconnect usage is 9% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "55 X22_Y12 X32_Y23 " "Info: Router estimated peak interconnect usage is 55% of the available device resources in the region that extends from location X22_Y12 to location X32_Y23" {  } {  } 0 0 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:03 " "Info: Fitter routing operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "265 " "Warning: Found 265 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[0\] 0 " "Info: Pin \"DRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[1\] 0 " "Info: Pin \"DRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[2\] 0 " "Info: Pin \"DRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[3\] 0 " "Info: Pin \"DRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[4\] 0 " "Info: Pin \"DRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[5\] 0 " "Info: Pin \"DRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[6\] 0 " "Info: Pin \"DRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[7\] 0 " "Info: Pin \"DRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[8\] 0 " "Info: Pin \"DRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[9\] 0 " "Info: Pin \"DRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[10\] 0 " "Info: Pin \"DRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[11\] 0 " "Info: Pin \"DRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[12\] 0 " "Info: Pin \"DRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[13\] 0 " "Info: Pin \"DRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[14\] 0 " "Info: Pin \"DRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[15\] 0 " "Info: Pin \"DRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[0\] 0 " "Info: Pin \"FL_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[1\] 0 " "Info: Pin \"FL_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[2\] 0 " "Info: Pin \"FL_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[3\] 0 " "Info: Pin \"FL_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[4\] 0 " "Info: Pin \"FL_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[5\] 0 " "Info: Pin \"FL_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[6\] 0 " "Info: Pin \"FL_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[7\] 0 " "Info: Pin \"FL_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[0\] 0 " "Info: Pin \"SRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[1\] 0 " "Info: Pin \"SRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[2\] 0 " "Info: Pin \"SRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[3\] 0 " "Info: Pin \"SRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[4\] 0 " "Info: Pin \"SRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[5\] 0 " "Info: Pin \"SRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[6\] 0 " "Info: Pin \"SRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[7\] 0 " "Info: Pin \"SRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[8\] 0 " "Info: Pin \"SRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[9\] 0 " "Info: Pin \"SRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[10\] 0 " "Info: Pin \"SRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[11\] 0 " "Info: Pin \"SRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[12\] 0 " "Info: Pin \"SRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[13\] 0 " "Info: Pin \"SRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[14\] 0 " "Info: Pin \"SRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[15\] 0 " "Info: Pin \"SRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[0\] 0 " "Info: Pin \"LCD_DATA\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[1\] 0 " "Info: Pin \"LCD_DATA\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[2\] 0 " "Info: Pin \"LCD_DATA\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[3\] 0 " "Info: Pin \"LCD_DATA\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[4\] 0 " "Info: Pin \"LCD_DATA\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[5\] 0 " "Info: Pin \"LCD_DATA\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[6\] 0 " "Info: Pin \"LCD_DATA\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[7\] 0 " "Info: Pin \"LCD_DATA\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT 0 " "Info: Pin \"SD_DAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT3 0 " "Info: Pin \"SD_DAT3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CMD 0 " "Info: Pin \"SD_CMD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SDAT 0 " "Info: Pin \"I2C_SDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_ADCLRCK 0 " "Info: Pin \"AUD_ADCLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACLRCK 0 " "Info: Pin \"AUD_DACLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_BCLK 0 " "Info: Pin \"AUD_BCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[0\] 0 " "Info: Pin \"GPIO_0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[1\] 0 " "Info: Pin \"GPIO_0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[2\] 0 " "Info: Pin \"GPIO_0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[3\] 0 " "Info: Pin \"GPIO_0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[4\] 0 " "Info: Pin \"GPIO_0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[5\] 0 " "Info: Pin \"GPIO_0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[6\] 0 " "Info: Pin \"GPIO_0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[7\] 0 " "Info: Pin \"GPIO_0\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[8\] 0 " "Info: Pin \"GPIO_0\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[9\] 0 " "Info: Pin \"GPIO_0\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[10\] 0 " "Info: Pin \"GPIO_0\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[11\] 0 " "Info: Pin \"GPIO_0\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[12\] 0 " "Info: Pin \"GPIO_0\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[13\] 0 " "Info: Pin \"GPIO_0\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[14\] 0 " "Info: Pin \"GPIO_0\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[15\] 0 " "Info: Pin \"GPIO_0\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[16\] 0 " "Info: Pin \"GPIO_0\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[17\] 0 " "Info: Pin \"GPIO_0\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[18\] 0 " "Info: Pin \"GPIO_0\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[19\] 0 " "Info: Pin \"GPIO_0\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[20\] 0 " "Info: Pin \"GPIO_0\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[21\] 0 " "Info: Pin \"GPIO_0\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[22\] 0 " "Info: Pin \"GPIO_0\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[23\] 0 " "Info: Pin \"GPIO_0\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[24\] 0 " "Info: Pin \"GPIO_0\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[25\] 0 " "Info: Pin \"GPIO_0\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[26\] 0 " "Info: Pin \"GPIO_0\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[27\] 0 " "Info: Pin \"GPIO_0\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[28\] 0 " "Info: Pin \"GPIO_0\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[29\] 0 " "Info: Pin \"GPIO_0\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[30\] 0 " "Info: Pin \"GPIO_0\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[31\] 0 " "Info: Pin \"GPIO_0\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[32\] 0 " "Info: Pin \"GPIO_0\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[33\] 0 " "Info: Pin \"GPIO_0\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[34\] 0 " "Info: Pin \"GPIO_0\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[35\] 0 " "Info: Pin \"GPIO_0\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[0\] 0 " "Info: Pin \"GPIO_1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[1\] 0 " "Info: Pin \"GPIO_1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[2\] 0 " "Info: Pin \"GPIO_1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[3\] 0 " "Info: Pin \"GPIO_1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[4\] 0 " "Info: Pin \"GPIO_1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[5\] 0 " "Info: Pin \"GPIO_1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[6\] 0 " "Info: Pin \"GPIO_1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[7\] 0 " "Info: Pin \"GPIO_1\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[8\] 0 " "Info: Pin \"GPIO_1\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[9\] 0 " "Info: Pin \"GPIO_1\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[10\] 0 " "Info: Pin \"GPIO_1\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[11\] 0 " "Info: Pin \"GPIO_1\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[12\] 0 " "Info: Pin \"GPIO_1\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[13\] 0 " "Info: Pin \"GPIO_1\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[14\] 0 " "Info: Pin \"GPIO_1\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[15\] 0 " "Info: Pin \"GPIO_1\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[16\] 0 " "Info: Pin \"GPIO_1\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[17\] 0 " "Info: Pin \"GPIO_1\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[18\] 0 " "Info: Pin \"GPIO_1\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[19\] 0 " "Info: Pin \"GPIO_1\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[20\] 0 " "Info: Pin \"GPIO_1\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[21\] 0 " "Info: Pin \"GPIO_1\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[22\] 0 " "Info: Pin \"GPIO_1\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[23\] 0 " "Info: Pin \"GPIO_1\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[24\] 0 " "Info: Pin \"GPIO_1\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[25\] 0 " "Info: Pin \"GPIO_1\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[26\] 0 " "Info: Pin \"GPIO_1\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[27\] 0 " "Info: Pin \"GPIO_1\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[28\] 0 " "Info: Pin \"GPIO_1\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[29\] 0 " "Info: Pin \"GPIO_1\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[30\] 0 " "Info: Pin \"GPIO_1\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[31\] 0 " "Info: Pin \"GPIO_1\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[32\] 0 " "Info: Pin \"GPIO_1\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[33\] 0 " "Info: Pin \"GPIO_1\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[34\] 0 " "Info: Pin \"GPIO_1\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[35\] 0 " "Info: Pin \"GPIO_1\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[0\] 0 " "Info: Pin \"HEX0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[1\] 0 " "Info: Pin \"HEX0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[2\] 0 " "Info: Pin \"HEX0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[3\] 0 " "Info: Pin \"HEX0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[4\] 0 " "Info: Pin \"HEX0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[5\] 0 " "Info: Pin \"HEX0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[6\] 0 " "Info: Pin \"HEX0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[0\] 0 " "Info: Pin \"HEX1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[1\] 0 " "Info: Pin \"HEX1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[2\] 0 " "Info: Pin \"HEX1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[3\] 0 " "Info: Pin \"HEX1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[4\] 0 " "Info: Pin \"HEX1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[5\] 0 " "Info: Pin \"HEX1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[6\] 0 " "Info: Pin \"HEX1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[0\] 0 " "Info: Pin \"HEX2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[1\] 0 " "Info: Pin \"HEX2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[2\] 0 " "Info: Pin \"HEX2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[3\] 0 " "Info: Pin \"HEX2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[4\] 0 " "Info: Pin \"HEX2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[5\] 0 " "Info: Pin \"HEX2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[6\] 0 " "Info: Pin \"HEX2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[0\] 0 " "Info: Pin \"HEX3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[1\] 0 " "Info: Pin \"HEX3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[2\] 0 " "Info: Pin \"HEX3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[3\] 0 " "Info: Pin \"HEX3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[4\] 0 " "Info: Pin \"HEX3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[5\] 0 " "Info: Pin \"HEX3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[6\] 0 " "Info: Pin \"HEX3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[0\] 0 " "Info: Pin \"HEX4\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[1\] 0 " "Info: Pin \"HEX4\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[2\] 0 " "Info: Pin \"HEX4\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[3\] 0 " "Info: Pin \"HEX4\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[4\] 0 " "Info: Pin \"HEX4\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[5\] 0 " "Info: Pin \"HEX4\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[6\] 0 " "Info: Pin \"HEX4\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[0\] 0 " "Info: Pin \"HEX5\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[1\] 0 " "Info: Pin \"HEX5\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[2\] 0 " "Info: Pin \"HEX5\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[3\] 0 " "Info: Pin \"HEX5\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[4\] 0 " "Info: Pin \"HEX5\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[5\] 0 " "Info: Pin \"HEX5\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[6\] 0 " "Info: Pin \"HEX5\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[0\] 0 " "Info: Pin \"HEX6\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[1\] 0 " "Info: Pin \"HEX6\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[2\] 0 " "Info: Pin \"HEX6\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[3\] 0 " "Info: Pin \"HEX6\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[4\] 0 " "Info: Pin \"HEX6\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[5\] 0 " "Info: Pin \"HEX6\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[6\] 0 " "Info: Pin \"HEX6\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[0\] 0 " "Info: Pin \"HEX7\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[1\] 0 " "Info: Pin \"HEX7\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[2\] 0 " "Info: Pin \"HEX7\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[3\] 0 " "Info: Pin \"HEX7\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[4\] 0 " "Info: Pin \"HEX7\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[5\] 0 " "Info: Pin \"HEX7\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[6\] 0 " "Info: Pin \"HEX7\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "UART_TXD 0 " "Info: Pin \"UART_TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IRDA_TXD 0 " "Info: Pin \"IRDA_TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[0\] 0 " "Info: Pin \"DRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[1\] 0 " "Info: Pin \"DRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[2\] 0 " "Info: Pin \"DRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[3\] 0 " "Info: Pin \"DRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[4\] 0 " "Info: Pin \"DRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[5\] 0 " "Info: Pin \"DRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[6\] 0 " "Info: Pin \"DRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[7\] 0 " "Info: Pin \"DRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[8\] 0 " "Info: Pin \"DRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[9\] 0 " "Info: Pin \"DRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[10\] 0 " "Info: Pin \"DRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[11\] 0 " "Info: Pin \"DRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_LDQM 0 " "Info: Pin \"DRAM_LDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_UDQM 0 " "Info: Pin \"DRAM_UDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_WE_N 0 " "Info: Pin \"DRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CAS_N 0 " "Info: Pin \"DRAM_CAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_RAS_N 0 " "Info: Pin \"DRAM_RAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CS_N 0 " "Info: Pin \"DRAM_CS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_0 0 " "Info: Pin \"DRAM_BA_0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_1 0 " "Info: Pin \"DRAM_BA_1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CLK 0 " "Info: Pin \"DRAM_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CKE 0 " "Info: Pin \"DRAM_CKE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[0\] 0 " "Info: Pin \"FL_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[1\] 0 " "Info: Pin \"FL_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[2\] 0 " "Info: Pin \"FL_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[3\] 0 " "Info: Pin \"FL_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[4\] 0 " "Info: Pin \"FL_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[5\] 0 " "Info: Pin \"FL_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[6\] 0 " "Info: Pin \"FL_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[7\] 0 " "Info: Pin \"FL_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[8\] 0 " "Info: Pin \"FL_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[9\] 0 " "Info: Pin \"FL_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[10\] 0 " "Info: Pin \"FL_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[11\] 0 " "Info: Pin \"FL_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[12\] 0 " "Info: Pin \"FL_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[13\] 0 " "Info: Pin \"FL_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[14\] 0 " "Info: Pin \"FL_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[15\] 0 " "Info: Pin \"FL_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[16\] 0 " "Info: Pin \"FL_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[17\] 0 " "Info: Pin \"FL_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[18\] 0 " "Info: Pin \"FL_ADDR\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[19\] 0 " "Info: Pin \"FL_ADDR\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[20\] 0 " "Info: Pin \"FL_ADDR\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[21\] 0 " "Info: Pin \"FL_ADDR\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_WE_N 0 " "Info: Pin \"FL_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_RST_N 0 " "Info: Pin \"FL_RST_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_OE_N 0 " "Info: Pin \"FL_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_CE_N 0 " "Info: Pin \"FL_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[0\] 0 " "Info: Pin \"SRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[1\] 0 " "Info: Pin \"SRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[2\] 0 " "Info: Pin \"SRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[3\] 0 " "Info: Pin \"SRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[4\] 0 " "Info: Pin \"SRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[5\] 0 " "Info: Pin \"SRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[6\] 0 " "Info: Pin \"SRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[7\] 0 " "Info: Pin \"SRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[8\] 0 " "Info: Pin \"SRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[9\] 0 " "Info: Pin \"SRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[10\] 0 " "Info: Pin \"SRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[11\] 0 " "Info: Pin \"SRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[12\] 0 " "Info: Pin \"SRAM_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[13\] 0 " "Info: Pin \"SRAM_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[14\] 0 " "Info: Pin \"SRAM_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[15\] 0 " "Info: Pin \"SRAM_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[16\] 0 " "Info: Pin \"SRAM_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[17\] 0 " "Info: Pin \"SRAM_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_UB_N 0 " "Info: Pin \"SRAM_UB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_LB_N 0 " "Info: Pin \"SRAM_LB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_WE_N 0 " "Info: Pin \"SRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_CE_N 0 " "Info: Pin \"SRAM_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_OE_N 0 " "Info: Pin \"SRAM_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_ON 0 " "Info: Pin \"LCD_ON\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_BLON 0 " "Info: Pin \"LCD_BLON\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_RW 0 " "Info: Pin \"LCD_RW\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_EN 0 " "Info: Pin \"LCD_EN\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_RS 0 " "Info: Pin \"LCD_RS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CLK 0 " "Info: Pin \"SD_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SCLK 0 " "Info: Pin \"I2C_SCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACDAT 0 " "Info: Pin \"AUD_DACDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_XCK 0 " "Info: Pin \"AUD_XCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 0 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "75 " "Warning: Following 75 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SD_DAT3 a permanently enabled " "Info: Pin SD_DAT3 has a permanently enabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { SD_DAT3 } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SD_DAT3" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 184 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 522 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_ADCLRCK a permanently enabled " "Info: Pin AUD_ADCLRCK has a permanently enabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { AUD_ADCLRCK } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 191 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 489 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_DACLRCK a permanently enabled " "Info: Pin AUD_DACLRCK has a permanently enabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { AUD_DACLRCK } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 193 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 528 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_BCLK a permanently enabled " "Info: Pin AUD_BCLK has a permanently enabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { AUD_BCLK } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 195 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 530 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[0\] a permanently disabled " "Info: Pin GPIO_0\[0\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[0] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 275 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[1\] a permanently disabled " "Info: Pin GPIO_0\[1\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[1] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 276 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[2\] a permanently disabled " "Info: Pin GPIO_0\[2\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[2] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 277 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[3\] a permanently disabled " "Info: Pin GPIO_0\[3\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[3] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 278 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[4\] a permanently disabled " "Info: Pin GPIO_0\[4\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[4] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 279 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[5\] a permanently disabled " "Info: Pin GPIO_0\[5\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[5] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 280 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[6\] a permanently disabled " "Info: Pin GPIO_0\[6\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[6] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 281 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[7\] a permanently disabled " "Info: Pin GPIO_0\[7\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[7] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 282 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[8\] a permanently disabled " "Info: Pin GPIO_0\[8\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[8] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 283 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[9\] a permanently disabled " "Info: Pin GPIO_0\[9\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[9] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 284 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[10\] a permanently disabled " "Info: Pin GPIO_0\[10\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[10] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 285 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[12\] a permanently disabled " "Info: Pin GPIO_0\[12\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[12] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 287 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[13\] a permanently enabled " "Info: Pin GPIO_0\[13\] has a permanently enabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[13] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 288 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[14\] a permanently disabled " "Info: Pin GPIO_0\[14\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[14] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 289 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[15\] a permanently disabled " "Info: Pin GPIO_0\[15\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[15] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 290 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[16\] a permanently disabled " "Info: Pin GPIO_0\[16\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[16] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 291 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[17\] a permanently disabled " "Info: Pin GPIO_0\[17\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[17] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 292 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[18\] a permanently disabled " "Info: Pin GPIO_0\[18\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[18] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 293 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[19\] a permanently disabled " "Info: Pin GPIO_0\[19\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[19] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 294 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[20\] a permanently disabled " "Info: Pin GPIO_0\[20\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[20] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 295 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[21\] a permanently disabled " "Info: Pin GPIO_0\[21\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[21] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 296 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[22\] a permanently disabled " "Info: Pin GPIO_0\[22\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[22] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 297 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[23\] a permanently disabled " "Info: Pin GPIO_0\[23\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[23] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 298 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[24\] a permanently disabled " "Info: Pin GPIO_0\[24\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[24] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 299 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[25\] a permanently disabled " "Info: Pin GPIO_0\[25\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[25] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 300 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[26\] a permanently disabled " "Info: Pin GPIO_0\[26\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[26] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 301 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[27\] a permanently disabled " "Info: Pin GPIO_0\[27\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[27] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 302 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[28\] a permanently disabled " "Info: Pin GPIO_0\[28\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[28] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 303 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[29\] a permanently disabled " "Info: Pin GPIO_0\[29\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[29] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 304 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[30\] a permanently disabled " "Info: Pin GPIO_0\[30\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[30] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 305 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[31\] a permanently disabled " "Info: Pin GPIO_0\[31\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[31] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 306 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[32\] a permanently disabled " "Info: Pin GPIO_0\[32\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[32] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 307 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[33\] a permanently disabled " "Info: Pin GPIO_0\[33\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[33] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 308 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[34\] a permanently disabled " "Info: Pin GPIO_0\[34\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[34] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 309 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[35\] a permanently disabled " "Info: Pin GPIO_0\[35\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[35] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 310 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Info: Pin GPIO_1\[0\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 239 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Info: Pin GPIO_1\[1\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 240 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Info: Pin GPIO_1\[2\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[2] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 241 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Info: Pin GPIO_1\[3\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[3] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 242 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Info: Pin GPIO_1\[4\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[4] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 243 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Info: Pin GPIO_1\[5\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[5] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 244 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Info: Pin GPIO_1\[6\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[6] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 245 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Info: Pin GPIO_1\[7\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[7] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 246 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Info: Pin GPIO_1\[8\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[8] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 247 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Info: Pin GPIO_1\[9\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[9] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 248 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Info: Pin GPIO_1\[10\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[10] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 249 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Info: Pin GPIO_1\[11\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[11] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 250 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Info: Pin GPIO_1\[12\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[12] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 251 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Info: Pin GPIO_1\[13\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[13] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 252 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Info: Pin GPIO_1\[14\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[14] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 253 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Info: Pin GPIO_1\[15\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[15] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 254 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Info: Pin GPIO_1\[16\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[16] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 255 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Info: Pin GPIO_1\[17\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[17] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 256 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Info: Pin GPIO_1\[18\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[18] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 257 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Info: Pin GPIO_1\[19\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[19] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 258 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Info: Pin GPIO_1\[20\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[20] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 259 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Info: Pin GPIO_1\[21\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[21] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 260 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Info: Pin GPIO_1\[22\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[22] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 261 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Info: Pin GPIO_1\[23\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[23] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 262 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Info: Pin GPIO_1\[24\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[24] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 263 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Info: Pin GPIO_1\[25\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[25] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 264 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Info: Pin GPIO_1\[26\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[26] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 265 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Info: Pin GPIO_1\[27\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[27] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 266 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Info: Pin GPIO_1\[28\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[28] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 267 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Info: Pin GPIO_1\[29\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[29] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 268 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Info: Pin GPIO_1\[30\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[30] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 269 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Info: Pin GPIO_1\[31\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[31] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 270 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Info: Pin GPIO_1\[32\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[32] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 271 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently disabled " "Info: Pin GPIO_1\[33\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[33] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 272 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[34\] a permanently disabled " "Info: Pin GPIO_1\[34\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[34] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 273 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[35\] a permanently disabled " "Info: Pin GPIO_1\[35\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[35] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 274 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1}  } {  } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.fit.smsg " "Info: Generated suppressed messages file /afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 194 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 194 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "387 " "Info: Peak virtual memory: 387 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 12 14:07:02 2013 " "Info: Processing ended: Fri Apr 12 14:07:02 2013" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Info: Elapsed time: 00:00:30" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Info: Total CPU time (on all processors): 00:00:27" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition " "Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 12 14:07:04 2013 " "Info: Processing started: Fri Apr 12 14:07:04 2013" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DE2_SD_Card_Audio -c DE2_SD_Card_Audio " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DE2_SD_Card_Audio -c DE2_SD_Card_Audio" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WIDU_QIC_OFF_NOT_SUPPORTED" "" "Critical Warning: Setting INCREMENTAL_COMPILATION to \"OFF\" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to \"ON\" instead." {  } {  } 1 0 "Setting INCREMENTAL_COMPILATION to \"OFF\" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to \"ON\" instead." 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "304 " "Info: Peak virtual memory: 304 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 12 14:07:08 2013 " "Info: Processing ended: Fri Apr 12 14:07:08 2013" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II " "Info: Running Quartus II TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition " "Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 12 14:07:09 2013 " "Info: Processing started: Fri Apr 12 14:07:09 2013" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DE2_SD_Card_Audio -c DE2_SD_Card_Audio " "Info: Command: quartus_sta DE2_SD_Card_Audio -c DE2_SD_Card_Audio" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: qsta_default_script.tcl version: #4" {  } {  } 0 0 "qsta_default_script.tcl version: #4" 0 0 "" 0 -1}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "system_0_clock_1 " "Warning: Ignored assignments for entity \"system_0_clock_1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[0\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[0\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[0\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[0\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[10\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[10\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[10\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[10\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[11\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[11\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[11\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[11\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[12\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[12\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[12\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[12\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[13\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[13\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[13\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[13\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[14\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[14\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[14\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[14\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[15\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[15\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[15\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[15\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[1\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[1\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[1\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[1\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[2\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[2\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[2\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[2\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[3\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[3\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[3\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[3\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[4\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[4\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[4\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[4\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[5\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[5\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[5\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[5\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[6\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[6\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[6\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[6\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[7\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[7\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[7\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[7\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[8\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[8\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[8\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[8\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[9\] -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[9\] -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to slave_readdata\[9\]~reg0 -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata\[9\]~reg0 -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[0\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[0\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[10\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[10\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[11\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[11\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[12\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[12\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[13\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[13\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[14\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[14\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[15\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[15\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[16\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[16\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[17\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[17\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[18\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[18\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[19\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[19\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[1\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[1\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[20\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[20\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[21\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[21\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[22\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[22\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[2\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[2\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[3\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[3\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[4\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[4\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[5\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[5\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[6\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[6\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[7\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[7\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[8\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[8\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_address_d1\[9\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1\[9\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_byteenable_d1\[0\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_byteenable_d1\[0\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_byteenable_d1\[1\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_byteenable_d1\[1\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[0\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[0\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[10\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[10\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[11\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[11\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[12\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[12\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[13\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[13\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[14\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[14\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[15\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[15\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[16\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[16\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[17\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[17\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[18\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[18\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[19\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[19\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[1\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[1\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[20\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[20\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[21\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[21\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[2\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[2\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[3\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[3\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[4\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[4\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[5\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[5\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[6\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[6\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[7\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[7\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[8\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[8\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[9\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1\[9\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[0\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[0\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[10\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[10\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[11\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[11\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[12\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[12\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[13\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[13\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[14\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[14\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[15\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[15\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[1\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[1\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[2\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[2\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[3\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[3\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[4\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[4\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[5\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[5\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[6\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[6\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[7\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[7\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[8\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[8\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from slave_writedata_d1\[9\] -to * -entity system_0_clock_1 -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1\[9\] -to * -entity system_0_clock_1 -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "" 0 -1}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "system_0_clock_1_bit_pipe " "Warning: Ignored assignments for entity \"system_0_clock_1_bit_pipe\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from data_in_d1 -to * -entity system_0_clock_1_bit_pipe -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from data_in_d1 -to * -entity system_0_clock_1_bit_pipe -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "" 0 -1}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "system_0_reset_clk_50_domain_synch_module " "Warning: Ignored assignments for entity \"system_0_reset_clk_50_domain_synch_module\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name CUT ON -from * -to data_in_d1 -entity system_0_reset_clk_50_domain_synch_module -tag quartusii " "Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to data_in_d1 -entity system_0_reset_clk_50_domain_synch_module -tag quartusii was ignored" {  } {  } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[19\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[19\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[21\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[21\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[23\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[23\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[25\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[25\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[18\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[18\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[26\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[26\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[27\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[27\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[16\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[16\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[24\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[24\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[17\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[17\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[20\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[20\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[28\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[28\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[29\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[29\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[22\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[22\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[30\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[30\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[31\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[31\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[0\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[0\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[1\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[1\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[2\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[2\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[3\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[3\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[4\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[4\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[5\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[5\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[6\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[6\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[7\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[7\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[10\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[10\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[11\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[11\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[8\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[8\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[9\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[9\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[12\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[12\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[13\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[13\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[14\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[14\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[15\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[15\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0 -1}
{ "Critical Warning" "WIDU_QIC_OFF_NOT_SUPPORTED" "" "Critical Warning: Setting INCREMENTAL_COMPILATION to \"OFF\" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to \"ON\" instead." {  } {  } 1 0 "Setting INCREMENTAL_COMPILATION to \"OFF\" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to \"ON\" instead." 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Info: Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\]  " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read_write1*\}\]  " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read_write1*\}\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Info: Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "Info: set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "dcfifo_hlj1 " "Info: Entity dcfifo_hlj1" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_id9:dffpipe20\|dffe21a*  " "Info: set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_id9:dffpipe20\|dffe21a* " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_hd9:dffpipe17\|dffe18a*  " "Info: set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_hd9:dffpipe17\|dffe18a* " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Info: Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "Info: create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "Info: set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_FOUND" "cpu_0.sdc " "Info: Reading SDC File: 'cpu_0.sdc'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_FOUND" "/opt/altera/10.1sp1/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter/altera_avalon_clock_adapter.sdc " "Info: Reading SDC File: '/opt/altera/10.1sp1/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter/altera_avalon_clock_adapter.sdc'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Warning: Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_0\[15\] " "Warning: Node: GPIO_0\[15\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_27 " "Warning: Node: CLOCK_27 was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "I2C_AV_Config:u1\|mI2C_CTRL_CLK " "Warning: Node: I2C_AV_Config:u1\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK " "Warning: Node: system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "system_0:u0\|cpu_0:the_cpu_0\|d_address\[10\] " "Warning: Node: system_0:u0\|cpu_0:the_cpu_0\|d_address\[10\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: u0\|the_altpll_0\|sd1\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: u0\|the_altpll_0\|sd1\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: u0\|the_altpll_0\|sd1\|pll\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: u0\|the_altpll_0\|sd1\|pll\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: PLL2\|altpll_component\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 37.037 " "Warning: Node: PLL2\|altpll_component\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 37.037" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Slow Model" {  } {  } 0 0 "Analyzing Slow Model" 0 0 "" 0 -1}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "Info: No fmax paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "Info: No Setup paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "Info: No Hold paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "Info: No Recovery paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "Info: No Removal paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 97.778 " "Info: Worst-case minimum pulse width slack is 97.778" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   97.778         0.000 altera_reserved_tck  " "Info:    97.778         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "Info: The selected device family is not supported by the report_metastability command." {  } {  } 0 0 "The selected device family is not supported by the report_metastability command." 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Fast Model" {  } {  } 0 0 "Analyzing Fast Model" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "265 " "Warning: Found 265 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[0\] 0 " "Info: Pin \"DRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[1\] 0 " "Info: Pin \"DRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[2\] 0 " "Info: Pin \"DRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[3\] 0 " "Info: Pin \"DRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[4\] 0 " "Info: Pin \"DRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[5\] 0 " "Info: Pin \"DRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[6\] 0 " "Info: Pin \"DRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[7\] 0 " "Info: Pin \"DRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[8\] 0 " "Info: Pin \"DRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[9\] 0 " "Info: Pin \"DRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[10\] 0 " "Info: Pin \"DRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[11\] 0 " "Info: Pin \"DRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[12\] 0 " "Info: Pin \"DRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[13\] 0 " "Info: Pin \"DRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[14\] 0 " "Info: Pin \"DRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[15\] 0 " "Info: Pin \"DRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[0\] 0 " "Info: Pin \"FL_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[1\] 0 " "Info: Pin \"FL_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[2\] 0 " "Info: Pin \"FL_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[3\] 0 " "Info: Pin \"FL_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[4\] 0 " "Info: Pin \"FL_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[5\] 0 " "Info: Pin \"FL_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[6\] 0 " "Info: Pin \"FL_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[7\] 0 " "Info: Pin \"FL_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[0\] 0 " "Info: Pin \"SRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[1\] 0 " "Info: Pin \"SRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[2\] 0 " "Info: Pin \"SRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[3\] 0 " "Info: Pin \"SRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[4\] 0 " "Info: Pin \"SRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[5\] 0 " "Info: Pin \"SRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[6\] 0 " "Info: Pin \"SRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[7\] 0 " "Info: Pin \"SRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[8\] 0 " "Info: Pin \"SRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[9\] 0 " "Info: Pin \"SRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[10\] 0 " "Info: Pin \"SRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[11\] 0 " "Info: Pin \"SRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[12\] 0 " "Info: Pin \"SRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[13\] 0 " "Info: Pin \"SRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[14\] 0 " "Info: Pin \"SRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[15\] 0 " "Info: Pin \"SRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[0\] 0 " "Info: Pin \"LCD_DATA\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[1\] 0 " "Info: Pin \"LCD_DATA\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[2\] 0 " "Info: Pin \"LCD_DATA\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[3\] 0 " "Info: Pin \"LCD_DATA\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[4\] 0 " "Info: Pin \"LCD_DATA\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[5\] 0 " "Info: Pin \"LCD_DATA\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[6\] 0 " "Info: Pin \"LCD_DATA\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[7\] 0 " "Info: Pin \"LCD_DATA\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT 0 " "Info: Pin \"SD_DAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT3 0 " "Info: Pin \"SD_DAT3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CMD 0 " "Info: Pin \"SD_CMD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SDAT 0 " "Info: Pin \"I2C_SDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_ADCLRCK 0 " "Info: Pin \"AUD_ADCLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACLRCK 0 " "Info: Pin \"AUD_DACLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_BCLK 0 " "Info: Pin \"AUD_BCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[0\] 0 " "Info: Pin \"GPIO_0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[1\] 0 " "Info: Pin \"GPIO_0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[2\] 0 " "Info: Pin \"GPIO_0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[3\] 0 " "Info: Pin \"GPIO_0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[4\] 0 " "Info: Pin \"GPIO_0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[5\] 0 " "Info: Pin \"GPIO_0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[6\] 0 " "Info: Pin \"GPIO_0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[7\] 0 " "Info: Pin \"GPIO_0\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[8\] 0 " "Info: Pin \"GPIO_0\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[9\] 0 " "Info: Pin \"GPIO_0\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[10\] 0 " "Info: Pin \"GPIO_0\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[11\] 0 " "Info: Pin \"GPIO_0\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[12\] 0 " "Info: Pin \"GPIO_0\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[13\] 0 " "Info: Pin \"GPIO_0\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[14\] 0 " "Info: Pin \"GPIO_0\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[15\] 0 " "Info: Pin \"GPIO_0\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[16\] 0 " "Info: Pin \"GPIO_0\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[17\] 0 " "Info: Pin \"GPIO_0\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[18\] 0 " "Info: Pin \"GPIO_0\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[19\] 0 " "Info: Pin \"GPIO_0\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[20\] 0 " "Info: Pin \"GPIO_0\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[21\] 0 " "Info: Pin \"GPIO_0\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[22\] 0 " "Info: Pin \"GPIO_0\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[23\] 0 " "Info: Pin \"GPIO_0\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[24\] 0 " "Info: Pin \"GPIO_0\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[25\] 0 " "Info: Pin \"GPIO_0\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[26\] 0 " "Info: Pin \"GPIO_0\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[27\] 0 " "Info: Pin \"GPIO_0\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[28\] 0 " "Info: Pin \"GPIO_0\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[29\] 0 " "Info: Pin \"GPIO_0\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[30\] 0 " "Info: Pin \"GPIO_0\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[31\] 0 " "Info: Pin \"GPIO_0\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[32\] 0 " "Info: Pin \"GPIO_0\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[33\] 0 " "Info: Pin \"GPIO_0\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[34\] 0 " "Info: Pin \"GPIO_0\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[35\] 0 " "Info: Pin \"GPIO_0\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[0\] 0 " "Info: Pin \"GPIO_1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[1\] 0 " "Info: Pin \"GPIO_1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[2\] 0 " "Info: Pin \"GPIO_1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[3\] 0 " "Info: Pin \"GPIO_1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[4\] 0 " "Info: Pin \"GPIO_1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[5\] 0 " "Info: Pin \"GPIO_1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[6\] 0 " "Info: Pin \"GPIO_1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[7\] 0 " "Info: Pin \"GPIO_1\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[8\] 0 " "Info: Pin \"GPIO_1\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[9\] 0 " "Info: Pin \"GPIO_1\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[10\] 0 " "Info: Pin \"GPIO_1\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[11\] 0 " "Info: Pin \"GPIO_1\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[12\] 0 " "Info: Pin \"GPIO_1\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[13\] 0 " "Info: Pin \"GPIO_1\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[14\] 0 " "Info: Pin \"GPIO_1\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[15\] 0 " "Info: Pin \"GPIO_1\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[16\] 0 " "Info: Pin \"GPIO_1\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[17\] 0 " "Info: Pin \"GPIO_1\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[18\] 0 " "Info: Pin \"GPIO_1\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[19\] 0 " "Info: Pin \"GPIO_1\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[20\] 0 " "Info: Pin \"GPIO_1\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[21\] 0 " "Info: Pin \"GPIO_1\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[22\] 0 " "Info: Pin \"GPIO_1\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[23\] 0 " "Info: Pin \"GPIO_1\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[24\] 0 " "Info: Pin \"GPIO_1\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[25\] 0 " "Info: Pin \"GPIO_1\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[26\] 0 " "Info: Pin \"GPIO_1\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[27\] 0 " "Info: Pin \"GPIO_1\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[28\] 0 " "Info: Pin \"GPIO_1\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[29\] 0 " "Info: Pin \"GPIO_1\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[30\] 0 " "Info: Pin \"GPIO_1\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[31\] 0 " "Info: Pin \"GPIO_1\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[32\] 0 " "Info: Pin \"GPIO_1\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[33\] 0 " "Info: Pin \"GPIO_1\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[34\] 0 " "Info: Pin \"GPIO_1\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[35\] 0 " "Info: Pin \"GPIO_1\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[0\] 0 " "Info: Pin \"HEX0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[1\] 0 " "Info: Pin \"HEX0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[2\] 0 " "Info: Pin \"HEX0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[3\] 0 " "Info: Pin \"HEX0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[4\] 0 " "Info: Pin \"HEX0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[5\] 0 " "Info: Pin \"HEX0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[6\] 0 " "Info: Pin \"HEX0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[0\] 0 " "Info: Pin \"HEX1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[1\] 0 " "Info: Pin \"HEX1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[2\] 0 " "Info: Pin \"HEX1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[3\] 0 " "Info: Pin \"HEX1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[4\] 0 " "Info: Pin \"HEX1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[5\] 0 " "Info: Pin \"HEX1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[6\] 0 " "Info: Pin \"HEX1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[0\] 0 " "Info: Pin \"HEX2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[1\] 0 " "Info: Pin \"HEX2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[2\] 0 " "Info: Pin \"HEX2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[3\] 0 " "Info: Pin \"HEX2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[4\] 0 " "Info: Pin \"HEX2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[5\] 0 " "Info: Pin \"HEX2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[6\] 0 " "Info: Pin \"HEX2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[0\] 0 " "Info: Pin \"HEX3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[1\] 0 " "Info: Pin \"HEX3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[2\] 0 " "Info: Pin \"HEX3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[3\] 0 " "Info: Pin \"HEX3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[4\] 0 " "Info: Pin \"HEX3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[5\] 0 " "Info: Pin \"HEX3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[6\] 0 " "Info: Pin \"HEX3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[0\] 0 " "Info: Pin \"HEX4\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[1\] 0 " "Info: Pin \"HEX4\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[2\] 0 " "Info: Pin \"HEX4\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[3\] 0 " "Info: Pin \"HEX4\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[4\] 0 " "Info: Pin \"HEX4\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[5\] 0 " "Info: Pin \"HEX4\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[6\] 0 " "Info: Pin \"HEX4\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[0\] 0 " "Info: Pin \"HEX5\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[1\] 0 " "Info: Pin \"HEX5\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[2\] 0 " "Info: Pin \"HEX5\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[3\] 0 " "Info: Pin \"HEX5\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[4\] 0 " "Info: Pin \"HEX5\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[5\] 0 " "Info: Pin \"HEX5\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[6\] 0 " "Info: Pin \"HEX5\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[0\] 0 " "Info: Pin \"HEX6\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[1\] 0 " "Info: Pin \"HEX6\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[2\] 0 " "Info: Pin \"HEX6\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[3\] 0 " "Info: Pin \"HEX6\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[4\] 0 " "Info: Pin \"HEX6\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[5\] 0 " "Info: Pin \"HEX6\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[6\] 0 " "Info: Pin \"HEX6\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[0\] 0 " "Info: Pin \"HEX7\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[1\] 0 " "Info: Pin \"HEX7\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[2\] 0 " "Info: Pin \"HEX7\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[3\] 0 " "Info: Pin \"HEX7\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[4\] 0 " "Info: Pin \"HEX7\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[5\] 0 " "Info: Pin \"HEX7\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[6\] 0 " "Info: Pin \"HEX7\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "UART_TXD 0 " "Info: Pin \"UART_TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IRDA_TXD 0 " "Info: Pin \"IRDA_TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[0\] 0 " "Info: Pin \"DRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[1\] 0 " "Info: Pin \"DRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[2\] 0 " "Info: Pin \"DRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[3\] 0 " "Info: Pin \"DRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[4\] 0 " "Info: Pin \"DRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[5\] 0 " "Info: Pin \"DRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[6\] 0 " "Info: Pin \"DRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[7\] 0 " "Info: Pin \"DRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[8\] 0 " "Info: Pin \"DRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[9\] 0 " "Info: Pin \"DRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[10\] 0 " "Info: Pin \"DRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[11\] 0 " "Info: Pin \"DRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_LDQM 0 " "Info: Pin \"DRAM_LDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_UDQM 0 " "Info: Pin \"DRAM_UDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_WE_N 0 " "Info: Pin \"DRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CAS_N 0 " "Info: Pin \"DRAM_CAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_RAS_N 0 " "Info: Pin \"DRAM_RAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CS_N 0 " "Info: Pin \"DRAM_CS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_0 0 " "Info: Pin \"DRAM_BA_0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_1 0 " "Info: Pin \"DRAM_BA_1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CLK 0 " "Info: Pin \"DRAM_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CKE 0 " "Info: Pin \"DRAM_CKE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[0\] 0 " "Info: Pin \"FL_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[1\] 0 " "Info: Pin \"FL_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[2\] 0 " "Info: Pin \"FL_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[3\] 0 " "Info: Pin \"FL_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[4\] 0 " "Info: Pin \"FL_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[5\] 0 " "Info: Pin \"FL_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[6\] 0 " "Info: Pin \"FL_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[7\] 0 " "Info: Pin \"FL_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[8\] 0 " "Info: Pin \"FL_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[9\] 0 " "Info: Pin \"FL_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[10\] 0 " "Info: Pin \"FL_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[11\] 0 " "Info: Pin \"FL_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[12\] 0 " "Info: Pin \"FL_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[13\] 0 " "Info: Pin \"FL_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[14\] 0 " "Info: Pin \"FL_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[15\] 0 " "Info: Pin \"FL_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[16\] 0 " "Info: Pin \"FL_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[17\] 0 " "Info: Pin \"FL_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[18\] 0 " "Info: Pin \"FL_ADDR\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[19\] 0 " "Info: Pin \"FL_ADDR\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[20\] 0 " "Info: Pin \"FL_ADDR\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[21\] 0 " "Info: Pin \"FL_ADDR\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_WE_N 0 " "Info: Pin \"FL_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_RST_N 0 " "Info: Pin \"FL_RST_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_OE_N 0 " "Info: Pin \"FL_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_CE_N 0 " "Info: Pin \"FL_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[0\] 0 " "Info: Pin \"SRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[1\] 0 " "Info: Pin \"SRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[2\] 0 " "Info: Pin \"SRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[3\] 0 " "Info: Pin \"SRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[4\] 0 " "Info: Pin \"SRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[5\] 0 " "Info: Pin \"SRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[6\] 0 " "Info: Pin \"SRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[7\] 0 " "Info: Pin \"SRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[8\] 0 " "Info: Pin \"SRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[9\] 0 " "Info: Pin \"SRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[10\] 0 " "Info: Pin \"SRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[11\] 0 " "Info: Pin \"SRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[12\] 0 " "Info: Pin \"SRAM_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[13\] 0 " "Info: Pin \"SRAM_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[14\] 0 " "Info: Pin \"SRAM_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[15\] 0 " "Info: Pin \"SRAM_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[16\] 0 " "Info: Pin \"SRAM_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[17\] 0 " "Info: Pin \"SRAM_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_UB_N 0 " "Info: Pin \"SRAM_UB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_LB_N 0 " "Info: Pin \"SRAM_LB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_WE_N 0 " "Info: Pin \"SRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_CE_N 0 " "Info: Pin \"SRAM_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_OE_N 0 " "Info: Pin \"SRAM_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_ON 0 " "Info: Pin \"LCD_ON\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_BLON 0 " "Info: Pin \"LCD_BLON\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_RW 0 " "Info: Pin \"LCD_RW\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_EN 0 " "Info: Pin \"LCD_EN\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_RS 0 " "Info: Pin \"LCD_RS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CLK 0 " "Info: Pin \"SD_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SCLK 0 " "Info: Pin \"I2C_SCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACDAT 0 " "Info: Pin \"AUD_DACDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_XCK 0 " "Info: Pin \"AUD_XCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Warning: Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_0\[15\] " "Warning: Node: GPIO_0\[15\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_27 " "Warning: Node: CLOCK_27 was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "I2C_AV_Config:u1\|mI2C_CTRL_CLK " "Warning: Node: I2C_AV_Config:u1\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK " "Warning: Node: system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "system_0:u0\|cpu_0:the_cpu_0\|d_address\[10\] " "Warning: Node: system_0:u0\|cpu_0:the_cpu_0\|d_address\[10\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: u0\|the_altpll_0\|sd1\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: u0\|the_altpll_0\|sd1\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: u0\|the_altpll_0\|sd1\|pll\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: u0\|the_altpll_0\|sd1\|pll\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: PLL2\|altpll_component\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 37.037 " "Warning: Node: PLL2\|altpll_component\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 37.037" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "Info: No Setup paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "Info: No Hold paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "Info: No Recovery paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "Info: No Removal paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 97.778 " "Info: Worst-case minimum pulse width slack is 97.778" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   97.778         0.000 altera_reserved_tck  " "Info:    97.778         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "Info: The selected device family is not supported by the report_metastability command." {  } {  } 0 0 "The selected device family is not supported by the report_metastability command." 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Info: Design is not fully constrained for setup requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Info: Design is not fully constrained for hold requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 155 s Quartus II " "Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 155 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "292 " "Info: Peak virtual memory: 292 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 12 14:07:19 2013 " "Info: Processing ended: Fri Apr 12 14:07:19 2013" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Info: Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 555 s " "Info: Quartus II Full Compilation was successful. 0 errors, 555 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
