{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition " "Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 12 14:16:38 2013 " "Info: Processing started: Fri Apr 12 14:16:38 2013" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DE2_SD_Card_Audio -c DE2_SD_Card_Audio " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DE2_SD_Card_Audio -c DE2_SD_Card_Audio" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WIDU_QIC_OFF_NOT_SUPPORTED" "" "Critical Warning: Setting INCREMENTAL_COMPILATION to \"OFF\" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to \"ON\" instead." {  } {  } 1 0 "Setting INCREMENTAL_COMPILATION to \"OFF\" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to \"ON\" instead." 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "DE2_SD_Card_Audio EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"DE2_SD_Card_Audio\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|pll Cyclone II PLL " "Info: Implemented PLL \"system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk0 2 1 -108 -3000 " "Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of -108 degrees (-3000 ps) for system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk0 port" {  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 920 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk1 2 1 0 0 " "Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk1 port" {  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 917 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 539 3 0 } }  } 0 0 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "Audio_PLL:PLL2\|altpll:altpll_component\|pll Cyclone II PLL " "Info: Implemented PLL \"Audio_PLL:PLL2\|altpll:altpll_component\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "Audio_PLL:PLL2\|altpll:altpll_component\|_clk0 15 22 0 0 " "Info: Implementing clock multiplication of 15, clock division of 22, and phase shift of 0 degrees (0 ps) for Audio_PLL:PLL2\|altpll:altpll_component\|_clk0 port" {  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 920 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 539 3 0 } }  } 0 0 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Info: Pin ~ASDO~ is reserved at location E3" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { ~ASDO~ } } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 26115 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Info: Pin ~nCSO~ is reserved at location D3" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { ~nCSO~ } } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 26116 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "TimeQuest " "Info: Timing-driven compilation is using the TimeQuest Timing Analyzer" {  } {  } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[21\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[21\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[1\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[1\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[22\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[22\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[15\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[15\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[23\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[23\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[10\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[10\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[31\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[31\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[24\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[24\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[26\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[26\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[17\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[17\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[25\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[25\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[14\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[14\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[13\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[13\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[16\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[16\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[18\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[18\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[19\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[19\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[7\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[7\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[20\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[20\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[0\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[0\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[9\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[9\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[30\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[30\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[29\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[29\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[12\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[12\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[8\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[8\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[11\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[11\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[27\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[27\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[28\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[28\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[5\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[5\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[3\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[3\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[6\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[6\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[4\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[4\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[2\]\|combout " "Warning: Node \"u0\|the_Accel_Control\|accel_control\|avalon_slave_readdata\[2\]\|combout\" is a latch" {  } { { "Accelerometer1/accelerometer.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Accelerometer1/accelerometer.vhd" 93 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Info: Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\]  " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read_write1*\}\]  " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read_write1*\}\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Info: Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "Info: set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "dcfifo_hlj1 " "Info: Entity dcfifo_hlj1" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_id9:dffpipe20\|dffe21a*  " "Info: set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_id9:dffpipe20\|dffe21a* " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_hd9:dffpipe17\|dffe18a*  " "Info: set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_hd9:dffpipe17\|dffe18a* " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Info: Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "Info: create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "Info: set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_FOUND" "cpu_0.sdc " "Info: Reading SDC File: 'cpu_0.sdc'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_FOUND" "/opt/altera/10.1sp1/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter/altera_avalon_clock_adapter.sdc " "Info: Reading SDC File: '/opt/altera/10.1sp1/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter/altera_avalon_clock_adapter.sdc'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Warning: Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_0\[15\] " "Warning: Node: GPIO_0\[15\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_27 " "Warning: Node: CLOCK_27 was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "I2C_AV_Config:u1\|mI2C_CTRL_CLK " "Warning: Node: I2C_AV_Config:u1\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK " "Warning: Node: system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "system_0:u0\|system_0_burst_32:the_system_0_burst_32\|reg_downstream_read " "Warning: Node: system_0:u0\|system_0_burst_32:the_system_0_burst_32\|reg_downstream_read was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: u0\|the_altpll_0\|sd1\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: u0\|the_altpll_0\|sd1\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: u0\|the_altpll_0\|sd1\|pll\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: u0\|the_altpll_0\|sd1\|pll\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: PLL2\|altpll_component\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 37.037 " "Warning: Node: PLL2\|altpll_component\|pll\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 37.037" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Info: Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Info: Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "Info:   Period   Clock Name" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "Info: ======== ============" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " "Info:  100.000 altera_reserved_tck" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Audio_PLL:PLL2\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_3) " "Info: Automatically promoted node Audio_PLL:PLL2\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_3)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G11 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G11" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 539 3 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Audio_PLL:PLL2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 11745 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50 (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CLOCK_50 (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 126 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 671 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk0 (placed in counter C2 of PLL_1) " "Info: Automatically promoted node system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk0 (placed in counter C2 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations External Clock Output CLKCTRL_X0_Y1_N1 " "Info: Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_X0_Y1_N1" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 539 3 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|altpll_0:the_altpll_0|altpll:sd1|_clk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 11334 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk1 (placed in counter C0 of PLL_1) " "Info: Automatically promoted node system_0:u0\|altpll_0:the_altpll_0\|altpll:sd1\|_clk1 (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 539 3 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|altpll_0:the_altpll_0|altpll:sd1|_clk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 11334 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "GPIO_0\[15\]~51 (placed in PIN G25 (LVDS112p, CDPCLK5/DQS2R/CQ3R)) " "Info: Automatically promoted node GPIO_0\[15\]~51 (placed in PIN G25 (LVDS112p, CDPCLK5/DQS2R/CQ3R))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G6 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G6" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[15] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 469 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Info: Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 12066 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "I2C_AV_Config:u1\|mI2C_CTRL_CLK  " "Info: Automatically promoted node I2C_AV_Config:u1\|mI2C_CTRL_CLK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~2 " "Info: Destination node I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~2" {  } { { "I2C_Controller.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_Controller.v" 62 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 12671 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "I2C_AV_Config:u1\|mI2C_CTRL_CLK~0 " "Info: Destination node I2C_AV_Config:u1\|mI2C_CTRL_CLK~0" {  } { { "I2C_AV_Config.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_AV_Config.v" 16 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|mI2C_CTRL_CLK~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 13032 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "I2C_AV_Config.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/I2C_AV_Config.v" 16 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|mI2C_CTRL_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 975 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|system_0_burst_32:the_system_0_burst_32\|reg_downstream_read  " "Info: Automatically promoted node system_0:u0\|system_0_burst_32:the_system_0_burst_32\|reg_downstream_read " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|system_0_burst_32:the_system_0_burst_32\|upstream_waitrequest~0 " "Info: Destination node system_0:u0\|system_0_burst_32:the_system_0_burst_32\|upstream_waitrequest~0" {  } { { "system_0_burst_32.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_burst_32.v" 95 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_burst_32:the_system_0_burst_32|upstream_waitrequest~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 13353 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|system_0_burst_32_upstream_arbitrator:the_system_0_burst_32_upstream\|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_32_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_32_upstream\|updated_one_count~1 " "Info: Destination node system_0:u0\|system_0_burst_32_upstream_arbitrator:the_system_0_burst_32_upstream\|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_32_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_32_upstream\|updated_one_count~1" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 38914 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_burst_32_upstream_arbitrator:the_system_0_burst_32_upstream|rdv_fifo_for_cpu_0_data_master_to_system_0_burst_32_upstream_module:rdv_fifo_for_cpu_0_data_master_to_system_0_burst_32_upstream|updated_one_count~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 13722 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|system_0_burst_32_downstream_arbitrator:the_system_0_burst_32_downstream\|r_0~0 " "Info: Destination node system_0:u0\|system_0_burst_32_downstream_arbitrator:the_system_0_burst_32_downstream\|r_0~0" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 39567 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_burst_32_downstream_arbitrator:the_system_0_burst_32_downstream|r_0~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 14475 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|system_0_burst_32_upstream_arbitrator:the_system_0_burst_32_upstream\|system_0_burst_32_upstream_this_cycle_is_the_last_burst~1 " "Info: Destination node system_0:u0\|system_0_burst_32_upstream_arbitrator:the_system_0_burst_32_upstream\|system_0_burst_32_upstream_this_cycle_is_the_last_burst~1" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 39205 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_burst_32_upstream_arbitrator:the_system_0_burst_32_upstream|system_0_burst_32_upstream_this_cycle_is_the_last_burst~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 15287 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[21\]~82 " "Info: Destination node system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[21\]~82" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 4079 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~82 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 18645 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[20\]~88 " "Info: Destination node system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[20\]~88" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 4079 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[20]~88 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 18652 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[16\]~111 " "Info: Destination node system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[16\]~111" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 4079 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~111 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 18679 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[11\]~133 " "Info: Destination node system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[11\]~133" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 4079 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[11]~133 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 18710 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[5\]~168 " "Info: Destination node system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[5\]~168" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 4079 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[5]~168 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 18764 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[1\]~203 " "Info: Destination node system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[1\]~203" {  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 4079 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[1]~203 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 18822 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" {  } {  } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "system_0_burst_32.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_burst_32.v" 90 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_burst_32:the_system_0_burst_32|reg_downstream_read } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 3158 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK  " "Info: Automatically promoted node system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "AUD_BCLK " "Info: Destination node AUD_BCLK" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { AUD_BCLK } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 195 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 709 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK~0 " "Info: Destination node system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|oAUD_BCK~0" {  } { { "AUDIO_DAC_FIFO.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/AUDIO_DAC_FIFO.v" 28 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|oAUD_BCK~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 13970 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "AUDIO_DAC_FIFO.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/AUDIO_DAC_FIFO.v" 28 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|oAUD_BCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 11669 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|system_0_reset_altpll_0_c1_out_domain_synch_module:system_0_reset_altpll_0_c1_out_domain_synch\|data_out  " "Info: Automatically promoted node system_0:u0\|system_0_reset_altpll_0_c1_out_domain_synch_module:system_0_reset_altpll_0_c1_out_domain_synch\|data_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|host_ack " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|host_ack" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 233 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|host_ack } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 6638 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[3\] " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[3\]" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 233 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|core_cmd[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 6633 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[2\] " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[2\]" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 233 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|core_cmd[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 6634 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[1\] " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[1\]" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 233 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|core_cmd[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 6635 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[0\] " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_cmd\[0\]" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 233 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|core_cmd[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 6636 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|i2c_master_bit_ctrl:u1\|iscl_oen " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|i2c_master_bit_ctrl:u1\|iscl_oen" {  } { { "altera_avalon_opencores_i2c/i2c_master_bit_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_bit_ctrl.vhd" 443 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|i2c_master_bit_ctrl:u1|iscl_oen } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 6617 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|ld " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|ld" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 150 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|ld } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 6654 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|shift " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|shift" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 150 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|shift } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 6640 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|i2c_master_bit_ctrl:u1\|isda_oen " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|i2c_master_bit_ctrl:u1\|isda_oen" {  } { { "altera_avalon_opencores_i2c/i2c_master_bit_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_bit_ctrl.vhd" 443 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|i2c_master_bit_ctrl:u1|isda_oen } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 6616 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_txd " "Info: Destination node system_0:u0\|i2c_master:the_i2c_master\|opencores_i2c_master:i2c_master\|i2c_master_top:i2c_top_inst\|i2c_master_byte_ctrl:u1\|core_txd" {  } { { "altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/altera_avalon_opencores_i2c/i2c_master_byte_ctrl.vhd" 146 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|i2c_master:the_i2c_master|opencores_i2c_master:i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|core_txd } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 6641 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" {  } {  } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 52444 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "system_0:u0\|system_0_reset_altpll_0_c1_out_domain_synch_module:system_0_reset_altpll_0_c1_out_domain_synch\|data_out" } } } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_altpll_0_c1_out_domain_synch_module:system_0_reset_altpll_0_c1_out_domain_synch|data_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 990 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|clr_reg  " "Info: Automatically promoted node sld_hub:auto_hub\|clr_reg " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|clr_reg~_wirecell " "Info: Destination node sld_hub:auto_hub\|clr_reg~_wirecell" {  } { { "sld_hub.vhd" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/sld_hub.vhd" 311 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|clr_reg~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 26090 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "sld_hub.vhd" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/sld_hub.vhd" 311 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "sld_hub:auto_hub\|clr_reg" } } } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|clr_reg } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 25926 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|system_0_burst_32:the_system_0_burst_32\|reg_downstream_write  " "Info: Automatically promoted node system_0:u0\|system_0_burst_32:the_system_0_burst_32\|reg_downstream_write " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "system_0_burst_32.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0_burst_32.v" 91 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_burst_32:the_system_0_burst_32|reg_downstream_write } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 3159 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out  " "Info: Automatically promoted node system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 52489 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out" } } } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 987 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|dffpipe_ngh:rdaclr\|dffe16a\[0\]  " "Info: Automatically promoted node system_0:u0\|Audio_0:the_Audio_0\|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO\|FIFO_16_256:u0\|dcfifo:dcfifo_component\|dcfifo_hlj1:auto_generated\|dffpipe_ngh:rdaclr\|dffe16a\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "db/dffpipe_ngh.tdf" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/db/dffpipe_ngh.tdf" 32 9 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_hlj1:auto_generated|dffpipe_ngh:rdaclr|dffe16a[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 11491 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state\[0\]  " "Info: Automatically promoted node sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state~0 " "Info: Destination node sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state~0" {  } { { "sld_hub.vhd" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/sld_hub.vhd" 1024 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 26005 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state~1 " "Info: Destination node sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state~1" {  } { { "sld_hub.vhd" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/sld_hub.vhd" 1024 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 26006 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell " "Info: Destination node sld_hub:auto_hub\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell" {  } { { "sld_hub.vhd" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/sld_hub.vhd" 1039 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 26091 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "sld_hub.vhd" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/sld_hub.vhd" 1039 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 25812 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|reset_n_sources~0  " "Info: Automatically promoted node system_0:u0\|reset_n_sources~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "system_0.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/system_0.v" 53213 -1 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { system_0:u0|reset_n_sources~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 13054 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Warning" "WFSAC_FSAC_IGNORED_FAST_REGISTER_IO_ASSIGNMENTS" "" "Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 0 "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "2 EC " "Extra Info: Packed 2 registers into blocks of type EC" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "117 I/O " "Extra Info: Packed 117 registers into blocks of type I/O" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "64 Embedded multiplier block " "Extra Info: Packed 64 registers into blocks of type Embedded multiplier block" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "73 " "Extra Info: Created 73 register duplicates" {  } {  } 1 0 "Created %1!d! register duplicates" 0 0 "" 0 -1}  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "Audio_PLL:PLL2\|altpll:altpll_component\|pll clk\[0\] AUD_XCK " "Warning: PLL \"Audio_PLL:PLL2\|altpll:altpll_component\|pll\" output port clk\[0\] feeds output pin \"AUD_XCK\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "/opt/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 920 3 0 } } { "Audio_PLL.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/Audio_PLL.v" 77 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 236 0 0 } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 196 0 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Warning: Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET_DATA\[0\] " "Warning: Ignored I/O standard assignment to node \"ENET_DATA\[0\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[0\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[0\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[0\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[1\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[1\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[2\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[2\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[3\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[3\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[4\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[4\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[5\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[5\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[6\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[6\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[7\] " "Warning: Ignored I/O standard assignment to node \"TD_DATA\[7\]\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_HS " "Warning: Ignored I/O standard assignment to node \"TD_HS\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_VS " "Warning: Ignored I/O standard assignment to node \"TD_VS\"" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Ignored I/O standard assignments to the following nodes" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CLK " "Warning: Node \"ENET_CLK\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_CLK" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CMD " "Warning: Node \"ENET_CMD\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_CMD" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CS_N " "Warning: Node \"ENET_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_CS_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[0\] " "Warning: Node \"ENET_DATA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[10\] " "Warning: Node \"ENET_DATA\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[10\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[11\] " "Warning: Node \"ENET_DATA\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[11\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[12\] " "Warning: Node \"ENET_DATA\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[12\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[13\] " "Warning: Node \"ENET_DATA\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[13\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[14\] " "Warning: Node \"ENET_DATA\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[14\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[15\] " "Warning: Node \"ENET_DATA\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[15\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[1\] " "Warning: Node \"ENET_DATA\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[2\] " "Warning: Node \"ENET_DATA\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[3\] " "Warning: Node \"ENET_DATA\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[4\] " "Warning: Node \"ENET_DATA\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[5\] " "Warning: Node \"ENET_DATA\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[6\] " "Warning: Node \"ENET_DATA\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[7\] " "Warning: Node \"ENET_DATA\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[8\] " "Warning: Node \"ENET_DATA\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[9\] " "Warning: Node \"ENET_DATA\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_INT " "Warning: Node \"ENET_INT\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_INT" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_RD_N " "Warning: Node \"ENET_RD_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_RD_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_RST_N " "Warning: Node \"ENET_RST_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_RST_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_WR_N " "Warning: Node \"ENET_WR_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ENET_WR_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Warning: Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Warning: Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Warning: Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Warning: Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Warning: Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Warning: Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Warning: Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Warning: Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Warning: Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Warning: Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Warning: Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Warning: Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Warning: Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Warning: Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Warning: Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Warning: Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Warning: Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Warning: Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Warning: Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Warning: Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Warning: Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Warning: Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Warning: Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Warning: Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Warning: Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Warning: Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Warning: Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Warning: Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Warning: Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Warning: Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK0_N " "Warning: Node \"OTG_DACK0_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DACK0_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK1_N " "Warning: Node \"OTG_DACK1_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DACK1_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Warning: Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Warning: Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Warning: Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Warning: Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Warning: Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Warning: Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Warning: Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Warning: Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Warning: Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Warning: Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Warning: Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Warning: Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Warning: Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Warning: Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Warning: Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Warning: Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ0 " "Warning: Node \"OTG_DREQ0\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DREQ0" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ1 " "Warning: Node \"OTG_DREQ1\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_DREQ1" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_FSPEED " "Warning: Node \"OTG_FSPEED\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT0 " "Warning: Node \"OTG_INT0\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_INT0" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT1 " "Warning: Node \"OTG_INT1\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_INT1" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_LSPEED " "Warning: Node \"OTG_LSPEED\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Warning: Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Warning: Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Warning: Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Warning: Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Warning: Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TCK " "Warning: Node \"TCK\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TCK" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TCS " "Warning: Node \"TCS\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TCS" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TDI " "Warning: Node \"TDI\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TDI" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TDO " "Warning: Node \"TDO\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TDO" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Warning: Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Warning: Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Warning: Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Warning: Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Warning: Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Warning: Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Warning: Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Warning: Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Warning: Node \"TD_HS\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET " "Warning: Node \"TD_RESET\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_RESET" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Warning: Node \"TD_VS\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK " "Warning: Node \"VGA_BLANK\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_BLANK" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Warning: Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Warning: Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Warning: Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Warning: Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Warning: Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Warning: Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Warning: Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Warning: Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[8\] " "Warning: Node \"VGA_B\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[9\] " "Warning: Node \"VGA_B\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_B\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Warning: Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Warning: Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Warning: Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Warning: Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Warning: Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Warning: Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Warning: Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Warning: Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Warning: Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[8\] " "Warning: Node \"VGA_G\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[9\] " "Warning: Node \"VGA_G\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_G\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Warning: Node \"VGA_HS\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Warning: Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Warning: Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Warning: Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Warning: Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Warning: Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Warning: Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Warning: Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Warning: Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[8\] " "Warning: Node \"VGA_R\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[9\] " "Warning: Node \"VGA_R\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_R\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC " "Warning: Node \"VGA_SYNC\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_SYNC" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Warning: Node \"VGA_VS\" is assigned to location or region, but does not exist in design" {  } { { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:11 " "Info: Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "13 " "Info: Router estimated average interconnect usage is 13% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "55 X22_Y12 X32_Y23 " "Info: Router estimated peak interconnect usage is 55% of the available device resources in the region that extends from location X22_Y12 to location X32_Y23" {  } {  } 0 0 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Info: Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "265 " "Warning: Found 265 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[0\] 0 " "Info: Pin \"DRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[1\] 0 " "Info: Pin \"DRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[2\] 0 " "Info: Pin \"DRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[3\] 0 " "Info: Pin \"DRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[4\] 0 " "Info: Pin \"DRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[5\] 0 " "Info: Pin \"DRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[6\] 0 " "Info: Pin \"DRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[7\] 0 " "Info: Pin \"DRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[8\] 0 " "Info: Pin \"DRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[9\] 0 " "Info: Pin \"DRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[10\] 0 " "Info: Pin \"DRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[11\] 0 " "Info: Pin \"DRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[12\] 0 " "Info: Pin \"DRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[13\] 0 " "Info: Pin \"DRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[14\] 0 " "Info: Pin \"DRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[15\] 0 " "Info: Pin \"DRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[0\] 0 " "Info: Pin \"FL_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[1\] 0 " "Info: Pin \"FL_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[2\] 0 " "Info: Pin \"FL_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[3\] 0 " "Info: Pin \"FL_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[4\] 0 " "Info: Pin \"FL_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[5\] 0 " "Info: Pin \"FL_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[6\] 0 " "Info: Pin \"FL_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[7\] 0 " "Info: Pin \"FL_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[0\] 0 " "Info: Pin \"SRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[1\] 0 " "Info: Pin \"SRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[2\] 0 " "Info: Pin \"SRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[3\] 0 " "Info: Pin \"SRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[4\] 0 " "Info: Pin \"SRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[5\] 0 " "Info: Pin \"SRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[6\] 0 " "Info: Pin \"SRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[7\] 0 " "Info: Pin \"SRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[8\] 0 " "Info: Pin \"SRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[9\] 0 " "Info: Pin \"SRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[10\] 0 " "Info: Pin \"SRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[11\] 0 " "Info: Pin \"SRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[12\] 0 " "Info: Pin \"SRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[13\] 0 " "Info: Pin \"SRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[14\] 0 " "Info: Pin \"SRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[15\] 0 " "Info: Pin \"SRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[0\] 0 " "Info: Pin \"LCD_DATA\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[1\] 0 " "Info: Pin \"LCD_DATA\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[2\] 0 " "Info: Pin \"LCD_DATA\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[3\] 0 " "Info: Pin \"LCD_DATA\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[4\] 0 " "Info: Pin \"LCD_DATA\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[5\] 0 " "Info: Pin \"LCD_DATA\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[6\] 0 " "Info: Pin \"LCD_DATA\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[7\] 0 " "Info: Pin \"LCD_DATA\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT 0 " "Info: Pin \"SD_DAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT3 0 " "Info: Pin \"SD_DAT3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CMD 0 " "Info: Pin \"SD_CMD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SDAT 0 " "Info: Pin \"I2C_SDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_ADCLRCK 0 " "Info: Pin \"AUD_ADCLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACLRCK 0 " "Info: Pin \"AUD_DACLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_BCLK 0 " "Info: Pin \"AUD_BCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[0\] 0 " "Info: Pin \"GPIO_0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[1\] 0 " "Info: Pin \"GPIO_0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[2\] 0 " "Info: Pin \"GPIO_0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[3\] 0 " "Info: Pin \"GPIO_0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[4\] 0 " "Info: Pin \"GPIO_0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[5\] 0 " "Info: Pin \"GPIO_0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[6\] 0 " "Info: Pin \"GPIO_0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[7\] 0 " "Info: Pin \"GPIO_0\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[8\] 0 " "Info: Pin \"GPIO_0\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[9\] 0 " "Info: Pin \"GPIO_0\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[10\] 0 " "Info: Pin \"GPIO_0\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[11\] 0 " "Info: Pin \"GPIO_0\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[12\] 0 " "Info: Pin \"GPIO_0\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[13\] 0 " "Info: Pin \"GPIO_0\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[14\] 0 " "Info: Pin \"GPIO_0\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[15\] 0 " "Info: Pin \"GPIO_0\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[16\] 0 " "Info: Pin \"GPIO_0\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[17\] 0 " "Info: Pin \"GPIO_0\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[18\] 0 " "Info: Pin \"GPIO_0\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[19\] 0 " "Info: Pin \"GPIO_0\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[20\] 0 " "Info: Pin \"GPIO_0\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[21\] 0 " "Info: Pin \"GPIO_0\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[22\] 0 " "Info: Pin \"GPIO_0\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[23\] 0 " "Info: Pin \"GPIO_0\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[24\] 0 " "Info: Pin \"GPIO_0\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[25\] 0 " "Info: Pin \"GPIO_0\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[26\] 0 " "Info: Pin \"GPIO_0\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[27\] 0 " "Info: Pin \"GPIO_0\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[28\] 0 " "Info: Pin \"GPIO_0\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[29\] 0 " "Info: Pin \"GPIO_0\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[30\] 0 " "Info: Pin \"GPIO_0\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[31\] 0 " "Info: Pin \"GPIO_0\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[32\] 0 " "Info: Pin \"GPIO_0\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[33\] 0 " "Info: Pin \"GPIO_0\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[34\] 0 " "Info: Pin \"GPIO_0\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[35\] 0 " "Info: Pin \"GPIO_0\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[0\] 0 " "Info: Pin \"GPIO_1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[1\] 0 " "Info: Pin \"GPIO_1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[2\] 0 " "Info: Pin \"GPIO_1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[3\] 0 " "Info: Pin \"GPIO_1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[4\] 0 " "Info: Pin \"GPIO_1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[5\] 0 " "Info: Pin \"GPIO_1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[6\] 0 " "Info: Pin \"GPIO_1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[7\] 0 " "Info: Pin \"GPIO_1\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[8\] 0 " "Info: Pin \"GPIO_1\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[9\] 0 " "Info: Pin \"GPIO_1\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[10\] 0 " "Info: Pin \"GPIO_1\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[11\] 0 " "Info: Pin \"GPIO_1\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[12\] 0 " "Info: Pin \"GPIO_1\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[13\] 0 " "Info: Pin \"GPIO_1\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[14\] 0 " "Info: Pin \"GPIO_1\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[15\] 0 " "Info: Pin \"GPIO_1\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[16\] 0 " "Info: Pin \"GPIO_1\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[17\] 0 " "Info: Pin \"GPIO_1\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[18\] 0 " "Info: Pin \"GPIO_1\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[19\] 0 " "Info: Pin \"GPIO_1\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[20\] 0 " "Info: Pin \"GPIO_1\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[21\] 0 " "Info: Pin \"GPIO_1\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[22\] 0 " "Info: Pin \"GPIO_1\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[23\] 0 " "Info: Pin \"GPIO_1\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[24\] 0 " "Info: Pin \"GPIO_1\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[25\] 0 " "Info: Pin \"GPIO_1\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[26\] 0 " "Info: Pin \"GPIO_1\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[27\] 0 " "Info: Pin \"GPIO_1\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[28\] 0 " "Info: Pin \"GPIO_1\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[29\] 0 " "Info: Pin \"GPIO_1\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[30\] 0 " "Info: Pin \"GPIO_1\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[31\] 0 " "Info: Pin \"GPIO_1\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[32\] 0 " "Info: Pin \"GPIO_1\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[33\] 0 " "Info: Pin \"GPIO_1\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[34\] 0 " "Info: Pin \"GPIO_1\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[35\] 0 " "Info: Pin \"GPIO_1\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[0\] 0 " "Info: Pin \"HEX0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[1\] 0 " "Info: Pin \"HEX0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[2\] 0 " "Info: Pin \"HEX0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[3\] 0 " "Info: Pin \"HEX0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[4\] 0 " "Info: Pin \"HEX0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[5\] 0 " "Info: Pin \"HEX0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[6\] 0 " "Info: Pin \"HEX0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[0\] 0 " "Info: Pin \"HEX1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[1\] 0 " "Info: Pin \"HEX1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[2\] 0 " "Info: Pin \"HEX1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[3\] 0 " "Info: Pin \"HEX1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[4\] 0 " "Info: Pin \"HEX1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[5\] 0 " "Info: Pin \"HEX1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[6\] 0 " "Info: Pin \"HEX1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[0\] 0 " "Info: Pin \"HEX2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[1\] 0 " "Info: Pin \"HEX2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[2\] 0 " "Info: Pin \"HEX2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[3\] 0 " "Info: Pin \"HEX2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[4\] 0 " "Info: Pin \"HEX2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[5\] 0 " "Info: Pin \"HEX2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[6\] 0 " "Info: Pin \"HEX2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[0\] 0 " "Info: Pin \"HEX3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[1\] 0 " "Info: Pin \"HEX3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[2\] 0 " "Info: Pin \"HEX3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[3\] 0 " "Info: Pin \"HEX3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[4\] 0 " "Info: Pin \"HEX3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[5\] 0 " "Info: Pin \"HEX3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[6\] 0 " "Info: Pin \"HEX3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[0\] 0 " "Info: Pin \"HEX4\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[1\] 0 " "Info: Pin \"HEX4\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[2\] 0 " "Info: Pin \"HEX4\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[3\] 0 " "Info: Pin \"HEX4\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[4\] 0 " "Info: Pin \"HEX4\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[5\] 0 " "Info: Pin \"HEX4\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[6\] 0 " "Info: Pin \"HEX4\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[0\] 0 " "Info: Pin \"HEX5\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[1\] 0 " "Info: Pin \"HEX5\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[2\] 0 " "Info: Pin \"HEX5\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[3\] 0 " "Info: Pin \"HEX5\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[4\] 0 " "Info: Pin \"HEX5\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[5\] 0 " "Info: Pin \"HEX5\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[6\] 0 " "Info: Pin \"HEX5\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[0\] 0 " "Info: Pin \"HEX6\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[1\] 0 " "Info: Pin \"HEX6\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[2\] 0 " "Info: Pin \"HEX6\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[3\] 0 " "Info: Pin \"HEX6\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[4\] 0 " "Info: Pin \"HEX6\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[5\] 0 " "Info: Pin \"HEX6\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[6\] 0 " "Info: Pin \"HEX6\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[0\] 0 " "Info: Pin \"HEX7\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[1\] 0 " "Info: Pin \"HEX7\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[2\] 0 " "Info: Pin \"HEX7\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[3\] 0 " "Info: Pin \"HEX7\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[4\] 0 " "Info: Pin \"HEX7\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[5\] 0 " "Info: Pin \"HEX7\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[6\] 0 " "Info: Pin \"HEX7\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "UART_TXD 0 " "Info: Pin \"UART_TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IRDA_TXD 0 " "Info: Pin \"IRDA_TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[0\] 0 " "Info: Pin \"DRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[1\] 0 " "Info: Pin \"DRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[2\] 0 " "Info: Pin \"DRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[3\] 0 " "Info: Pin \"DRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[4\] 0 " "Info: Pin \"DRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[5\] 0 " "Info: Pin \"DRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[6\] 0 " "Info: Pin \"DRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[7\] 0 " "Info: Pin \"DRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[8\] 0 " "Info: Pin \"DRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[9\] 0 " "Info: Pin \"DRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[10\] 0 " "Info: Pin \"DRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[11\] 0 " "Info: Pin \"DRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_LDQM 0 " "Info: Pin \"DRAM_LDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_UDQM 0 " "Info: Pin \"DRAM_UDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_WE_N 0 " "Info: Pin \"DRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CAS_N 0 " "Info: Pin \"DRAM_CAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_RAS_N 0 " "Info: Pin \"DRAM_RAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CS_N 0 " "Info: Pin \"DRAM_CS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_0 0 " "Info: Pin \"DRAM_BA_0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_1 0 " "Info: Pin \"DRAM_BA_1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CLK 0 " "Info: Pin \"DRAM_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CKE 0 " "Info: Pin \"DRAM_CKE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[0\] 0 " "Info: Pin \"FL_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[1\] 0 " "Info: Pin \"FL_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[2\] 0 " "Info: Pin \"FL_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[3\] 0 " "Info: Pin \"FL_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[4\] 0 " "Info: Pin \"FL_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[5\] 0 " "Info: Pin \"FL_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[6\] 0 " "Info: Pin \"FL_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[7\] 0 " "Info: Pin \"FL_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[8\] 0 " "Info: Pin \"FL_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[9\] 0 " "Info: Pin \"FL_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[10\] 0 " "Info: Pin \"FL_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[11\] 0 " "Info: Pin \"FL_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[12\] 0 " "Info: Pin \"FL_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[13\] 0 " "Info: Pin \"FL_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[14\] 0 " "Info: Pin \"FL_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[15\] 0 " "Info: Pin \"FL_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[16\] 0 " "Info: Pin \"FL_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[17\] 0 " "Info: Pin \"FL_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[18\] 0 " "Info: Pin \"FL_ADDR\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[19\] 0 " "Info: Pin \"FL_ADDR\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[20\] 0 " "Info: Pin \"FL_ADDR\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[21\] 0 " "Info: Pin \"FL_ADDR\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_WE_N 0 " "Info: Pin \"FL_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_RST_N 0 " "Info: Pin \"FL_RST_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_OE_N 0 " "Info: Pin \"FL_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_CE_N 0 " "Info: Pin \"FL_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[0\] 0 " "Info: Pin \"SRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[1\] 0 " "Info: Pin \"SRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[2\] 0 " "Info: Pin \"SRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[3\] 0 " "Info: Pin \"SRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[4\] 0 " "Info: Pin \"SRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[5\] 0 " "Info: Pin \"SRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[6\] 0 " "Info: Pin \"SRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[7\] 0 " "Info: Pin \"SRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[8\] 0 " "Info: Pin \"SRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[9\] 0 " "Info: Pin \"SRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[10\] 0 " "Info: Pin \"SRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[11\] 0 " "Info: Pin \"SRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[12\] 0 " "Info: Pin \"SRAM_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[13\] 0 " "Info: Pin \"SRAM_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[14\] 0 " "Info: Pin \"SRAM_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[15\] 0 " "Info: Pin \"SRAM_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[16\] 0 " "Info: Pin \"SRAM_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[17\] 0 " "Info: Pin \"SRAM_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_UB_N 0 " "Info: Pin \"SRAM_UB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_LB_N 0 " "Info: Pin \"SRAM_LB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_WE_N 0 " "Info: Pin \"SRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_CE_N 0 " "Info: Pin \"SRAM_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_OE_N 0 " "Info: Pin \"SRAM_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_ON 0 " "Info: Pin \"LCD_ON\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_BLON 0 " "Info: Pin \"LCD_BLON\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_RW 0 " "Info: Pin \"LCD_RW\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_EN 0 " "Info: Pin \"LCD_EN\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_RS 0 " "Info: Pin \"LCD_RS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CLK 0 " "Info: Pin \"SD_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SCLK 0 " "Info: Pin \"I2C_SCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACDAT 0 " "Info: Pin \"AUD_DACDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_XCK 0 " "Info: Pin \"AUD_XCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 0 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "75 " "Warning: Following 75 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SD_DAT3 a permanently enabled " "Info: Pin SD_DAT3 has a permanently enabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { SD_DAT3 } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SD_DAT3" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 184 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 701 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_ADCLRCK a permanently enabled " "Info: Pin AUD_ADCLRCK has a permanently enabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { AUD_ADCLRCK } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 191 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 668 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_DACLRCK a permanently enabled " "Info: Pin AUD_DACLRCK has a permanently enabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { AUD_DACLRCK } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 193 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 707 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_BCLK a permanently enabled " "Info: Pin AUD_BCLK has a permanently enabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { AUD_BCLK } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 195 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 709 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[0\] a permanently disabled " "Info: Pin GPIO_0\[0\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[0] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 454 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[1\] a permanently disabled " "Info: Pin GPIO_0\[1\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[1] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 455 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[2\] a permanently disabled " "Info: Pin GPIO_0\[2\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[2] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 456 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[3\] a permanently disabled " "Info: Pin GPIO_0\[3\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[3] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 457 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[4\] a permanently disabled " "Info: Pin GPIO_0\[4\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[4] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 458 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[5\] a permanently disabled " "Info: Pin GPIO_0\[5\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[5] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 459 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[6\] a permanently disabled " "Info: Pin GPIO_0\[6\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[6] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 460 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[7\] a permanently disabled " "Info: Pin GPIO_0\[7\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[7] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 461 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[8\] a permanently disabled " "Info: Pin GPIO_0\[8\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[8] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 462 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[9\] a permanently disabled " "Info: Pin GPIO_0\[9\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[9] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 463 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[10\] a permanently disabled " "Info: Pin GPIO_0\[10\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[10] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 464 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[12\] a permanently disabled " "Info: Pin GPIO_0\[12\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[12] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 466 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[13\] a permanently enabled " "Info: Pin GPIO_0\[13\] has a permanently enabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[13] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 467 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[14\] a permanently disabled " "Info: Pin GPIO_0\[14\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[14] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 468 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[15\] a permanently disabled " "Info: Pin GPIO_0\[15\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[15] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 469 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[16\] a permanently disabled " "Info: Pin GPIO_0\[16\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[16] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 470 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[17\] a permanently disabled " "Info: Pin GPIO_0\[17\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[17] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 471 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[18\] a permanently disabled " "Info: Pin GPIO_0\[18\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[18] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 472 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[19\] a permanently disabled " "Info: Pin GPIO_0\[19\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[19] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 473 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[20\] a permanently disabled " "Info: Pin GPIO_0\[20\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[20] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 474 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[21\] a permanently disabled " "Info: Pin GPIO_0\[21\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[21] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 475 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[22\] a permanently disabled " "Info: Pin GPIO_0\[22\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[22] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 476 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[23\] a permanently disabled " "Info: Pin GPIO_0\[23\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[23] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 477 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[24\] a permanently disabled " "Info: Pin GPIO_0\[24\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[24] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 478 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[25\] a permanently disabled " "Info: Pin GPIO_0\[25\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[25] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 479 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[26\] a permanently disabled " "Info: Pin GPIO_0\[26\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[26] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 480 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[27\] a permanently disabled " "Info: Pin GPIO_0\[27\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[27] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 481 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[28\] a permanently disabled " "Info: Pin GPIO_0\[28\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[28] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 482 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[29\] a permanently disabled " "Info: Pin GPIO_0\[29\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[29] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 483 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[30\] a permanently disabled " "Info: Pin GPIO_0\[30\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[30] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 484 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[31\] a permanently disabled " "Info: Pin GPIO_0\[31\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[31] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 485 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[32\] a permanently disabled " "Info: Pin GPIO_0\[32\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[32] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 486 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[33\] a permanently disabled " "Info: Pin GPIO_0\[33\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[33] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 487 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[34\] a permanently disabled " "Info: Pin GPIO_0\[34\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[34] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 488 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[35\] a permanently disabled " "Info: Pin GPIO_0\[35\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_0[35] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 198 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 489 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Info: Pin GPIO_1\[0\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 418 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Info: Pin GPIO_1\[1\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 419 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Info: Pin GPIO_1\[2\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[2] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 420 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Info: Pin GPIO_1\[3\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[3] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 421 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Info: Pin GPIO_1\[4\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[4] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 422 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Info: Pin GPIO_1\[5\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[5] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 423 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Info: Pin GPIO_1\[6\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[6] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 424 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Info: Pin GPIO_1\[7\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[7] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 425 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Info: Pin GPIO_1\[8\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[8] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 426 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Info: Pin GPIO_1\[9\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[9] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 427 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Info: Pin GPIO_1\[10\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[10] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 428 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Info: Pin GPIO_1\[11\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[11] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 429 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Info: Pin GPIO_1\[12\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[12] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 430 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Info: Pin GPIO_1\[13\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[13] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 431 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Info: Pin GPIO_1\[14\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[14] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 432 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Info: Pin GPIO_1\[15\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[15] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 433 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Info: Pin GPIO_1\[16\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[16] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 434 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Info: Pin GPIO_1\[17\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[17] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 435 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Info: Pin GPIO_1\[18\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[18] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 436 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Info: Pin GPIO_1\[19\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[19] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 437 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Info: Pin GPIO_1\[20\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[20] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 438 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Info: Pin GPIO_1\[21\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[21] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 439 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Info: Pin GPIO_1\[22\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[22] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 440 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Info: Pin GPIO_1\[23\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[23] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 441 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Info: Pin GPIO_1\[24\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[24] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 442 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Info: Pin GPIO_1\[25\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[25] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 443 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Info: Pin GPIO_1\[26\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[26] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 444 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Info: Pin GPIO_1\[27\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[27] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 445 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Info: Pin GPIO_1\[28\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[28] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 446 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Info: Pin GPIO_1\[29\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[29] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 447 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Info: Pin GPIO_1\[30\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[30] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 448 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Info: Pin GPIO_1\[31\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[31] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 449 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Info: Pin GPIO_1\[32\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[32] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 450 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently disabled " "Info: Pin GPIO_1\[33\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[33] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 451 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[34\] a permanently disabled " "Info: Pin GPIO_1\[34\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[34] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 452 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[35\] a permanently disabled " "Info: Pin GPIO_1\[35\] has a permanently disabled output enable" {  } { { "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/altera/10.1sp1/quartus/linux/pin_planner.ppl" { GPIO_1[35] } } } { "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/altera/10.1sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } { "DE2_SD_Card_Audio.v" "" { Text "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.v" 199 0 0 } } { "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/altera/10.1sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/" { { 0 { 0 ""} 0 453 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1}  } {  } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.fit.smsg " "Info: Generated suppressed messages file /afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial/DE2_SD_Card_Audio.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 194 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 194 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "411 " "Info: Peak virtual memory: 411 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 12 14:17:20 2013 " "Info: Processing ended: Fri Apr 12 14:17:20 2013" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:42 " "Info: Elapsed time: 00:00:42" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:38 " "Info: Total CPU time (on all processors): 00:00:38" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
