<?xml version="1.0" encoding="UTF-8"?>
<system name="system_0">
 <parameter name="bonusData"><![CDATA[bonusData 
{
   element Accel_Control
   {
      datum _sortIndex
      {
         value = "29";
         type = "int";
      }
   }
   element Audio_0
   {
      datum _sortIndex
      {
         value = "13";
         type = "int";
      }
   }
   element MS
   {
      datum _sortIndex
      {
         value = "24";
         type = "int";
      }
   }
   element Oct_DOWN
   {
      datum _sortIndex
      {
         value = "28";
         type = "int";
      }
   }
   element Oct_UP
   {
      datum _sortIndex
      {
         value = "27";
         type = "int";
      }
   }
   element RST
   {
      datum _sortIndex
      {
         value = "26";
         type = "int";
      }
   }
   element SD_CLK
   {
      datum _sortIndex
      {
         value = "16";
         type = "int";
      }
   }
   element SD_CMD
   {
      datum _sortIndex
      {
         value = "15";
         type = "int";
      }
   }
   element SD_DAT
   {
      datum _sortIndex
      {
         value = "14";
         type = "int";
      }
   }
   element SEG7_Display
   {
      datum _sortIndex
      {
         value = "11";
         type = "int";
      }
   }
   element altpll_0
   {
      datum _sortIndex
      {
         value = "31";
         type = "int";
      }
   }
   element jtag_uart_0.avalon_jtag_slave
   {
      datum baseAddress
      {
         value = "26255824";
         type = "long";
      }
   }
   element Accel_Control.avalon_slave
   {
      datum baseAddress
      {
         value = "26255488";
         type = "long";
      }
   }
   element sram_0.avalon_slave_0
   {
      datum baseAddress
      {
         value = "25690112";
         type = "long";
      }
   }
   element SEG7_Display.avalon_slave_0
   {
      datum baseAddress
      {
         value = "26255832";
         type = "long";
      }
   }
   element i2c_master.avalon_slave_0
   {
      datum baseAddress
      {
         value = "26255520";
         type = "long";
      }
   }
   element Audio_0.avalon_slave_0
   {
      datum baseAddress
      {
         value = "26255836";
         type = "long";
      }
   }
   element cfi_flash_0
   {
      datum _sortIndex
      {
         value = "3";
         type = "int";
      }
   }
   element clk.clk
   {
      datum clock_domain
      {
         value = "clk";
         type = "String";
      }
   }
   element clk
   {
      datum _sortIndex
      {
         value = "0";
         type = "int";
      }
   }
   element lcd_16207_0.control_slave
   {
      datum baseAddress
      {
         value = "26255552";
         type = "long";
      }
   }
   element cpu_0
   {
      datum _sortIndex
      {
         value = "1";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{output_language=VERILOG, output_directory=/afs/ualberta.ca/home/q/i/qingyue/ece492/backup/allgood/capstone_accel_trial}";
         type = "String";
      }
   }
   element dist_sensor
   {
      datum _sortIndex
      {
         value = "25";
         type = "int";
      }
   }
   element epcs_controller.epcs_control_port
   {
      datum baseAddress
      {
         value = "26253312";
         type = "long";
      }
   }
   element epcs_controller
   {
      datum _sortIndex
      {
         value = "5";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{output_language=VERILOG, output_directory=/afs/ualberta.ca/home/e/j/ejong/ece492/DE2_SD_Card_Audio}";
         type = "String";
      }
   }
   element i2c_master
   {
      datum _sortIndex
      {
         value = "30";
         type = "int";
      }
   }
   element cpu_0.jtag_debug_module
   {
      datum baseAddress
      {
         value = "26251264";
         type = "long";
      }
   }
   element jtag_uart_0
   {
      datum _sortIndex
      {
         value = "6";
         type = "int";
      }
   }
   element lcd_16207_0
   {
      datum _sortIndex
      {
         value = "10";
         type = "int";
      }
   }
   element noteA
   {
      datum _sortIndex
      {
         value = "17";
         type = "int";
      }
   }
   element noteB
   {
      datum _sortIndex
      {
         value = "18";
         type = "int";
      }
   }
   element noteC
   {
      datum _sortIndex
      {
         value = "19";
         type = "int";
      }
   }
   element noteD
   {
      datum _sortIndex
      {
         value = "20";
         type = "int";
      }
   }
   element noteE
   {
      datum _sortIndex
      {
         value = "21";
         type = "int";
      }
   }
   element noteF
   {
      datum _sortIndex
      {
         value = "22";
         type = "int";
      }
   }
   element noteG
   {
      datum _sortIndex
      {
         value = "23";
         type = "int";
      }
   }
   element altpll_0.pll_slave
   {
      datum baseAddress
      {
         value = "26255808";
         type = "long";
      }
   }
   element cfi_flash_0.s1
   {
      datum baseAddress
      {
         value = "20971520";
         type = "long";
      }
   }
   element noteD.s1
   {
      datum baseAddress
      {
         value = "26255664";
         type = "long";
      }
   }
   element noteE.s1
   {
      datum baseAddress
      {
         value = "26255680";
         type = "long";
      }
   }
   element noteG.s1
   {
      datum baseAddress
      {
         value = "26255712";
         type = "long";
      }
   }
   element noteC.s1
   {
      datum baseAddress
      {
         value = "26255648";
         type = "long";
      }
   }
   element sdram_0.s1
   {
      datum baseAddress
      {
         value = "8388608";
         type = "long";
      }
   }
   element SD_CMD.s1
   {
      datum baseAddress
      {
         value = "26255584";
         type = "long";
      }
   }
   element uart_0.s1
   {
      datum baseAddress
      {
         value = "26255392";
         type = "long";
      }
   }
   element timer_0.s1
   {
      datum baseAddress
      {
         value = "26255424";
         type = "long";
      }
   }
   element RST.s1
   {
      datum baseAddress
      {
         value = "26255760";
         type = "long";
      }
   }
   element timer_1.s1
   {
      datum baseAddress
      {
         value = "26255456";
         type = "long";
      }
   }
   element noteF.s1
   {
      datum baseAddress
      {
         value = "26255696";
         type = "long";
      }
   }
   element Oct_DOWN.s1
   {
      datum baseAddress
      {
         value = "26255792";
         type = "long";
      }
   }
   element noteA.s1
   {
      datum baseAddress
      {
         value = "26255616";
         type = "long";
      }
   }
   element dist_sensor.s1
   {
      datum baseAddress
      {
         value = "26255744";
         type = "long";
      }
   }
   element MS.s1
   {
      datum baseAddress
      {
         value = "26255728";
         type = "long";
      }
   }
   element Oct_UP.s1
   {
      datum baseAddress
      {
         value = "26255776";
         type = "long";
      }
   }
   element noteB.s1
   {
      datum baseAddress
      {
         value = "26255632";
         type = "long";
      }
   }
   element SD_CLK.s1
   {
      datum baseAddress
      {
         value = "26255600";
         type = "long";
      }
   }
   element SD_DAT.s1
   {
      datum baseAddress
      {
         value = "26255568";
         type = "long";
      }
   }
   element sdram_0
   {
      datum _sortIndex
      {
         value = "4";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{}";
         type = "String";
      }
   }
   element sram_0
   {
      datum _sortIndex
      {
         value = "12";
         type = "int";
      }
   }
   element system_0
   {
   }
   element timer_0
   {
      datum _sortIndex
      {
         value = "8";
         type = "int";
      }
   }
   element timer_1
   {
      datum _sortIndex
      {
         value = "9";
         type = "int";
      }
   }
   element tri_state_bridge_0
   {
      datum _sortIndex
      {
         value = "2";
         type = "int";
      }
   }
   element uart_0
   {
      datum _sortIndex
      {
         value = "7";
         type = "int";
      }
   }
}
]]></parameter>
 <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
 <parameter name="deviceFamily" value="CYCLONEII" />
 <parameter name="fabricMode" value="SOPC" />
 <parameter name="generateLegacySim" value="false" />
 <parameter name="generationId" value="0" />
 <parameter name="globalResetBus" value="true" />
 <parameter name="hdlLanguage" value="VERILOG" />
 <parameter name="maxAdditionalLatency" value="0" />
 <parameter name="projectName">DE2_SD_Card_Audio.qpf</parameter>
 <parameter name="sopcBorderPoints" value="true" />
 <parameter name="systemHash" value="27103120008" />
 <parameter name="timeStamp" value="1365797471861" />
 <module kind="clock_source" version="10.1" enabled="1" name="clk">
  <parameter name="clockFrequency" value="50000000" />
  <parameter name="clockFrequencyKnown" value="true" />
  <parameter name="inputClockFrequency" value="0" />
  <parameter name="resetSynchronousEdges" value="NONE" />
 </module>
 <module kind="altera_nios2" version="10.1" enabled="1" name="cpu_0">
  <parameter name="userDefinedSettings" value="" />
  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
  <parameter name="setting_showUnpublishedSettings" value="false" />
  <parameter name="setting_showInternalSettings" value="false" />
  <parameter name="setting_shadowRegisterSets" value="0" />
  <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
  <parameter name="setting_preciseDivisionErrorException" value="false" />
  <parameter name="setting_performanceCounter" value="false" />
  <parameter name="setting_perfCounterWidth" value="_32" />
  <parameter name="setting_interruptControllerType" value="Internal" />
  <parameter name="setting_illegalMemAccessDetection" value="false" />
  <parameter name="setting_illegalInstructionsTrap" value="false" />
  <parameter name="setting_fullWaveformSignals" value="false" />
  <parameter name="setting_extraExceptionInfo" value="false" />
  <parameter name="setting_exportPCB" value="false" />
  <parameter name="setting_debugSimGen" value="false" />
  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
  <parameter name="setting_branchPredictionType" value="Dynamic" />
  <parameter name="setting_bit31BypassDCache" value="true" />
  <parameter name="setting_bigEndian" value="false" />
  <parameter name="setting_bhtPtrSz" value="_8" />
  <parameter name="setting_bhtIndexPcOnly" value="false" />
  <parameter name="setting_avalonDebugPortPresent" value="false" />
  <parameter name="setting_alwaysEncrypt" value="true" />
  <parameter name="setting_allowFullAddressRange" value="false" />
  <parameter name="setting_activateTrace" value="true" />
  <parameter name="setting_activateTestEndChecker" value="false" />
  <parameter name="setting_activateMonitors" value="true" />
  <parameter name="setting_activateModelChecker" value="false" />
  <parameter name="setting_HDLSimCachesCleared" value="true" />
  <parameter name="setting_HBreakTest" value="false" />
  <parameter name="resetSlave" value="cfi_flash_0.s1" />
  <parameter name="resetOffset" value="0" />
  <parameter name="muldiv_multiplierType" value="EmbeddedMulFast" />
  <parameter name="muldiv_divider" value="false" />
  <parameter name="mpu_useLimit" value="false" />
  <parameter name="mpu_numOfInstRegion" value="8" />
  <parameter name="mpu_numOfDataRegion" value="8" />
  <parameter name="mpu_minInstRegionSize" value="_12" />
  <parameter name="mpu_minDataRegionSize" value="_12" />
  <parameter name="mpu_enabled" value="false" />
  <parameter name="mmu_uitlbNumEntries" value="_4" />
  <parameter name="mmu_udtlbNumEntries" value="_6" />
  <parameter name="mmu_tlbPtrSz" value="_7" />
  <parameter name="mmu_tlbNumWays" value="_16" />
  <parameter name="mmu_processIDNumBits" value="_10" />
  <parameter name="mmu_enabled" value="false" />
  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
  <parameter name="mmu_TLBMissExcSlave" value="" />
  <parameter name="mmu_TLBMissExcOffset" value="0" />
  <parameter name="manuallyAssignCpuID" value="false" />
  <parameter name="internalIrqMaskSystemInfo" value="2047" />
  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sdram_0.s1' start='0x800000' end='0x1000000' /><slave name='cfi_flash_0.s1' start='0x1400000' end='0x1800000' /><slave name='sram_0.avalon_slave_0' start='0x1880000' end='0x1900000' /><slave name='cpu_0.jtag_debug_module' start='0x1909000' end='0x1909800' /><slave name='epcs_controller.epcs_control_port' start='0x1909800' end='0x190A000' /><slave name='i2c_master.avalon_slave_0' start='0x190A0A0' end='0x190A0C0' /></address-map>]]></parameter>
  <parameter name="instAddrWidth" value="25" />
  <parameter name="impl" value="Fast" />
  <parameter name="icache_size" value="_8192" />
  <parameter name="icache_ramBlockType" value="Automatic" />
  <parameter name="icache_numTCIM" value="_0" />
  <parameter name="icache_burstType" value="Sequential" />
  <parameter name="exceptionSlave" value="sdram_0.s1" />
  <parameter name="exceptionOffset" value="32" />
  <parameter name="deviceFeaturesSystemInfo">M512_MEMORY 0 M4K_MEMORY 1 M9K_MEMORY 0 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0</parameter>
  <parameter name="deviceFamilyName" value="Cyclone II" />
  <parameter name="debug_triggerArming" value="true" />
  <parameter name="debug_level" value="Level1" />
  <parameter name="debug_jtagInstanceID" value="0" />
  <parameter name="debug_embeddedPLL" value="true" />
  <parameter name="debug_debugReqSignals" value="false" />
  <parameter name="debug_assignJtagInstanceID" value="false" />
  <parameter name="debug_OCIOnchipTrace" value="_128" />
  <parameter name="dcache_size" value="_8192" />
  <parameter name="dcache_ramBlockType" value="Automatic" />
  <parameter name="dcache_omitDataMaster" value="false" />
  <parameter name="dcache_numTCDM" value="_0" />
  <parameter name="dcache_lineSize" value="_32" />
  <parameter name="dcache_bursts" value="true" />
  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sdram_0.s1' start='0x800000' end='0x1000000' /><slave name='cfi_flash_0.s1' start='0x1400000' end='0x1800000' /><slave name='sram_0.avalon_slave_0' start='0x1880000' end='0x1900000' /><slave name='cpu_0.jtag_debug_module' start='0x1909000' end='0x1909800' /><slave name='epcs_controller.epcs_control_port' start='0x1909800' end='0x190A000' /><slave name='uart_0.s1' start='0x190A020' end='0x190A040' /><slave name='timer_0.s1' start='0x190A040' end='0x190A060' /><slave name='timer_1.s1' start='0x190A060' end='0x190A080' /><slave name='Accel_Control.avalon_slave' start='0x190A080' end='0x190A0A0' /><slave name='i2c_master.avalon_slave_0' start='0x190A0A0' end='0x190A0C0' /><slave name='lcd_16207_0.control_slave' start='0x190A0C0' end='0x190A0D0' /><slave name='SD_DAT.s1' start='0x190A0D0' end='0x190A0E0' /><slave name='SD_CMD.s1' start='0x190A0E0' end='0x190A0F0' /><slave name='SD_CLK.s1' start='0x190A0F0' end='0x190A100' /><slave name='noteA.s1' start='0x190A100' end='0x190A110' /><slave name='noteB.s1' start='0x190A110' end='0x190A120' /><slave name='noteC.s1' start='0x190A120' end='0x190A130' /><slave name='noteD.s1' start='0x190A130' end='0x190A140' /><slave name='noteE.s1' start='0x190A140' end='0x190A150' /><slave name='noteF.s1' start='0x190A150' end='0x190A160' /><slave name='noteG.s1' start='0x190A160' end='0x190A170' /><slave name='MS.s1' start='0x190A170' end='0x190A180' /><slave name='dist_sensor.s1' start='0x190A180' end='0x190A190' /><slave name='RST.s1' start='0x190A190' end='0x190A1A0' /><slave name='Oct_UP.s1' start='0x190A1A0' end='0x190A1B0' /><slave name='Oct_DOWN.s1' start='0x190A1B0' end='0x190A1C0' /><slave name='altpll_0.pll_slave' start='0x190A1C0' end='0x190A1D0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x190A1D0' end='0x190A1D8' /><slave name='SEG7_Display.avalon_slave_0' start='0x190A1D8' end='0x190A1DC' /><slave name='Audio_0.avalon_slave_0' start='0x190A1DC' end='0x190A1E0' /></address-map>]]></parameter>
  <parameter name="dataAddrWidth" value="25" />
  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
  <parameter name="cpuReset" value="false" />
  <parameter name="cpuID" value="0" />
  <parameter name="clockFrequency" value="100000000" />
  <parameter name="breakSlave">cpu_0.jtag_debug_module</parameter>
  <parameter name="breakOffset" value="32" />
 </module>
 <module
   kind="altera_avalon_tri_state_bridge"
   version="10.1"
   enabled="1"
   name="tri_state_bridge_0">
  <parameter name="registerIncomingSignals" value="true" />
 </module>
 <module
   kind="altera_avalon_cfi_flash"
   version="10.1"
   enabled="1"
   name="cfi_flash_0">
  <parameter name="addressWidth" value="22" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="corePreset" value="CUSTOM" />
  <parameter name="dataWidth" value="8" />
  <parameter name="holdTime" value="40" />
  <parameter name="setupTime" value="40" />
  <parameter name="sharedPorts">s1/data,s1/address,s1/read_n</parameter>
  <parameter name="timingUnits" value="NS" />
  <parameter name="waitTime" value="160" />
 </module>
 <module
   kind="altera_avalon_new_sdram_controller"
   version="10.1"
   enabled="1"
   name="sdram_0">
  <parameter name="TAC" value="5.5" />
  <parameter name="TMRD" value="3" />
  <parameter name="TRCD" value="20.0" />
  <parameter name="TRFC" value="70.0" />
  <parameter name="TRP" value="20.0" />
  <parameter name="TWR" value="14.0" />
  <parameter name="casLatency" value="3" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="columnWidth" value="8" />
  <parameter name="dataWidth" value="16" />
  <parameter name="generateSimulationModel" value="true" />
  <parameter name="initNOPDelay" value="0.0" />
  <parameter name="initRefreshCommands" value="2" />
  <parameter name="masteredTristateBridgeSlave" value="" />
  <parameter name="model" value="custom" />
  <parameter name="numberOfBanks" value="4" />
  <parameter name="numberOfChipSelects" value="1" />
  <parameter name="pinsSharedViaTriState" value="false" />
  <parameter name="powerUpDelay" value="100.0" />
  <parameter name="refreshPeriod" value="15.625" />
  <parameter name="registerDataIn" value="true" />
  <parameter name="rowWidth" value="12" />
 </module>
 <module
   kind="altera_avalon_epcs_flash_controller"
   version="10.1"
   enabled="1"
   name="epcs_controller">
  <parameter name="autoSelectASMIAtom" value="true" />
  <parameter name="deviceFamilyString" value="Cyclone II" />
  <parameter name="useASMIAtom" value="true" />
 </module>
 <module
   kind="altera_avalon_jtag_uart"
   version="10.1"
   enabled="1"
   name="jtag_uart_0">
  <parameter name="allowMultipleConnections" value="false" />
  <parameter name="hubInstanceID" value="0" />
  <parameter name="readBufferDepth" value="64" />
  <parameter name="readIRQThreshold" value="8" />
  <parameter name="simInputCharacterStream" value="" />
  <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
  <parameter name="useRegistersForReadBuffer" value="false" />
  <parameter name="useRegistersForWriteBuffer" value="false" />
  <parameter name="useRelativePathForSimFile" value="false" />
  <parameter name="writeBufferDepth" value="64" />
  <parameter name="writeIRQThreshold" value="8" />
 </module>
 <module kind="altera_avalon_uart" version="10.1" enabled="1" name="uart_0">
  <parameter name="baud" value="115200" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="dataBits" value="8" />
  <parameter name="fixedBaud" value="true" />
  <parameter name="parity" value="NONE" />
  <parameter name="simCharStream" value="" />
  <parameter name="simInteractiveInputEnable" value="false" />
  <parameter name="simInteractiveOutputEnable" value="false" />
  <parameter name="simTrueBaud" value="false" />
  <parameter name="stopBits" value="1" />
  <parameter name="syncRegDepth" value="2" />
  <parameter name="useCtsRts" value="false" />
  <parameter name="useEopRegister" value="false" />
  <parameter name="useRelativePathForSimFile" value="false" />
 </module>
 <module kind="altera_avalon_timer" version="10.1" enabled="1" name="timer_0">
  <parameter name="alwaysRun" value="false" />
  <parameter name="counterSize" value="32" />
  <parameter name="fixedPeriod" value="false" />
  <parameter name="period" value="1" />
  <parameter name="periodUnits" value="MSEC" />
  <parameter name="resetOutput" value="false" />
  <parameter name="snapshot" value="true" />
  <parameter name="systemFrequency" value="100000000" />
  <parameter name="timeoutPulseOutput" value="false" />
  <parameter name="timerPreset" value="CUSTOM" />
 </module>
 <module kind="altera_avalon_timer" version="10.1" enabled="1" name="timer_1">
  <parameter name="alwaysRun" value="false" />
  <parameter name="counterSize" value="32" />
  <parameter name="fixedPeriod" value="false" />
  <parameter name="period" value="1" />
  <parameter name="periodUnits" value="MSEC" />
  <parameter name="resetOutput" value="false" />
  <parameter name="snapshot" value="true" />
  <parameter name="systemFrequency" value="100000000" />
  <parameter name="timeoutPulseOutput" value="false" />
  <parameter name="timerPreset" value="CUSTOM" />
 </module>
 <module
   kind="altera_avalon_lcd_16207"
   version="10.1"
   enabled="1"
   name="lcd_16207_0" />
 <module kind="seg7_lut_8" version="1.0" enabled="1" name="SEG7_Display">
  <parameter name="instancePTF"><![CDATA[MODULE SEG7_Display
{
   class = "seg7_lut_8";
   class_version = "1.0";
   SYSTEM_BUILDER_INFO 
   {
      Instantiate_In_System_Module = "1";
      Has_Clock = "1";
      Top_Level_Ports_Are_Enumerated = "1";
      Is_Enabled = "1";
      Clock_Source = "clk";
      View 
      {
         MESSAGES 
         {
         }
         Is_Collapsed = "1";
      }
   }
   COMPONENT_BUILDER 
   {
      GLS_SETTINGS 
      {
      }
   }
   PORT_WIRING 
   {
      PORT iCLK
      {
         width = "1";
         width_expression = "";
         direction = "input";
         type = "clk";
         is_shared = "0";
         vhdl_record_name = "";
         vhdl_record_type = "";
      }
   }
   WIZARD_SCRIPT_ARGUMENTS 
   {
      hdl_parameters 
      {
      }
   }
   SIMULATION 
   {
      DISPLAY 
      {
      }
   }
   SLAVE avalon_slave_0
   {
      SYSTEM_BUILDER_INFO 
      {
         Bus_Type = "avalon";
         Address_Group = "1";
         Has_Clock = "0";
         Address_Width = "0";
         Address_Alignment = "native";
         Data_Width = "32";
         Has_Base_Address = "1";
         Has_IRQ = "0";
         Setup_Time = "0cycles";
         Hold_Time = "0cycles";
         Read_Wait_States = "1cycles";
         Write_Wait_States = "1cycles";
         Read_Latency = "0";
         Maximum_Pending_Read_Transactions = "0";
         Active_CS_Through_Read_Latency = "0";
         Is_Printable_Device = "0";
         Is_Memory_Device = "0";
         Is_Readable = "0";
         Is_Writable = "1";
         Minimum_Uninterrupted_Run_Length = "1";
         MASTERED_BY cpu_0/data_master
         {
            priority = "1";
         }
         Base_Address = "0x00681100";
         IRQ_MASTER cpu_0/data_master
         {
            IRQ_Number = "NC";
         }
      }
      COMPONENT_BUILDER 
      {
         AVS_SETTINGS 
         {
            Setup_Value = "0";
            Read_Wait_Value = "1";
            Write_Wait_Value = "1";
            Hold_Value = "0";
            Timing_Units = "cycles";
            Read_Latency_Value = "0";
            Minimum_Arbitration_Shares = "1";
            Active_CS_Through_Read_Latency = "0";
            Max_Pending_Read_Transactions_Value = "1";
            Address_Alignment = "native";
            Is_Printable_Device = "0";
            Interleave_Bursts = "0";
            interface_name = "Avalon Slave";
            external_wait = "0";
            Is_Memory_Device = "0";
         }
      }
      PORT_WIRING 
      {
         PORT iDIG
         {
            width = "32";
            width_expression = "";
            direction = "input";
            type = "writedata";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT iWR
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "write";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT iRST_N
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "reset_n";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT oSEG0
         {
            width = "7";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT oSEG1
         {
            width = "7";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT oSEG2
         {
            width = "7";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT oSEG3
         {
            width = "7";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT oSEG4
         {
            width = "7";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT oSEG5
         {
            width = "7";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT oSEG6
         {
            width = "7";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT oSEG7
         {
            width = "7";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
      }
   }
   HDL_INFO 
   {
      Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/SEG7_LUT.v,__PROJECT_DIRECTORY__/SEG7_LUT_8.v, __PROJECT_DIRECTORY__/SEG7_Display.v";
   }
}
]]></parameter>
 </module>
 <module kind="sram_16bit_512k" version="1.0" enabled="1" name="sram_0">
  <parameter name="instancePTF"><![CDATA[MODULE sram_0
{
   class = "sram_16bit_512k";
   class_version = "1.0";
   SYSTEM_BUILDER_INFO 
   {
      Instantiate_In_System_Module = "1";
      Has_Clock = "1";
      Top_Level_Ports_Are_Enumerated = "1";
      Is_Enabled = "1";
      Clock_Source = "clk";
      View 
      {
         MESSAGES 
         {
         }
         Is_Collapsed = "1";
      }
   }
   COMPONENT_BUILDER 
   {
      GLS_SETTINGS 
      {
      }
   }
   PORT_WIRING 
   {
      PORT iCLK
      {
         width = "1";
         width_expression = "";
         direction = "input";
         type = "clk";
         is_shared = "0";
         vhdl_record_name = "";
         vhdl_record_type = "";
      }
   }
   WIZARD_SCRIPT_ARGUMENTS 
   {
      hdl_parameters 
      {
      }
   }
   SIMULATION 
   {
      DISPLAY 
      {
      }
   }
   SLAVE avalon_slave_0
   {
      SYSTEM_BUILDER_INFO 
      {
         Bus_Type = "avalon";
         Address_Group = "1";
         Has_Clock = "0";
         Address_Width = "18";
         Address_Alignment = "dynamic";
         Data_Width = "16";
         Has_Base_Address = "1";
         Has_IRQ = "0";
         Setup_Time = "20ns";
         Hold_Time = "20ns";
         Read_Wait_States = "20ns";
         Write_Wait_States = "20ns";
         Read_Latency = "0";
         Maximum_Pending_Read_Transactions = "0";
         Active_CS_Through_Read_Latency = "0";
         Is_Printable_Device = "0";
         Is_Memory_Device = "1";
         Is_Readable = "1";
         Is_Writable = "1";
         Minimum_Uninterrupted_Run_Length = "1";
         Base_Address = "0x00600000";
      }
      COMPONENT_BUILDER 
      {
         AVS_SETTINGS 
         {
            Setup_Value = "20";
            Read_Wait_Value = "20";
            Write_Wait_Value = "20";
            Hold_Value = "20";
            Timing_Units = "ns";
            Read_Latency_Value = "0";
            Minimum_Arbitration_Shares = "1";
            Active_CS_Through_Read_Latency = "0";
            Max_Pending_Read_Transactions_Value = "1";
            Address_Alignment = "dynamic";
            Is_Printable_Device = "0";
            Interleave_Bursts = "0";
            interface_name = "Avalon Slave";
            external_wait = "0";
            Is_Memory_Device = "1";
         }
      }
      PORT_WIRING 
      {
         PORT iDATA
         {
            width = "16";
            width_expression = "";
            direction = "input";
            type = "writedata";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT oDATA
         {
            width = "16";
            width_expression = "";
            direction = "output";
            type = "readdata";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT iADDR
         {
            width = "18";
            width_expression = "";
            direction = "input";
            type = "address";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT iWE_N
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "write_n";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT iOE_N
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "read_n";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT iCE_N
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "chipselect_n";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT iBE_N
         {
            width = "2";
            width_expression = "";
            direction = "input";
            type = "byteenable_n";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT SRAM_DQ
         {
            width = "16";
            width_expression = "";
            direction = "inout";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT SRAM_ADDR
         {
            width = "18";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT SRAM_UB_N
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT SRAM_LB_N
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT SRAM_WE_N
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT SRAM_CE_N
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT SRAM_OE_N
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
      }
   }
   HDL_INFO 
   {
      Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/SRAM_16Bit_512K.v, __PROJECT_DIRECTORY__/sram_0.v";
   }
}
]]></parameter>
 </module>
 <module kind="audio_dac_fifo" version="1.0" enabled="1" name="Audio_0">
  <parameter name="instancePTF"><![CDATA[MODULE Audio_0
{
   class = "audio_dac_fifo";
   class_version = "1.0";
   SYSTEM_BUILDER_INFO 
   {
      Instantiate_In_System_Module = "1";
      Has_Clock = "1";
      Top_Level_Ports_Are_Enumerated = "1";
      Is_Enabled = "1";
      Clock_Source = "clk";
      View 
      {
         MESSAGES 
         {
         }
         Is_Collapsed = "1";
      }
   }
   COMPONENT_BUILDER 
   {
      GLS_SETTINGS 
      {
      }
   }
   PORT_WIRING 
   {
      PORT iWR_CLK
      {
         width = "1";
         width_expression = "";
         direction = "input";
         type = "clk";
         is_shared = "0";
         vhdl_record_name = "";
         vhdl_record_type = "";
      }
   }
   WIZARD_SCRIPT_ARGUMENTS 
   {
      hdl_parameters 
      {
         ref_clk = "18432000";
         sample_rate = "48000";
         data_width = "16";
         channel_num = "2";
      }
   }
   SIMULATION 
   {
      DISPLAY 
      {
      }
   }
   SLAVE avalon_slave_0
   {
      SYSTEM_BUILDER_INFO 
      {
         Bus_Type = "avalon";
         Address_Group = "1";
         Has_Clock = "0";
         Address_Width = "0";
         Address_Alignment = "native";
         Data_Width = "16";
         Has_Base_Address = "1";
         Has_IRQ = "0";
         Setup_Time = "0cycles";
         Hold_Time = "0cycles";
         Read_Wait_States = "0cycles";
         Write_Wait_States = "0cycles";
         Read_Latency = "0";
         Maximum_Pending_Read_Transactions = "0";
         Active_CS_Through_Read_Latency = "0";
         Is_Printable_Device = "0";
         Is_Memory_Device = "0";
         Is_Readable = "0";
         Is_Writable = "1";
         Minimum_Uninterrupted_Run_Length = "1";
         Base_Address = "0x00681104";
      }
      COMPONENT_BUILDER 
      {
         AVS_SETTINGS 
         {
            Setup_Value = "0";
            Read_Wait_Value = "0";
            Write_Wait_Value = "0";
            Hold_Value = "0";
            Timing_Units = "cycles";
            Read_Latency_Value = "0";
            Minimum_Arbitration_Shares = "1";
            Active_CS_Through_Read_Latency = "0";
            Max_Pending_Read_Transactions_Value = "1";
            Address_Alignment = "native";
            Is_Printable_Device = "0";
            Interleave_Bursts = "0";
            interface_name = "Avalon Slave";
            external_wait = "0";
            Is_Memory_Device = "0";
         }
      }
      PORT_WIRING 
      {
         PORT iDATA
         {
            width = "16";
            width_expression = "((DATA_WIDTH - 1)) - (0) + 1";
            direction = "input";
            type = "writedata";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT iWR
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "write";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT oDATA
         {
            width = "16";
            width_expression = "((DATA_WIDTH - 1)) - (0) + 1";
            direction = "output";
            type = "readdata";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT oAUD_DATA
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT oAUD_LRCK
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT oAUD_BCK
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT oAUD_XCK
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT iCLK_18_4
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT iRST_N
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "reset_n";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
      }
   }
   HDL_INFO 
   {
      Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/AUDIO_DAC_FIFO.v,__PROJECT_DIRECTORY__/FIFO_16_256.v, __PROJECT_DIRECTORY__/Audio_0.v";
   }
}
]]></parameter>
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="SD_DAT">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="direction" value="Bidir" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="SD_CMD">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="direction" value="Bidir" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="SD_CLK">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="direction" value="Output" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="noteA">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="noteB">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="noteC">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="noteD">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="noteE">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="noteF">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="noteG">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="MS">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="true" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="FALLING" />
  <parameter name="generateIRQ" value="true" />
  <parameter name="irqType" value="EDGE" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module
   kind="altera_avalon_pio"
   version="10.1"
   enabled="1"
   name="dist_sensor">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="true" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="FALLING" />
  <parameter name="generateIRQ" value="true" />
  <parameter name="irqType" value="EDGE" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="RST">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="true" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="FALLING" />
  <parameter name="generateIRQ" value="true" />
  <parameter name="irqType" value="EDGE" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="Oct_UP">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="true" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="FALLING" />
  <parameter name="generateIRQ" value="true" />
  <parameter name="irqType" value="EDGE" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="Oct_DOWN">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="true" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="FALLING" />
  <parameter name="generateIRQ" value="true" />
  <parameter name="irqType" value="EDGE" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="accelerometer" version="1.0" enabled="1" name="Accel_Control">
  <parameter name="AUTO_CLOCK_CLOCK_RATE" value="100000000" />
 </module>
 <module
   kind="opencores_i2c_master"
   version="1.0"
   enabled="1"
   name="i2c_master">
  <parameter name="AUTO_AVALON_SLAVE_0_CLOCK_CLOCK_RATE" value="100000000" />
 </module>
 <module kind="altpll" version="10.1" enabled="1" name="altpll_0">
  <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
  <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
  <parameter name="INTENDED_DEVICE_FAMILY" value="Cyclone II" />
  <parameter name="WIDTH_CLOCK" value="" />
  <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
  <parameter name="PRIMARY_CLOCK" value="" />
  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
  <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
  <parameter name="OPERATION_MODE" value="NORMAL" />
  <parameter name="PLL_TYPE" value="" />
  <parameter name="QUALIFY_CONF_DONE" value="" />
  <parameter name="COMPENSATE_CLOCK" value="CLK1" />
  <parameter name="SCAN_CHAIN" value="" />
  <parameter name="GATE_LOCK_SIGNAL" value="NO" />
  <parameter name="GATE_LOCK_COUNTER" value="" />
  <parameter name="LOCK_HIGH" value="" />
  <parameter name="LOCK_LOW" value="" />
  <parameter name="VALID_LOCK_MULTIPLIER" value="1" />
  <parameter name="INVALID_LOCK_MULTIPLIER" value="5" />
  <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
  <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
  <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
  <parameter name="SKIP_VCO" value="" />
  <parameter name="SWITCH_OVER_COUNTER" value="" />
  <parameter name="SWITCH_OVER_TYPE" value="" />
  <parameter name="FEEDBACK_SOURCE" value="" />
  <parameter name="BANDWIDTH" value="" />
  <parameter name="BANDWIDTH_TYPE" value="" />
  <parameter name="SPREAD_FREQUENCY" value="" />
  <parameter name="DOWN_SPREAD" value="" />
  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
  <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
  <parameter name="CLK0_MULTIPLY_BY" value="2" />
  <parameter name="CLK1_MULTIPLY_BY" value="2" />
  <parameter name="CLK2_MULTIPLY_BY" value="" />
  <parameter name="CLK3_MULTIPLY_BY" value="" />
  <parameter name="CLK4_MULTIPLY_BY" value="" />
  <parameter name="CLK5_MULTIPLY_BY" value="" />
  <parameter name="CLK6_MULTIPLY_BY" value="" />
  <parameter name="CLK7_MULTIPLY_BY" value="" />
  <parameter name="CLK8_MULTIPLY_BY" value="" />
  <parameter name="CLK9_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
  <parameter name="CLK0_DIVIDE_BY" value="1" />
  <parameter name="CLK1_DIVIDE_BY" value="1" />
  <parameter name="CLK2_DIVIDE_BY" value="" />
  <parameter name="CLK3_DIVIDE_BY" value="" />
  <parameter name="CLK4_DIVIDE_BY" value="" />
  <parameter name="CLK5_DIVIDE_BY" value="" />
  <parameter name="CLK6_DIVIDE_BY" value="" />
  <parameter name="CLK7_DIVIDE_BY" value="" />
  <parameter name="CLK8_DIVIDE_BY" value="" />
  <parameter name="CLK9_DIVIDE_BY" value="" />
  <parameter name="EXTCLK0_DIVIDE_BY" value="" />
  <parameter name="EXTCLK1_DIVIDE_BY" value="" />
  <parameter name="EXTCLK2_DIVIDE_BY" value="" />
  <parameter name="EXTCLK3_DIVIDE_BY" value="" />
  <parameter name="CLK0_PHASE_SHIFT" value="-3000" />
  <parameter name="CLK1_PHASE_SHIFT" value="0" />
  <parameter name="CLK2_PHASE_SHIFT" value="" />
  <parameter name="CLK3_PHASE_SHIFT" value="" />
  <parameter name="CLK4_PHASE_SHIFT" value="" />
  <parameter name="CLK5_PHASE_SHIFT" value="" />
  <parameter name="CLK6_PHASE_SHIFT" value="" />
  <parameter name="CLK7_PHASE_SHIFT" value="" />
  <parameter name="CLK8_PHASE_SHIFT" value="" />
  <parameter name="CLK9_PHASE_SHIFT" value="" />
  <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
  <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
  <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
  <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
  <parameter name="CLK0_DUTY_CYCLE" value="50" />
  <parameter name="CLK1_DUTY_CYCLE" value="50" />
  <parameter name="CLK2_DUTY_CYCLE" value="" />
  <parameter name="CLK3_DUTY_CYCLE" value="" />
  <parameter name="CLK4_DUTY_CYCLE" value="" />
  <parameter name="CLK5_DUTY_CYCLE" value="" />
  <parameter name="CLK6_DUTY_CYCLE" value="" />
  <parameter name="CLK7_DUTY_CYCLE" value="" />
  <parameter name="CLK8_DUTY_CYCLE" value="" />
  <parameter name="CLK9_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
  <parameter name="PORT_clkena0" value="PORT_UNUSED" />
  <parameter name="PORT_clkena1" value="PORT_UNUSED" />
  <parameter name="PORT_clkena2" value="PORT_UNUSED" />
  <parameter name="PORT_clkena3" value="PORT_UNUSED" />
  <parameter name="PORT_clkena4" value="PORT_UNUSED" />
  <parameter name="PORT_clkena5" value="PORT_UNUSED" />
  <parameter name="PORT_extclkena0" value="" />
  <parameter name="PORT_extclkena1" value="" />
  <parameter name="PORT_extclkena2" value="" />
  <parameter name="PORT_extclkena3" value="" />
  <parameter name="PORT_extclk0" value="PORT_UNUSED" />
  <parameter name="PORT_extclk1" value="PORT_UNUSED" />
  <parameter name="PORT_extclk2" value="PORT_UNUSED" />
  <parameter name="PORT_extclk3" value="PORT_UNUSED" />
  <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
  <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
  <parameter name="PORT_clk0" value="PORT_USED" />
  <parameter name="PORT_clk1" value="PORT_USED" />
  <parameter name="PORT_clk2" value="PORT_UNUSED" />
  <parameter name="PORT_clk3" value="PORT_UNUSED" />
  <parameter name="PORT_clk4" value="PORT_UNUSED" />
  <parameter name="PORT_clk5" value="PORT_UNUSED" />
  <parameter name="PORT_clk6" value="" />
  <parameter name="PORT_clk7" value="" />
  <parameter name="PORT_clk8" value="" />
  <parameter name="PORT_clk9" value="" />
  <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
  <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
  <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
  <parameter name="PORT_SCLKOUT1" value="" />
  <parameter name="PORT_SCLKOUT0" value="" />
  <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
  <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
  <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
  <parameter name="PORT_INCLK0" value="PORT_USED" />
  <parameter name="PORT_FBIN" value="PORT_UNUSED" />
  <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
  <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
  <parameter name="PORT_ARESET" value="PORT_USED" />
  <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
  <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
  <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
  <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
  <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
  <parameter name="PORT_ENABLE0" value="" />
  <parameter name="PORT_ENABLE1" value="" />
  <parameter name="PORT_LOCKED" value="PORT_USED" />
  <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
  <parameter name="PORT_FBOUT" value="" />
  <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
  <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
  <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
  <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
  <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
  <parameter name="PORT_VCOOVERRANGE" value="" />
  <parameter name="PORT_VCOUNDERRANGE" value="" />
  <parameter name="DPA_MULTIPLY_BY" value="" />
  <parameter name="DPA_DIVIDE_BY" value="" />
  <parameter name="DPA_DIVIDER" value="" />
  <parameter name="VCO_MULTIPLY_BY" value="" />
  <parameter name="VCO_DIVIDE_BY" value="" />
  <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
  <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
  <parameter name="VCO_FREQUENCY_CONTROL" value="" />
  <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
  <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
  <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
  <parameter name="HIDDEN_CONSTANTS">CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#VALID_LOCK_MULTIPLIER 1 CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#CLK0_PHASE_SHIFT -3000 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 2 CT#COMPENSATE_CLOCK CLK1 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_USED CT#INVALID_LOCK_MULTIPLIER 5 CT#INTENDED_DEVICE_FAMILY {Cyclone II} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#GATE_LOCK_SIGNAL NO CT#PORT_LOCKED PORT_USED</parameter>
  <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 1 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c1 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 0 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 1 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 0 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_ENA_CHECK 0 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 0 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 0.00000000 PT#PHASE_SHIFT0 -3.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#BANDWIDTH_USE_CUSTOM 0 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 100.000000 PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 ns PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone II} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1365795009376962.mif PT#ACTIVECLK_CHECK 0</parameter>
  <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
  <parameter name="HIDDEN_IS_NUMERIC">IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#VALID_LOCK_MULTIPLIER 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#INVALID_LOCK_MULTIPLIER 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
  <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
  <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0}</parameter>
  <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone II" />
 </module>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.instruction_master"
   end="cpu_0.jtag_debug_module">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x01909000" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="cpu_0.jtag_debug_module">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x01909000" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.instruction_master"
   end="tri_state_bridge_0.avalon_slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0000" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="tri_state_bridge_0.avalon_slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0000" />
 </connection>
 <connection
   kind="avalon_tristate"
   version="10.1"
   start="tri_state_bridge_0.tristate_master"
   end="cfi_flash_0.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x01400000" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.instruction_master"
   end="sdram_0.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00800000" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="sdram_0.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00800000" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.instruction_master"
   end="epcs_controller.epcs_control_port">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x01909800" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="epcs_controller.epcs_control_port">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x01909800" />
 </connection>
 <connection
   kind="interrupt"
   version="10.1"
   start="cpu_0.d_irq"
   end="epcs_controller.irq">
  <parameter name="irqNumber" value="0" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="jtag_uart_0.avalon_jtag_slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a1d0" />
 </connection>
 <connection
   kind="interrupt"
   version="10.1"
   start="cpu_0.d_irq"
   end="jtag_uart_0.irq">
  <parameter name="irqNumber" value="1" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="uart_0.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a020" />
 </connection>
 <connection kind="interrupt" version="10.1" start="cpu_0.d_irq" end="uart_0.irq">
  <parameter name="irqNumber" value="2" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="timer_0.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a040" />
 </connection>
 <connection kind="interrupt" version="10.1" start="cpu_0.d_irq" end="timer_0.irq">
  <parameter name="irqNumber" value="3" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="timer_1.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a060" />
 </connection>
 <connection kind="interrupt" version="10.1" start="cpu_0.d_irq" end="timer_1.irq">
  <parameter name="irqNumber" value="4" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="lcd_16207_0.control_slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a0c0" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="SEG7_Display.avalon_slave_0">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a1d8" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.instruction_master"
   end="sram_0.avalon_slave_0">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x01880000" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="sram_0.avalon_slave_0">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x01880000" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="Audio_0.avalon_slave_0">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a1dc" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="SD_DAT.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a0d0" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="SD_CMD.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a0e0" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="SD_CLK.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a0f0" />
 </connection>
 <connection kind="avalon" version="10.1" start="cpu_0.data_master" end="noteA.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a100" />
 </connection>
 <connection kind="avalon" version="10.1" start="cpu_0.data_master" end="noteB.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a110" />
 </connection>
 <connection kind="avalon" version="10.1" start="cpu_0.data_master" end="noteC.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a120" />
 </connection>
 <connection kind="avalon" version="10.1" start="cpu_0.data_master" end="noteD.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a130" />
 </connection>
 <connection kind="avalon" version="10.1" start="cpu_0.data_master" end="noteE.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a140" />
 </connection>
 <connection kind="avalon" version="10.1" start="cpu_0.data_master" end="noteF.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a150" />
 </connection>
 <connection kind="avalon" version="10.1" start="cpu_0.data_master" end="noteG.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a160" />
 </connection>
 <connection kind="avalon" version="10.1" start="cpu_0.data_master" end="MS.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a170" />
 </connection>
 <connection kind="interrupt" version="10.1" start="cpu_0.d_irq" end="MS.irq">
  <parameter name="irqNumber" value="5" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="dist_sensor.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a180" />
 </connection>
 <connection kind="avalon" version="10.1" start="cpu_0.data_master" end="RST.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a190" />
 </connection>
 <connection kind="interrupt" version="10.1" start="cpu_0.d_irq" end="RST.irq">
  <parameter name="irqNumber" value="6" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="Oct_UP.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a1a0" />
 </connection>
 <connection kind="interrupt" version="10.1" start="cpu_0.d_irq" end="Oct_UP.irq">
  <parameter name="irqNumber" value="7" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="Oct_DOWN.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a1b0" />
 </connection>
 <connection
   kind="interrupt"
   version="10.1"
   start="cpu_0.d_irq"
   end="Oct_DOWN.irq">
  <parameter name="irqNumber" value="8" />
 </connection>
 <connection
   kind="interrupt"
   version="10.1"
   start="cpu_0.d_irq"
   end="dist_sensor.irq">
  <parameter name="irqNumber" value="9" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="Accel_Control.avalon_slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a080" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.instruction_master"
   end="i2c_master.avalon_slave_0">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a0a0" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="i2c_master.avalon_slave_0">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a0a0" />
 </connection>
 <connection
   kind="interrupt"
   version="10.1"
   start="cpu_0.d_irq"
   end="i2c_master.avalon_slave_0_irq">
  <parameter name="irqNumber" value="10" />
 </connection>
 <connection
   kind="clock"
   version="10.1"
   start="clk.clk"
   end="altpll_0.inclk_interface" />
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="altpll_0.pll_slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0190a1c0" />
 </connection>
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="sdram_0.clk" />
 <connection
   kind="clock"
   version="10.1"
   start="altpll_0.c1"
   end="i2c_master.avalon_slave_0_clock" />
 <connection
   kind="clock"
   version="10.1"
   start="altpll_0.c1"
   end="Accel_Control.clock" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="Oct_DOWN.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="Oct_UP.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="RST.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="dist_sensor.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="MS.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="noteG.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="noteF.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="noteE.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="noteD.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="noteC.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="noteB.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="noteA.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="SD_CLK.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="SD_CMD.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="SD_DAT.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="Audio_0.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="sram_0.clk" />
 <connection
   kind="clock"
   version="10.1"
   start="altpll_0.c1"
   end="SEG7_Display.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="lcd_16207_0.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="timer_1.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="timer_0.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="uart_0.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="jtag_uart_0.clk" />
 <connection
   kind="clock"
   version="10.1"
   start="altpll_0.c1"
   end="epcs_controller.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="cfi_flash_0.clk" />
 <connection
   kind="clock"
   version="10.1"
   start="altpll_0.c1"
   end="tri_state_bridge_0.clk" />
 <connection kind="clock" version="10.1" start="altpll_0.c1" end="cpu_0.clk" />
</system>
