/* system.h
 *
 * Machine generated for a CPU named "cpu_0" as defined in:
 * /media/20A7-C8B8/492/Bkp/sdramwithoutnoise/capstone_accel_trial/software/hello_ucosii_0_syslib/../../system_0.ptf
 *
 * Generated: 2013-04-12 19:45:57.063
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "system_0"
#define ALT_CPU_NAME "cpu_0"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONEII"
#define ALT_STDIN "/dev/jtag_uart_0"
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN_BASE 0x0190a1d0
#define ALT_STDIN_DEV jtag_uart_0
#define ALT_STDIN_PRESENT
#define ALT_STDOUT "/dev/jtag_uart_0"
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT_BASE 0x0190a1d0
#define ALT_STDOUT_DEV jtag_uart_0
#define ALT_STDOUT_PRESENT
#define ALT_STDERR "/dev/jtag_uart_0"
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDERR_BASE 0x0190a1d0
#define ALT_STDERR_DEV jtag_uart_0
#define ALT_STDERR_PRESENT
#define ALT_CPU_FREQ 100000000
#define ALT_IRQ_BASE NULL
#define ALT_LEGACY_INTERRUPT_API_PRESENT

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "fast"
#define NIOS2_BIG_ENDIAN 0
#define NIOS2_INTERRUPT_CONTROLLER_ID 0

#define NIOS2_ICACHE_SIZE 8192
#define NIOS2_DCACHE_SIZE 8192
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 32
#define NIOS2_DCACHE_LINE_SIZE_LOG2 5
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x00800020
#define NIOS2_RESET_ADDR 0x01400000
#define NIOS2_BREAK_ADDR 0x01909020

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_TRI_STATE_BRIDGE
#define __ALTERA_AVALON_CFI_FLASH
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_UART
#define __ALTERA_AVALON_TIMER
#define __ALTERA_AVALON_LCD_16207
#define __SEG7_LUT_8
#define __SRAM_16BIT_512K
#define __AUDIO_DAC_FIFO
#define __ALTERA_AVALON_PIO
#define __ACCELEROMETER
#define __OPENCORES_I2C_MASTER
#define __ALTPLL

/*
 * tri_state_bridge_0 configuration
 *
 */

#define TRI_STATE_BRIDGE_0_NAME "/dev/tri_state_bridge_0"
#define TRI_STATE_BRIDGE_0_TYPE "altera_avalon_tri_state_bridge"
#define ALT_MODULE_CLASS_tri_state_bridge_0 altera_avalon_tri_state_bridge

/*
 * cfi_flash_0 configuration
 *
 */

#define CFI_FLASH_0_NAME "/dev/cfi_flash_0"
#define CFI_FLASH_0_TYPE "altera_avalon_cfi_flash"
#define CFI_FLASH_0_BASE 0x01400000
#define CFI_FLASH_0_SPAN 4194304
#define CFI_FLASH_0_SETUP_VALUE 40
#define CFI_FLASH_0_WAIT_VALUE 160
#define CFI_FLASH_0_HOLD_VALUE 40
#define CFI_FLASH_0_TIMING_UNITS "ns"
#define CFI_FLASH_0_UNIT_MULTIPLIER 1
#define CFI_FLASH_0_SIZE 4194304
#define ALT_MODULE_CLASS_cfi_flash_0 altera_avalon_cfi_flash

/*
 * sdram_0 configuration
 *
 */

#define SDRAM_0_NAME "/dev/sdram_0"
#define SDRAM_0_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_0_BASE 0x00800000
#define SDRAM_0_SPAN 8388608
#define SDRAM_0_REGISTER_DATA_IN 1
#define SDRAM_0_SIM_MODEL_BASE 1
#define SDRAM_0_SDRAM_DATA_WIDTH 16
#define SDRAM_0_SDRAM_ADDR_WIDTH 12
#define SDRAM_0_SDRAM_ROW_WIDTH 12
#define SDRAM_0_SDRAM_COL_WIDTH 8
#define SDRAM_0_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_0_SDRAM_NUM_BANKS 4
#define SDRAM_0_REFRESH_PERIOD 15.625
#define SDRAM_0_POWERUP_DELAY 100.0
#define SDRAM_0_CAS_LATENCY 3
#define SDRAM_0_T_RFC 70.0
#define SDRAM_0_T_RP 20.0
#define SDRAM_0_T_MRD 3
#define SDRAM_0_T_RCD 20.0
#define SDRAM_0_T_AC 5.5
#define SDRAM_0_T_WR 14.0
#define SDRAM_0_INIT_REFRESH_COMMANDS 2
#define SDRAM_0_INIT_NOP_DELAY 0.0
#define SDRAM_0_SHARED_DATA 0
#define SDRAM_0_SDRAM_BANK_WIDTH 2
#define SDRAM_0_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_0_STARVATION_INDICATOR 0
#define SDRAM_0_IS_INITIALIZED 1
#define ALT_MODULE_CLASS_sdram_0 altera_avalon_new_sdram_controller

/*
 * epcs_controller configuration
 *
 */

#define EPCS_CONTROLLER_NAME "/dev/epcs_controller"
#define EPCS_CONTROLLER_TYPE "altera_avalon_epcs_flash_controller"
#define EPCS_CONTROLLER_BASE 0x01909800
#define EPCS_CONTROLLER_SPAN 2048
#define EPCS_CONTROLLER_IRQ 0
#define EPCS_CONTROLLER_IRQ_INTERRUPT_CONTROLLER_ID 0
#define EPCS_CONTROLLER_DATABITS 8
#define EPCS_CONTROLLER_TARGETCLOCK 20
#define EPCS_CONTROLLER_CLOCKUNITS "MHz"
#define EPCS_CONTROLLER_CLOCKMULT 1000000
#define EPCS_CONTROLLER_NUMSLAVES 1
#define EPCS_CONTROLLER_ISMASTER 1
#define EPCS_CONTROLLER_CLOCKPOLARITY 0
#define EPCS_CONTROLLER_CLOCKPHASE 0
#define EPCS_CONTROLLER_LSBFIRST 0
#define EPCS_CONTROLLER_EXTRADELAY 0
#define EPCS_CONTROLLER_TARGETSSDELAY 100
#define EPCS_CONTROLLER_DELAYUNITS "us"
#define EPCS_CONTROLLER_DELAYMULT "1e-06"
#define EPCS_CONTROLLER_PREFIX "epcs_"
#define EPCS_CONTROLLER_REGISTER_OFFSET 0x200
#define EPCS_CONTROLLER_IGNORE_LEGACY_CHECK 1
#define EPCS_CONTROLLER_USE_ASMI_ATOM 1
#define EPCS_CONTROLLER_CLOCKUNIT "kHz"
#define EPCS_CONTROLLER_DELAYUNIT "us"
#define EPCS_CONTROLLER_DISABLEAVALONFLOWCONTROL 0
#define EPCS_CONTROLLER_INSERT_SYNC 0
#define EPCS_CONTROLLER_SYNC_REG_DEPTH 2
#define ALT_MODULE_CLASS_epcs_controller altera_avalon_epcs_flash_controller

/*
 * jtag_uart_0 configuration
 *
 */

#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_0_BASE 0x0190a1d0
#define JTAG_UART_0_SPAN 8
#define JTAG_UART_0_IRQ 1
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_0_WRITE_DEPTH 64
#define JTAG_UART_0_READ_DEPTH 64
#define JTAG_UART_0_WRITE_THRESHOLD 8
#define JTAG_UART_0_READ_THRESHOLD 8
#define JTAG_UART_0_READ_CHAR_STREAM ""
#define JTAG_UART_0_SHOWASCII 1
#define JTAG_UART_0_RELATIVEPATH 1
#define JTAG_UART_0_READ_LE 0
#define JTAG_UART_0_WRITE_LE 0
#define JTAG_UART_0_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0
#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart

/*
 * uart_0 configuration
 *
 */

#define UART_0_NAME "/dev/uart_0"
#define UART_0_TYPE "altera_avalon_uart"
#define UART_0_BASE 0x0190a020
#define UART_0_SPAN 32
#define UART_0_IRQ 2
#define UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define UART_0_BAUD 115200
#define UART_0_DATA_BITS 8
#define UART_0_FIXED_BAUD 1
#define UART_0_PARITY 'N'
#define UART_0_STOP_BITS 1
#define UART_0_SYNC_REG_DEPTH 2
#define UART_0_USE_CTS_RTS 0
#define UART_0_USE_EOP_REGISTER 0
#define UART_0_SIM_TRUE_BAUD 0
#define UART_0_SIM_CHAR_STREAM ""
#define UART_0_RELATIVEPATH 1
#define UART_0_FREQ 100000000
#define ALT_MODULE_CLASS_uart_0 altera_avalon_uart

/*
 * timer_0 configuration
 *
 */

#define TIMER_0_NAME "/dev/timer_0"
#define TIMER_0_TYPE "altera_avalon_timer"
#define TIMER_0_BASE 0x0190a040
#define TIMER_0_SPAN 32
#define TIMER_0_IRQ 3
#define TIMER_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define TIMER_0_ALWAYS_RUN 0
#define TIMER_0_FIXED_PERIOD 0
#define TIMER_0_SNAPSHOT 1
#define TIMER_0_PERIOD 1
#define TIMER_0_PERIOD_UNITS "ms"
#define TIMER_0_RESET_OUTPUT 0
#define TIMER_0_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_0_LOAD_VALUE 99999
#define TIMER_0_COUNTER_SIZE 32
#define TIMER_0_MULT 0.0010
#define TIMER_0_TICKS_PER_SEC 1000
#define TIMER_0_FREQ 100000000
#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer

/*
 * timer_1 configuration
 *
 */

#define TIMER_1_NAME "/dev/timer_1"
#define TIMER_1_TYPE "altera_avalon_timer"
#define TIMER_1_BASE 0x0190a060
#define TIMER_1_SPAN 32
#define TIMER_1_IRQ 4
#define TIMER_1_IRQ_INTERRUPT_CONTROLLER_ID 0
#define TIMER_1_ALWAYS_RUN 0
#define TIMER_1_FIXED_PERIOD 0
#define TIMER_1_SNAPSHOT 1
#define TIMER_1_PERIOD 1
#define TIMER_1_PERIOD_UNITS "ms"
#define TIMER_1_RESET_OUTPUT 0
#define TIMER_1_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_1_LOAD_VALUE 99999
#define TIMER_1_COUNTER_SIZE 32
#define TIMER_1_MULT 0.0010
#define TIMER_1_TICKS_PER_SEC 1000
#define TIMER_1_FREQ 100000000
#define ALT_MODULE_CLASS_timer_1 altera_avalon_timer

/*
 * lcd_16207_0 configuration
 *
 */

#define LCD_16207_0_NAME "/dev/lcd_16207_0"
#define LCD_16207_0_TYPE "altera_avalon_lcd_16207"
#define LCD_16207_0_BASE 0x0190a0c0
#define LCD_16207_0_SPAN 16
#define ALT_MODULE_CLASS_lcd_16207_0 altera_avalon_lcd_16207

/*
 * SEG7_Display configuration
 *
 */

#define SEG7_DISPLAY_NAME "/dev/SEG7_Display"
#define SEG7_DISPLAY_TYPE "seg7_lut_8"
#define SEG7_DISPLAY_BASE 0x0190a1d8
#define SEG7_DISPLAY_SPAN 4
#define SEG7_DISPLAY_HDL_PARAMETERS ""
#define ALT_MODULE_CLASS_SEG7_Display seg7_lut_8

/*
 * sram_0 configuration
 *
 */

#define SRAM_0_NAME "/dev/sram_0"
#define SRAM_0_TYPE "sram_16bit_512k"
#define SRAM_0_BASE 0x01880000
#define SRAM_0_SPAN 524288
#define SRAM_0_HDL_PARAMETERS ""
#define ALT_MODULE_CLASS_sram_0 sram_16bit_512k

/*
 * Audio_0 configuration
 *
 */

#define AUDIO_0_NAME "/dev/Audio_0"
#define AUDIO_0_TYPE "audio_dac_fifo"
#define AUDIO_0_BASE 0x0190a1dc
#define AUDIO_0_SPAN 4
#define ALT_MODULE_CLASS_Audio_0 audio_dac_fifo

/*
 * SD_DAT configuration
 *
 */

#define SD_DAT_NAME "/dev/SD_DAT"
#define SD_DAT_TYPE "altera_avalon_pio"
#define SD_DAT_BASE 0x0190a0d0
#define SD_DAT_SPAN 16
#define SD_DAT_DO_TEST_BENCH_WIRING 0
#define SD_DAT_DRIVEN_SIM_VALUE 0
#define SD_DAT_HAS_TRI 1
#define SD_DAT_HAS_OUT 0
#define SD_DAT_HAS_IN 0
#define SD_DAT_CAPTURE 0
#define SD_DAT_DATA_WIDTH 1
#define SD_DAT_RESET_VALUE 0
#define SD_DAT_EDGE_TYPE "NONE"
#define SD_DAT_IRQ_TYPE "NONE"
#define SD_DAT_BIT_CLEARING_EDGE_REGISTER 0
#define SD_DAT_BIT_MODIFYING_OUTPUT_REGISTER 0
#define SD_DAT_FREQ 100000000
#define ALT_MODULE_CLASS_SD_DAT altera_avalon_pio

/*
 * SD_CMD configuration
 *
 */

#define SD_CMD_NAME "/dev/SD_CMD"
#define SD_CMD_TYPE "altera_avalon_pio"
#define SD_CMD_BASE 0x0190a0e0
#define SD_CMD_SPAN 16
#define SD_CMD_DO_TEST_BENCH_WIRING 0
#define SD_CMD_DRIVEN_SIM_VALUE 0
#define SD_CMD_HAS_TRI 1
#define SD_CMD_HAS_OUT 0
#define SD_CMD_HAS_IN 0
#define SD_CMD_CAPTURE 0
#define SD_CMD_DATA_WIDTH 1
#define SD_CMD_RESET_VALUE 0
#define SD_CMD_EDGE_TYPE "NONE"
#define SD_CMD_IRQ_TYPE "NONE"
#define SD_CMD_BIT_CLEARING_EDGE_REGISTER 0
#define SD_CMD_BIT_MODIFYING_OUTPUT_REGISTER 0
#define SD_CMD_FREQ 100000000
#define ALT_MODULE_CLASS_SD_CMD altera_avalon_pio

/*
 * SD_CLK configuration
 *
 */

#define SD_CLK_NAME "/dev/SD_CLK"
#define SD_CLK_TYPE "altera_avalon_pio"
#define SD_CLK_BASE 0x0190a0f0
#define SD_CLK_SPAN 16
#define SD_CLK_DO_TEST_BENCH_WIRING 0
#define SD_CLK_DRIVEN_SIM_VALUE 0
#define SD_CLK_HAS_TRI 0
#define SD_CLK_HAS_OUT 1
#define SD_CLK_HAS_IN 0
#define SD_CLK_CAPTURE 0
#define SD_CLK_DATA_WIDTH 1
#define SD_CLK_RESET_VALUE 0
#define SD_CLK_EDGE_TYPE "NONE"
#define SD_CLK_IRQ_TYPE "NONE"
#define SD_CLK_BIT_CLEARING_EDGE_REGISTER 0
#define SD_CLK_BIT_MODIFYING_OUTPUT_REGISTER 0
#define SD_CLK_FREQ 100000000
#define ALT_MODULE_CLASS_SD_CLK altera_avalon_pio

/*
 * noteA configuration
 *
 */

#define NOTEA_NAME "/dev/noteA"
#define NOTEA_TYPE "altera_avalon_pio"
#define NOTEA_BASE 0x0190a100
#define NOTEA_SPAN 16
#define NOTEA_DO_TEST_BENCH_WIRING 0
#define NOTEA_DRIVEN_SIM_VALUE 0
#define NOTEA_HAS_TRI 0
#define NOTEA_HAS_OUT 0
#define NOTEA_HAS_IN 1
#define NOTEA_CAPTURE 0
#define NOTEA_DATA_WIDTH 1
#define NOTEA_RESET_VALUE 0
#define NOTEA_EDGE_TYPE "NONE"
#define NOTEA_IRQ_TYPE "NONE"
#define NOTEA_BIT_CLEARING_EDGE_REGISTER 0
#define NOTEA_BIT_MODIFYING_OUTPUT_REGISTER 0
#define NOTEA_FREQ 100000000
#define ALT_MODULE_CLASS_noteA altera_avalon_pio

/*
 * noteB configuration
 *
 */

#define NOTEB_NAME "/dev/noteB"
#define NOTEB_TYPE "altera_avalon_pio"
#define NOTEB_BASE 0x0190a110
#define NOTEB_SPAN 16
#define NOTEB_DO_TEST_BENCH_WIRING 0
#define NOTEB_DRIVEN_SIM_VALUE 0
#define NOTEB_HAS_TRI 0
#define NOTEB_HAS_OUT 0
#define NOTEB_HAS_IN 1
#define NOTEB_CAPTURE 0
#define NOTEB_DATA_WIDTH 1
#define NOTEB_RESET_VALUE 0
#define NOTEB_EDGE_TYPE "NONE"
#define NOTEB_IRQ_TYPE "NONE"
#define NOTEB_BIT_CLEARING_EDGE_REGISTER 0
#define NOTEB_BIT_MODIFYING_OUTPUT_REGISTER 0
#define NOTEB_FREQ 100000000
#define ALT_MODULE_CLASS_noteB altera_avalon_pio

/*
 * noteC configuration
 *
 */

#define NOTEC_NAME "/dev/noteC"
#define NOTEC_TYPE "altera_avalon_pio"
#define NOTEC_BASE 0x0190a120
#define NOTEC_SPAN 16
#define NOTEC_DO_TEST_BENCH_WIRING 0
#define NOTEC_DRIVEN_SIM_VALUE 0
#define NOTEC_HAS_TRI 0
#define NOTEC_HAS_OUT 0
#define NOTEC_HAS_IN 1
#define NOTEC_CAPTURE 0
#define NOTEC_DATA_WIDTH 1
#define NOTEC_RESET_VALUE 0
#define NOTEC_EDGE_TYPE "NONE"
#define NOTEC_IRQ_TYPE "NONE"
#define NOTEC_BIT_CLEARING_EDGE_REGISTER 0
#define NOTEC_BIT_MODIFYING_OUTPUT_REGISTER 0
#define NOTEC_FREQ 100000000
#define ALT_MODULE_CLASS_noteC altera_avalon_pio

/*
 * noteD configuration
 *
 */

#define NOTED_NAME "/dev/noteD"
#define NOTED_TYPE "altera_avalon_pio"
#define NOTED_BASE 0x0190a130
#define NOTED_SPAN 16
#define NOTED_DO_TEST_BENCH_WIRING 0
#define NOTED_DRIVEN_SIM_VALUE 0
#define NOTED_HAS_TRI 0
#define NOTED_HAS_OUT 0
#define NOTED_HAS_IN 1
#define NOTED_CAPTURE 0
#define NOTED_DATA_WIDTH 1
#define NOTED_RESET_VALUE 0
#define NOTED_EDGE_TYPE "NONE"
#define NOTED_IRQ_TYPE "NONE"
#define NOTED_BIT_CLEARING_EDGE_REGISTER 0
#define NOTED_BIT_MODIFYING_OUTPUT_REGISTER 0
#define NOTED_FREQ 100000000
#define ALT_MODULE_CLASS_noteD altera_avalon_pio

/*
 * noteE configuration
 *
 */

#define NOTEE_NAME "/dev/noteE"
#define NOTEE_TYPE "altera_avalon_pio"
#define NOTEE_BASE 0x0190a140
#define NOTEE_SPAN 16
#define NOTEE_DO_TEST_BENCH_WIRING 0
#define NOTEE_DRIVEN_SIM_VALUE 0
#define NOTEE_HAS_TRI 0
#define NOTEE_HAS_OUT 0
#define NOTEE_HAS_IN 1
#define NOTEE_CAPTURE 0
#define NOTEE_DATA_WIDTH 1
#define NOTEE_RESET_VALUE 0
#define NOTEE_EDGE_TYPE "NONE"
#define NOTEE_IRQ_TYPE "NONE"
#define NOTEE_BIT_CLEARING_EDGE_REGISTER 0
#define NOTEE_BIT_MODIFYING_OUTPUT_REGISTER 0
#define NOTEE_FREQ 100000000
#define ALT_MODULE_CLASS_noteE altera_avalon_pio

/*
 * noteF configuration
 *
 */

#define NOTEF_NAME "/dev/noteF"
#define NOTEF_TYPE "altera_avalon_pio"
#define NOTEF_BASE 0x0190a150
#define NOTEF_SPAN 16
#define NOTEF_DO_TEST_BENCH_WIRING 0
#define NOTEF_DRIVEN_SIM_VALUE 0
#define NOTEF_HAS_TRI 0
#define NOTEF_HAS_OUT 0
#define NOTEF_HAS_IN 1
#define NOTEF_CAPTURE 0
#define NOTEF_DATA_WIDTH 1
#define NOTEF_RESET_VALUE 0
#define NOTEF_EDGE_TYPE "NONE"
#define NOTEF_IRQ_TYPE "NONE"
#define NOTEF_BIT_CLEARING_EDGE_REGISTER 0
#define NOTEF_BIT_MODIFYING_OUTPUT_REGISTER 0
#define NOTEF_FREQ 100000000
#define ALT_MODULE_CLASS_noteF altera_avalon_pio

/*
 * noteG configuration
 *
 */

#define NOTEG_NAME "/dev/noteG"
#define NOTEG_TYPE "altera_avalon_pio"
#define NOTEG_BASE 0x0190a160
#define NOTEG_SPAN 16
#define NOTEG_DO_TEST_BENCH_WIRING 0
#define NOTEG_DRIVEN_SIM_VALUE 0
#define NOTEG_HAS_TRI 0
#define NOTEG_HAS_OUT 0
#define NOTEG_HAS_IN 1
#define NOTEG_CAPTURE 0
#define NOTEG_DATA_WIDTH 1
#define NOTEG_RESET_VALUE 0
#define NOTEG_EDGE_TYPE "NONE"
#define NOTEG_IRQ_TYPE "NONE"
#define NOTEG_BIT_CLEARING_EDGE_REGISTER 0
#define NOTEG_BIT_MODIFYING_OUTPUT_REGISTER 0
#define NOTEG_FREQ 100000000
#define ALT_MODULE_CLASS_noteG altera_avalon_pio

/*
 * MS configuration
 *
 */

#define MS_NAME "/dev/MS"
#define MS_TYPE "altera_avalon_pio"
#define MS_BASE 0x0190a170
#define MS_SPAN 16
#define MS_IRQ 5
#define MS_IRQ_INTERRUPT_CONTROLLER_ID 0
#define MS_DO_TEST_BENCH_WIRING 0
#define MS_DRIVEN_SIM_VALUE 0
#define MS_HAS_TRI 0
#define MS_HAS_OUT 0
#define MS_HAS_IN 1
#define MS_CAPTURE 1
#define MS_DATA_WIDTH 1
#define MS_RESET_VALUE 0
#define MS_EDGE_TYPE "FALLING"
#define MS_IRQ_TYPE "EDGE"
#define MS_BIT_CLEARING_EDGE_REGISTER 0
#define MS_BIT_MODIFYING_OUTPUT_REGISTER 0
#define MS_FREQ 100000000
#define ALT_MODULE_CLASS_MS altera_avalon_pio

/*
 * dist_sensor configuration
 *
 */

#define DIST_SENSOR_NAME "/dev/dist_sensor"
#define DIST_SENSOR_TYPE "altera_avalon_pio"
#define DIST_SENSOR_BASE 0x0190a180
#define DIST_SENSOR_SPAN 16
#define DIST_SENSOR_IRQ 9
#define DIST_SENSOR_IRQ_INTERRUPT_CONTROLLER_ID 0
#define DIST_SENSOR_DO_TEST_BENCH_WIRING 0
#define DIST_SENSOR_DRIVEN_SIM_VALUE 0
#define DIST_SENSOR_HAS_TRI 0
#define DIST_SENSOR_HAS_OUT 0
#define DIST_SENSOR_HAS_IN 1
#define DIST_SENSOR_CAPTURE 1
#define DIST_SENSOR_DATA_WIDTH 1
#define DIST_SENSOR_RESET_VALUE 0
#define DIST_SENSOR_EDGE_TYPE "FALLING"
#define DIST_SENSOR_IRQ_TYPE "EDGE"
#define DIST_SENSOR_BIT_CLEARING_EDGE_REGISTER 0
#define DIST_SENSOR_BIT_MODIFYING_OUTPUT_REGISTER 0
#define DIST_SENSOR_FREQ 100000000
#define ALT_MODULE_CLASS_dist_sensor altera_avalon_pio

/*
 * RST configuration
 *
 */

#define RST_NAME "/dev/RST"
#define RST_TYPE "altera_avalon_pio"
#define RST_BASE 0x0190a190
#define RST_SPAN 16
#define RST_IRQ 6
#define RST_IRQ_INTERRUPT_CONTROLLER_ID 0
#define RST_DO_TEST_BENCH_WIRING 0
#define RST_DRIVEN_SIM_VALUE 0
#define RST_HAS_TRI 0
#define RST_HAS_OUT 0
#define RST_HAS_IN 1
#define RST_CAPTURE 1
#define RST_DATA_WIDTH 1
#define RST_RESET_VALUE 0
#define RST_EDGE_TYPE "FALLING"
#define RST_IRQ_TYPE "EDGE"
#define RST_BIT_CLEARING_EDGE_REGISTER 0
#define RST_BIT_MODIFYING_OUTPUT_REGISTER 0
#define RST_FREQ 100000000
#define ALT_MODULE_CLASS_RST altera_avalon_pio

/*
 * Oct_UP configuration
 *
 */

#define OCT_UP_NAME "/dev/Oct_UP"
#define OCT_UP_TYPE "altera_avalon_pio"
#define OCT_UP_BASE 0x0190a1a0
#define OCT_UP_SPAN 16
#define OCT_UP_IRQ 7
#define OCT_UP_IRQ_INTERRUPT_CONTROLLER_ID 0
#define OCT_UP_DO_TEST_BENCH_WIRING 0
#define OCT_UP_DRIVEN_SIM_VALUE 0
#define OCT_UP_HAS_TRI 0
#define OCT_UP_HAS_OUT 0
#define OCT_UP_HAS_IN 1
#define OCT_UP_CAPTURE 1
#define OCT_UP_DATA_WIDTH 1
#define OCT_UP_RESET_VALUE 0
#define OCT_UP_EDGE_TYPE "FALLING"
#define OCT_UP_IRQ_TYPE "EDGE"
#define OCT_UP_BIT_CLEARING_EDGE_REGISTER 0
#define OCT_UP_BIT_MODIFYING_OUTPUT_REGISTER 0
#define OCT_UP_FREQ 100000000
#define ALT_MODULE_CLASS_Oct_UP altera_avalon_pio

/*
 * Oct_DOWN configuration
 *
 */

#define OCT_DOWN_NAME "/dev/Oct_DOWN"
#define OCT_DOWN_TYPE "altera_avalon_pio"
#define OCT_DOWN_BASE 0x0190a1b0
#define OCT_DOWN_SPAN 16
#define OCT_DOWN_IRQ 8
#define OCT_DOWN_IRQ_INTERRUPT_CONTROLLER_ID 0
#define OCT_DOWN_DO_TEST_BENCH_WIRING 0
#define OCT_DOWN_DRIVEN_SIM_VALUE 0
#define OCT_DOWN_HAS_TRI 0
#define OCT_DOWN_HAS_OUT 0
#define OCT_DOWN_HAS_IN 1
#define OCT_DOWN_CAPTURE 1
#define OCT_DOWN_DATA_WIDTH 1
#define OCT_DOWN_RESET_VALUE 0
#define OCT_DOWN_EDGE_TYPE "FALLING"
#define OCT_DOWN_IRQ_TYPE "EDGE"
#define OCT_DOWN_BIT_CLEARING_EDGE_REGISTER 0
#define OCT_DOWN_BIT_MODIFYING_OUTPUT_REGISTER 0
#define OCT_DOWN_FREQ 100000000
#define ALT_MODULE_CLASS_Oct_DOWN altera_avalon_pio

/*
 * Accel_Control configuration
 *
 */

#define ACCEL_CONTROL_NAME "/dev/Accel_Control"
#define ACCEL_CONTROL_TYPE "accelerometer"
#define ACCEL_CONTROL_BASE 0x0190a080
#define ACCEL_CONTROL_SPAN 32
#define ALT_MODULE_CLASS_Accel_Control accelerometer

/*
 * i2c_master configuration
 *
 */

#define I2C_MASTER_NAME "/dev/i2c_master"
#define I2C_MASTER_TYPE "opencores_i2c_master"
#define I2C_MASTER_BASE 0x0190a0a0
#define I2C_MASTER_SPAN 32
#define I2C_MASTER_IRQ 10
#define I2C_MASTER_IRQ_INTERRUPT_CONTROLLER_ID 0
#define ALT_MODULE_CLASS_i2c_master opencores_i2c_master

/*
 * altpll_0 configuration
 *
 */

#define ALTPLL_0_NAME "/dev/altpll_0"
#define ALTPLL_0_TYPE "altpll"
#define ALTPLL_0_BASE 0x0190a1c0
#define ALTPLL_0_SPAN 16
#define ALT_MODULE_CLASS_altpll_0 altpll

/*
 * MicroC/OS-II configuration
 *
 */

#define ALT_MAX_FD 32
#define OS_MAX_TASKS 10
#define OS_LOWEST_PRIO 20
#define OS_FLAG_EN 1
#define OS_THREAD_SAFE_NEWLIB 1
#define OS_MUTEX_EN 1
#define OS_SEM_EN 1
#define OS_MBOX_EN 1
#define OS_Q_EN 1
#define OS_MEM_EN 1
#define OS_FLAG_WAIT_CLR_EN 1
#define OS_FLAG_ACCEPT_EN 1
#define OS_FLAG_DEL_EN 1
#define OS_FLAG_QUERY_EN 1
#define OS_FLAG_NAME_SIZE 32
#define OS_MAX_FLAGS 20
#define OS_FLAGS_NBITS 16
#define OS_MUTEX_ACCEPT_EN 1
#define OS_MUTEX_DEL_EN 1
#define OS_MUTEX_QUERY_EN 1
#define OS_SEM_ACCEPT_EN 1
#define OS_SEM_SET_EN 1
#define OS_SEM_DEL_EN 1
#define OS_SEM_QUERY_EN 1
#define OS_MBOX_ACCEPT_EN 1
#define OS_MBOX_DEL_EN 1
#define OS_MBOX_POST_EN 1
#define OS_MBOX_POST_OPT_EN 1
#define OS_MBOX_QUERY_EN 1
#define OS_Q_ACCEPT_EN 1
#define OS_Q_DEL_EN 1
#define OS_Q_FLUSH_EN 1
#define OS_Q_POST_EN 1
#define OS_Q_POST_FRONT_EN 1
#define OS_Q_POST_OPT_EN 1
#define OS_Q_QUERY_EN 1
#define OS_MAX_QS 20
#define OS_MEM_QUERY_EN 1
#define OS_MEM_NAME_SIZE 32
#define OS_MAX_MEM_PART 60
#define OS_ARG_CHK_EN 1
#define OS_CPU_HOOKS_EN 1
#define OS_DEBUG_EN 1
#define OS_SCHED_LOCK_EN 1
#define OS_TASK_STAT_EN 1
#define OS_TASK_STAT_STK_CHK_EN 1
#define OS_TICK_STEP_EN 1
#define OS_EVENT_NAME_SIZE 32
#define OS_MAX_EVENTS 60
#define OS_TASK_IDLE_STK_SIZE 512
#define OS_TASK_STAT_STK_SIZE 512
#define OS_TASK_CHANGE_PRIO_EN 1
#define OS_TASK_CREATE_EN 1
#define OS_TASK_CREATE_EXT_EN 1
#define OS_TASK_DEL_EN 1
#define OS_TASK_NAME_SIZE 32
#define OS_TASK_PROFILE_EN 1
#define OS_TASK_QUERY_EN 1
#define OS_TASK_SUSPEND_EN 1
#define OS_TASK_SW_HOOK_EN 1
#define OS_TIME_TICK_HOOK_EN 1
#define OS_TIME_GET_SET_EN 1
#define OS_TIME_DLY_RESUME_EN 1
#define OS_TIME_DLY_HMSM_EN 1
#define OS_TMR_EN 0
#define OS_TMR_CFG_MAX 16
#define OS_TMR_CFG_NAME_SIZE 16
#define OS_TMR_CFG_TICKS_PER_SEC 10
#define OS_TMR_CFG_WHEEL_SIZE 2
#define OS_TASK_TMR_STK_SIZE 512
#define OS_TASK_TMR_PRIO 1
#define ALT_SYS_CLK TIMER_0
#define ALT_TIMESTAMP_CLK none
#define OS_TICKS_PER_SEC 1000

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SDRAM_0
#define ALT_RODATA_DEVICE     SDRAM_0
#define ALT_RWDATA_DEVICE     SDRAM_0
#define ALT_EXCEPTIONS_DEVICE SDRAM_0
#define ALT_RESET_DEVICE      CFI_FLASH_0


#endif /* __SYSTEM_H_ */
