TimeQuest Timing Analyzer report for DE2_SD_Card_Audio
Fri Apr 12 14:17:40 2013
Quartus II Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow Model Fmax Summary
  7. Slow Model Setup Summary
  8. Slow Model Hold Summary
  9. Slow Model Recovery Summary
 10. Slow Model Removal Summary
 11. Slow Model Minimum Pulse Width Summary
 12. Slow Model Minimum Pulse Width: 'altera_reserved_tck'
 13. Propagation Delay
 14. Minimum Propagation Delay
 15. Fast Model Setup Summary
 16. Fast Model Hold Summary
 17. Fast Model Recovery Summary
 18. Fast Model Removal Summary
 19. Fast Model Minimum Pulse Width Summary
 20. Fast Model Minimum Pulse Width: 'altera_reserved_tck'
 21. Propagation Delay
 22. Minimum Propagation Delay
 23. Multicorner Timing Analysis Summary
 24. Progagation Delay
 25. Minimum Progagation Delay
 26. Clock Transfers
 27. Report TCCS
 28. Report RSKM
 29. Unconstrained Paths
 30. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                    ;
+--------------------+-----------------------------------------------------------------+
; Quartus II Version ; Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition ;
; Revision Name      ; DE2_SD_Card_Audio                                               ;
; Device Family      ; Cyclone II                                                      ;
; Device Name        ; EP2C35F672C6                                                    ;
; Timing Models      ; Final                                                           ;
; Delay Model        ; Combined                                                        ;
; Rise/Fall Delays   ; Unavailable                                                     ;
+--------------------+-----------------------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; SDC File List                                                                                                                                 ;
+-----------------------------------------------------------------------------------------------------------+--------+--------------------------+
; SDC File Path                                                                                             ; Status ; Read at                  ;
+-----------------------------------------------------------------------------------------------------------+--------+--------------------------+
; cpu_0.sdc                                                                                                 ; OK     ; Fri Apr 12 14:17:30 2013 ;
; /opt/altera/10.1sp1/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter/altera_avalon_clock_adapter.sdc ; OK     ; Fri Apr 12 14:17:31 2013 ;
+-----------------------------------------------------------------------------------------------------------+--------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                    ;
+---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+
; Clock Name          ; Type ; Period  ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                 ;
+---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+
; altera_reserved_tck ; Base ; 100.000 ; 10.0 MHz  ; 0.000 ; 50.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { altera_reserved_tck } ;
+---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+


---------------------------
; Slow Model Fmax Summary ;
---------------------------
No paths to report.


----------------------------
; Slow Model Setup Summary ;
----------------------------
No paths to report.


---------------------------
; Slow Model Hold Summary ;
---------------------------
No paths to report.


-------------------------------
; Slow Model Recovery Summary ;
-------------------------------
No paths to report.


------------------------------
; Slow Model Removal Summary ;
------------------------------
No paths to report.


+----------------------------------------------+
; Slow Model Minimum Pulse Width Summary       ;
+---------------------+--------+---------------+
; Clock               ; Slack  ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; 97.778 ; 0.000         ;
+---------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'altera_reserved_tck'                                                       ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock               ; Clock Edge ; Target              ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+
; 97.778 ; 100.000      ; 2.222          ; Port Rate ; altera_reserved_tck ; Rise       ; altera_reserved_tck ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+


+----------------------------------------------------------+
; Propagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CLOCK_27   ; AUD_XCK     ;       ; 2.917 ; 2.917 ;       ;
; CLOCK_50   ; DRAM_CLK    ; 0.868 ;       ;       ; 0.868 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CLOCK_27   ; AUD_XCK     ;       ; 2.917 ; 2.917 ;       ;
; CLOCK_50   ; DRAM_CLK    ; 0.868 ;       ;       ; 0.868 ;
+------------+-------------+-------+-------+-------+-------+


----------------------------
; Fast Model Setup Summary ;
----------------------------
No paths to report.


---------------------------
; Fast Model Hold Summary ;
---------------------------
No paths to report.


-------------------------------
; Fast Model Recovery Summary ;
-------------------------------
No paths to report.


------------------------------
; Fast Model Removal Summary ;
------------------------------
No paths to report.


+----------------------------------------------+
; Fast Model Minimum Pulse Width Summary       ;
+---------------------+--------+---------------+
; Clock               ; Slack  ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; 97.778 ; 0.000         ;
+---------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'altera_reserved_tck'                                                       ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock               ; Clock Edge ; Target              ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+
; 97.778 ; 100.000      ; 2.222          ; Port Rate ; altera_reserved_tck ; Rise       ; altera_reserved_tck ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+


+----------------------------------------------------------+
; Propagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CLOCK_27   ; AUD_XCK     ;       ; 1.463 ; 1.463 ;       ;
; CLOCK_50   ; DRAM_CLK    ; 0.154 ;       ;       ; 0.154 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CLOCK_27   ; AUD_XCK     ;       ; 1.463 ; 1.463 ;       ;
; CLOCK_50   ; DRAM_CLK    ; 0.154 ;       ;       ; 0.154 ;
+------------+-------------+-------+-------+-------+-------+


+--------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                            ;
+----------------------+-------+------+----------+---------+---------------------+
; Clock                ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+----------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack     ; N/A   ; N/A  ; N/A      ; N/A     ; 97.778              ;
;  altera_reserved_tck ; N/A   ; N/A  ; N/A      ; N/A     ; 97.778              ;
; Design-wide TNS      ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
;  altera_reserved_tck ; N/A   ; N/A  ; N/A      ; N/A     ; 0.000               ;
+----------------------+-------+------+----------+---------+---------------------+


+----------------------------------------------------------+
; Progagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CLOCK_27   ; AUD_XCK     ;       ; 2.917 ; 2.917 ;       ;
; CLOCK_50   ; DRAM_CLK    ; 0.868 ;       ;       ; 0.868 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Progagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CLOCK_27   ; AUD_XCK     ;       ; 1.463 ; 1.463 ;       ;
; CLOCK_50   ; DRAM_CLK    ; 0.154 ;       ;       ; 0.154 ;
+------------+-------------+-------+-------+-------+-------+


-------------------
; Clock Transfers ;
-------------------
Nothing to report.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 6     ; 6    ;
; Unconstrained Input Ports       ; 67    ; 67   ;
; Unconstrained Input Port Paths  ; 219   ; 219  ;
; Unconstrained Output Ports      ; 189   ; 189  ;
; Unconstrained Output Port Paths ; 810   ; 810  ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
    Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition
    Info: Processing started: Fri Apr 12 14:17:27 2013
Info: Command: quartus_sta DE2_SD_Card_Audio -c DE2_SD_Card_Audio
Info: qsta_default_script.tcl version: #4
Warning: Ignored assignments for entity "system_0_clock_1" -- entity does not exist in design
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[0] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[0]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[10] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[10]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[11] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[11]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[12] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[12]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[13] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[13]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[14] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[14]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[15] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[15]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[1] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[1]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[2] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[2]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[3] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[3]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[4] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[4]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[5] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[5]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[6] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[6]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[7] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[7]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[8] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[8]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[9] -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to slave_readdata[9]~reg0 -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[0] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[10] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[11] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[12] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[13] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[14] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[15] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[16] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[17] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[18] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[19] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[1] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[20] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[21] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[22] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[2] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[3] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[4] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[5] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[6] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[7] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[8] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_address_d1[9] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_byteenable_d1[0] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_byteenable_d1[1] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[0] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[10] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[11] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[12] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[13] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[14] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[15] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[16] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[17] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[18] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[19] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[1] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[20] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[21] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[2] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[3] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[4] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[5] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[6] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[7] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[8] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_nativeaddress_d1[9] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[0] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[10] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[11] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[12] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[13] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[14] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[15] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[1] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[2] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[3] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[4] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[5] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[6] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[7] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[8] -to * -entity system_0_clock_1 -tag quartusii was ignored
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from slave_writedata_d1[9] -to * -entity system_0_clock_1 -tag quartusii was ignored
Warning: Ignored assignments for entity "system_0_clock_1_bit_pipe" -- entity does not exist in design
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from data_in_d1 -to * -entity system_0_clock_1_bit_pipe -tag quartusii was ignored
Warning: Ignored assignments for entity "system_0_reset_clk_50_domain_synch_module" -- entity does not exist in design
    Warning: Assignment for entity set_instance_assignment -name CUT ON -from * -to data_in_d1 -entity system_0_reset_clk_50_domain_synch_module -tag quartusii was ignored
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[10]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[12]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[13]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[14]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[15]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[17]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[19]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[21]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[23]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[18]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[26]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[20]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[16]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[24]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[25]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[11]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[27]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[28]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[29]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[22]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[30]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[31]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[2]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[0]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[8]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[1]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[9]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[3]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[4]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[5]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[6]|combout" is a latch
    Warning: Node "u0|the_Accel_Control|accel_control|avalon_slave_readdata[7]|combout" is a latch
Critical Warning: Setting INCREMENTAL_COMPILATION to "OFF" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to "ON" instead.
Info: Evaluating HDL-embedded SDC commands
    Info: Entity alt_jtag_atlantic
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}] 
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_write}] -to [get_registers {*|alt_jtag_atlantic:*|read_write1*}] 
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
        Info: set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}]
        Info: set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}]
    Info: Entity altera_std_synchronizer
        Info: set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
    Info: Entity dcfifo_hlj1
        Info: set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_id9:dffpipe20|dffe21a* 
        Info: set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_hd9:dffpipe17|dffe18a* 
    Info: Entity sld_hub
        Info: create_clock -period 10MHz -name altera_reserved_tck [get_ports {altera_reserved_tck}]
        Info: set_clock_groups -asynchronous -group {altera_reserved_tck}
Info: Reading SDC File: 'cpu_0.sdc'
Info: Reading SDC File: '/opt/altera/10.1sp1/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter/altera_avalon_clock_adapter.sdc'
Warning: Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
Warning: Node: GPIO_0[15] was determined to be a clock but was found without an associated clock assignment.
Warning: Node: CLOCK_27 was determined to be a clock but was found without an associated clock assignment.
Warning: Node: I2C_AV_Config:u1|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
Warning: Node: system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|oAUD_BCK was determined to be a clock but was found without an associated clock assignment.
Warning: Node: system_0:u0|system_0_burst_32:the_system_0_burst_32|reg_downstream_read was determined to be a clock but was found without an associated clock assignment.
Warning: PLL cross checking found inconsistent PLL clock settings:
    Warning: Node: u0|the_altpll_0|sd1|pll|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
    Warning: Node: u0|the_altpll_0|sd1|pll|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
    Warning: Node: PLL2|altpll_component|pll|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 37.037
Info: Analyzing Slow Model
Info: No fmax paths to report
Info: No Setup paths to report
Info: No Hold paths to report
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is 97.778
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    97.778         0.000 altera_reserved_tck 
Info: The selected device family is not supported by the report_metastability command.
Info: Analyzing Fast Model
Info: Started post-fitting delay annotation
Warning: Found 265 output pins without output pin load capacitance assignment
    Info: Pin "DRAM_DQ[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_DQ[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_DQ[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_DQ[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_DQ[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_DQ[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_DQ[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_DQ[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_DQ[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_DATA[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_DATA[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_DATA[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_DATA[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_DATA[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_DATA[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_DATA[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_DATA[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SD_DAT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SD_DAT3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SD_CMD" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "I2C_SDAT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "AUD_ADCLRCK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "AUD_DACLRCK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "AUD_BCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[32]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[33]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[34]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_0[35]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[32]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[33]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[34]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPIO_1[35]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX1[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX1[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX1[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX1[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX1[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX1[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX1[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX2[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX2[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX2[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX2[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX2[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX2[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX2[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX3[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX3[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX3[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX3[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX3[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX3[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX3[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX4[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX4[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX4[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX4[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX4[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX4[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX4[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX5[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX5[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX5[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX5[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX5[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX5[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX5[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX6[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX6[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX6[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX6[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX6[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX6[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX6[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX7[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX7[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX7[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX7[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX7[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX7[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX7[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "UART_TXD" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "IRDA_TXD" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_LDQM" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_UDQM" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_WE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_CAS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_RAS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_CS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_BA_0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_BA_1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_CLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_CKE" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_ADDR[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_WE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_RST_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_OE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FL_CE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_ADDR[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_UB_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_LB_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_WE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_CE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_OE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_ON" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_BLON" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_RW" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_EN" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LCD_RS" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SD_CLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "I2C_SCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "AUD_DACDAT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "AUD_XCK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
Warning: Node: GPIO_0[15] was determined to be a clock but was found without an associated clock assignment.
Warning: Node: CLOCK_27 was determined to be a clock but was found without an associated clock assignment.
Warning: Node: I2C_AV_Config:u1|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
Warning: Node: system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|oAUD_BCK was determined to be a clock but was found without an associated clock assignment.
Warning: Node: system_0:u0|system_0_burst_32:the_system_0_burst_32|reg_downstream_read was determined to be a clock but was found without an associated clock assignment.
Warning: PLL cross checking found inconsistent PLL clock settings:
    Warning: Node: u0|the_altpll_0|sd1|pll|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
    Warning: Node: u0|the_altpll_0|sd1|pll|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
    Warning: Node: PLL2|altpll_component|pll|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 37.037
Info: No Setup paths to report
Info: No Hold paths to report
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is 97.778
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    97.778         0.000 altera_reserved_tck 
Info: The selected device family is not supported by the report_metastability command.
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 155 warnings
    Info: Peak virtual memory: 317 megabytes
    Info: Processing ended: Fri Apr 12 14:17:40 2013
    Info: Elapsed time: 00:00:13
    Info: Total CPU time (on all processors): 00:00:09


