//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0


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// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module Accel_Control_avalon_slave_arbitrator (
                                               // inputs:
                                                Accel_Control_avalon_slave_readdata,
                                                clk,
                                                reset_n,
                                                system_0_burst_32_downstream_address_to_slave,
                                                system_0_burst_32_downstream_arbitrationshare,
                                                system_0_burst_32_downstream_burstcount,
                                                system_0_burst_32_downstream_byteenable,
                                                system_0_burst_32_downstream_latency_counter,
                                                system_0_burst_32_downstream_read,
                                                system_0_burst_32_downstream_write,
                                                system_0_burst_32_downstream_writedata,

                                               // outputs:
                                                Accel_Control_avalon_slave_address,
                                                Accel_Control_avalon_slave_byteenable,
                                                Accel_Control_avalon_slave_chipselect,
                                                Accel_Control_avalon_slave_read,
                                                Accel_Control_avalon_slave_readdata_from_sa,
                                                Accel_Control_avalon_slave_reset_n,
                                                Accel_Control_avalon_slave_write_n,
                                                Accel_Control_avalon_slave_writedata,
                                                d1_Accel_Control_avalon_slave_end_xfer,
                                                system_0_burst_32_downstream_granted_Accel_Control_avalon_slave,
                                                system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave,
                                                system_0_burst_32_downstream_read_data_valid_Accel_Control_avalon_slave,
                                                system_0_burst_32_downstream_requests_Accel_Control_avalon_slave
                                             )
;

  output  [  2: 0] Accel_Control_avalon_slave_address;
  output  [  3: 0] Accel_Control_avalon_slave_byteenable;
  output           Accel_Control_avalon_slave_chipselect;
  output           Accel_Control_avalon_slave_read;
  output  [ 31: 0] Accel_Control_avalon_slave_readdata_from_sa;
  output           Accel_Control_avalon_slave_reset_n;
  output           Accel_Control_avalon_slave_write_n;
  output  [ 31: 0] Accel_Control_avalon_slave_writedata;
  output           d1_Accel_Control_avalon_slave_end_xfer;
  output           system_0_burst_32_downstream_granted_Accel_Control_avalon_slave;
  output           system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave;
  output           system_0_burst_32_downstream_read_data_valid_Accel_Control_avalon_slave;
  output           system_0_burst_32_downstream_requests_Accel_Control_avalon_slave;
  input   [ 31: 0] Accel_Control_avalon_slave_readdata;
  input            clk;
  input            reset_n;
  input   [  4: 0] system_0_burst_32_downstream_address_to_slave;
  input   [  3: 0] system_0_burst_32_downstream_arbitrationshare;
  input            system_0_burst_32_downstream_burstcount;
  input   [  3: 0] system_0_burst_32_downstream_byteenable;
  input            system_0_burst_32_downstream_latency_counter;
  input            system_0_burst_32_downstream_read;
  input            system_0_burst_32_downstream_write;
  input   [ 31: 0] system_0_burst_32_downstream_writedata;

  wire    [  2: 0] Accel_Control_avalon_slave_address;
  wire             Accel_Control_avalon_slave_allgrants;
  wire             Accel_Control_avalon_slave_allow_new_arb_cycle;
  wire             Accel_Control_avalon_slave_any_bursting_master_saved_grant;
  wire             Accel_Control_avalon_slave_any_continuerequest;
  wire             Accel_Control_avalon_slave_arb_counter_enable;
  reg     [  3: 0] Accel_Control_avalon_slave_arb_share_counter;
  wire    [  3: 0] Accel_Control_avalon_slave_arb_share_counter_next_value;
  wire    [  3: 0] Accel_Control_avalon_slave_arb_share_set_values;
  wire             Accel_Control_avalon_slave_beginbursttransfer_internal;
  wire             Accel_Control_avalon_slave_begins_xfer;
  wire    [  3: 0] Accel_Control_avalon_slave_byteenable;
  wire             Accel_Control_avalon_slave_chipselect;
  wire             Accel_Control_avalon_slave_end_xfer;
  wire             Accel_Control_avalon_slave_firsttransfer;
  wire             Accel_Control_avalon_slave_grant_vector;
  wire             Accel_Control_avalon_slave_in_a_read_cycle;
  wire             Accel_Control_avalon_slave_in_a_write_cycle;
  wire             Accel_Control_avalon_slave_master_qreq_vector;
  wire             Accel_Control_avalon_slave_non_bursting_master_requests;
  wire             Accel_Control_avalon_slave_read;
  wire    [ 31: 0] Accel_Control_avalon_slave_readdata_from_sa;
  reg              Accel_Control_avalon_slave_reg_firsttransfer;
  wire             Accel_Control_avalon_slave_reset_n;
  reg              Accel_Control_avalon_slave_slavearbiterlockenable;
  wire             Accel_Control_avalon_slave_slavearbiterlockenable2;
  wire             Accel_Control_avalon_slave_unreg_firsttransfer;
  wire             Accel_Control_avalon_slave_waits_for_read;
  wire             Accel_Control_avalon_slave_waits_for_write;
  wire             Accel_Control_avalon_slave_write_n;
  wire    [ 31: 0] Accel_Control_avalon_slave_writedata;
  reg              d1_Accel_Control_avalon_slave_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_Accel_Control_avalon_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  4: 0] shifted_address_to_Accel_Control_avalon_slave_from_system_0_burst_32_downstream;
  wire             system_0_burst_32_downstream_arbiterlock;
  wire             system_0_burst_32_downstream_arbiterlock2;
  wire             system_0_burst_32_downstream_continuerequest;
  wire             system_0_burst_32_downstream_granted_Accel_Control_avalon_slave;
  wire             system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave;
  wire             system_0_burst_32_downstream_read_data_valid_Accel_Control_avalon_slave;
  wire             system_0_burst_32_downstream_requests_Accel_Control_avalon_slave;
  wire             system_0_burst_32_downstream_saved_grant_Accel_Control_avalon_slave;
  wire             wait_for_Accel_Control_avalon_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~Accel_Control_avalon_slave_end_xfer;
    end


  assign Accel_Control_avalon_slave_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave));
  //assign Accel_Control_avalon_slave_readdata_from_sa = Accel_Control_avalon_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign Accel_Control_avalon_slave_readdata_from_sa = Accel_Control_avalon_slave_readdata;

  assign system_0_burst_32_downstream_requests_Accel_Control_avalon_slave = (1) & (system_0_burst_32_downstream_read | system_0_burst_32_downstream_write);
  //Accel_Control_avalon_slave_arb_share_counter set values, which is an e_mux
  assign Accel_Control_avalon_slave_arb_share_set_values = (system_0_burst_32_downstream_granted_Accel_Control_avalon_slave)? system_0_burst_32_downstream_arbitrationshare :
    1;

  //Accel_Control_avalon_slave_non_bursting_master_requests mux, which is an e_mux
  assign Accel_Control_avalon_slave_non_bursting_master_requests = 0;

  //Accel_Control_avalon_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign Accel_Control_avalon_slave_any_bursting_master_saved_grant = system_0_burst_32_downstream_saved_grant_Accel_Control_avalon_slave;

  //Accel_Control_avalon_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign Accel_Control_avalon_slave_arb_share_counter_next_value = Accel_Control_avalon_slave_firsttransfer ? (Accel_Control_avalon_slave_arb_share_set_values - 1) : |Accel_Control_avalon_slave_arb_share_counter ? (Accel_Control_avalon_slave_arb_share_counter - 1) : 0;

  //Accel_Control_avalon_slave_allgrants all slave grants, which is an e_mux
  assign Accel_Control_avalon_slave_allgrants = |Accel_Control_avalon_slave_grant_vector;

  //Accel_Control_avalon_slave_end_xfer assignment, which is an e_assign
  assign Accel_Control_avalon_slave_end_xfer = ~(Accel_Control_avalon_slave_waits_for_read | Accel_Control_avalon_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_Accel_Control_avalon_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_Accel_Control_avalon_slave = Accel_Control_avalon_slave_end_xfer & (~Accel_Control_avalon_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //Accel_Control_avalon_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign Accel_Control_avalon_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_Accel_Control_avalon_slave & Accel_Control_avalon_slave_allgrants) | (end_xfer_arb_share_counter_term_Accel_Control_avalon_slave & ~Accel_Control_avalon_slave_non_bursting_master_requests);

  //Accel_Control_avalon_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Accel_Control_avalon_slave_arb_share_counter <= 0;
      else if (Accel_Control_avalon_slave_arb_counter_enable)
          Accel_Control_avalon_slave_arb_share_counter <= Accel_Control_avalon_slave_arb_share_counter_next_value;
    end


  //Accel_Control_avalon_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Accel_Control_avalon_slave_slavearbiterlockenable <= 0;
      else if ((|Accel_Control_avalon_slave_master_qreq_vector & end_xfer_arb_share_counter_term_Accel_Control_avalon_slave) | (end_xfer_arb_share_counter_term_Accel_Control_avalon_slave & ~Accel_Control_avalon_slave_non_bursting_master_requests))
          Accel_Control_avalon_slave_slavearbiterlockenable <= |Accel_Control_avalon_slave_arb_share_counter_next_value;
    end


  //system_0_burst_32/downstream Accel_Control/avalon_slave arbiterlock, which is an e_assign
  assign system_0_burst_32_downstream_arbiterlock = Accel_Control_avalon_slave_slavearbiterlockenable & system_0_burst_32_downstream_continuerequest;

  //Accel_Control_avalon_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign Accel_Control_avalon_slave_slavearbiterlockenable2 = |Accel_Control_avalon_slave_arb_share_counter_next_value;

  //system_0_burst_32/downstream Accel_Control/avalon_slave arbiterlock2, which is an e_assign
  assign system_0_burst_32_downstream_arbiterlock2 = Accel_Control_avalon_slave_slavearbiterlockenable2 & system_0_burst_32_downstream_continuerequest;

  //Accel_Control_avalon_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign Accel_Control_avalon_slave_any_continuerequest = 1;

  //system_0_burst_32_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_32_downstream_continuerequest = 1;

  assign system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave = system_0_burst_32_downstream_requests_Accel_Control_avalon_slave & ~((system_0_burst_32_downstream_read & ((system_0_burst_32_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_32_downstream_read_data_valid_Accel_Control_avalon_slave, which is an e_mux
  assign system_0_burst_32_downstream_read_data_valid_Accel_Control_avalon_slave = system_0_burst_32_downstream_granted_Accel_Control_avalon_slave & system_0_burst_32_downstream_read & ~Accel_Control_avalon_slave_waits_for_read;

  //Accel_Control_avalon_slave_writedata mux, which is an e_mux
  assign Accel_Control_avalon_slave_writedata = system_0_burst_32_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_32_downstream_granted_Accel_Control_avalon_slave = system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave;

  //system_0_burst_32/downstream saved-grant Accel_Control/avalon_slave, which is an e_assign
  assign system_0_burst_32_downstream_saved_grant_Accel_Control_avalon_slave = system_0_burst_32_downstream_requests_Accel_Control_avalon_slave;

  //allow new arb cycle for Accel_Control/avalon_slave, which is an e_assign
  assign Accel_Control_avalon_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign Accel_Control_avalon_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign Accel_Control_avalon_slave_master_qreq_vector = 1;

  //Accel_Control_avalon_slave_reset_n assignment, which is an e_assign
  assign Accel_Control_avalon_slave_reset_n = reset_n;

  assign Accel_Control_avalon_slave_chipselect = system_0_burst_32_downstream_granted_Accel_Control_avalon_slave;
  //Accel_Control_avalon_slave_firsttransfer first transaction, which is an e_assign
  assign Accel_Control_avalon_slave_firsttransfer = Accel_Control_avalon_slave_begins_xfer ? Accel_Control_avalon_slave_unreg_firsttransfer : Accel_Control_avalon_slave_reg_firsttransfer;

  //Accel_Control_avalon_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign Accel_Control_avalon_slave_unreg_firsttransfer = ~(Accel_Control_avalon_slave_slavearbiterlockenable & Accel_Control_avalon_slave_any_continuerequest);

  //Accel_Control_avalon_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Accel_Control_avalon_slave_reg_firsttransfer <= 1'b1;
      else if (Accel_Control_avalon_slave_begins_xfer)
          Accel_Control_avalon_slave_reg_firsttransfer <= Accel_Control_avalon_slave_unreg_firsttransfer;
    end


  //Accel_Control_avalon_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign Accel_Control_avalon_slave_beginbursttransfer_internal = Accel_Control_avalon_slave_begins_xfer;

  //Accel_Control_avalon_slave_read assignment, which is an e_mux
  assign Accel_Control_avalon_slave_read = system_0_burst_32_downstream_granted_Accel_Control_avalon_slave & system_0_burst_32_downstream_read;

  //~Accel_Control_avalon_slave_write_n assignment, which is an e_mux
  assign Accel_Control_avalon_slave_write_n = ~(system_0_burst_32_downstream_granted_Accel_Control_avalon_slave & system_0_burst_32_downstream_write);

  assign shifted_address_to_Accel_Control_avalon_slave_from_system_0_burst_32_downstream = system_0_burst_32_downstream_address_to_slave;
  //Accel_Control_avalon_slave_address mux, which is an e_mux
  assign Accel_Control_avalon_slave_address = shifted_address_to_Accel_Control_avalon_slave_from_system_0_burst_32_downstream >> 2;

  //d1_Accel_Control_avalon_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_Accel_Control_avalon_slave_end_xfer <= 1;
      else 
        d1_Accel_Control_avalon_slave_end_xfer <= Accel_Control_avalon_slave_end_xfer;
    end


  //Accel_Control_avalon_slave_waits_for_read in a cycle, which is an e_mux
  assign Accel_Control_avalon_slave_waits_for_read = Accel_Control_avalon_slave_in_a_read_cycle & Accel_Control_avalon_slave_begins_xfer;

  //Accel_Control_avalon_slave_in_a_read_cycle assignment, which is an e_assign
  assign Accel_Control_avalon_slave_in_a_read_cycle = system_0_burst_32_downstream_granted_Accel_Control_avalon_slave & system_0_burst_32_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = Accel_Control_avalon_slave_in_a_read_cycle;

  //Accel_Control_avalon_slave_waits_for_write in a cycle, which is an e_mux
  assign Accel_Control_avalon_slave_waits_for_write = Accel_Control_avalon_slave_in_a_write_cycle & 0;

  //Accel_Control_avalon_slave_in_a_write_cycle assignment, which is an e_assign
  assign Accel_Control_avalon_slave_in_a_write_cycle = system_0_burst_32_downstream_granted_Accel_Control_avalon_slave & system_0_burst_32_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = Accel_Control_avalon_slave_in_a_write_cycle;

  assign wait_for_Accel_Control_avalon_slave_counter = 0;
  //Accel_Control_avalon_slave_byteenable byte enable port mux, which is an e_mux
  assign Accel_Control_avalon_slave_byteenable = (system_0_burst_32_downstream_granted_Accel_Control_avalon_slave)? system_0_burst_32_downstream_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //Accel_Control/avalon_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_32/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_32_downstream_requests_Accel_Control_avalon_slave && (system_0_burst_32_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_32/downstream drove 0 on its 'arbitrationshare' port while accessing slave Accel_Control/avalon_slave", $time);
          $stop;
        end
    end


  //system_0_burst_32/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_32_downstream_requests_Accel_Control_avalon_slave && (system_0_burst_32_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_32/downstream drove 0 on its 'burstcount' port while accessing slave Accel_Control/avalon_slave", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module Audio_0_avalon_slave_0_arbitrator (
                                           // inputs:
                                            Audio_0_avalon_slave_0_readdata,
                                            clk,
                                            reset_n,
                                            system_0_burst_16_downstream_address_to_slave,
                                            system_0_burst_16_downstream_arbitrationshare,
                                            system_0_burst_16_downstream_burstcount,
                                            system_0_burst_16_downstream_latency_counter,
                                            system_0_burst_16_downstream_read,
                                            system_0_burst_16_downstream_write,
                                            system_0_burst_16_downstream_writedata,

                                           // outputs:
                                            Audio_0_avalon_slave_0_readdata_from_sa,
                                            Audio_0_avalon_slave_0_reset_n,
                                            Audio_0_avalon_slave_0_write,
                                            Audio_0_avalon_slave_0_writedata,
                                            d1_Audio_0_avalon_slave_0_end_xfer,
                                            system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0,
                                            system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0,
                                            system_0_burst_16_downstream_read_data_valid_Audio_0_avalon_slave_0,
                                            system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0
                                         )
;

  output  [ 15: 0] Audio_0_avalon_slave_0_readdata_from_sa;
  output           Audio_0_avalon_slave_0_reset_n;
  output           Audio_0_avalon_slave_0_write;
  output  [ 15: 0] Audio_0_avalon_slave_0_writedata;
  output           d1_Audio_0_avalon_slave_0_end_xfer;
  output           system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0;
  output           system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0;
  output           system_0_burst_16_downstream_read_data_valid_Audio_0_avalon_slave_0;
  output           system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0;
  input   [ 15: 0] Audio_0_avalon_slave_0_readdata;
  input            clk;
  input            reset_n;
  input            system_0_burst_16_downstream_address_to_slave;
  input   [  4: 0] system_0_burst_16_downstream_arbitrationshare;
  input            system_0_burst_16_downstream_burstcount;
  input            system_0_burst_16_downstream_latency_counter;
  input            system_0_burst_16_downstream_read;
  input            system_0_burst_16_downstream_write;
  input   [ 15: 0] system_0_burst_16_downstream_writedata;

  wire             Audio_0_avalon_slave_0_allgrants;
  wire             Audio_0_avalon_slave_0_allow_new_arb_cycle;
  wire             Audio_0_avalon_slave_0_any_bursting_master_saved_grant;
  wire             Audio_0_avalon_slave_0_any_continuerequest;
  wire             Audio_0_avalon_slave_0_arb_counter_enable;
  reg     [  4: 0] Audio_0_avalon_slave_0_arb_share_counter;
  wire    [  4: 0] Audio_0_avalon_slave_0_arb_share_counter_next_value;
  wire    [  4: 0] Audio_0_avalon_slave_0_arb_share_set_values;
  wire             Audio_0_avalon_slave_0_beginbursttransfer_internal;
  wire             Audio_0_avalon_slave_0_begins_xfer;
  wire             Audio_0_avalon_slave_0_end_xfer;
  wire             Audio_0_avalon_slave_0_firsttransfer;
  wire             Audio_0_avalon_slave_0_grant_vector;
  wire             Audio_0_avalon_slave_0_in_a_read_cycle;
  wire             Audio_0_avalon_slave_0_in_a_write_cycle;
  wire             Audio_0_avalon_slave_0_master_qreq_vector;
  wire             Audio_0_avalon_slave_0_non_bursting_master_requests;
  wire    [ 15: 0] Audio_0_avalon_slave_0_readdata_from_sa;
  reg              Audio_0_avalon_slave_0_reg_firsttransfer;
  wire             Audio_0_avalon_slave_0_reset_n;
  reg              Audio_0_avalon_slave_0_slavearbiterlockenable;
  wire             Audio_0_avalon_slave_0_slavearbiterlockenable2;
  wire             Audio_0_avalon_slave_0_unreg_firsttransfer;
  wire             Audio_0_avalon_slave_0_waits_for_read;
  wire             Audio_0_avalon_slave_0_waits_for_write;
  wire             Audio_0_avalon_slave_0_write;
  wire    [ 15: 0] Audio_0_avalon_slave_0_writedata;
  reg              d1_Audio_0_avalon_slave_0_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_Audio_0_avalon_slave_0;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             system_0_burst_16_downstream_arbiterlock;
  wire             system_0_burst_16_downstream_arbiterlock2;
  wire             system_0_burst_16_downstream_continuerequest;
  wire             system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0;
  wire             system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0;
  wire             system_0_burst_16_downstream_read_data_valid_Audio_0_avalon_slave_0;
  wire             system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0;
  wire             system_0_burst_16_downstream_saved_grant_Audio_0_avalon_slave_0;
  wire             wait_for_Audio_0_avalon_slave_0_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~Audio_0_avalon_slave_0_end_xfer;
    end


  assign Audio_0_avalon_slave_0_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0));
  //assign Audio_0_avalon_slave_0_readdata_from_sa = Audio_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign Audio_0_avalon_slave_0_readdata_from_sa = Audio_0_avalon_slave_0_readdata;

  assign system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0 = (1) & (system_0_burst_16_downstream_read | system_0_burst_16_downstream_write);
  //Audio_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
  assign Audio_0_avalon_slave_0_arb_share_set_values = (system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0)? system_0_burst_16_downstream_arbitrationshare :
    1;

  //Audio_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
  assign Audio_0_avalon_slave_0_non_bursting_master_requests = 0;

  //Audio_0_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
  assign Audio_0_avalon_slave_0_any_bursting_master_saved_grant = system_0_burst_16_downstream_saved_grant_Audio_0_avalon_slave_0;

  //Audio_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
  assign Audio_0_avalon_slave_0_arb_share_counter_next_value = Audio_0_avalon_slave_0_firsttransfer ? (Audio_0_avalon_slave_0_arb_share_set_values - 1) : |Audio_0_avalon_slave_0_arb_share_counter ? (Audio_0_avalon_slave_0_arb_share_counter - 1) : 0;

  //Audio_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
  assign Audio_0_avalon_slave_0_allgrants = |Audio_0_avalon_slave_0_grant_vector;

  //Audio_0_avalon_slave_0_end_xfer assignment, which is an e_assign
  assign Audio_0_avalon_slave_0_end_xfer = ~(Audio_0_avalon_slave_0_waits_for_read | Audio_0_avalon_slave_0_waits_for_write);

  //end_xfer_arb_share_counter_term_Audio_0_avalon_slave_0 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_Audio_0_avalon_slave_0 = Audio_0_avalon_slave_0_end_xfer & (~Audio_0_avalon_slave_0_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //Audio_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
  assign Audio_0_avalon_slave_0_arb_counter_enable = (end_xfer_arb_share_counter_term_Audio_0_avalon_slave_0 & Audio_0_avalon_slave_0_allgrants) | (end_xfer_arb_share_counter_term_Audio_0_avalon_slave_0 & ~Audio_0_avalon_slave_0_non_bursting_master_requests);

  //Audio_0_avalon_slave_0_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Audio_0_avalon_slave_0_arb_share_counter <= 0;
      else if (Audio_0_avalon_slave_0_arb_counter_enable)
          Audio_0_avalon_slave_0_arb_share_counter <= Audio_0_avalon_slave_0_arb_share_counter_next_value;
    end


  //Audio_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Audio_0_avalon_slave_0_slavearbiterlockenable <= 0;
      else if ((|Audio_0_avalon_slave_0_master_qreq_vector & end_xfer_arb_share_counter_term_Audio_0_avalon_slave_0) | (end_xfer_arb_share_counter_term_Audio_0_avalon_slave_0 & ~Audio_0_avalon_slave_0_non_bursting_master_requests))
          Audio_0_avalon_slave_0_slavearbiterlockenable <= |Audio_0_avalon_slave_0_arb_share_counter_next_value;
    end


  //system_0_burst_16/downstream Audio_0/avalon_slave_0 arbiterlock, which is an e_assign
  assign system_0_burst_16_downstream_arbiterlock = Audio_0_avalon_slave_0_slavearbiterlockenable & system_0_burst_16_downstream_continuerequest;

  //Audio_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign Audio_0_avalon_slave_0_slavearbiterlockenable2 = |Audio_0_avalon_slave_0_arb_share_counter_next_value;

  //system_0_burst_16/downstream Audio_0/avalon_slave_0 arbiterlock2, which is an e_assign
  assign system_0_burst_16_downstream_arbiterlock2 = Audio_0_avalon_slave_0_slavearbiterlockenable2 & system_0_burst_16_downstream_continuerequest;

  //Audio_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
  assign Audio_0_avalon_slave_0_any_continuerequest = 1;

  //system_0_burst_16_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_16_downstream_continuerequest = 1;

  assign system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0 = system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0 & ~((system_0_burst_16_downstream_read & ((system_0_burst_16_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_16_downstream_read_data_valid_Audio_0_avalon_slave_0, which is an e_mux
  assign system_0_burst_16_downstream_read_data_valid_Audio_0_avalon_slave_0 = system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0 & system_0_burst_16_downstream_read & ~Audio_0_avalon_slave_0_waits_for_read;

  //Audio_0_avalon_slave_0_writedata mux, which is an e_mux
  assign Audio_0_avalon_slave_0_writedata = system_0_burst_16_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0 = system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0;

  //system_0_burst_16/downstream saved-grant Audio_0/avalon_slave_0, which is an e_assign
  assign system_0_burst_16_downstream_saved_grant_Audio_0_avalon_slave_0 = system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0;

  //allow new arb cycle for Audio_0/avalon_slave_0, which is an e_assign
  assign Audio_0_avalon_slave_0_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign Audio_0_avalon_slave_0_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign Audio_0_avalon_slave_0_master_qreq_vector = 1;

  //Audio_0_avalon_slave_0_reset_n assignment, which is an e_assign
  assign Audio_0_avalon_slave_0_reset_n = reset_n;

  //Audio_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
  assign Audio_0_avalon_slave_0_firsttransfer = Audio_0_avalon_slave_0_begins_xfer ? Audio_0_avalon_slave_0_unreg_firsttransfer : Audio_0_avalon_slave_0_reg_firsttransfer;

  //Audio_0_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
  assign Audio_0_avalon_slave_0_unreg_firsttransfer = ~(Audio_0_avalon_slave_0_slavearbiterlockenable & Audio_0_avalon_slave_0_any_continuerequest);

  //Audio_0_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Audio_0_avalon_slave_0_reg_firsttransfer <= 1'b1;
      else if (Audio_0_avalon_slave_0_begins_xfer)
          Audio_0_avalon_slave_0_reg_firsttransfer <= Audio_0_avalon_slave_0_unreg_firsttransfer;
    end


  //Audio_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign Audio_0_avalon_slave_0_beginbursttransfer_internal = Audio_0_avalon_slave_0_begins_xfer;

  //Audio_0_avalon_slave_0_write assignment, which is an e_mux
  assign Audio_0_avalon_slave_0_write = system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0 & system_0_burst_16_downstream_write;

  //d1_Audio_0_avalon_slave_0_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_Audio_0_avalon_slave_0_end_xfer <= 1;
      else 
        d1_Audio_0_avalon_slave_0_end_xfer <= Audio_0_avalon_slave_0_end_xfer;
    end


  //Audio_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
  assign Audio_0_avalon_slave_0_waits_for_read = Audio_0_avalon_slave_0_in_a_read_cycle & 0;

  //Audio_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
  assign Audio_0_avalon_slave_0_in_a_read_cycle = system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0 & system_0_burst_16_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = Audio_0_avalon_slave_0_in_a_read_cycle;

  //Audio_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
  assign Audio_0_avalon_slave_0_waits_for_write = Audio_0_avalon_slave_0_in_a_write_cycle & 0;

  //Audio_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
  assign Audio_0_avalon_slave_0_in_a_write_cycle = system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0 & system_0_burst_16_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = Audio_0_avalon_slave_0_in_a_write_cycle;

  assign wait_for_Audio_0_avalon_slave_0_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //Audio_0/avalon_slave_0 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_16/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0 && (system_0_burst_16_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_16/downstream drove 0 on its 'arbitrationshare' port while accessing slave Audio_0/avalon_slave_0", $time);
          $stop;
        end
    end


  //system_0_burst_16/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0 && (system_0_burst_16_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_16/downstream drove 0 on its 'burstcount' port while accessing slave Audio_0/avalon_slave_0", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module MS_s1_arbitrator (
                          // inputs:
                           MS_s1_irq,
                           MS_s1_readdata,
                           clk,
                           reset_n,
                           system_0_burst_27_downstream_address_to_slave,
                           system_0_burst_27_downstream_arbitrationshare,
                           system_0_burst_27_downstream_burstcount,
                           system_0_burst_27_downstream_latency_counter,
                           system_0_burst_27_downstream_nativeaddress,
                           system_0_burst_27_downstream_read,
                           system_0_burst_27_downstream_write,
                           system_0_burst_27_downstream_writedata,

                          // outputs:
                           MS_s1_address,
                           MS_s1_chipselect,
                           MS_s1_irq_from_sa,
                           MS_s1_readdata_from_sa,
                           MS_s1_reset_n,
                           MS_s1_write_n,
                           MS_s1_writedata,
                           d1_MS_s1_end_xfer,
                           system_0_burst_27_downstream_granted_MS_s1,
                           system_0_burst_27_downstream_qualified_request_MS_s1,
                           system_0_burst_27_downstream_read_data_valid_MS_s1,
                           system_0_burst_27_downstream_requests_MS_s1
                        )
;

  output  [  1: 0] MS_s1_address;
  output           MS_s1_chipselect;
  output           MS_s1_irq_from_sa;
  output           MS_s1_readdata_from_sa;
  output           MS_s1_reset_n;
  output           MS_s1_write_n;
  output           MS_s1_writedata;
  output           d1_MS_s1_end_xfer;
  output           system_0_burst_27_downstream_granted_MS_s1;
  output           system_0_burst_27_downstream_qualified_request_MS_s1;
  output           system_0_burst_27_downstream_read_data_valid_MS_s1;
  output           system_0_burst_27_downstream_requests_MS_s1;
  input            MS_s1_irq;
  input            MS_s1_readdata;
  input            clk;
  input            reset_n;
  input   [  1: 0] system_0_burst_27_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_27_downstream_arbitrationshare;
  input            system_0_burst_27_downstream_burstcount;
  input            system_0_burst_27_downstream_latency_counter;
  input   [  1: 0] system_0_burst_27_downstream_nativeaddress;
  input            system_0_burst_27_downstream_read;
  input            system_0_burst_27_downstream_write;
  input   [  7: 0] system_0_burst_27_downstream_writedata;

  wire    [  1: 0] MS_s1_address;
  wire             MS_s1_allgrants;
  wire             MS_s1_allow_new_arb_cycle;
  wire             MS_s1_any_bursting_master_saved_grant;
  wire             MS_s1_any_continuerequest;
  wire             MS_s1_arb_counter_enable;
  reg     [  5: 0] MS_s1_arb_share_counter;
  wire    [  5: 0] MS_s1_arb_share_counter_next_value;
  wire    [  5: 0] MS_s1_arb_share_set_values;
  wire             MS_s1_beginbursttransfer_internal;
  wire             MS_s1_begins_xfer;
  wire             MS_s1_chipselect;
  wire             MS_s1_end_xfer;
  wire             MS_s1_firsttransfer;
  wire             MS_s1_grant_vector;
  wire             MS_s1_in_a_read_cycle;
  wire             MS_s1_in_a_write_cycle;
  wire             MS_s1_irq_from_sa;
  wire             MS_s1_master_qreq_vector;
  wire             MS_s1_non_bursting_master_requests;
  wire             MS_s1_readdata_from_sa;
  reg              MS_s1_reg_firsttransfer;
  wire             MS_s1_reset_n;
  reg              MS_s1_slavearbiterlockenable;
  wire             MS_s1_slavearbiterlockenable2;
  wire             MS_s1_unreg_firsttransfer;
  wire             MS_s1_waits_for_read;
  wire             MS_s1_waits_for_write;
  wire             MS_s1_write_n;
  wire             MS_s1_writedata;
  reg              d1_MS_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_MS_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             system_0_burst_27_downstream_arbiterlock;
  wire             system_0_burst_27_downstream_arbiterlock2;
  wire             system_0_burst_27_downstream_continuerequest;
  wire             system_0_burst_27_downstream_granted_MS_s1;
  wire             system_0_burst_27_downstream_qualified_request_MS_s1;
  wire             system_0_burst_27_downstream_read_data_valid_MS_s1;
  wire             system_0_burst_27_downstream_requests_MS_s1;
  wire             system_0_burst_27_downstream_saved_grant_MS_s1;
  wire             wait_for_MS_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~MS_s1_end_xfer;
    end


  assign MS_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_27_downstream_qualified_request_MS_s1));
  //assign MS_s1_readdata_from_sa = MS_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign MS_s1_readdata_from_sa = MS_s1_readdata;

  assign system_0_burst_27_downstream_requests_MS_s1 = (1) & (system_0_burst_27_downstream_read | system_0_burst_27_downstream_write);
  //MS_s1_arb_share_counter set values, which is an e_mux
  assign MS_s1_arb_share_set_values = (system_0_burst_27_downstream_granted_MS_s1)? system_0_burst_27_downstream_arbitrationshare :
    1;

  //MS_s1_non_bursting_master_requests mux, which is an e_mux
  assign MS_s1_non_bursting_master_requests = 0;

  //MS_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign MS_s1_any_bursting_master_saved_grant = system_0_burst_27_downstream_saved_grant_MS_s1;

  //MS_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign MS_s1_arb_share_counter_next_value = MS_s1_firsttransfer ? (MS_s1_arb_share_set_values - 1) : |MS_s1_arb_share_counter ? (MS_s1_arb_share_counter - 1) : 0;

  //MS_s1_allgrants all slave grants, which is an e_mux
  assign MS_s1_allgrants = |MS_s1_grant_vector;

  //MS_s1_end_xfer assignment, which is an e_assign
  assign MS_s1_end_xfer = ~(MS_s1_waits_for_read | MS_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_MS_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_MS_s1 = MS_s1_end_xfer & (~MS_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //MS_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign MS_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_MS_s1 & MS_s1_allgrants) | (end_xfer_arb_share_counter_term_MS_s1 & ~MS_s1_non_bursting_master_requests);

  //MS_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          MS_s1_arb_share_counter <= 0;
      else if (MS_s1_arb_counter_enable)
          MS_s1_arb_share_counter <= MS_s1_arb_share_counter_next_value;
    end


  //MS_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          MS_s1_slavearbiterlockenable <= 0;
      else if ((|MS_s1_master_qreq_vector & end_xfer_arb_share_counter_term_MS_s1) | (end_xfer_arb_share_counter_term_MS_s1 & ~MS_s1_non_bursting_master_requests))
          MS_s1_slavearbiterlockenable <= |MS_s1_arb_share_counter_next_value;
    end


  //system_0_burst_27/downstream MS/s1 arbiterlock, which is an e_assign
  assign system_0_burst_27_downstream_arbiterlock = MS_s1_slavearbiterlockenable & system_0_burst_27_downstream_continuerequest;

  //MS_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign MS_s1_slavearbiterlockenable2 = |MS_s1_arb_share_counter_next_value;

  //system_0_burst_27/downstream MS/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_27_downstream_arbiterlock2 = MS_s1_slavearbiterlockenable2 & system_0_burst_27_downstream_continuerequest;

  //MS_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign MS_s1_any_continuerequest = 1;

  //system_0_burst_27_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_27_downstream_continuerequest = 1;

  assign system_0_burst_27_downstream_qualified_request_MS_s1 = system_0_burst_27_downstream_requests_MS_s1 & ~((system_0_burst_27_downstream_read & ((system_0_burst_27_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_27_downstream_read_data_valid_MS_s1, which is an e_mux
  assign system_0_burst_27_downstream_read_data_valid_MS_s1 = system_0_burst_27_downstream_granted_MS_s1 & system_0_burst_27_downstream_read & ~MS_s1_waits_for_read;

  //MS_s1_writedata mux, which is an e_mux
  assign MS_s1_writedata = system_0_burst_27_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_27_downstream_granted_MS_s1 = system_0_burst_27_downstream_qualified_request_MS_s1;

  //system_0_burst_27/downstream saved-grant MS/s1, which is an e_assign
  assign system_0_burst_27_downstream_saved_grant_MS_s1 = system_0_burst_27_downstream_requests_MS_s1;

  //allow new arb cycle for MS/s1, which is an e_assign
  assign MS_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign MS_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign MS_s1_master_qreq_vector = 1;

  //MS_s1_reset_n assignment, which is an e_assign
  assign MS_s1_reset_n = reset_n;

  assign MS_s1_chipselect = system_0_burst_27_downstream_granted_MS_s1;
  //MS_s1_firsttransfer first transaction, which is an e_assign
  assign MS_s1_firsttransfer = MS_s1_begins_xfer ? MS_s1_unreg_firsttransfer : MS_s1_reg_firsttransfer;

  //MS_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign MS_s1_unreg_firsttransfer = ~(MS_s1_slavearbiterlockenable & MS_s1_any_continuerequest);

  //MS_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          MS_s1_reg_firsttransfer <= 1'b1;
      else if (MS_s1_begins_xfer)
          MS_s1_reg_firsttransfer <= MS_s1_unreg_firsttransfer;
    end


  //MS_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign MS_s1_beginbursttransfer_internal = MS_s1_begins_xfer;

  //~MS_s1_write_n assignment, which is an e_mux
  assign MS_s1_write_n = ~(system_0_burst_27_downstream_granted_MS_s1 & system_0_burst_27_downstream_write);

  //MS_s1_address mux, which is an e_mux
  assign MS_s1_address = system_0_burst_27_downstream_nativeaddress;

  //d1_MS_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_MS_s1_end_xfer <= 1;
      else 
        d1_MS_s1_end_xfer <= MS_s1_end_xfer;
    end


  //MS_s1_waits_for_read in a cycle, which is an e_mux
  assign MS_s1_waits_for_read = MS_s1_in_a_read_cycle & MS_s1_begins_xfer;

  //MS_s1_in_a_read_cycle assignment, which is an e_assign
  assign MS_s1_in_a_read_cycle = system_0_burst_27_downstream_granted_MS_s1 & system_0_burst_27_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = MS_s1_in_a_read_cycle;

  //MS_s1_waits_for_write in a cycle, which is an e_mux
  assign MS_s1_waits_for_write = MS_s1_in_a_write_cycle & 0;

  //MS_s1_in_a_write_cycle assignment, which is an e_assign
  assign MS_s1_in_a_write_cycle = system_0_burst_27_downstream_granted_MS_s1 & system_0_burst_27_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = MS_s1_in_a_write_cycle;

  assign wait_for_MS_s1_counter = 0;
  //assign MS_s1_irq_from_sa = MS_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign MS_s1_irq_from_sa = MS_s1_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //MS/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_27/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_27_downstream_requests_MS_s1 && (system_0_burst_27_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_27/downstream drove 0 on its 'arbitrationshare' port while accessing slave MS/s1", $time);
          $stop;
        end
    end


  //system_0_burst_27/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_27_downstream_requests_MS_s1 && (system_0_burst_27_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_27/downstream drove 0 on its 'burstcount' port while accessing slave MS/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module Oct_DOWN_s1_arbitrator (
                                // inputs:
                                 Oct_DOWN_s1_irq,
                                 Oct_DOWN_s1_readdata,
                                 clk,
                                 reset_n,
                                 system_0_burst_31_downstream_address_to_slave,
                                 system_0_burst_31_downstream_arbitrationshare,
                                 system_0_burst_31_downstream_burstcount,
                                 system_0_burst_31_downstream_latency_counter,
                                 system_0_burst_31_downstream_nativeaddress,
                                 system_0_burst_31_downstream_read,
                                 system_0_burst_31_downstream_write,
                                 system_0_burst_31_downstream_writedata,

                                // outputs:
                                 Oct_DOWN_s1_address,
                                 Oct_DOWN_s1_chipselect,
                                 Oct_DOWN_s1_irq_from_sa,
                                 Oct_DOWN_s1_readdata_from_sa,
                                 Oct_DOWN_s1_reset_n,
                                 Oct_DOWN_s1_write_n,
                                 Oct_DOWN_s1_writedata,
                                 d1_Oct_DOWN_s1_end_xfer,
                                 system_0_burst_31_downstream_granted_Oct_DOWN_s1,
                                 system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1,
                                 system_0_burst_31_downstream_read_data_valid_Oct_DOWN_s1,
                                 system_0_burst_31_downstream_requests_Oct_DOWN_s1
                              )
;

  output  [  1: 0] Oct_DOWN_s1_address;
  output           Oct_DOWN_s1_chipselect;
  output           Oct_DOWN_s1_irq_from_sa;
  output           Oct_DOWN_s1_readdata_from_sa;
  output           Oct_DOWN_s1_reset_n;
  output           Oct_DOWN_s1_write_n;
  output           Oct_DOWN_s1_writedata;
  output           d1_Oct_DOWN_s1_end_xfer;
  output           system_0_burst_31_downstream_granted_Oct_DOWN_s1;
  output           system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1;
  output           system_0_burst_31_downstream_read_data_valid_Oct_DOWN_s1;
  output           system_0_burst_31_downstream_requests_Oct_DOWN_s1;
  input            Oct_DOWN_s1_irq;
  input            Oct_DOWN_s1_readdata;
  input            clk;
  input            reset_n;
  input   [  1: 0] system_0_burst_31_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_31_downstream_arbitrationshare;
  input            system_0_burst_31_downstream_burstcount;
  input            system_0_burst_31_downstream_latency_counter;
  input   [  1: 0] system_0_burst_31_downstream_nativeaddress;
  input            system_0_burst_31_downstream_read;
  input            system_0_burst_31_downstream_write;
  input   [  7: 0] system_0_burst_31_downstream_writedata;

  wire    [  1: 0] Oct_DOWN_s1_address;
  wire             Oct_DOWN_s1_allgrants;
  wire             Oct_DOWN_s1_allow_new_arb_cycle;
  wire             Oct_DOWN_s1_any_bursting_master_saved_grant;
  wire             Oct_DOWN_s1_any_continuerequest;
  wire             Oct_DOWN_s1_arb_counter_enable;
  reg     [  5: 0] Oct_DOWN_s1_arb_share_counter;
  wire    [  5: 0] Oct_DOWN_s1_arb_share_counter_next_value;
  wire    [  5: 0] Oct_DOWN_s1_arb_share_set_values;
  wire             Oct_DOWN_s1_beginbursttransfer_internal;
  wire             Oct_DOWN_s1_begins_xfer;
  wire             Oct_DOWN_s1_chipselect;
  wire             Oct_DOWN_s1_end_xfer;
  wire             Oct_DOWN_s1_firsttransfer;
  wire             Oct_DOWN_s1_grant_vector;
  wire             Oct_DOWN_s1_in_a_read_cycle;
  wire             Oct_DOWN_s1_in_a_write_cycle;
  wire             Oct_DOWN_s1_irq_from_sa;
  wire             Oct_DOWN_s1_master_qreq_vector;
  wire             Oct_DOWN_s1_non_bursting_master_requests;
  wire             Oct_DOWN_s1_readdata_from_sa;
  reg              Oct_DOWN_s1_reg_firsttransfer;
  wire             Oct_DOWN_s1_reset_n;
  reg              Oct_DOWN_s1_slavearbiterlockenable;
  wire             Oct_DOWN_s1_slavearbiterlockenable2;
  wire             Oct_DOWN_s1_unreg_firsttransfer;
  wire             Oct_DOWN_s1_waits_for_read;
  wire             Oct_DOWN_s1_waits_for_write;
  wire             Oct_DOWN_s1_write_n;
  wire             Oct_DOWN_s1_writedata;
  reg              d1_Oct_DOWN_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_Oct_DOWN_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             system_0_burst_31_downstream_arbiterlock;
  wire             system_0_burst_31_downstream_arbiterlock2;
  wire             system_0_burst_31_downstream_continuerequest;
  wire             system_0_burst_31_downstream_granted_Oct_DOWN_s1;
  wire             system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1;
  wire             system_0_burst_31_downstream_read_data_valid_Oct_DOWN_s1;
  wire             system_0_burst_31_downstream_requests_Oct_DOWN_s1;
  wire             system_0_burst_31_downstream_saved_grant_Oct_DOWN_s1;
  wire             wait_for_Oct_DOWN_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~Oct_DOWN_s1_end_xfer;
    end


  assign Oct_DOWN_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1));
  //assign Oct_DOWN_s1_readdata_from_sa = Oct_DOWN_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign Oct_DOWN_s1_readdata_from_sa = Oct_DOWN_s1_readdata;

  assign system_0_burst_31_downstream_requests_Oct_DOWN_s1 = (1) & (system_0_burst_31_downstream_read | system_0_burst_31_downstream_write);
  //Oct_DOWN_s1_arb_share_counter set values, which is an e_mux
  assign Oct_DOWN_s1_arb_share_set_values = (system_0_burst_31_downstream_granted_Oct_DOWN_s1)? system_0_burst_31_downstream_arbitrationshare :
    1;

  //Oct_DOWN_s1_non_bursting_master_requests mux, which is an e_mux
  assign Oct_DOWN_s1_non_bursting_master_requests = 0;

  //Oct_DOWN_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign Oct_DOWN_s1_any_bursting_master_saved_grant = system_0_burst_31_downstream_saved_grant_Oct_DOWN_s1;

  //Oct_DOWN_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign Oct_DOWN_s1_arb_share_counter_next_value = Oct_DOWN_s1_firsttransfer ? (Oct_DOWN_s1_arb_share_set_values - 1) : |Oct_DOWN_s1_arb_share_counter ? (Oct_DOWN_s1_arb_share_counter - 1) : 0;

  //Oct_DOWN_s1_allgrants all slave grants, which is an e_mux
  assign Oct_DOWN_s1_allgrants = |Oct_DOWN_s1_grant_vector;

  //Oct_DOWN_s1_end_xfer assignment, which is an e_assign
  assign Oct_DOWN_s1_end_xfer = ~(Oct_DOWN_s1_waits_for_read | Oct_DOWN_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_Oct_DOWN_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_Oct_DOWN_s1 = Oct_DOWN_s1_end_xfer & (~Oct_DOWN_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //Oct_DOWN_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign Oct_DOWN_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_Oct_DOWN_s1 & Oct_DOWN_s1_allgrants) | (end_xfer_arb_share_counter_term_Oct_DOWN_s1 & ~Oct_DOWN_s1_non_bursting_master_requests);

  //Oct_DOWN_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Oct_DOWN_s1_arb_share_counter <= 0;
      else if (Oct_DOWN_s1_arb_counter_enable)
          Oct_DOWN_s1_arb_share_counter <= Oct_DOWN_s1_arb_share_counter_next_value;
    end


  //Oct_DOWN_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Oct_DOWN_s1_slavearbiterlockenable <= 0;
      else if ((|Oct_DOWN_s1_master_qreq_vector & end_xfer_arb_share_counter_term_Oct_DOWN_s1) | (end_xfer_arb_share_counter_term_Oct_DOWN_s1 & ~Oct_DOWN_s1_non_bursting_master_requests))
          Oct_DOWN_s1_slavearbiterlockenable <= |Oct_DOWN_s1_arb_share_counter_next_value;
    end


  //system_0_burst_31/downstream Oct_DOWN/s1 arbiterlock, which is an e_assign
  assign system_0_burst_31_downstream_arbiterlock = Oct_DOWN_s1_slavearbiterlockenable & system_0_burst_31_downstream_continuerequest;

  //Oct_DOWN_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign Oct_DOWN_s1_slavearbiterlockenable2 = |Oct_DOWN_s1_arb_share_counter_next_value;

  //system_0_burst_31/downstream Oct_DOWN/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_31_downstream_arbiterlock2 = Oct_DOWN_s1_slavearbiterlockenable2 & system_0_burst_31_downstream_continuerequest;

  //Oct_DOWN_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign Oct_DOWN_s1_any_continuerequest = 1;

  //system_0_burst_31_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_31_downstream_continuerequest = 1;

  assign system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1 = system_0_burst_31_downstream_requests_Oct_DOWN_s1 & ~((system_0_burst_31_downstream_read & ((system_0_burst_31_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_31_downstream_read_data_valid_Oct_DOWN_s1, which is an e_mux
  assign system_0_burst_31_downstream_read_data_valid_Oct_DOWN_s1 = system_0_burst_31_downstream_granted_Oct_DOWN_s1 & system_0_burst_31_downstream_read & ~Oct_DOWN_s1_waits_for_read;

  //Oct_DOWN_s1_writedata mux, which is an e_mux
  assign Oct_DOWN_s1_writedata = system_0_burst_31_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_31_downstream_granted_Oct_DOWN_s1 = system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1;

  //system_0_burst_31/downstream saved-grant Oct_DOWN/s1, which is an e_assign
  assign system_0_burst_31_downstream_saved_grant_Oct_DOWN_s1 = system_0_burst_31_downstream_requests_Oct_DOWN_s1;

  //allow new arb cycle for Oct_DOWN/s1, which is an e_assign
  assign Oct_DOWN_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign Oct_DOWN_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign Oct_DOWN_s1_master_qreq_vector = 1;

  //Oct_DOWN_s1_reset_n assignment, which is an e_assign
  assign Oct_DOWN_s1_reset_n = reset_n;

  assign Oct_DOWN_s1_chipselect = system_0_burst_31_downstream_granted_Oct_DOWN_s1;
  //Oct_DOWN_s1_firsttransfer first transaction, which is an e_assign
  assign Oct_DOWN_s1_firsttransfer = Oct_DOWN_s1_begins_xfer ? Oct_DOWN_s1_unreg_firsttransfer : Oct_DOWN_s1_reg_firsttransfer;

  //Oct_DOWN_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign Oct_DOWN_s1_unreg_firsttransfer = ~(Oct_DOWN_s1_slavearbiterlockenable & Oct_DOWN_s1_any_continuerequest);

  //Oct_DOWN_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Oct_DOWN_s1_reg_firsttransfer <= 1'b1;
      else if (Oct_DOWN_s1_begins_xfer)
          Oct_DOWN_s1_reg_firsttransfer <= Oct_DOWN_s1_unreg_firsttransfer;
    end


  //Oct_DOWN_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign Oct_DOWN_s1_beginbursttransfer_internal = Oct_DOWN_s1_begins_xfer;

  //~Oct_DOWN_s1_write_n assignment, which is an e_mux
  assign Oct_DOWN_s1_write_n = ~(system_0_burst_31_downstream_granted_Oct_DOWN_s1 & system_0_burst_31_downstream_write);

  //Oct_DOWN_s1_address mux, which is an e_mux
  assign Oct_DOWN_s1_address = system_0_burst_31_downstream_nativeaddress;

  //d1_Oct_DOWN_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_Oct_DOWN_s1_end_xfer <= 1;
      else 
        d1_Oct_DOWN_s1_end_xfer <= Oct_DOWN_s1_end_xfer;
    end


  //Oct_DOWN_s1_waits_for_read in a cycle, which is an e_mux
  assign Oct_DOWN_s1_waits_for_read = Oct_DOWN_s1_in_a_read_cycle & Oct_DOWN_s1_begins_xfer;

  //Oct_DOWN_s1_in_a_read_cycle assignment, which is an e_assign
  assign Oct_DOWN_s1_in_a_read_cycle = system_0_burst_31_downstream_granted_Oct_DOWN_s1 & system_0_burst_31_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = Oct_DOWN_s1_in_a_read_cycle;

  //Oct_DOWN_s1_waits_for_write in a cycle, which is an e_mux
  assign Oct_DOWN_s1_waits_for_write = Oct_DOWN_s1_in_a_write_cycle & 0;

  //Oct_DOWN_s1_in_a_write_cycle assignment, which is an e_assign
  assign Oct_DOWN_s1_in_a_write_cycle = system_0_burst_31_downstream_granted_Oct_DOWN_s1 & system_0_burst_31_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = Oct_DOWN_s1_in_a_write_cycle;

  assign wait_for_Oct_DOWN_s1_counter = 0;
  //assign Oct_DOWN_s1_irq_from_sa = Oct_DOWN_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign Oct_DOWN_s1_irq_from_sa = Oct_DOWN_s1_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //Oct_DOWN/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_31/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_31_downstream_requests_Oct_DOWN_s1 && (system_0_burst_31_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_31/downstream drove 0 on its 'arbitrationshare' port while accessing slave Oct_DOWN/s1", $time);
          $stop;
        end
    end


  //system_0_burst_31/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_31_downstream_requests_Oct_DOWN_s1 && (system_0_burst_31_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_31/downstream drove 0 on its 'burstcount' port while accessing slave Oct_DOWN/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module Oct_UP_s1_arbitrator (
                              // inputs:
                               Oct_UP_s1_irq,
                               Oct_UP_s1_readdata,
                               clk,
                               reset_n,
                               system_0_burst_30_downstream_address_to_slave,
                               system_0_burst_30_downstream_arbitrationshare,
                               system_0_burst_30_downstream_burstcount,
                               system_0_burst_30_downstream_latency_counter,
                               system_0_burst_30_downstream_nativeaddress,
                               system_0_burst_30_downstream_read,
                               system_0_burst_30_downstream_write,
                               system_0_burst_30_downstream_writedata,

                              // outputs:
                               Oct_UP_s1_address,
                               Oct_UP_s1_chipselect,
                               Oct_UP_s1_irq_from_sa,
                               Oct_UP_s1_readdata_from_sa,
                               Oct_UP_s1_reset_n,
                               Oct_UP_s1_write_n,
                               Oct_UP_s1_writedata,
                               d1_Oct_UP_s1_end_xfer,
                               system_0_burst_30_downstream_granted_Oct_UP_s1,
                               system_0_burst_30_downstream_qualified_request_Oct_UP_s1,
                               system_0_burst_30_downstream_read_data_valid_Oct_UP_s1,
                               system_0_burst_30_downstream_requests_Oct_UP_s1
                            )
;

  output  [  1: 0] Oct_UP_s1_address;
  output           Oct_UP_s1_chipselect;
  output           Oct_UP_s1_irq_from_sa;
  output           Oct_UP_s1_readdata_from_sa;
  output           Oct_UP_s1_reset_n;
  output           Oct_UP_s1_write_n;
  output           Oct_UP_s1_writedata;
  output           d1_Oct_UP_s1_end_xfer;
  output           system_0_burst_30_downstream_granted_Oct_UP_s1;
  output           system_0_burst_30_downstream_qualified_request_Oct_UP_s1;
  output           system_0_burst_30_downstream_read_data_valid_Oct_UP_s1;
  output           system_0_burst_30_downstream_requests_Oct_UP_s1;
  input            Oct_UP_s1_irq;
  input            Oct_UP_s1_readdata;
  input            clk;
  input            reset_n;
  input   [  1: 0] system_0_burst_30_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_30_downstream_arbitrationshare;
  input            system_0_burst_30_downstream_burstcount;
  input            system_0_burst_30_downstream_latency_counter;
  input   [  1: 0] system_0_burst_30_downstream_nativeaddress;
  input            system_0_burst_30_downstream_read;
  input            system_0_burst_30_downstream_write;
  input   [  7: 0] system_0_burst_30_downstream_writedata;

  wire    [  1: 0] Oct_UP_s1_address;
  wire             Oct_UP_s1_allgrants;
  wire             Oct_UP_s1_allow_new_arb_cycle;
  wire             Oct_UP_s1_any_bursting_master_saved_grant;
  wire             Oct_UP_s1_any_continuerequest;
  wire             Oct_UP_s1_arb_counter_enable;
  reg     [  5: 0] Oct_UP_s1_arb_share_counter;
  wire    [  5: 0] Oct_UP_s1_arb_share_counter_next_value;
  wire    [  5: 0] Oct_UP_s1_arb_share_set_values;
  wire             Oct_UP_s1_beginbursttransfer_internal;
  wire             Oct_UP_s1_begins_xfer;
  wire             Oct_UP_s1_chipselect;
  wire             Oct_UP_s1_end_xfer;
  wire             Oct_UP_s1_firsttransfer;
  wire             Oct_UP_s1_grant_vector;
  wire             Oct_UP_s1_in_a_read_cycle;
  wire             Oct_UP_s1_in_a_write_cycle;
  wire             Oct_UP_s1_irq_from_sa;
  wire             Oct_UP_s1_master_qreq_vector;
  wire             Oct_UP_s1_non_bursting_master_requests;
  wire             Oct_UP_s1_readdata_from_sa;
  reg              Oct_UP_s1_reg_firsttransfer;
  wire             Oct_UP_s1_reset_n;
  reg              Oct_UP_s1_slavearbiterlockenable;
  wire             Oct_UP_s1_slavearbiterlockenable2;
  wire             Oct_UP_s1_unreg_firsttransfer;
  wire             Oct_UP_s1_waits_for_read;
  wire             Oct_UP_s1_waits_for_write;
  wire             Oct_UP_s1_write_n;
  wire             Oct_UP_s1_writedata;
  reg              d1_Oct_UP_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_Oct_UP_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             system_0_burst_30_downstream_arbiterlock;
  wire             system_0_burst_30_downstream_arbiterlock2;
  wire             system_0_burst_30_downstream_continuerequest;
  wire             system_0_burst_30_downstream_granted_Oct_UP_s1;
  wire             system_0_burst_30_downstream_qualified_request_Oct_UP_s1;
  wire             system_0_burst_30_downstream_read_data_valid_Oct_UP_s1;
  wire             system_0_burst_30_downstream_requests_Oct_UP_s1;
  wire             system_0_burst_30_downstream_saved_grant_Oct_UP_s1;
  wire             wait_for_Oct_UP_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~Oct_UP_s1_end_xfer;
    end


  assign Oct_UP_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_30_downstream_qualified_request_Oct_UP_s1));
  //assign Oct_UP_s1_readdata_from_sa = Oct_UP_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign Oct_UP_s1_readdata_from_sa = Oct_UP_s1_readdata;

  assign system_0_burst_30_downstream_requests_Oct_UP_s1 = (1) & (system_0_burst_30_downstream_read | system_0_burst_30_downstream_write);
  //Oct_UP_s1_arb_share_counter set values, which is an e_mux
  assign Oct_UP_s1_arb_share_set_values = (system_0_burst_30_downstream_granted_Oct_UP_s1)? system_0_burst_30_downstream_arbitrationshare :
    1;

  //Oct_UP_s1_non_bursting_master_requests mux, which is an e_mux
  assign Oct_UP_s1_non_bursting_master_requests = 0;

  //Oct_UP_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign Oct_UP_s1_any_bursting_master_saved_grant = system_0_burst_30_downstream_saved_grant_Oct_UP_s1;

  //Oct_UP_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign Oct_UP_s1_arb_share_counter_next_value = Oct_UP_s1_firsttransfer ? (Oct_UP_s1_arb_share_set_values - 1) : |Oct_UP_s1_arb_share_counter ? (Oct_UP_s1_arb_share_counter - 1) : 0;

  //Oct_UP_s1_allgrants all slave grants, which is an e_mux
  assign Oct_UP_s1_allgrants = |Oct_UP_s1_grant_vector;

  //Oct_UP_s1_end_xfer assignment, which is an e_assign
  assign Oct_UP_s1_end_xfer = ~(Oct_UP_s1_waits_for_read | Oct_UP_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_Oct_UP_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_Oct_UP_s1 = Oct_UP_s1_end_xfer & (~Oct_UP_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //Oct_UP_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign Oct_UP_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_Oct_UP_s1 & Oct_UP_s1_allgrants) | (end_xfer_arb_share_counter_term_Oct_UP_s1 & ~Oct_UP_s1_non_bursting_master_requests);

  //Oct_UP_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Oct_UP_s1_arb_share_counter <= 0;
      else if (Oct_UP_s1_arb_counter_enable)
          Oct_UP_s1_arb_share_counter <= Oct_UP_s1_arb_share_counter_next_value;
    end


  //Oct_UP_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Oct_UP_s1_slavearbiterlockenable <= 0;
      else if ((|Oct_UP_s1_master_qreq_vector & end_xfer_arb_share_counter_term_Oct_UP_s1) | (end_xfer_arb_share_counter_term_Oct_UP_s1 & ~Oct_UP_s1_non_bursting_master_requests))
          Oct_UP_s1_slavearbiterlockenable <= |Oct_UP_s1_arb_share_counter_next_value;
    end


  //system_0_burst_30/downstream Oct_UP/s1 arbiterlock, which is an e_assign
  assign system_0_burst_30_downstream_arbiterlock = Oct_UP_s1_slavearbiterlockenable & system_0_burst_30_downstream_continuerequest;

  //Oct_UP_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign Oct_UP_s1_slavearbiterlockenable2 = |Oct_UP_s1_arb_share_counter_next_value;

  //system_0_burst_30/downstream Oct_UP/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_30_downstream_arbiterlock2 = Oct_UP_s1_slavearbiterlockenable2 & system_0_burst_30_downstream_continuerequest;

  //Oct_UP_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign Oct_UP_s1_any_continuerequest = 1;

  //system_0_burst_30_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_30_downstream_continuerequest = 1;

  assign system_0_burst_30_downstream_qualified_request_Oct_UP_s1 = system_0_burst_30_downstream_requests_Oct_UP_s1 & ~((system_0_burst_30_downstream_read & ((system_0_burst_30_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_30_downstream_read_data_valid_Oct_UP_s1, which is an e_mux
  assign system_0_burst_30_downstream_read_data_valid_Oct_UP_s1 = system_0_burst_30_downstream_granted_Oct_UP_s1 & system_0_burst_30_downstream_read & ~Oct_UP_s1_waits_for_read;

  //Oct_UP_s1_writedata mux, which is an e_mux
  assign Oct_UP_s1_writedata = system_0_burst_30_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_30_downstream_granted_Oct_UP_s1 = system_0_burst_30_downstream_qualified_request_Oct_UP_s1;

  //system_0_burst_30/downstream saved-grant Oct_UP/s1, which is an e_assign
  assign system_0_burst_30_downstream_saved_grant_Oct_UP_s1 = system_0_burst_30_downstream_requests_Oct_UP_s1;

  //allow new arb cycle for Oct_UP/s1, which is an e_assign
  assign Oct_UP_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign Oct_UP_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign Oct_UP_s1_master_qreq_vector = 1;

  //Oct_UP_s1_reset_n assignment, which is an e_assign
  assign Oct_UP_s1_reset_n = reset_n;

  assign Oct_UP_s1_chipselect = system_0_burst_30_downstream_granted_Oct_UP_s1;
  //Oct_UP_s1_firsttransfer first transaction, which is an e_assign
  assign Oct_UP_s1_firsttransfer = Oct_UP_s1_begins_xfer ? Oct_UP_s1_unreg_firsttransfer : Oct_UP_s1_reg_firsttransfer;

  //Oct_UP_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign Oct_UP_s1_unreg_firsttransfer = ~(Oct_UP_s1_slavearbiterlockenable & Oct_UP_s1_any_continuerequest);

  //Oct_UP_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Oct_UP_s1_reg_firsttransfer <= 1'b1;
      else if (Oct_UP_s1_begins_xfer)
          Oct_UP_s1_reg_firsttransfer <= Oct_UP_s1_unreg_firsttransfer;
    end


  //Oct_UP_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign Oct_UP_s1_beginbursttransfer_internal = Oct_UP_s1_begins_xfer;

  //~Oct_UP_s1_write_n assignment, which is an e_mux
  assign Oct_UP_s1_write_n = ~(system_0_burst_30_downstream_granted_Oct_UP_s1 & system_0_burst_30_downstream_write);

  //Oct_UP_s1_address mux, which is an e_mux
  assign Oct_UP_s1_address = system_0_burst_30_downstream_nativeaddress;

  //d1_Oct_UP_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_Oct_UP_s1_end_xfer <= 1;
      else 
        d1_Oct_UP_s1_end_xfer <= Oct_UP_s1_end_xfer;
    end


  //Oct_UP_s1_waits_for_read in a cycle, which is an e_mux
  assign Oct_UP_s1_waits_for_read = Oct_UP_s1_in_a_read_cycle & Oct_UP_s1_begins_xfer;

  //Oct_UP_s1_in_a_read_cycle assignment, which is an e_assign
  assign Oct_UP_s1_in_a_read_cycle = system_0_burst_30_downstream_granted_Oct_UP_s1 & system_0_burst_30_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = Oct_UP_s1_in_a_read_cycle;

  //Oct_UP_s1_waits_for_write in a cycle, which is an e_mux
  assign Oct_UP_s1_waits_for_write = Oct_UP_s1_in_a_write_cycle & 0;

  //Oct_UP_s1_in_a_write_cycle assignment, which is an e_assign
  assign Oct_UP_s1_in_a_write_cycle = system_0_burst_30_downstream_granted_Oct_UP_s1 & system_0_burst_30_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = Oct_UP_s1_in_a_write_cycle;

  assign wait_for_Oct_UP_s1_counter = 0;
  //assign Oct_UP_s1_irq_from_sa = Oct_UP_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign Oct_UP_s1_irq_from_sa = Oct_UP_s1_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //Oct_UP/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_30/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_30_downstream_requests_Oct_UP_s1 && (system_0_burst_30_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_30/downstream drove 0 on its 'arbitrationshare' port while accessing slave Oct_UP/s1", $time);
          $stop;
        end
    end


  //system_0_burst_30/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_30_downstream_requests_Oct_UP_s1 && (system_0_burst_30_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_30/downstream drove 0 on its 'burstcount' port while accessing slave Oct_UP/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module RST_s1_arbitrator (
                           // inputs:
                            RST_s1_irq,
                            RST_s1_readdata,
                            clk,
                            reset_n,
                            system_0_burst_29_downstream_address_to_slave,
                            system_0_burst_29_downstream_arbitrationshare,
                            system_0_burst_29_downstream_burstcount,
                            system_0_burst_29_downstream_latency_counter,
                            system_0_burst_29_downstream_nativeaddress,
                            system_0_burst_29_downstream_read,
                            system_0_burst_29_downstream_write,
                            system_0_burst_29_downstream_writedata,

                           // outputs:
                            RST_s1_address,
                            RST_s1_chipselect,
                            RST_s1_irq_from_sa,
                            RST_s1_readdata_from_sa,
                            RST_s1_reset_n,
                            RST_s1_write_n,
                            RST_s1_writedata,
                            d1_RST_s1_end_xfer,
                            system_0_burst_29_downstream_granted_RST_s1,
                            system_0_burst_29_downstream_qualified_request_RST_s1,
                            system_0_burst_29_downstream_read_data_valid_RST_s1,
                            system_0_burst_29_downstream_requests_RST_s1
                         )
;

  output  [  1: 0] RST_s1_address;
  output           RST_s1_chipselect;
  output           RST_s1_irq_from_sa;
  output           RST_s1_readdata_from_sa;
  output           RST_s1_reset_n;
  output           RST_s1_write_n;
  output           RST_s1_writedata;
  output           d1_RST_s1_end_xfer;
  output           system_0_burst_29_downstream_granted_RST_s1;
  output           system_0_burst_29_downstream_qualified_request_RST_s1;
  output           system_0_burst_29_downstream_read_data_valid_RST_s1;
  output           system_0_burst_29_downstream_requests_RST_s1;
  input            RST_s1_irq;
  input            RST_s1_readdata;
  input            clk;
  input            reset_n;
  input   [  1: 0] system_0_burst_29_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_29_downstream_arbitrationshare;
  input            system_0_burst_29_downstream_burstcount;
  input            system_0_burst_29_downstream_latency_counter;
  input   [  1: 0] system_0_burst_29_downstream_nativeaddress;
  input            system_0_burst_29_downstream_read;
  input            system_0_burst_29_downstream_write;
  input   [  7: 0] system_0_burst_29_downstream_writedata;

  wire    [  1: 0] RST_s1_address;
  wire             RST_s1_allgrants;
  wire             RST_s1_allow_new_arb_cycle;
  wire             RST_s1_any_bursting_master_saved_grant;
  wire             RST_s1_any_continuerequest;
  wire             RST_s1_arb_counter_enable;
  reg     [  5: 0] RST_s1_arb_share_counter;
  wire    [  5: 0] RST_s1_arb_share_counter_next_value;
  wire    [  5: 0] RST_s1_arb_share_set_values;
  wire             RST_s1_beginbursttransfer_internal;
  wire             RST_s1_begins_xfer;
  wire             RST_s1_chipselect;
  wire             RST_s1_end_xfer;
  wire             RST_s1_firsttransfer;
  wire             RST_s1_grant_vector;
  wire             RST_s1_in_a_read_cycle;
  wire             RST_s1_in_a_write_cycle;
  wire             RST_s1_irq_from_sa;
  wire             RST_s1_master_qreq_vector;
  wire             RST_s1_non_bursting_master_requests;
  wire             RST_s1_readdata_from_sa;
  reg              RST_s1_reg_firsttransfer;
  wire             RST_s1_reset_n;
  reg              RST_s1_slavearbiterlockenable;
  wire             RST_s1_slavearbiterlockenable2;
  wire             RST_s1_unreg_firsttransfer;
  wire             RST_s1_waits_for_read;
  wire             RST_s1_waits_for_write;
  wire             RST_s1_write_n;
  wire             RST_s1_writedata;
  reg              d1_RST_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_RST_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             system_0_burst_29_downstream_arbiterlock;
  wire             system_0_burst_29_downstream_arbiterlock2;
  wire             system_0_burst_29_downstream_continuerequest;
  wire             system_0_burst_29_downstream_granted_RST_s1;
  wire             system_0_burst_29_downstream_qualified_request_RST_s1;
  wire             system_0_burst_29_downstream_read_data_valid_RST_s1;
  wire             system_0_burst_29_downstream_requests_RST_s1;
  wire             system_0_burst_29_downstream_saved_grant_RST_s1;
  wire             wait_for_RST_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~RST_s1_end_xfer;
    end


  assign RST_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_29_downstream_qualified_request_RST_s1));
  //assign RST_s1_readdata_from_sa = RST_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign RST_s1_readdata_from_sa = RST_s1_readdata;

  assign system_0_burst_29_downstream_requests_RST_s1 = (1) & (system_0_burst_29_downstream_read | system_0_burst_29_downstream_write);
  //RST_s1_arb_share_counter set values, which is an e_mux
  assign RST_s1_arb_share_set_values = (system_0_burst_29_downstream_granted_RST_s1)? system_0_burst_29_downstream_arbitrationshare :
    1;

  //RST_s1_non_bursting_master_requests mux, which is an e_mux
  assign RST_s1_non_bursting_master_requests = 0;

  //RST_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign RST_s1_any_bursting_master_saved_grant = system_0_burst_29_downstream_saved_grant_RST_s1;

  //RST_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign RST_s1_arb_share_counter_next_value = RST_s1_firsttransfer ? (RST_s1_arb_share_set_values - 1) : |RST_s1_arb_share_counter ? (RST_s1_arb_share_counter - 1) : 0;

  //RST_s1_allgrants all slave grants, which is an e_mux
  assign RST_s1_allgrants = |RST_s1_grant_vector;

  //RST_s1_end_xfer assignment, which is an e_assign
  assign RST_s1_end_xfer = ~(RST_s1_waits_for_read | RST_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_RST_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_RST_s1 = RST_s1_end_xfer & (~RST_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //RST_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign RST_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_RST_s1 & RST_s1_allgrants) | (end_xfer_arb_share_counter_term_RST_s1 & ~RST_s1_non_bursting_master_requests);

  //RST_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          RST_s1_arb_share_counter <= 0;
      else if (RST_s1_arb_counter_enable)
          RST_s1_arb_share_counter <= RST_s1_arb_share_counter_next_value;
    end


  //RST_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          RST_s1_slavearbiterlockenable <= 0;
      else if ((|RST_s1_master_qreq_vector & end_xfer_arb_share_counter_term_RST_s1) | (end_xfer_arb_share_counter_term_RST_s1 & ~RST_s1_non_bursting_master_requests))
          RST_s1_slavearbiterlockenable <= |RST_s1_arb_share_counter_next_value;
    end


  //system_0_burst_29/downstream RST/s1 arbiterlock, which is an e_assign
  assign system_0_burst_29_downstream_arbiterlock = RST_s1_slavearbiterlockenable & system_0_burst_29_downstream_continuerequest;

  //RST_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign RST_s1_slavearbiterlockenable2 = |RST_s1_arb_share_counter_next_value;

  //system_0_burst_29/downstream RST/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_29_downstream_arbiterlock2 = RST_s1_slavearbiterlockenable2 & system_0_burst_29_downstream_continuerequest;

  //RST_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign RST_s1_any_continuerequest = 1;

  //system_0_burst_29_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_29_downstream_continuerequest = 1;

  assign system_0_burst_29_downstream_qualified_request_RST_s1 = system_0_burst_29_downstream_requests_RST_s1 & ~((system_0_burst_29_downstream_read & ((system_0_burst_29_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_29_downstream_read_data_valid_RST_s1, which is an e_mux
  assign system_0_burst_29_downstream_read_data_valid_RST_s1 = system_0_burst_29_downstream_granted_RST_s1 & system_0_burst_29_downstream_read & ~RST_s1_waits_for_read;

  //RST_s1_writedata mux, which is an e_mux
  assign RST_s1_writedata = system_0_burst_29_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_29_downstream_granted_RST_s1 = system_0_burst_29_downstream_qualified_request_RST_s1;

  //system_0_burst_29/downstream saved-grant RST/s1, which is an e_assign
  assign system_0_burst_29_downstream_saved_grant_RST_s1 = system_0_burst_29_downstream_requests_RST_s1;

  //allow new arb cycle for RST/s1, which is an e_assign
  assign RST_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign RST_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign RST_s1_master_qreq_vector = 1;

  //RST_s1_reset_n assignment, which is an e_assign
  assign RST_s1_reset_n = reset_n;

  assign RST_s1_chipselect = system_0_burst_29_downstream_granted_RST_s1;
  //RST_s1_firsttransfer first transaction, which is an e_assign
  assign RST_s1_firsttransfer = RST_s1_begins_xfer ? RST_s1_unreg_firsttransfer : RST_s1_reg_firsttransfer;

  //RST_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign RST_s1_unreg_firsttransfer = ~(RST_s1_slavearbiterlockenable & RST_s1_any_continuerequest);

  //RST_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          RST_s1_reg_firsttransfer <= 1'b1;
      else if (RST_s1_begins_xfer)
          RST_s1_reg_firsttransfer <= RST_s1_unreg_firsttransfer;
    end


  //RST_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign RST_s1_beginbursttransfer_internal = RST_s1_begins_xfer;

  //~RST_s1_write_n assignment, which is an e_mux
  assign RST_s1_write_n = ~(system_0_burst_29_downstream_granted_RST_s1 & system_0_burst_29_downstream_write);

  //RST_s1_address mux, which is an e_mux
  assign RST_s1_address = system_0_burst_29_downstream_nativeaddress;

  //d1_RST_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_RST_s1_end_xfer <= 1;
      else 
        d1_RST_s1_end_xfer <= RST_s1_end_xfer;
    end


  //RST_s1_waits_for_read in a cycle, which is an e_mux
  assign RST_s1_waits_for_read = RST_s1_in_a_read_cycle & RST_s1_begins_xfer;

  //RST_s1_in_a_read_cycle assignment, which is an e_assign
  assign RST_s1_in_a_read_cycle = system_0_burst_29_downstream_granted_RST_s1 & system_0_burst_29_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = RST_s1_in_a_read_cycle;

  //RST_s1_waits_for_write in a cycle, which is an e_mux
  assign RST_s1_waits_for_write = RST_s1_in_a_write_cycle & 0;

  //RST_s1_in_a_write_cycle assignment, which is an e_assign
  assign RST_s1_in_a_write_cycle = system_0_burst_29_downstream_granted_RST_s1 & system_0_burst_29_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = RST_s1_in_a_write_cycle;

  assign wait_for_RST_s1_counter = 0;
  //assign RST_s1_irq_from_sa = RST_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign RST_s1_irq_from_sa = RST_s1_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //RST/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_29/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_29_downstream_requests_RST_s1 && (system_0_burst_29_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_29/downstream drove 0 on its 'arbitrationshare' port while accessing slave RST/s1", $time);
          $stop;
        end
    end


  //system_0_burst_29/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_29_downstream_requests_RST_s1 && (system_0_burst_29_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_29/downstream drove 0 on its 'burstcount' port while accessing slave RST/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module SD_CLK_s1_arbitrator (
                              // inputs:
                               SD_CLK_s1_readdata,
                               clk,
                               reset_n,
                               system_0_burst_19_downstream_address_to_slave,
                               system_0_burst_19_downstream_arbitrationshare,
                               system_0_burst_19_downstream_burstcount,
                               system_0_burst_19_downstream_latency_counter,
                               system_0_burst_19_downstream_nativeaddress,
                               system_0_burst_19_downstream_read,
                               system_0_burst_19_downstream_write,
                               system_0_burst_19_downstream_writedata,

                              // outputs:
                               SD_CLK_s1_address,
                               SD_CLK_s1_chipselect,
                               SD_CLK_s1_readdata_from_sa,
                               SD_CLK_s1_reset_n,
                               SD_CLK_s1_write_n,
                               SD_CLK_s1_writedata,
                               d1_SD_CLK_s1_end_xfer,
                               system_0_burst_19_downstream_granted_SD_CLK_s1,
                               system_0_burst_19_downstream_qualified_request_SD_CLK_s1,
                               system_0_burst_19_downstream_read_data_valid_SD_CLK_s1,
                               system_0_burst_19_downstream_requests_SD_CLK_s1
                            )
;

  output  [  1: 0] SD_CLK_s1_address;
  output           SD_CLK_s1_chipselect;
  output           SD_CLK_s1_readdata_from_sa;
  output           SD_CLK_s1_reset_n;
  output           SD_CLK_s1_write_n;
  output           SD_CLK_s1_writedata;
  output           d1_SD_CLK_s1_end_xfer;
  output           system_0_burst_19_downstream_granted_SD_CLK_s1;
  output           system_0_burst_19_downstream_qualified_request_SD_CLK_s1;
  output           system_0_burst_19_downstream_read_data_valid_SD_CLK_s1;
  output           system_0_burst_19_downstream_requests_SD_CLK_s1;
  input            SD_CLK_s1_readdata;
  input            clk;
  input            reset_n;
  input   [  1: 0] system_0_burst_19_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_19_downstream_arbitrationshare;
  input            system_0_burst_19_downstream_burstcount;
  input            system_0_burst_19_downstream_latency_counter;
  input   [  1: 0] system_0_burst_19_downstream_nativeaddress;
  input            system_0_burst_19_downstream_read;
  input            system_0_burst_19_downstream_write;
  input   [  7: 0] system_0_burst_19_downstream_writedata;

  wire    [  1: 0] SD_CLK_s1_address;
  wire             SD_CLK_s1_allgrants;
  wire             SD_CLK_s1_allow_new_arb_cycle;
  wire             SD_CLK_s1_any_bursting_master_saved_grant;
  wire             SD_CLK_s1_any_continuerequest;
  wire             SD_CLK_s1_arb_counter_enable;
  reg     [  5: 0] SD_CLK_s1_arb_share_counter;
  wire    [  5: 0] SD_CLK_s1_arb_share_counter_next_value;
  wire    [  5: 0] SD_CLK_s1_arb_share_set_values;
  wire             SD_CLK_s1_beginbursttransfer_internal;
  wire             SD_CLK_s1_begins_xfer;
  wire             SD_CLK_s1_chipselect;
  wire             SD_CLK_s1_end_xfer;
  wire             SD_CLK_s1_firsttransfer;
  wire             SD_CLK_s1_grant_vector;
  wire             SD_CLK_s1_in_a_read_cycle;
  wire             SD_CLK_s1_in_a_write_cycle;
  wire             SD_CLK_s1_master_qreq_vector;
  wire             SD_CLK_s1_non_bursting_master_requests;
  wire             SD_CLK_s1_readdata_from_sa;
  reg              SD_CLK_s1_reg_firsttransfer;
  wire             SD_CLK_s1_reset_n;
  reg              SD_CLK_s1_slavearbiterlockenable;
  wire             SD_CLK_s1_slavearbiterlockenable2;
  wire             SD_CLK_s1_unreg_firsttransfer;
  wire             SD_CLK_s1_waits_for_read;
  wire             SD_CLK_s1_waits_for_write;
  wire             SD_CLK_s1_write_n;
  wire             SD_CLK_s1_writedata;
  reg              d1_SD_CLK_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_SD_CLK_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             system_0_burst_19_downstream_arbiterlock;
  wire             system_0_burst_19_downstream_arbiterlock2;
  wire             system_0_burst_19_downstream_continuerequest;
  wire             system_0_burst_19_downstream_granted_SD_CLK_s1;
  wire             system_0_burst_19_downstream_qualified_request_SD_CLK_s1;
  wire             system_0_burst_19_downstream_read_data_valid_SD_CLK_s1;
  wire             system_0_burst_19_downstream_requests_SD_CLK_s1;
  wire             system_0_burst_19_downstream_saved_grant_SD_CLK_s1;
  wire             wait_for_SD_CLK_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~SD_CLK_s1_end_xfer;
    end


  assign SD_CLK_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_19_downstream_qualified_request_SD_CLK_s1));
  //assign SD_CLK_s1_readdata_from_sa = SD_CLK_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign SD_CLK_s1_readdata_from_sa = SD_CLK_s1_readdata;

  assign system_0_burst_19_downstream_requests_SD_CLK_s1 = (1) & (system_0_burst_19_downstream_read | system_0_burst_19_downstream_write);
  //SD_CLK_s1_arb_share_counter set values, which is an e_mux
  assign SD_CLK_s1_arb_share_set_values = (system_0_burst_19_downstream_granted_SD_CLK_s1)? system_0_burst_19_downstream_arbitrationshare :
    1;

  //SD_CLK_s1_non_bursting_master_requests mux, which is an e_mux
  assign SD_CLK_s1_non_bursting_master_requests = 0;

  //SD_CLK_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign SD_CLK_s1_any_bursting_master_saved_grant = system_0_burst_19_downstream_saved_grant_SD_CLK_s1;

  //SD_CLK_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign SD_CLK_s1_arb_share_counter_next_value = SD_CLK_s1_firsttransfer ? (SD_CLK_s1_arb_share_set_values - 1) : |SD_CLK_s1_arb_share_counter ? (SD_CLK_s1_arb_share_counter - 1) : 0;

  //SD_CLK_s1_allgrants all slave grants, which is an e_mux
  assign SD_CLK_s1_allgrants = |SD_CLK_s1_grant_vector;

  //SD_CLK_s1_end_xfer assignment, which is an e_assign
  assign SD_CLK_s1_end_xfer = ~(SD_CLK_s1_waits_for_read | SD_CLK_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_SD_CLK_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_SD_CLK_s1 = SD_CLK_s1_end_xfer & (~SD_CLK_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //SD_CLK_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign SD_CLK_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_SD_CLK_s1 & SD_CLK_s1_allgrants) | (end_xfer_arb_share_counter_term_SD_CLK_s1 & ~SD_CLK_s1_non_bursting_master_requests);

  //SD_CLK_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SD_CLK_s1_arb_share_counter <= 0;
      else if (SD_CLK_s1_arb_counter_enable)
          SD_CLK_s1_arb_share_counter <= SD_CLK_s1_arb_share_counter_next_value;
    end


  //SD_CLK_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SD_CLK_s1_slavearbiterlockenable <= 0;
      else if ((|SD_CLK_s1_master_qreq_vector & end_xfer_arb_share_counter_term_SD_CLK_s1) | (end_xfer_arb_share_counter_term_SD_CLK_s1 & ~SD_CLK_s1_non_bursting_master_requests))
          SD_CLK_s1_slavearbiterlockenable <= |SD_CLK_s1_arb_share_counter_next_value;
    end


  //system_0_burst_19/downstream SD_CLK/s1 arbiterlock, which is an e_assign
  assign system_0_burst_19_downstream_arbiterlock = SD_CLK_s1_slavearbiterlockenable & system_0_burst_19_downstream_continuerequest;

  //SD_CLK_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign SD_CLK_s1_slavearbiterlockenable2 = |SD_CLK_s1_arb_share_counter_next_value;

  //system_0_burst_19/downstream SD_CLK/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_19_downstream_arbiterlock2 = SD_CLK_s1_slavearbiterlockenable2 & system_0_burst_19_downstream_continuerequest;

  //SD_CLK_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign SD_CLK_s1_any_continuerequest = 1;

  //system_0_burst_19_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_19_downstream_continuerequest = 1;

  assign system_0_burst_19_downstream_qualified_request_SD_CLK_s1 = system_0_burst_19_downstream_requests_SD_CLK_s1 & ~((system_0_burst_19_downstream_read & ((system_0_burst_19_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_19_downstream_read_data_valid_SD_CLK_s1, which is an e_mux
  assign system_0_burst_19_downstream_read_data_valid_SD_CLK_s1 = system_0_burst_19_downstream_granted_SD_CLK_s1 & system_0_burst_19_downstream_read & ~SD_CLK_s1_waits_for_read;

  //SD_CLK_s1_writedata mux, which is an e_mux
  assign SD_CLK_s1_writedata = system_0_burst_19_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_19_downstream_granted_SD_CLK_s1 = system_0_burst_19_downstream_qualified_request_SD_CLK_s1;

  //system_0_burst_19/downstream saved-grant SD_CLK/s1, which is an e_assign
  assign system_0_burst_19_downstream_saved_grant_SD_CLK_s1 = system_0_burst_19_downstream_requests_SD_CLK_s1;

  //allow new arb cycle for SD_CLK/s1, which is an e_assign
  assign SD_CLK_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign SD_CLK_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign SD_CLK_s1_master_qreq_vector = 1;

  //SD_CLK_s1_reset_n assignment, which is an e_assign
  assign SD_CLK_s1_reset_n = reset_n;

  assign SD_CLK_s1_chipselect = system_0_burst_19_downstream_granted_SD_CLK_s1;
  //SD_CLK_s1_firsttransfer first transaction, which is an e_assign
  assign SD_CLK_s1_firsttransfer = SD_CLK_s1_begins_xfer ? SD_CLK_s1_unreg_firsttransfer : SD_CLK_s1_reg_firsttransfer;

  //SD_CLK_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign SD_CLK_s1_unreg_firsttransfer = ~(SD_CLK_s1_slavearbiterlockenable & SD_CLK_s1_any_continuerequest);

  //SD_CLK_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SD_CLK_s1_reg_firsttransfer <= 1'b1;
      else if (SD_CLK_s1_begins_xfer)
          SD_CLK_s1_reg_firsttransfer <= SD_CLK_s1_unreg_firsttransfer;
    end


  //SD_CLK_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign SD_CLK_s1_beginbursttransfer_internal = SD_CLK_s1_begins_xfer;

  //~SD_CLK_s1_write_n assignment, which is an e_mux
  assign SD_CLK_s1_write_n = ~(system_0_burst_19_downstream_granted_SD_CLK_s1 & system_0_burst_19_downstream_write);

  //SD_CLK_s1_address mux, which is an e_mux
  assign SD_CLK_s1_address = system_0_burst_19_downstream_nativeaddress;

  //d1_SD_CLK_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_SD_CLK_s1_end_xfer <= 1;
      else 
        d1_SD_CLK_s1_end_xfer <= SD_CLK_s1_end_xfer;
    end


  //SD_CLK_s1_waits_for_read in a cycle, which is an e_mux
  assign SD_CLK_s1_waits_for_read = SD_CLK_s1_in_a_read_cycle & SD_CLK_s1_begins_xfer;

  //SD_CLK_s1_in_a_read_cycle assignment, which is an e_assign
  assign SD_CLK_s1_in_a_read_cycle = system_0_burst_19_downstream_granted_SD_CLK_s1 & system_0_burst_19_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = SD_CLK_s1_in_a_read_cycle;

  //SD_CLK_s1_waits_for_write in a cycle, which is an e_mux
  assign SD_CLK_s1_waits_for_write = SD_CLK_s1_in_a_write_cycle & 0;

  //SD_CLK_s1_in_a_write_cycle assignment, which is an e_assign
  assign SD_CLK_s1_in_a_write_cycle = system_0_burst_19_downstream_granted_SD_CLK_s1 & system_0_burst_19_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = SD_CLK_s1_in_a_write_cycle;

  assign wait_for_SD_CLK_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //SD_CLK/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_19/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_19_downstream_requests_SD_CLK_s1 && (system_0_burst_19_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_19/downstream drove 0 on its 'arbitrationshare' port while accessing slave SD_CLK/s1", $time);
          $stop;
        end
    end


  //system_0_burst_19/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_19_downstream_requests_SD_CLK_s1 && (system_0_burst_19_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_19/downstream drove 0 on its 'burstcount' port while accessing slave SD_CLK/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module SD_CMD_s1_arbitrator (
                              // inputs:
                               SD_CMD_s1_readdata,
                               clk,
                               reset_n,
                               system_0_burst_18_downstream_address_to_slave,
                               system_0_burst_18_downstream_arbitrationshare,
                               system_0_burst_18_downstream_burstcount,
                               system_0_burst_18_downstream_latency_counter,
                               system_0_burst_18_downstream_nativeaddress,
                               system_0_burst_18_downstream_read,
                               system_0_burst_18_downstream_write,
                               system_0_burst_18_downstream_writedata,

                              // outputs:
                               SD_CMD_s1_address,
                               SD_CMD_s1_chipselect,
                               SD_CMD_s1_readdata_from_sa,
                               SD_CMD_s1_reset_n,
                               SD_CMD_s1_write_n,
                               SD_CMD_s1_writedata,
                               d1_SD_CMD_s1_end_xfer,
                               system_0_burst_18_downstream_granted_SD_CMD_s1,
                               system_0_burst_18_downstream_qualified_request_SD_CMD_s1,
                               system_0_burst_18_downstream_read_data_valid_SD_CMD_s1,
                               system_0_burst_18_downstream_requests_SD_CMD_s1
                            )
;

  output  [  1: 0] SD_CMD_s1_address;
  output           SD_CMD_s1_chipselect;
  output           SD_CMD_s1_readdata_from_sa;
  output           SD_CMD_s1_reset_n;
  output           SD_CMD_s1_write_n;
  output           SD_CMD_s1_writedata;
  output           d1_SD_CMD_s1_end_xfer;
  output           system_0_burst_18_downstream_granted_SD_CMD_s1;
  output           system_0_burst_18_downstream_qualified_request_SD_CMD_s1;
  output           system_0_burst_18_downstream_read_data_valid_SD_CMD_s1;
  output           system_0_burst_18_downstream_requests_SD_CMD_s1;
  input            SD_CMD_s1_readdata;
  input            clk;
  input            reset_n;
  input   [  1: 0] system_0_burst_18_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_18_downstream_arbitrationshare;
  input            system_0_burst_18_downstream_burstcount;
  input            system_0_burst_18_downstream_latency_counter;
  input   [  1: 0] system_0_burst_18_downstream_nativeaddress;
  input            system_0_burst_18_downstream_read;
  input            system_0_burst_18_downstream_write;
  input   [  7: 0] system_0_burst_18_downstream_writedata;

  wire    [  1: 0] SD_CMD_s1_address;
  wire             SD_CMD_s1_allgrants;
  wire             SD_CMD_s1_allow_new_arb_cycle;
  wire             SD_CMD_s1_any_bursting_master_saved_grant;
  wire             SD_CMD_s1_any_continuerequest;
  wire             SD_CMD_s1_arb_counter_enable;
  reg     [  5: 0] SD_CMD_s1_arb_share_counter;
  wire    [  5: 0] SD_CMD_s1_arb_share_counter_next_value;
  wire    [  5: 0] SD_CMD_s1_arb_share_set_values;
  wire             SD_CMD_s1_beginbursttransfer_internal;
  wire             SD_CMD_s1_begins_xfer;
  wire             SD_CMD_s1_chipselect;
  wire             SD_CMD_s1_end_xfer;
  wire             SD_CMD_s1_firsttransfer;
  wire             SD_CMD_s1_grant_vector;
  wire             SD_CMD_s1_in_a_read_cycle;
  wire             SD_CMD_s1_in_a_write_cycle;
  wire             SD_CMD_s1_master_qreq_vector;
  wire             SD_CMD_s1_non_bursting_master_requests;
  wire             SD_CMD_s1_readdata_from_sa;
  reg              SD_CMD_s1_reg_firsttransfer;
  wire             SD_CMD_s1_reset_n;
  reg              SD_CMD_s1_slavearbiterlockenable;
  wire             SD_CMD_s1_slavearbiterlockenable2;
  wire             SD_CMD_s1_unreg_firsttransfer;
  wire             SD_CMD_s1_waits_for_read;
  wire             SD_CMD_s1_waits_for_write;
  wire             SD_CMD_s1_write_n;
  wire             SD_CMD_s1_writedata;
  reg              d1_SD_CMD_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_SD_CMD_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             system_0_burst_18_downstream_arbiterlock;
  wire             system_0_burst_18_downstream_arbiterlock2;
  wire             system_0_burst_18_downstream_continuerequest;
  wire             system_0_burst_18_downstream_granted_SD_CMD_s1;
  wire             system_0_burst_18_downstream_qualified_request_SD_CMD_s1;
  wire             system_0_burst_18_downstream_read_data_valid_SD_CMD_s1;
  wire             system_0_burst_18_downstream_requests_SD_CMD_s1;
  wire             system_0_burst_18_downstream_saved_grant_SD_CMD_s1;
  wire             wait_for_SD_CMD_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~SD_CMD_s1_end_xfer;
    end


  assign SD_CMD_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_18_downstream_qualified_request_SD_CMD_s1));
  //assign SD_CMD_s1_readdata_from_sa = SD_CMD_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign SD_CMD_s1_readdata_from_sa = SD_CMD_s1_readdata;

  assign system_0_burst_18_downstream_requests_SD_CMD_s1 = (1) & (system_0_burst_18_downstream_read | system_0_burst_18_downstream_write);
  //SD_CMD_s1_arb_share_counter set values, which is an e_mux
  assign SD_CMD_s1_arb_share_set_values = (system_0_burst_18_downstream_granted_SD_CMD_s1)? system_0_burst_18_downstream_arbitrationshare :
    1;

  //SD_CMD_s1_non_bursting_master_requests mux, which is an e_mux
  assign SD_CMD_s1_non_bursting_master_requests = 0;

  //SD_CMD_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign SD_CMD_s1_any_bursting_master_saved_grant = system_0_burst_18_downstream_saved_grant_SD_CMD_s1;

  //SD_CMD_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign SD_CMD_s1_arb_share_counter_next_value = SD_CMD_s1_firsttransfer ? (SD_CMD_s1_arb_share_set_values - 1) : |SD_CMD_s1_arb_share_counter ? (SD_CMD_s1_arb_share_counter - 1) : 0;

  //SD_CMD_s1_allgrants all slave grants, which is an e_mux
  assign SD_CMD_s1_allgrants = |SD_CMD_s1_grant_vector;

  //SD_CMD_s1_end_xfer assignment, which is an e_assign
  assign SD_CMD_s1_end_xfer = ~(SD_CMD_s1_waits_for_read | SD_CMD_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_SD_CMD_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_SD_CMD_s1 = SD_CMD_s1_end_xfer & (~SD_CMD_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //SD_CMD_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign SD_CMD_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_SD_CMD_s1 & SD_CMD_s1_allgrants) | (end_xfer_arb_share_counter_term_SD_CMD_s1 & ~SD_CMD_s1_non_bursting_master_requests);

  //SD_CMD_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SD_CMD_s1_arb_share_counter <= 0;
      else if (SD_CMD_s1_arb_counter_enable)
          SD_CMD_s1_arb_share_counter <= SD_CMD_s1_arb_share_counter_next_value;
    end


  //SD_CMD_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SD_CMD_s1_slavearbiterlockenable <= 0;
      else if ((|SD_CMD_s1_master_qreq_vector & end_xfer_arb_share_counter_term_SD_CMD_s1) | (end_xfer_arb_share_counter_term_SD_CMD_s1 & ~SD_CMD_s1_non_bursting_master_requests))
          SD_CMD_s1_slavearbiterlockenable <= |SD_CMD_s1_arb_share_counter_next_value;
    end


  //system_0_burst_18/downstream SD_CMD/s1 arbiterlock, which is an e_assign
  assign system_0_burst_18_downstream_arbiterlock = SD_CMD_s1_slavearbiterlockenable & system_0_burst_18_downstream_continuerequest;

  //SD_CMD_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign SD_CMD_s1_slavearbiterlockenable2 = |SD_CMD_s1_arb_share_counter_next_value;

  //system_0_burst_18/downstream SD_CMD/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_18_downstream_arbiterlock2 = SD_CMD_s1_slavearbiterlockenable2 & system_0_burst_18_downstream_continuerequest;

  //SD_CMD_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign SD_CMD_s1_any_continuerequest = 1;

  //system_0_burst_18_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_18_downstream_continuerequest = 1;

  assign system_0_burst_18_downstream_qualified_request_SD_CMD_s1 = system_0_burst_18_downstream_requests_SD_CMD_s1 & ~((system_0_burst_18_downstream_read & ((system_0_burst_18_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_18_downstream_read_data_valid_SD_CMD_s1, which is an e_mux
  assign system_0_burst_18_downstream_read_data_valid_SD_CMD_s1 = system_0_burst_18_downstream_granted_SD_CMD_s1 & system_0_burst_18_downstream_read & ~SD_CMD_s1_waits_for_read;

  //SD_CMD_s1_writedata mux, which is an e_mux
  assign SD_CMD_s1_writedata = system_0_burst_18_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_18_downstream_granted_SD_CMD_s1 = system_0_burst_18_downstream_qualified_request_SD_CMD_s1;

  //system_0_burst_18/downstream saved-grant SD_CMD/s1, which is an e_assign
  assign system_0_burst_18_downstream_saved_grant_SD_CMD_s1 = system_0_burst_18_downstream_requests_SD_CMD_s1;

  //allow new arb cycle for SD_CMD/s1, which is an e_assign
  assign SD_CMD_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign SD_CMD_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign SD_CMD_s1_master_qreq_vector = 1;

  //SD_CMD_s1_reset_n assignment, which is an e_assign
  assign SD_CMD_s1_reset_n = reset_n;

  assign SD_CMD_s1_chipselect = system_0_burst_18_downstream_granted_SD_CMD_s1;
  //SD_CMD_s1_firsttransfer first transaction, which is an e_assign
  assign SD_CMD_s1_firsttransfer = SD_CMD_s1_begins_xfer ? SD_CMD_s1_unreg_firsttransfer : SD_CMD_s1_reg_firsttransfer;

  //SD_CMD_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign SD_CMD_s1_unreg_firsttransfer = ~(SD_CMD_s1_slavearbiterlockenable & SD_CMD_s1_any_continuerequest);

  //SD_CMD_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SD_CMD_s1_reg_firsttransfer <= 1'b1;
      else if (SD_CMD_s1_begins_xfer)
          SD_CMD_s1_reg_firsttransfer <= SD_CMD_s1_unreg_firsttransfer;
    end


  //SD_CMD_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign SD_CMD_s1_beginbursttransfer_internal = SD_CMD_s1_begins_xfer;

  //~SD_CMD_s1_write_n assignment, which is an e_mux
  assign SD_CMD_s1_write_n = ~(system_0_burst_18_downstream_granted_SD_CMD_s1 & system_0_burst_18_downstream_write);

  //SD_CMD_s1_address mux, which is an e_mux
  assign SD_CMD_s1_address = system_0_burst_18_downstream_nativeaddress;

  //d1_SD_CMD_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_SD_CMD_s1_end_xfer <= 1;
      else 
        d1_SD_CMD_s1_end_xfer <= SD_CMD_s1_end_xfer;
    end


  //SD_CMD_s1_waits_for_read in a cycle, which is an e_mux
  assign SD_CMD_s1_waits_for_read = SD_CMD_s1_in_a_read_cycle & SD_CMD_s1_begins_xfer;

  //SD_CMD_s1_in_a_read_cycle assignment, which is an e_assign
  assign SD_CMD_s1_in_a_read_cycle = system_0_burst_18_downstream_granted_SD_CMD_s1 & system_0_burst_18_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = SD_CMD_s1_in_a_read_cycle;

  //SD_CMD_s1_waits_for_write in a cycle, which is an e_mux
  assign SD_CMD_s1_waits_for_write = SD_CMD_s1_in_a_write_cycle & 0;

  //SD_CMD_s1_in_a_write_cycle assignment, which is an e_assign
  assign SD_CMD_s1_in_a_write_cycle = system_0_burst_18_downstream_granted_SD_CMD_s1 & system_0_burst_18_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = SD_CMD_s1_in_a_write_cycle;

  assign wait_for_SD_CMD_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //SD_CMD/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_18/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_18_downstream_requests_SD_CMD_s1 && (system_0_burst_18_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_18/downstream drove 0 on its 'arbitrationshare' port while accessing slave SD_CMD/s1", $time);
          $stop;
        end
    end


  //system_0_burst_18/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_18_downstream_requests_SD_CMD_s1 && (system_0_burst_18_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_18/downstream drove 0 on its 'burstcount' port while accessing slave SD_CMD/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module SD_DAT_s1_arbitrator (
                              // inputs:
                               SD_DAT_s1_readdata,
                               clk,
                               reset_n,
                               system_0_burst_17_downstream_address_to_slave,
                               system_0_burst_17_downstream_arbitrationshare,
                               system_0_burst_17_downstream_burstcount,
                               system_0_burst_17_downstream_latency_counter,
                               system_0_burst_17_downstream_nativeaddress,
                               system_0_burst_17_downstream_read,
                               system_0_burst_17_downstream_write,
                               system_0_burst_17_downstream_writedata,

                              // outputs:
                               SD_DAT_s1_address,
                               SD_DAT_s1_chipselect,
                               SD_DAT_s1_readdata_from_sa,
                               SD_DAT_s1_reset_n,
                               SD_DAT_s1_write_n,
                               SD_DAT_s1_writedata,
                               d1_SD_DAT_s1_end_xfer,
                               system_0_burst_17_downstream_granted_SD_DAT_s1,
                               system_0_burst_17_downstream_qualified_request_SD_DAT_s1,
                               system_0_burst_17_downstream_read_data_valid_SD_DAT_s1,
                               system_0_burst_17_downstream_requests_SD_DAT_s1
                            )
;

  output  [  1: 0] SD_DAT_s1_address;
  output           SD_DAT_s1_chipselect;
  output           SD_DAT_s1_readdata_from_sa;
  output           SD_DAT_s1_reset_n;
  output           SD_DAT_s1_write_n;
  output           SD_DAT_s1_writedata;
  output           d1_SD_DAT_s1_end_xfer;
  output           system_0_burst_17_downstream_granted_SD_DAT_s1;
  output           system_0_burst_17_downstream_qualified_request_SD_DAT_s1;
  output           system_0_burst_17_downstream_read_data_valid_SD_DAT_s1;
  output           system_0_burst_17_downstream_requests_SD_DAT_s1;
  input            SD_DAT_s1_readdata;
  input            clk;
  input            reset_n;
  input   [  1: 0] system_0_burst_17_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_17_downstream_arbitrationshare;
  input            system_0_burst_17_downstream_burstcount;
  input            system_0_burst_17_downstream_latency_counter;
  input   [  1: 0] system_0_burst_17_downstream_nativeaddress;
  input            system_0_burst_17_downstream_read;
  input            system_0_burst_17_downstream_write;
  input   [  7: 0] system_0_burst_17_downstream_writedata;

  wire    [  1: 0] SD_DAT_s1_address;
  wire             SD_DAT_s1_allgrants;
  wire             SD_DAT_s1_allow_new_arb_cycle;
  wire             SD_DAT_s1_any_bursting_master_saved_grant;
  wire             SD_DAT_s1_any_continuerequest;
  wire             SD_DAT_s1_arb_counter_enable;
  reg     [  5: 0] SD_DAT_s1_arb_share_counter;
  wire    [  5: 0] SD_DAT_s1_arb_share_counter_next_value;
  wire    [  5: 0] SD_DAT_s1_arb_share_set_values;
  wire             SD_DAT_s1_beginbursttransfer_internal;
  wire             SD_DAT_s1_begins_xfer;
  wire             SD_DAT_s1_chipselect;
  wire             SD_DAT_s1_end_xfer;
  wire             SD_DAT_s1_firsttransfer;
  wire             SD_DAT_s1_grant_vector;
  wire             SD_DAT_s1_in_a_read_cycle;
  wire             SD_DAT_s1_in_a_write_cycle;
  wire             SD_DAT_s1_master_qreq_vector;
  wire             SD_DAT_s1_non_bursting_master_requests;
  wire             SD_DAT_s1_readdata_from_sa;
  reg              SD_DAT_s1_reg_firsttransfer;
  wire             SD_DAT_s1_reset_n;
  reg              SD_DAT_s1_slavearbiterlockenable;
  wire             SD_DAT_s1_slavearbiterlockenable2;
  wire             SD_DAT_s1_unreg_firsttransfer;
  wire             SD_DAT_s1_waits_for_read;
  wire             SD_DAT_s1_waits_for_write;
  wire             SD_DAT_s1_write_n;
  wire             SD_DAT_s1_writedata;
  reg              d1_SD_DAT_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_SD_DAT_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             system_0_burst_17_downstream_arbiterlock;
  wire             system_0_burst_17_downstream_arbiterlock2;
  wire             system_0_burst_17_downstream_continuerequest;
  wire             system_0_burst_17_downstream_granted_SD_DAT_s1;
  wire             system_0_burst_17_downstream_qualified_request_SD_DAT_s1;
  wire             system_0_burst_17_downstream_read_data_valid_SD_DAT_s1;
  wire             system_0_burst_17_downstream_requests_SD_DAT_s1;
  wire             system_0_burst_17_downstream_saved_grant_SD_DAT_s1;
  wire             wait_for_SD_DAT_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~SD_DAT_s1_end_xfer;
    end


  assign SD_DAT_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_17_downstream_qualified_request_SD_DAT_s1));
  //assign SD_DAT_s1_readdata_from_sa = SD_DAT_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign SD_DAT_s1_readdata_from_sa = SD_DAT_s1_readdata;

  assign system_0_burst_17_downstream_requests_SD_DAT_s1 = (1) & (system_0_burst_17_downstream_read | system_0_burst_17_downstream_write);
  //SD_DAT_s1_arb_share_counter set values, which is an e_mux
  assign SD_DAT_s1_arb_share_set_values = (system_0_burst_17_downstream_granted_SD_DAT_s1)? system_0_burst_17_downstream_arbitrationshare :
    1;

  //SD_DAT_s1_non_bursting_master_requests mux, which is an e_mux
  assign SD_DAT_s1_non_bursting_master_requests = 0;

  //SD_DAT_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign SD_DAT_s1_any_bursting_master_saved_grant = system_0_burst_17_downstream_saved_grant_SD_DAT_s1;

  //SD_DAT_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign SD_DAT_s1_arb_share_counter_next_value = SD_DAT_s1_firsttransfer ? (SD_DAT_s1_arb_share_set_values - 1) : |SD_DAT_s1_arb_share_counter ? (SD_DAT_s1_arb_share_counter - 1) : 0;

  //SD_DAT_s1_allgrants all slave grants, which is an e_mux
  assign SD_DAT_s1_allgrants = |SD_DAT_s1_grant_vector;

  //SD_DAT_s1_end_xfer assignment, which is an e_assign
  assign SD_DAT_s1_end_xfer = ~(SD_DAT_s1_waits_for_read | SD_DAT_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_SD_DAT_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_SD_DAT_s1 = SD_DAT_s1_end_xfer & (~SD_DAT_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //SD_DAT_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign SD_DAT_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_SD_DAT_s1 & SD_DAT_s1_allgrants) | (end_xfer_arb_share_counter_term_SD_DAT_s1 & ~SD_DAT_s1_non_bursting_master_requests);

  //SD_DAT_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SD_DAT_s1_arb_share_counter <= 0;
      else if (SD_DAT_s1_arb_counter_enable)
          SD_DAT_s1_arb_share_counter <= SD_DAT_s1_arb_share_counter_next_value;
    end


  //SD_DAT_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SD_DAT_s1_slavearbiterlockenable <= 0;
      else if ((|SD_DAT_s1_master_qreq_vector & end_xfer_arb_share_counter_term_SD_DAT_s1) | (end_xfer_arb_share_counter_term_SD_DAT_s1 & ~SD_DAT_s1_non_bursting_master_requests))
          SD_DAT_s1_slavearbiterlockenable <= |SD_DAT_s1_arb_share_counter_next_value;
    end


  //system_0_burst_17/downstream SD_DAT/s1 arbiterlock, which is an e_assign
  assign system_0_burst_17_downstream_arbiterlock = SD_DAT_s1_slavearbiterlockenable & system_0_burst_17_downstream_continuerequest;

  //SD_DAT_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign SD_DAT_s1_slavearbiterlockenable2 = |SD_DAT_s1_arb_share_counter_next_value;

  //system_0_burst_17/downstream SD_DAT/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_17_downstream_arbiterlock2 = SD_DAT_s1_slavearbiterlockenable2 & system_0_burst_17_downstream_continuerequest;

  //SD_DAT_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign SD_DAT_s1_any_continuerequest = 1;

  //system_0_burst_17_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_17_downstream_continuerequest = 1;

  assign system_0_burst_17_downstream_qualified_request_SD_DAT_s1 = system_0_burst_17_downstream_requests_SD_DAT_s1 & ~((system_0_burst_17_downstream_read & ((system_0_burst_17_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_17_downstream_read_data_valid_SD_DAT_s1, which is an e_mux
  assign system_0_burst_17_downstream_read_data_valid_SD_DAT_s1 = system_0_burst_17_downstream_granted_SD_DAT_s1 & system_0_burst_17_downstream_read & ~SD_DAT_s1_waits_for_read;

  //SD_DAT_s1_writedata mux, which is an e_mux
  assign SD_DAT_s1_writedata = system_0_burst_17_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_17_downstream_granted_SD_DAT_s1 = system_0_burst_17_downstream_qualified_request_SD_DAT_s1;

  //system_0_burst_17/downstream saved-grant SD_DAT/s1, which is an e_assign
  assign system_0_burst_17_downstream_saved_grant_SD_DAT_s1 = system_0_burst_17_downstream_requests_SD_DAT_s1;

  //allow new arb cycle for SD_DAT/s1, which is an e_assign
  assign SD_DAT_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign SD_DAT_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign SD_DAT_s1_master_qreq_vector = 1;

  //SD_DAT_s1_reset_n assignment, which is an e_assign
  assign SD_DAT_s1_reset_n = reset_n;

  assign SD_DAT_s1_chipselect = system_0_burst_17_downstream_granted_SD_DAT_s1;
  //SD_DAT_s1_firsttransfer first transaction, which is an e_assign
  assign SD_DAT_s1_firsttransfer = SD_DAT_s1_begins_xfer ? SD_DAT_s1_unreg_firsttransfer : SD_DAT_s1_reg_firsttransfer;

  //SD_DAT_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign SD_DAT_s1_unreg_firsttransfer = ~(SD_DAT_s1_slavearbiterlockenable & SD_DAT_s1_any_continuerequest);

  //SD_DAT_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SD_DAT_s1_reg_firsttransfer <= 1'b1;
      else if (SD_DAT_s1_begins_xfer)
          SD_DAT_s1_reg_firsttransfer <= SD_DAT_s1_unreg_firsttransfer;
    end


  //SD_DAT_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign SD_DAT_s1_beginbursttransfer_internal = SD_DAT_s1_begins_xfer;

  //~SD_DAT_s1_write_n assignment, which is an e_mux
  assign SD_DAT_s1_write_n = ~(system_0_burst_17_downstream_granted_SD_DAT_s1 & system_0_burst_17_downstream_write);

  //SD_DAT_s1_address mux, which is an e_mux
  assign SD_DAT_s1_address = system_0_burst_17_downstream_nativeaddress;

  //d1_SD_DAT_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_SD_DAT_s1_end_xfer <= 1;
      else 
        d1_SD_DAT_s1_end_xfer <= SD_DAT_s1_end_xfer;
    end


  //SD_DAT_s1_waits_for_read in a cycle, which is an e_mux
  assign SD_DAT_s1_waits_for_read = SD_DAT_s1_in_a_read_cycle & SD_DAT_s1_begins_xfer;

  //SD_DAT_s1_in_a_read_cycle assignment, which is an e_assign
  assign SD_DAT_s1_in_a_read_cycle = system_0_burst_17_downstream_granted_SD_DAT_s1 & system_0_burst_17_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = SD_DAT_s1_in_a_read_cycle;

  //SD_DAT_s1_waits_for_write in a cycle, which is an e_mux
  assign SD_DAT_s1_waits_for_write = SD_DAT_s1_in_a_write_cycle & 0;

  //SD_DAT_s1_in_a_write_cycle assignment, which is an e_assign
  assign SD_DAT_s1_in_a_write_cycle = system_0_burst_17_downstream_granted_SD_DAT_s1 & system_0_burst_17_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = SD_DAT_s1_in_a_write_cycle;

  assign wait_for_SD_DAT_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //SD_DAT/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_17/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_17_downstream_requests_SD_DAT_s1 && (system_0_burst_17_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_17/downstream drove 0 on its 'arbitrationshare' port while accessing slave SD_DAT/s1", $time);
          $stop;
        end
    end


  //system_0_burst_17/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_17_downstream_requests_SD_DAT_s1 && (system_0_burst_17_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_17/downstream drove 0 on its 'burstcount' port while accessing slave SD_DAT/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module SEG7_Display_avalon_slave_0_arbitrator (
                                                // inputs:
                                                 clk,
                                                 reset_n,
                                                 system_0_burst_13_downstream_address_to_slave,
                                                 system_0_burst_13_downstream_arbitrationshare,
                                                 system_0_burst_13_downstream_burstcount,
                                                 system_0_burst_13_downstream_latency_counter,
                                                 system_0_burst_13_downstream_read,
                                                 system_0_burst_13_downstream_write,
                                                 system_0_burst_13_downstream_writedata,

                                                // outputs:
                                                 SEG7_Display_avalon_slave_0_reset_n,
                                                 SEG7_Display_avalon_slave_0_write,
                                                 SEG7_Display_avalon_slave_0_writedata,
                                                 d1_SEG7_Display_avalon_slave_0_end_xfer,
                                                 system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0,
                                                 system_0_burst_13_downstream_qualified_request_SEG7_Display_avalon_slave_0,
                                                 system_0_burst_13_downstream_read_data_valid_SEG7_Display_avalon_slave_0,
                                                 system_0_burst_13_downstream_requests_SEG7_Display_avalon_slave_0
                                              )
;

  output           SEG7_Display_avalon_slave_0_reset_n;
  output           SEG7_Display_avalon_slave_0_write;
  output  [ 31: 0] SEG7_Display_avalon_slave_0_writedata;
  output           d1_SEG7_Display_avalon_slave_0_end_xfer;
  output           system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0;
  output           system_0_burst_13_downstream_qualified_request_SEG7_Display_avalon_slave_0;
  output           system_0_burst_13_downstream_read_data_valid_SEG7_Display_avalon_slave_0;
  output           system_0_burst_13_downstream_requests_SEG7_Display_avalon_slave_0;
  input            clk;
  input            reset_n;
  input   [  1: 0] system_0_burst_13_downstream_address_to_slave;
  input   [  3: 0] system_0_burst_13_downstream_arbitrationshare;
  input            system_0_burst_13_downstream_burstcount;
  input            system_0_burst_13_downstream_latency_counter;
  input            system_0_burst_13_downstream_read;
  input            system_0_burst_13_downstream_write;
  input   [ 31: 0] system_0_burst_13_downstream_writedata;

  wire             SEG7_Display_avalon_slave_0_allgrants;
  wire             SEG7_Display_avalon_slave_0_allow_new_arb_cycle;
  wire             SEG7_Display_avalon_slave_0_any_bursting_master_saved_grant;
  wire             SEG7_Display_avalon_slave_0_any_continuerequest;
  wire             SEG7_Display_avalon_slave_0_arb_counter_enable;
  reg     [  3: 0] SEG7_Display_avalon_slave_0_arb_share_counter;
  wire    [  3: 0] SEG7_Display_avalon_slave_0_arb_share_counter_next_value;
  wire    [  3: 0] SEG7_Display_avalon_slave_0_arb_share_set_values;
  wire             SEG7_Display_avalon_slave_0_beginbursttransfer_internal;
  wire             SEG7_Display_avalon_slave_0_begins_xfer;
  wire             SEG7_Display_avalon_slave_0_end_xfer;
  wire             SEG7_Display_avalon_slave_0_firsttransfer;
  wire             SEG7_Display_avalon_slave_0_grant_vector;
  wire             SEG7_Display_avalon_slave_0_in_a_read_cycle;
  wire             SEG7_Display_avalon_slave_0_in_a_write_cycle;
  wire             SEG7_Display_avalon_slave_0_master_qreq_vector;
  wire             SEG7_Display_avalon_slave_0_non_bursting_master_requests;
  reg              SEG7_Display_avalon_slave_0_reg_firsttransfer;
  wire             SEG7_Display_avalon_slave_0_reset_n;
  reg              SEG7_Display_avalon_slave_0_slavearbiterlockenable;
  wire             SEG7_Display_avalon_slave_0_slavearbiterlockenable2;
  wire             SEG7_Display_avalon_slave_0_unreg_firsttransfer;
  wire             SEG7_Display_avalon_slave_0_waits_for_read;
  wire             SEG7_Display_avalon_slave_0_waits_for_write;
  wire             SEG7_Display_avalon_slave_0_write;
  wire    [ 31: 0] SEG7_Display_avalon_slave_0_writedata;
  reg              d1_SEG7_Display_avalon_slave_0_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_SEG7_Display_avalon_slave_0;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             system_0_burst_13_downstream_arbiterlock;
  wire             system_0_burst_13_downstream_arbiterlock2;
  wire             system_0_burst_13_downstream_continuerequest;
  wire             system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0;
  wire             system_0_burst_13_downstream_qualified_request_SEG7_Display_avalon_slave_0;
  wire             system_0_burst_13_downstream_read_data_valid_SEG7_Display_avalon_slave_0;
  wire             system_0_burst_13_downstream_requests_SEG7_Display_avalon_slave_0;
  wire             system_0_burst_13_downstream_saved_grant_SEG7_Display_avalon_slave_0;
  wire             wait_for_SEG7_Display_avalon_slave_0_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~SEG7_Display_avalon_slave_0_end_xfer;
    end


  assign SEG7_Display_avalon_slave_0_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_13_downstream_qualified_request_SEG7_Display_avalon_slave_0));
  assign system_0_burst_13_downstream_requests_SEG7_Display_avalon_slave_0 = ((1) & (system_0_burst_13_downstream_read | system_0_burst_13_downstream_write)) & system_0_burst_13_downstream_write;
  //SEG7_Display_avalon_slave_0_arb_share_counter set values, which is an e_mux
  assign SEG7_Display_avalon_slave_0_arb_share_set_values = (system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0)? system_0_burst_13_downstream_arbitrationshare :
    1;

  //SEG7_Display_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
  assign SEG7_Display_avalon_slave_0_non_bursting_master_requests = 0;

  //SEG7_Display_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
  assign SEG7_Display_avalon_slave_0_any_bursting_master_saved_grant = system_0_burst_13_downstream_saved_grant_SEG7_Display_avalon_slave_0;

  //SEG7_Display_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
  assign SEG7_Display_avalon_slave_0_arb_share_counter_next_value = SEG7_Display_avalon_slave_0_firsttransfer ? (SEG7_Display_avalon_slave_0_arb_share_set_values - 1) : |SEG7_Display_avalon_slave_0_arb_share_counter ? (SEG7_Display_avalon_slave_0_arb_share_counter - 1) : 0;

  //SEG7_Display_avalon_slave_0_allgrants all slave grants, which is an e_mux
  assign SEG7_Display_avalon_slave_0_allgrants = |SEG7_Display_avalon_slave_0_grant_vector;

  //SEG7_Display_avalon_slave_0_end_xfer assignment, which is an e_assign
  assign SEG7_Display_avalon_slave_0_end_xfer = ~(SEG7_Display_avalon_slave_0_waits_for_read | SEG7_Display_avalon_slave_0_waits_for_write);

  //end_xfer_arb_share_counter_term_SEG7_Display_avalon_slave_0 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_SEG7_Display_avalon_slave_0 = SEG7_Display_avalon_slave_0_end_xfer & (~SEG7_Display_avalon_slave_0_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //SEG7_Display_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
  assign SEG7_Display_avalon_slave_0_arb_counter_enable = (end_xfer_arb_share_counter_term_SEG7_Display_avalon_slave_0 & SEG7_Display_avalon_slave_0_allgrants) | (end_xfer_arb_share_counter_term_SEG7_Display_avalon_slave_0 & ~SEG7_Display_avalon_slave_0_non_bursting_master_requests);

  //SEG7_Display_avalon_slave_0_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SEG7_Display_avalon_slave_0_arb_share_counter <= 0;
      else if (SEG7_Display_avalon_slave_0_arb_counter_enable)
          SEG7_Display_avalon_slave_0_arb_share_counter <= SEG7_Display_avalon_slave_0_arb_share_counter_next_value;
    end


  //SEG7_Display_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SEG7_Display_avalon_slave_0_slavearbiterlockenable <= 0;
      else if ((|SEG7_Display_avalon_slave_0_master_qreq_vector & end_xfer_arb_share_counter_term_SEG7_Display_avalon_slave_0) | (end_xfer_arb_share_counter_term_SEG7_Display_avalon_slave_0 & ~SEG7_Display_avalon_slave_0_non_bursting_master_requests))
          SEG7_Display_avalon_slave_0_slavearbiterlockenable <= |SEG7_Display_avalon_slave_0_arb_share_counter_next_value;
    end


  //system_0_burst_13/downstream SEG7_Display/avalon_slave_0 arbiterlock, which is an e_assign
  assign system_0_burst_13_downstream_arbiterlock = SEG7_Display_avalon_slave_0_slavearbiterlockenable & system_0_burst_13_downstream_continuerequest;

  //SEG7_Display_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign SEG7_Display_avalon_slave_0_slavearbiterlockenable2 = |SEG7_Display_avalon_slave_0_arb_share_counter_next_value;

  //system_0_burst_13/downstream SEG7_Display/avalon_slave_0 arbiterlock2, which is an e_assign
  assign system_0_burst_13_downstream_arbiterlock2 = SEG7_Display_avalon_slave_0_slavearbiterlockenable2 & system_0_burst_13_downstream_continuerequest;

  //SEG7_Display_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
  assign SEG7_Display_avalon_slave_0_any_continuerequest = 1;

  //system_0_burst_13_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_13_downstream_continuerequest = 1;

  assign system_0_burst_13_downstream_qualified_request_SEG7_Display_avalon_slave_0 = system_0_burst_13_downstream_requests_SEG7_Display_avalon_slave_0;
  //local readdatavalid system_0_burst_13_downstream_read_data_valid_SEG7_Display_avalon_slave_0, which is an e_mux
  assign system_0_burst_13_downstream_read_data_valid_SEG7_Display_avalon_slave_0 = system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0 & system_0_burst_13_downstream_read & ~SEG7_Display_avalon_slave_0_waits_for_read;

  //SEG7_Display_avalon_slave_0_writedata mux, which is an e_mux
  assign SEG7_Display_avalon_slave_0_writedata = system_0_burst_13_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0 = system_0_burst_13_downstream_qualified_request_SEG7_Display_avalon_slave_0;

  //system_0_burst_13/downstream saved-grant SEG7_Display/avalon_slave_0, which is an e_assign
  assign system_0_burst_13_downstream_saved_grant_SEG7_Display_avalon_slave_0 = system_0_burst_13_downstream_requests_SEG7_Display_avalon_slave_0;

  //allow new arb cycle for SEG7_Display/avalon_slave_0, which is an e_assign
  assign SEG7_Display_avalon_slave_0_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign SEG7_Display_avalon_slave_0_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign SEG7_Display_avalon_slave_0_master_qreq_vector = 1;

  //SEG7_Display_avalon_slave_0_reset_n assignment, which is an e_assign
  assign SEG7_Display_avalon_slave_0_reset_n = reset_n;

  //SEG7_Display_avalon_slave_0_firsttransfer first transaction, which is an e_assign
  assign SEG7_Display_avalon_slave_0_firsttransfer = SEG7_Display_avalon_slave_0_begins_xfer ? SEG7_Display_avalon_slave_0_unreg_firsttransfer : SEG7_Display_avalon_slave_0_reg_firsttransfer;

  //SEG7_Display_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
  assign SEG7_Display_avalon_slave_0_unreg_firsttransfer = ~(SEG7_Display_avalon_slave_0_slavearbiterlockenable & SEG7_Display_avalon_slave_0_any_continuerequest);

  //SEG7_Display_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SEG7_Display_avalon_slave_0_reg_firsttransfer <= 1'b1;
      else if (SEG7_Display_avalon_slave_0_begins_xfer)
          SEG7_Display_avalon_slave_0_reg_firsttransfer <= SEG7_Display_avalon_slave_0_unreg_firsttransfer;
    end


  //SEG7_Display_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign SEG7_Display_avalon_slave_0_beginbursttransfer_internal = SEG7_Display_avalon_slave_0_begins_xfer;

  //SEG7_Display_avalon_slave_0_write assignment, which is an e_mux
  assign SEG7_Display_avalon_slave_0_write = system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0 & system_0_burst_13_downstream_write;

  //d1_SEG7_Display_avalon_slave_0_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_SEG7_Display_avalon_slave_0_end_xfer <= 1;
      else 
        d1_SEG7_Display_avalon_slave_0_end_xfer <= SEG7_Display_avalon_slave_0_end_xfer;
    end


  //SEG7_Display_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
  assign SEG7_Display_avalon_slave_0_waits_for_read = SEG7_Display_avalon_slave_0_in_a_read_cycle & SEG7_Display_avalon_slave_0_begins_xfer;

  //SEG7_Display_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
  assign SEG7_Display_avalon_slave_0_in_a_read_cycle = system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0 & system_0_burst_13_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = SEG7_Display_avalon_slave_0_in_a_read_cycle;

  //SEG7_Display_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
  assign SEG7_Display_avalon_slave_0_waits_for_write = SEG7_Display_avalon_slave_0_in_a_write_cycle & SEG7_Display_avalon_slave_0_begins_xfer;

  //SEG7_Display_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
  assign SEG7_Display_avalon_slave_0_in_a_write_cycle = system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0 & system_0_burst_13_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = SEG7_Display_avalon_slave_0_in_a_write_cycle;

  assign wait_for_SEG7_Display_avalon_slave_0_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //SEG7_Display/avalon_slave_0 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_13/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_13_downstream_requests_SEG7_Display_avalon_slave_0 && (system_0_burst_13_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_13/downstream drove 0 on its 'arbitrationshare' port while accessing slave SEG7_Display/avalon_slave_0", $time);
          $stop;
        end
    end


  //system_0_burst_13/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_13_downstream_requests_SEG7_Display_avalon_slave_0 && (system_0_burst_13_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_13/downstream drove 0 on its 'burstcount' port while accessing slave SEG7_Display/avalon_slave_0", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module altpll_0_pll_slave_arbitrator (
                                       // inputs:
                                        altpll_0_pll_slave_readdata,
                                        clk,
                                        reset_n,
                                        system_0_clock_0_out_address_to_slave,
                                        system_0_clock_0_out_read,
                                        system_0_clock_0_out_write,
                                        system_0_clock_0_out_writedata,

                                       // outputs:
                                        altpll_0_pll_slave_address,
                                        altpll_0_pll_slave_read,
                                        altpll_0_pll_slave_readdata_from_sa,
                                        altpll_0_pll_slave_reset,
                                        altpll_0_pll_slave_write,
                                        altpll_0_pll_slave_writedata,
                                        d1_altpll_0_pll_slave_end_xfer,
                                        system_0_clock_0_out_granted_altpll_0_pll_slave,
                                        system_0_clock_0_out_qualified_request_altpll_0_pll_slave,
                                        system_0_clock_0_out_read_data_valid_altpll_0_pll_slave,
                                        system_0_clock_0_out_requests_altpll_0_pll_slave
                                     )
;

  output  [  1: 0] altpll_0_pll_slave_address;
  output           altpll_0_pll_slave_read;
  output  [ 31: 0] altpll_0_pll_slave_readdata_from_sa;
  output           altpll_0_pll_slave_reset;
  output           altpll_0_pll_slave_write;
  output  [ 31: 0] altpll_0_pll_slave_writedata;
  output           d1_altpll_0_pll_slave_end_xfer;
  output           system_0_clock_0_out_granted_altpll_0_pll_slave;
  output           system_0_clock_0_out_qualified_request_altpll_0_pll_slave;
  output           system_0_clock_0_out_read_data_valid_altpll_0_pll_slave;
  output           system_0_clock_0_out_requests_altpll_0_pll_slave;
  input   [ 31: 0] altpll_0_pll_slave_readdata;
  input            clk;
  input            reset_n;
  input   [  3: 0] system_0_clock_0_out_address_to_slave;
  input            system_0_clock_0_out_read;
  input            system_0_clock_0_out_write;
  input   [ 31: 0] system_0_clock_0_out_writedata;

  wire    [  1: 0] altpll_0_pll_slave_address;
  wire             altpll_0_pll_slave_allgrants;
  wire             altpll_0_pll_slave_allow_new_arb_cycle;
  wire             altpll_0_pll_slave_any_bursting_master_saved_grant;
  wire             altpll_0_pll_slave_any_continuerequest;
  wire             altpll_0_pll_slave_arb_counter_enable;
  reg              altpll_0_pll_slave_arb_share_counter;
  wire             altpll_0_pll_slave_arb_share_counter_next_value;
  wire             altpll_0_pll_slave_arb_share_set_values;
  wire             altpll_0_pll_slave_beginbursttransfer_internal;
  wire             altpll_0_pll_slave_begins_xfer;
  wire             altpll_0_pll_slave_end_xfer;
  wire             altpll_0_pll_slave_firsttransfer;
  wire             altpll_0_pll_slave_grant_vector;
  wire             altpll_0_pll_slave_in_a_read_cycle;
  wire             altpll_0_pll_slave_in_a_write_cycle;
  wire             altpll_0_pll_slave_master_qreq_vector;
  wire             altpll_0_pll_slave_non_bursting_master_requests;
  wire             altpll_0_pll_slave_read;
  wire    [ 31: 0] altpll_0_pll_slave_readdata_from_sa;
  reg              altpll_0_pll_slave_reg_firsttransfer;
  wire             altpll_0_pll_slave_reset;
  reg              altpll_0_pll_slave_slavearbiterlockenable;
  wire             altpll_0_pll_slave_slavearbiterlockenable2;
  wire             altpll_0_pll_slave_unreg_firsttransfer;
  wire             altpll_0_pll_slave_waits_for_read;
  wire             altpll_0_pll_slave_waits_for_write;
  wire             altpll_0_pll_slave_write;
  wire    [ 31: 0] altpll_0_pll_slave_writedata;
  reg              d1_altpll_0_pll_slave_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_altpll_0_pll_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  3: 0] shifted_address_to_altpll_0_pll_slave_from_system_0_clock_0_out;
  wire             system_0_clock_0_out_arbiterlock;
  wire             system_0_clock_0_out_arbiterlock2;
  wire             system_0_clock_0_out_continuerequest;
  wire             system_0_clock_0_out_granted_altpll_0_pll_slave;
  wire             system_0_clock_0_out_qualified_request_altpll_0_pll_slave;
  wire             system_0_clock_0_out_read_data_valid_altpll_0_pll_slave;
  wire             system_0_clock_0_out_requests_altpll_0_pll_slave;
  wire             system_0_clock_0_out_saved_grant_altpll_0_pll_slave;
  wire             wait_for_altpll_0_pll_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~altpll_0_pll_slave_end_xfer;
    end


  assign altpll_0_pll_slave_begins_xfer = ~d1_reasons_to_wait & ((system_0_clock_0_out_qualified_request_altpll_0_pll_slave));
  //assign altpll_0_pll_slave_readdata_from_sa = altpll_0_pll_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign altpll_0_pll_slave_readdata_from_sa = altpll_0_pll_slave_readdata;

  assign system_0_clock_0_out_requests_altpll_0_pll_slave = (1) & (system_0_clock_0_out_read | system_0_clock_0_out_write);
  //altpll_0_pll_slave_arb_share_counter set values, which is an e_mux
  assign altpll_0_pll_slave_arb_share_set_values = 1;

  //altpll_0_pll_slave_non_bursting_master_requests mux, which is an e_mux
  assign altpll_0_pll_slave_non_bursting_master_requests = system_0_clock_0_out_requests_altpll_0_pll_slave;

  //altpll_0_pll_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign altpll_0_pll_slave_any_bursting_master_saved_grant = 0;

  //altpll_0_pll_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign altpll_0_pll_slave_arb_share_counter_next_value = altpll_0_pll_slave_firsttransfer ? (altpll_0_pll_slave_arb_share_set_values - 1) : |altpll_0_pll_slave_arb_share_counter ? (altpll_0_pll_slave_arb_share_counter - 1) : 0;

  //altpll_0_pll_slave_allgrants all slave grants, which is an e_mux
  assign altpll_0_pll_slave_allgrants = |altpll_0_pll_slave_grant_vector;

  //altpll_0_pll_slave_end_xfer assignment, which is an e_assign
  assign altpll_0_pll_slave_end_xfer = ~(altpll_0_pll_slave_waits_for_read | altpll_0_pll_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_altpll_0_pll_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_altpll_0_pll_slave = altpll_0_pll_slave_end_xfer & (~altpll_0_pll_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //altpll_0_pll_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign altpll_0_pll_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_altpll_0_pll_slave & altpll_0_pll_slave_allgrants) | (end_xfer_arb_share_counter_term_altpll_0_pll_slave & ~altpll_0_pll_slave_non_bursting_master_requests);

  //altpll_0_pll_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          altpll_0_pll_slave_arb_share_counter <= 0;
      else if (altpll_0_pll_slave_arb_counter_enable)
          altpll_0_pll_slave_arb_share_counter <= altpll_0_pll_slave_arb_share_counter_next_value;
    end


  //altpll_0_pll_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          altpll_0_pll_slave_slavearbiterlockenable <= 0;
      else if ((|altpll_0_pll_slave_master_qreq_vector & end_xfer_arb_share_counter_term_altpll_0_pll_slave) | (end_xfer_arb_share_counter_term_altpll_0_pll_slave & ~altpll_0_pll_slave_non_bursting_master_requests))
          altpll_0_pll_slave_slavearbiterlockenable <= |altpll_0_pll_slave_arb_share_counter_next_value;
    end


  //system_0_clock_0/out altpll_0/pll_slave arbiterlock, which is an e_assign
  assign system_0_clock_0_out_arbiterlock = altpll_0_pll_slave_slavearbiterlockenable & system_0_clock_0_out_continuerequest;

  //altpll_0_pll_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign altpll_0_pll_slave_slavearbiterlockenable2 = |altpll_0_pll_slave_arb_share_counter_next_value;

  //system_0_clock_0/out altpll_0/pll_slave arbiterlock2, which is an e_assign
  assign system_0_clock_0_out_arbiterlock2 = altpll_0_pll_slave_slavearbiterlockenable2 & system_0_clock_0_out_continuerequest;

  //altpll_0_pll_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign altpll_0_pll_slave_any_continuerequest = 1;

  //system_0_clock_0_out_continuerequest continued request, which is an e_assign
  assign system_0_clock_0_out_continuerequest = 1;

  assign system_0_clock_0_out_qualified_request_altpll_0_pll_slave = system_0_clock_0_out_requests_altpll_0_pll_slave;
  //altpll_0_pll_slave_writedata mux, which is an e_mux
  assign altpll_0_pll_slave_writedata = system_0_clock_0_out_writedata;

  //master is always granted when requested
  assign system_0_clock_0_out_granted_altpll_0_pll_slave = system_0_clock_0_out_qualified_request_altpll_0_pll_slave;

  //system_0_clock_0/out saved-grant altpll_0/pll_slave, which is an e_assign
  assign system_0_clock_0_out_saved_grant_altpll_0_pll_slave = system_0_clock_0_out_requests_altpll_0_pll_slave;

  //allow new arb cycle for altpll_0/pll_slave, which is an e_assign
  assign altpll_0_pll_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign altpll_0_pll_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign altpll_0_pll_slave_master_qreq_vector = 1;

  //~altpll_0_pll_slave_reset assignment, which is an e_assign
  assign altpll_0_pll_slave_reset = ~reset_n;

  //altpll_0_pll_slave_firsttransfer first transaction, which is an e_assign
  assign altpll_0_pll_slave_firsttransfer = altpll_0_pll_slave_begins_xfer ? altpll_0_pll_slave_unreg_firsttransfer : altpll_0_pll_slave_reg_firsttransfer;

  //altpll_0_pll_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign altpll_0_pll_slave_unreg_firsttransfer = ~(altpll_0_pll_slave_slavearbiterlockenable & altpll_0_pll_slave_any_continuerequest);

  //altpll_0_pll_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          altpll_0_pll_slave_reg_firsttransfer <= 1'b1;
      else if (altpll_0_pll_slave_begins_xfer)
          altpll_0_pll_slave_reg_firsttransfer <= altpll_0_pll_slave_unreg_firsttransfer;
    end


  //altpll_0_pll_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign altpll_0_pll_slave_beginbursttransfer_internal = altpll_0_pll_slave_begins_xfer;

  //altpll_0_pll_slave_read assignment, which is an e_mux
  assign altpll_0_pll_slave_read = system_0_clock_0_out_granted_altpll_0_pll_slave & system_0_clock_0_out_read;

  //altpll_0_pll_slave_write assignment, which is an e_mux
  assign altpll_0_pll_slave_write = system_0_clock_0_out_granted_altpll_0_pll_slave & system_0_clock_0_out_write;

  assign shifted_address_to_altpll_0_pll_slave_from_system_0_clock_0_out = system_0_clock_0_out_address_to_slave;
  //altpll_0_pll_slave_address mux, which is an e_mux
  assign altpll_0_pll_slave_address = shifted_address_to_altpll_0_pll_slave_from_system_0_clock_0_out >> 2;

  //d1_altpll_0_pll_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_altpll_0_pll_slave_end_xfer <= 1;
      else 
        d1_altpll_0_pll_slave_end_xfer <= altpll_0_pll_slave_end_xfer;
    end


  //altpll_0_pll_slave_waits_for_read in a cycle, which is an e_mux
  assign altpll_0_pll_slave_waits_for_read = altpll_0_pll_slave_in_a_read_cycle & 0;

  //altpll_0_pll_slave_in_a_read_cycle assignment, which is an e_assign
  assign altpll_0_pll_slave_in_a_read_cycle = system_0_clock_0_out_granted_altpll_0_pll_slave & system_0_clock_0_out_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = altpll_0_pll_slave_in_a_read_cycle;

  //altpll_0_pll_slave_waits_for_write in a cycle, which is an e_mux
  assign altpll_0_pll_slave_waits_for_write = altpll_0_pll_slave_in_a_write_cycle & 0;

  //altpll_0_pll_slave_in_a_write_cycle assignment, which is an e_assign
  assign altpll_0_pll_slave_in_a_write_cycle = system_0_clock_0_out_granted_altpll_0_pll_slave & system_0_clock_0_out_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = altpll_0_pll_slave_in_a_write_cycle;

  assign wait_for_altpll_0_pll_slave_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //altpll_0/pll_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_0_jtag_debug_module_arbitrator (
                                            // inputs:
                                             clk,
                                             cpu_0_jtag_debug_module_readdata,
                                             cpu_0_jtag_debug_module_resetrequest,
                                             reset_n,
                                             system_0_burst_0_downstream_address_to_slave,
                                             system_0_burst_0_downstream_arbitrationshare,
                                             system_0_burst_0_downstream_burstcount,
                                             system_0_burst_0_downstream_byteenable,
                                             system_0_burst_0_downstream_debugaccess,
                                             system_0_burst_0_downstream_latency_counter,
                                             system_0_burst_0_downstream_read,
                                             system_0_burst_0_downstream_write,
                                             system_0_burst_0_downstream_writedata,
                                             system_0_burst_1_downstream_address_to_slave,
                                             system_0_burst_1_downstream_arbitrationshare,
                                             system_0_burst_1_downstream_burstcount,
                                             system_0_burst_1_downstream_byteenable,
                                             system_0_burst_1_downstream_debugaccess,
                                             system_0_burst_1_downstream_latency_counter,
                                             system_0_burst_1_downstream_read,
                                             system_0_burst_1_downstream_write,
                                             system_0_burst_1_downstream_writedata,

                                            // outputs:
                                             cpu_0_jtag_debug_module_address,
                                             cpu_0_jtag_debug_module_begintransfer,
                                             cpu_0_jtag_debug_module_byteenable,
                                             cpu_0_jtag_debug_module_chipselect,
                                             cpu_0_jtag_debug_module_debugaccess,
                                             cpu_0_jtag_debug_module_readdata_from_sa,
                                             cpu_0_jtag_debug_module_reset_n,
                                             cpu_0_jtag_debug_module_resetrequest_from_sa,
                                             cpu_0_jtag_debug_module_write,
                                             cpu_0_jtag_debug_module_writedata,
                                             d1_cpu_0_jtag_debug_module_end_xfer,
                                             system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module,
                                             system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module,
                                             system_0_burst_0_downstream_read_data_valid_cpu_0_jtag_debug_module,
                                             system_0_burst_0_downstream_requests_cpu_0_jtag_debug_module,
                                             system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module,
                                             system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module,
                                             system_0_burst_1_downstream_read_data_valid_cpu_0_jtag_debug_module,
                                             system_0_burst_1_downstream_requests_cpu_0_jtag_debug_module
                                          )
;

  output  [  8: 0] cpu_0_jtag_debug_module_address;
  output           cpu_0_jtag_debug_module_begintransfer;
  output  [  3: 0] cpu_0_jtag_debug_module_byteenable;
  output           cpu_0_jtag_debug_module_chipselect;
  output           cpu_0_jtag_debug_module_debugaccess;
  output  [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
  output           cpu_0_jtag_debug_module_reset_n;
  output           cpu_0_jtag_debug_module_resetrequest_from_sa;
  output           cpu_0_jtag_debug_module_write;
  output  [ 31: 0] cpu_0_jtag_debug_module_writedata;
  output           d1_cpu_0_jtag_debug_module_end_xfer;
  output           system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module;
  output           system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module;
  output           system_0_burst_0_downstream_read_data_valid_cpu_0_jtag_debug_module;
  output           system_0_burst_0_downstream_requests_cpu_0_jtag_debug_module;
  output           system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module;
  output           system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module;
  output           system_0_burst_1_downstream_read_data_valid_cpu_0_jtag_debug_module;
  output           system_0_burst_1_downstream_requests_cpu_0_jtag_debug_module;
  input            clk;
  input   [ 31: 0] cpu_0_jtag_debug_module_readdata;
  input            cpu_0_jtag_debug_module_resetrequest;
  input            reset_n;
  input   [ 10: 0] system_0_burst_0_downstream_address_to_slave;
  input   [  3: 0] system_0_burst_0_downstream_arbitrationshare;
  input            system_0_burst_0_downstream_burstcount;
  input   [  3: 0] system_0_burst_0_downstream_byteenable;
  input            system_0_burst_0_downstream_debugaccess;
  input            system_0_burst_0_downstream_latency_counter;
  input            system_0_burst_0_downstream_read;
  input            system_0_burst_0_downstream_write;
  input   [ 31: 0] system_0_burst_0_downstream_writedata;
  input   [ 10: 0] system_0_burst_1_downstream_address_to_slave;
  input   [  3: 0] system_0_burst_1_downstream_arbitrationshare;
  input            system_0_burst_1_downstream_burstcount;
  input   [  3: 0] system_0_burst_1_downstream_byteenable;
  input            system_0_burst_1_downstream_debugaccess;
  input            system_0_burst_1_downstream_latency_counter;
  input            system_0_burst_1_downstream_read;
  input            system_0_burst_1_downstream_write;
  input   [ 31: 0] system_0_burst_1_downstream_writedata;

  wire    [  8: 0] cpu_0_jtag_debug_module_address;
  wire             cpu_0_jtag_debug_module_allgrants;
  wire             cpu_0_jtag_debug_module_allow_new_arb_cycle;
  wire             cpu_0_jtag_debug_module_any_bursting_master_saved_grant;
  wire             cpu_0_jtag_debug_module_any_continuerequest;
  reg     [  1: 0] cpu_0_jtag_debug_module_arb_addend;
  wire             cpu_0_jtag_debug_module_arb_counter_enable;
  reg     [  3: 0] cpu_0_jtag_debug_module_arb_share_counter;
  wire    [  3: 0] cpu_0_jtag_debug_module_arb_share_counter_next_value;
  wire    [  3: 0] cpu_0_jtag_debug_module_arb_share_set_values;
  wire    [  1: 0] cpu_0_jtag_debug_module_arb_winner;
  wire             cpu_0_jtag_debug_module_arbitration_holdoff_internal;
  wire             cpu_0_jtag_debug_module_beginbursttransfer_internal;
  wire             cpu_0_jtag_debug_module_begins_xfer;
  wire             cpu_0_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu_0_jtag_debug_module_byteenable;
  wire             cpu_0_jtag_debug_module_chipselect;
  wire    [  3: 0] cpu_0_jtag_debug_module_chosen_master_double_vector;
  wire    [  1: 0] cpu_0_jtag_debug_module_chosen_master_rot_left;
  wire             cpu_0_jtag_debug_module_debugaccess;
  wire             cpu_0_jtag_debug_module_end_xfer;
  wire             cpu_0_jtag_debug_module_firsttransfer;
  wire    [  1: 0] cpu_0_jtag_debug_module_grant_vector;
  wire             cpu_0_jtag_debug_module_in_a_read_cycle;
  wire             cpu_0_jtag_debug_module_in_a_write_cycle;
  wire    [  1: 0] cpu_0_jtag_debug_module_master_qreq_vector;
  wire             cpu_0_jtag_debug_module_non_bursting_master_requests;
  wire    [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
  reg              cpu_0_jtag_debug_module_reg_firsttransfer;
  wire             cpu_0_jtag_debug_module_reset_n;
  wire             cpu_0_jtag_debug_module_resetrequest_from_sa;
  reg     [  1: 0] cpu_0_jtag_debug_module_saved_chosen_master_vector;
  reg              cpu_0_jtag_debug_module_slavearbiterlockenable;
  wire             cpu_0_jtag_debug_module_slavearbiterlockenable2;
  wire             cpu_0_jtag_debug_module_unreg_firsttransfer;
  wire             cpu_0_jtag_debug_module_waits_for_read;
  wire             cpu_0_jtag_debug_module_waits_for_write;
  wire             cpu_0_jtag_debug_module_write;
  wire    [ 31: 0] cpu_0_jtag_debug_module_writedata;
  reg              d1_cpu_0_jtag_debug_module_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_system_0_burst_0_downstream_granted_slave_cpu_0_jtag_debug_module;
  reg              last_cycle_system_0_burst_1_downstream_granted_slave_cpu_0_jtag_debug_module;
  wire    [ 10: 0] shifted_address_to_cpu_0_jtag_debug_module_from_system_0_burst_0_downstream;
  wire    [ 10: 0] shifted_address_to_cpu_0_jtag_debug_module_from_system_0_burst_1_downstream;
  wire             system_0_burst_0_downstream_arbiterlock;
  wire             system_0_burst_0_downstream_arbiterlock2;
  wire             system_0_burst_0_downstream_continuerequest;
  wire             system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module;
  wire             system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module;
  wire             system_0_burst_0_downstream_read_data_valid_cpu_0_jtag_debug_module;
  wire             system_0_burst_0_downstream_requests_cpu_0_jtag_debug_module;
  wire             system_0_burst_0_downstream_saved_grant_cpu_0_jtag_debug_module;
  wire             system_0_burst_1_downstream_arbiterlock;
  wire             system_0_burst_1_downstream_arbiterlock2;
  wire             system_0_burst_1_downstream_continuerequest;
  wire             system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module;
  wire             system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module;
  wire             system_0_burst_1_downstream_read_data_valid_cpu_0_jtag_debug_module;
  wire             system_0_burst_1_downstream_requests_cpu_0_jtag_debug_module;
  wire             system_0_burst_1_downstream_saved_grant_cpu_0_jtag_debug_module;
  wire             wait_for_cpu_0_jtag_debug_module_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~cpu_0_jtag_debug_module_end_xfer;
    end


  assign cpu_0_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module | system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module));
  //assign cpu_0_jtag_debug_module_readdata_from_sa = cpu_0_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_0_jtag_debug_module_readdata_from_sa = cpu_0_jtag_debug_module_readdata;

  assign system_0_burst_0_downstream_requests_cpu_0_jtag_debug_module = (1) & (system_0_burst_0_downstream_read | system_0_burst_0_downstream_write);
  //cpu_0_jtag_debug_module_arb_share_counter set values, which is an e_mux
  assign cpu_0_jtag_debug_module_arb_share_set_values = (system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module)? system_0_burst_0_downstream_arbitrationshare :
    (system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module)? system_0_burst_1_downstream_arbitrationshare :
    (system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module)? system_0_burst_0_downstream_arbitrationshare :
    (system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module)? system_0_burst_1_downstream_arbitrationshare :
    1;

  //cpu_0_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux
  assign cpu_0_jtag_debug_module_non_bursting_master_requests = 0;

  //cpu_0_jtag_debug_module_any_bursting_master_saved_grant mux, which is an e_mux
  assign cpu_0_jtag_debug_module_any_bursting_master_saved_grant = system_0_burst_0_downstream_saved_grant_cpu_0_jtag_debug_module |
    system_0_burst_1_downstream_saved_grant_cpu_0_jtag_debug_module |
    system_0_burst_0_downstream_saved_grant_cpu_0_jtag_debug_module |
    system_0_burst_1_downstream_saved_grant_cpu_0_jtag_debug_module;

  //cpu_0_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
  assign cpu_0_jtag_debug_module_arb_share_counter_next_value = cpu_0_jtag_debug_module_firsttransfer ? (cpu_0_jtag_debug_module_arb_share_set_values - 1) : |cpu_0_jtag_debug_module_arb_share_counter ? (cpu_0_jtag_debug_module_arb_share_counter - 1) : 0;

  //cpu_0_jtag_debug_module_allgrants all slave grants, which is an e_mux
  assign cpu_0_jtag_debug_module_allgrants = (|cpu_0_jtag_debug_module_grant_vector) |
    (|cpu_0_jtag_debug_module_grant_vector) |
    (|cpu_0_jtag_debug_module_grant_vector) |
    (|cpu_0_jtag_debug_module_grant_vector);

  //cpu_0_jtag_debug_module_end_xfer assignment, which is an e_assign
  assign cpu_0_jtag_debug_module_end_xfer = ~(cpu_0_jtag_debug_module_waits_for_read | cpu_0_jtag_debug_module_waits_for_write);

  //end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_end_xfer & (~cpu_0_jtag_debug_module_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //cpu_0_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
  assign cpu_0_jtag_debug_module_arb_counter_enable = (end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module & cpu_0_jtag_debug_module_allgrants) | (end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module & ~cpu_0_jtag_debug_module_non_bursting_master_requests);

  //cpu_0_jtag_debug_module_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_jtag_debug_module_arb_share_counter <= 0;
      else if (cpu_0_jtag_debug_module_arb_counter_enable)
          cpu_0_jtag_debug_module_arb_share_counter <= cpu_0_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu_0_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_jtag_debug_module_slavearbiterlockenable <= 0;
      else if ((|cpu_0_jtag_debug_module_master_qreq_vector & end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module) | (end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module & ~cpu_0_jtag_debug_module_non_bursting_master_requests))
          cpu_0_jtag_debug_module_slavearbiterlockenable <= |cpu_0_jtag_debug_module_arb_share_counter_next_value;
    end


  //system_0_burst_0/downstream cpu_0/jtag_debug_module arbiterlock, which is an e_assign
  assign system_0_burst_0_downstream_arbiterlock = cpu_0_jtag_debug_module_slavearbiterlockenable & system_0_burst_0_downstream_continuerequest;

  //cpu_0_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign cpu_0_jtag_debug_module_slavearbiterlockenable2 = |cpu_0_jtag_debug_module_arb_share_counter_next_value;

  //system_0_burst_0/downstream cpu_0/jtag_debug_module arbiterlock2, which is an e_assign
  assign system_0_burst_0_downstream_arbiterlock2 = cpu_0_jtag_debug_module_slavearbiterlockenable2 & system_0_burst_0_downstream_continuerequest;

  //system_0_burst_1/downstream cpu_0/jtag_debug_module arbiterlock, which is an e_assign
  assign system_0_burst_1_downstream_arbiterlock = cpu_0_jtag_debug_module_slavearbiterlockenable & system_0_burst_1_downstream_continuerequest;

  //system_0_burst_1/downstream cpu_0/jtag_debug_module arbiterlock2, which is an e_assign
  assign system_0_burst_1_downstream_arbiterlock2 = cpu_0_jtag_debug_module_slavearbiterlockenable2 & system_0_burst_1_downstream_continuerequest;

  //system_0_burst_1/downstream granted cpu_0/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_system_0_burst_1_downstream_granted_slave_cpu_0_jtag_debug_module <= 0;
      else 
        last_cycle_system_0_burst_1_downstream_granted_slave_cpu_0_jtag_debug_module <= system_0_burst_1_downstream_saved_grant_cpu_0_jtag_debug_module ? 1 : (cpu_0_jtag_debug_module_arbitration_holdoff_internal | 0) ? 0 : last_cycle_system_0_burst_1_downstream_granted_slave_cpu_0_jtag_debug_module;
    end


  //system_0_burst_1_downstream_continuerequest continued request, which is an e_mux
  assign system_0_burst_1_downstream_continuerequest = last_cycle_system_0_burst_1_downstream_granted_slave_cpu_0_jtag_debug_module & 1;

  //cpu_0_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
  assign cpu_0_jtag_debug_module_any_continuerequest = system_0_burst_1_downstream_continuerequest |
    system_0_burst_0_downstream_continuerequest;

  assign system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module = system_0_burst_0_downstream_requests_cpu_0_jtag_debug_module & ~((system_0_burst_0_downstream_read & ((system_0_burst_0_downstream_latency_counter != 0))) | system_0_burst_1_downstream_arbiterlock);
  //local readdatavalid system_0_burst_0_downstream_read_data_valid_cpu_0_jtag_debug_module, which is an e_mux
  assign system_0_burst_0_downstream_read_data_valid_cpu_0_jtag_debug_module = system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module & system_0_burst_0_downstream_read & ~cpu_0_jtag_debug_module_waits_for_read;

  //cpu_0_jtag_debug_module_writedata mux, which is an e_mux
  assign cpu_0_jtag_debug_module_writedata = (system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module)? system_0_burst_0_downstream_writedata :
    system_0_burst_1_downstream_writedata;

  assign system_0_burst_1_downstream_requests_cpu_0_jtag_debug_module = (1) & (system_0_burst_1_downstream_read | system_0_burst_1_downstream_write);
  //system_0_burst_0/downstream granted cpu_0/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_system_0_burst_0_downstream_granted_slave_cpu_0_jtag_debug_module <= 0;
      else 
        last_cycle_system_0_burst_0_downstream_granted_slave_cpu_0_jtag_debug_module <= system_0_burst_0_downstream_saved_grant_cpu_0_jtag_debug_module ? 1 : (cpu_0_jtag_debug_module_arbitration_holdoff_internal | 0) ? 0 : last_cycle_system_0_burst_0_downstream_granted_slave_cpu_0_jtag_debug_module;
    end


  //system_0_burst_0_downstream_continuerequest continued request, which is an e_mux
  assign system_0_burst_0_downstream_continuerequest = last_cycle_system_0_burst_0_downstream_granted_slave_cpu_0_jtag_debug_module & 1;

  assign system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module = system_0_burst_1_downstream_requests_cpu_0_jtag_debug_module & ~((system_0_burst_1_downstream_read & ((system_0_burst_1_downstream_latency_counter != 0))) | system_0_burst_0_downstream_arbiterlock);
  //local readdatavalid system_0_burst_1_downstream_read_data_valid_cpu_0_jtag_debug_module, which is an e_mux
  assign system_0_burst_1_downstream_read_data_valid_cpu_0_jtag_debug_module = system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module & system_0_burst_1_downstream_read & ~cpu_0_jtag_debug_module_waits_for_read;

  //allow new arb cycle for cpu_0/jtag_debug_module, which is an e_assign
  assign cpu_0_jtag_debug_module_allow_new_arb_cycle = ~system_0_burst_0_downstream_arbiterlock & ~system_0_burst_1_downstream_arbiterlock;

  //system_0_burst_1/downstream assignment into master qualified-requests vector for cpu_0/jtag_debug_module, which is an e_assign
  assign cpu_0_jtag_debug_module_master_qreq_vector[0] = system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module;

  //system_0_burst_1/downstream grant cpu_0/jtag_debug_module, which is an e_assign
  assign system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_grant_vector[0];

  //system_0_burst_1/downstream saved-grant cpu_0/jtag_debug_module, which is an e_assign
  assign system_0_burst_1_downstream_saved_grant_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_arb_winner[0];

  //system_0_burst_0/downstream assignment into master qualified-requests vector for cpu_0/jtag_debug_module, which is an e_assign
  assign cpu_0_jtag_debug_module_master_qreq_vector[1] = system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module;

  //system_0_burst_0/downstream grant cpu_0/jtag_debug_module, which is an e_assign
  assign system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_grant_vector[1];

  //system_0_burst_0/downstream saved-grant cpu_0/jtag_debug_module, which is an e_assign
  assign system_0_burst_0_downstream_saved_grant_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_arb_winner[1];

  //cpu_0/jtag_debug_module chosen-master double-vector, which is an e_assign
  assign cpu_0_jtag_debug_module_chosen_master_double_vector = {cpu_0_jtag_debug_module_master_qreq_vector, cpu_0_jtag_debug_module_master_qreq_vector} & ({~cpu_0_jtag_debug_module_master_qreq_vector, ~cpu_0_jtag_debug_module_master_qreq_vector} + cpu_0_jtag_debug_module_arb_addend);

  //stable onehot encoding of arb winner
  assign cpu_0_jtag_debug_module_arb_winner = (cpu_0_jtag_debug_module_allow_new_arb_cycle & | cpu_0_jtag_debug_module_grant_vector) ? cpu_0_jtag_debug_module_grant_vector : cpu_0_jtag_debug_module_saved_chosen_master_vector;

  //saved cpu_0_jtag_debug_module_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_jtag_debug_module_saved_chosen_master_vector <= 0;
      else if (cpu_0_jtag_debug_module_allow_new_arb_cycle)
          cpu_0_jtag_debug_module_saved_chosen_master_vector <= |cpu_0_jtag_debug_module_grant_vector ? cpu_0_jtag_debug_module_grant_vector : cpu_0_jtag_debug_module_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign cpu_0_jtag_debug_module_grant_vector = {(cpu_0_jtag_debug_module_chosen_master_double_vector[1] | cpu_0_jtag_debug_module_chosen_master_double_vector[3]),
    (cpu_0_jtag_debug_module_chosen_master_double_vector[0] | cpu_0_jtag_debug_module_chosen_master_double_vector[2])};

  //cpu_0/jtag_debug_module chosen master rotated left, which is an e_assign
  assign cpu_0_jtag_debug_module_chosen_master_rot_left = (cpu_0_jtag_debug_module_arb_winner << 1) ? (cpu_0_jtag_debug_module_arb_winner << 1) : 1;

  //cpu_0/jtag_debug_module's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_jtag_debug_module_arb_addend <= 1;
      else if (|cpu_0_jtag_debug_module_grant_vector)
          cpu_0_jtag_debug_module_arb_addend <= cpu_0_jtag_debug_module_end_xfer? cpu_0_jtag_debug_module_chosen_master_rot_left : cpu_0_jtag_debug_module_grant_vector;
    end


  assign cpu_0_jtag_debug_module_begintransfer = cpu_0_jtag_debug_module_begins_xfer;
  //cpu_0_jtag_debug_module_reset_n assignment, which is an e_assign
  assign cpu_0_jtag_debug_module_reset_n = reset_n;

  //assign cpu_0_jtag_debug_module_resetrequest_from_sa = cpu_0_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_0_jtag_debug_module_resetrequest_from_sa = cpu_0_jtag_debug_module_resetrequest;

  assign cpu_0_jtag_debug_module_chipselect = system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module | system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module;
  //cpu_0_jtag_debug_module_firsttransfer first transaction, which is an e_assign
  assign cpu_0_jtag_debug_module_firsttransfer = cpu_0_jtag_debug_module_begins_xfer ? cpu_0_jtag_debug_module_unreg_firsttransfer : cpu_0_jtag_debug_module_reg_firsttransfer;

  //cpu_0_jtag_debug_module_unreg_firsttransfer first transaction, which is an e_assign
  assign cpu_0_jtag_debug_module_unreg_firsttransfer = ~(cpu_0_jtag_debug_module_slavearbiterlockenable & cpu_0_jtag_debug_module_any_continuerequest);

  //cpu_0_jtag_debug_module_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_jtag_debug_module_reg_firsttransfer <= 1'b1;
      else if (cpu_0_jtag_debug_module_begins_xfer)
          cpu_0_jtag_debug_module_reg_firsttransfer <= cpu_0_jtag_debug_module_unreg_firsttransfer;
    end


  //cpu_0_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign cpu_0_jtag_debug_module_beginbursttransfer_internal = cpu_0_jtag_debug_module_begins_xfer;

  //cpu_0_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign cpu_0_jtag_debug_module_arbitration_holdoff_internal = cpu_0_jtag_debug_module_begins_xfer & cpu_0_jtag_debug_module_firsttransfer;

  //cpu_0_jtag_debug_module_write assignment, which is an e_mux
  assign cpu_0_jtag_debug_module_write = (system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module & system_0_burst_0_downstream_write) | (system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module & system_0_burst_1_downstream_write);

  assign shifted_address_to_cpu_0_jtag_debug_module_from_system_0_burst_0_downstream = system_0_burst_0_downstream_address_to_slave;
  //cpu_0_jtag_debug_module_address mux, which is an e_mux
  assign cpu_0_jtag_debug_module_address = (system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module)? (shifted_address_to_cpu_0_jtag_debug_module_from_system_0_burst_0_downstream >> 2) :
    (shifted_address_to_cpu_0_jtag_debug_module_from_system_0_burst_1_downstream >> 2);

  assign shifted_address_to_cpu_0_jtag_debug_module_from_system_0_burst_1_downstream = system_0_burst_1_downstream_address_to_slave;
  //d1_cpu_0_jtag_debug_module_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_cpu_0_jtag_debug_module_end_xfer <= 1;
      else 
        d1_cpu_0_jtag_debug_module_end_xfer <= cpu_0_jtag_debug_module_end_xfer;
    end


  //cpu_0_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
  assign cpu_0_jtag_debug_module_waits_for_read = cpu_0_jtag_debug_module_in_a_read_cycle & cpu_0_jtag_debug_module_begins_xfer;

  //cpu_0_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
  assign cpu_0_jtag_debug_module_in_a_read_cycle = (system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module & system_0_burst_0_downstream_read) | (system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module & system_0_burst_1_downstream_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = cpu_0_jtag_debug_module_in_a_read_cycle;

  //cpu_0_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
  assign cpu_0_jtag_debug_module_waits_for_write = cpu_0_jtag_debug_module_in_a_write_cycle & 0;

  //cpu_0_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
  assign cpu_0_jtag_debug_module_in_a_write_cycle = (system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module & system_0_burst_0_downstream_write) | (system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module & system_0_burst_1_downstream_write);

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = cpu_0_jtag_debug_module_in_a_write_cycle;

  assign wait_for_cpu_0_jtag_debug_module_counter = 0;
  //cpu_0_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
  assign cpu_0_jtag_debug_module_byteenable = (system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module)? system_0_burst_0_downstream_byteenable :
    (system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module)? system_0_burst_1_downstream_byteenable :
    -1;

  //debugaccess mux, which is an e_mux
  assign cpu_0_jtag_debug_module_debugaccess = (system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module)? system_0_burst_0_downstream_debugaccess :
    (system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module)? system_0_burst_1_downstream_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu_0/jtag_debug_module enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_0/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_0_downstream_requests_cpu_0_jtag_debug_module && (system_0_burst_0_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_0/downstream drove 0 on its 'arbitrationshare' port while accessing slave cpu_0/jtag_debug_module", $time);
          $stop;
        end
    end


  //system_0_burst_0/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_0_downstream_requests_cpu_0_jtag_debug_module && (system_0_burst_0_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_0/downstream drove 0 on its 'burstcount' port while accessing slave cpu_0/jtag_debug_module", $time);
          $stop;
        end
    end


  //system_0_burst_1/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_1_downstream_requests_cpu_0_jtag_debug_module && (system_0_burst_1_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_1/downstream drove 0 on its 'arbitrationshare' port while accessing slave cpu_0/jtag_debug_module", $time);
          $stop;
        end
    end


  //system_0_burst_1/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_1_downstream_requests_cpu_0_jtag_debug_module && (system_0_burst_1_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_1/downstream drove 0 on its 'burstcount' port while accessing slave cpu_0/jtag_debug_module", $time);
          $stop;
        end
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module + system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_0_downstream_saved_grant_cpu_0_jtag_debug_module + system_0_burst_1_downstream_saved_grant_cpu_0_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_0_data_master_arbitrator (
                                      // inputs:
                                       MS_s1_irq_from_sa,
                                       Oct_DOWN_s1_irq_from_sa,
                                       Oct_UP_s1_irq_from_sa,
                                       RST_s1_irq_from_sa,
                                       clk,
                                       cpu_0_data_master_address,
                                       cpu_0_data_master_burstcount,
                                       cpu_0_data_master_byteenable,
                                       cpu_0_data_master_byteenable_system_0_burst_15_upstream,
                                       cpu_0_data_master_byteenable_system_0_burst_3_upstream,
                                       cpu_0_data_master_byteenable_system_0_burst_5_upstream,
                                       cpu_0_data_master_granted_system_0_burst_10_upstream,
                                       cpu_0_data_master_granted_system_0_burst_11_upstream,
                                       cpu_0_data_master_granted_system_0_burst_12_upstream,
                                       cpu_0_data_master_granted_system_0_burst_13_upstream,
                                       cpu_0_data_master_granted_system_0_burst_15_upstream,
                                       cpu_0_data_master_granted_system_0_burst_16_upstream,
                                       cpu_0_data_master_granted_system_0_burst_17_upstream,
                                       cpu_0_data_master_granted_system_0_burst_18_upstream,
                                       cpu_0_data_master_granted_system_0_burst_19_upstream,
                                       cpu_0_data_master_granted_system_0_burst_1_upstream,
                                       cpu_0_data_master_granted_system_0_burst_20_upstream,
                                       cpu_0_data_master_granted_system_0_burst_21_upstream,
                                       cpu_0_data_master_granted_system_0_burst_22_upstream,
                                       cpu_0_data_master_granted_system_0_burst_23_upstream,
                                       cpu_0_data_master_granted_system_0_burst_24_upstream,
                                       cpu_0_data_master_granted_system_0_burst_25_upstream,
                                       cpu_0_data_master_granted_system_0_burst_26_upstream,
                                       cpu_0_data_master_granted_system_0_burst_27_upstream,
                                       cpu_0_data_master_granted_system_0_burst_28_upstream,
                                       cpu_0_data_master_granted_system_0_burst_29_upstream,
                                       cpu_0_data_master_granted_system_0_burst_30_upstream,
                                       cpu_0_data_master_granted_system_0_burst_31_upstream,
                                       cpu_0_data_master_granted_system_0_burst_32_upstream,
                                       cpu_0_data_master_granted_system_0_burst_34_upstream,
                                       cpu_0_data_master_granted_system_0_burst_35_upstream,
                                       cpu_0_data_master_granted_system_0_burst_3_upstream,
                                       cpu_0_data_master_granted_system_0_burst_5_upstream,
                                       cpu_0_data_master_granted_system_0_burst_7_upstream,
                                       cpu_0_data_master_granted_system_0_burst_8_upstream,
                                       cpu_0_data_master_granted_system_0_burst_9_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_10_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_11_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_12_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_13_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_15_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_16_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_17_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_18_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_19_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_1_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_20_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_21_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_22_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_23_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_24_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_25_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_26_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_27_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_28_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_29_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_30_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_31_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_32_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_34_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_35_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_3_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_5_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_7_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_8_upstream,
                                       cpu_0_data_master_qualified_request_system_0_burst_9_upstream,
                                       cpu_0_data_master_read,
                                       cpu_0_data_master_read_data_valid_system_0_burst_10_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_11_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_12_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_13_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_15_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_16_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_17_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_18_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_19_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_1_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_20_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_21_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_22_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_23_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_24_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_25_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_26_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_27_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_28_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_29_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_30_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_31_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_32_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_34_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_35_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_3_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_5_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_7_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_8_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                       cpu_0_data_master_read_data_valid_system_0_burst_9_upstream,
                                       cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                       cpu_0_data_master_requests_system_0_burst_10_upstream,
                                       cpu_0_data_master_requests_system_0_burst_11_upstream,
                                       cpu_0_data_master_requests_system_0_burst_12_upstream,
                                       cpu_0_data_master_requests_system_0_burst_13_upstream,
                                       cpu_0_data_master_requests_system_0_burst_15_upstream,
                                       cpu_0_data_master_requests_system_0_burst_16_upstream,
                                       cpu_0_data_master_requests_system_0_burst_17_upstream,
                                       cpu_0_data_master_requests_system_0_burst_18_upstream,
                                       cpu_0_data_master_requests_system_0_burst_19_upstream,
                                       cpu_0_data_master_requests_system_0_burst_1_upstream,
                                       cpu_0_data_master_requests_system_0_burst_20_upstream,
                                       cpu_0_data_master_requests_system_0_burst_21_upstream,
                                       cpu_0_data_master_requests_system_0_burst_22_upstream,
                                       cpu_0_data_master_requests_system_0_burst_23_upstream,
                                       cpu_0_data_master_requests_system_0_burst_24_upstream,
                                       cpu_0_data_master_requests_system_0_burst_25_upstream,
                                       cpu_0_data_master_requests_system_0_burst_26_upstream,
                                       cpu_0_data_master_requests_system_0_burst_27_upstream,
                                       cpu_0_data_master_requests_system_0_burst_28_upstream,
                                       cpu_0_data_master_requests_system_0_burst_29_upstream,
                                       cpu_0_data_master_requests_system_0_burst_30_upstream,
                                       cpu_0_data_master_requests_system_0_burst_31_upstream,
                                       cpu_0_data_master_requests_system_0_burst_32_upstream,
                                       cpu_0_data_master_requests_system_0_burst_34_upstream,
                                       cpu_0_data_master_requests_system_0_burst_35_upstream,
                                       cpu_0_data_master_requests_system_0_burst_3_upstream,
                                       cpu_0_data_master_requests_system_0_burst_5_upstream,
                                       cpu_0_data_master_requests_system_0_burst_7_upstream,
                                       cpu_0_data_master_requests_system_0_burst_8_upstream,
                                       cpu_0_data_master_requests_system_0_burst_9_upstream,
                                       cpu_0_data_master_write,
                                       cpu_0_data_master_writedata,
                                       d1_system_0_burst_10_upstream_end_xfer,
                                       d1_system_0_burst_11_upstream_end_xfer,
                                       d1_system_0_burst_12_upstream_end_xfer,
                                       d1_system_0_burst_13_upstream_end_xfer,
                                       d1_system_0_burst_15_upstream_end_xfer,
                                       d1_system_0_burst_16_upstream_end_xfer,
                                       d1_system_0_burst_17_upstream_end_xfer,
                                       d1_system_0_burst_18_upstream_end_xfer,
                                       d1_system_0_burst_19_upstream_end_xfer,
                                       d1_system_0_burst_1_upstream_end_xfer,
                                       d1_system_0_burst_20_upstream_end_xfer,
                                       d1_system_0_burst_21_upstream_end_xfer,
                                       d1_system_0_burst_22_upstream_end_xfer,
                                       d1_system_0_burst_23_upstream_end_xfer,
                                       d1_system_0_burst_24_upstream_end_xfer,
                                       d1_system_0_burst_25_upstream_end_xfer,
                                       d1_system_0_burst_26_upstream_end_xfer,
                                       d1_system_0_burst_27_upstream_end_xfer,
                                       d1_system_0_burst_28_upstream_end_xfer,
                                       d1_system_0_burst_29_upstream_end_xfer,
                                       d1_system_0_burst_30_upstream_end_xfer,
                                       d1_system_0_burst_31_upstream_end_xfer,
                                       d1_system_0_burst_32_upstream_end_xfer,
                                       d1_system_0_burst_34_upstream_end_xfer,
                                       d1_system_0_burst_35_upstream_end_xfer,
                                       d1_system_0_burst_3_upstream_end_xfer,
                                       d1_system_0_burst_5_upstream_end_xfer,
                                       d1_system_0_burst_7_upstream_end_xfer,
                                       d1_system_0_burst_8_upstream_end_xfer,
                                       d1_system_0_burst_9_upstream_end_xfer,
                                       dist_sensor_s1_irq_from_sa,
                                       epcs_controller_epcs_control_port_irq_from_sa,
                                       i2c_master_avalon_slave_0_irq_from_sa,
                                       jtag_uart_0_avalon_jtag_slave_irq_from_sa,
                                       reset_n,
                                       system_0_burst_10_upstream_readdata_from_sa,
                                       system_0_burst_10_upstream_waitrequest_from_sa,
                                       system_0_burst_11_upstream_readdata_from_sa,
                                       system_0_burst_11_upstream_waitrequest_from_sa,
                                       system_0_burst_12_upstream_readdata_from_sa,
                                       system_0_burst_12_upstream_waitrequest_from_sa,
                                       system_0_burst_13_upstream_readdata_from_sa,
                                       system_0_burst_13_upstream_waitrequest_from_sa,
                                       system_0_burst_15_upstream_readdata_from_sa,
                                       system_0_burst_15_upstream_waitrequest_from_sa,
                                       system_0_burst_16_upstream_readdata_from_sa,
                                       system_0_burst_16_upstream_waitrequest_from_sa,
                                       system_0_burst_17_upstream_readdata_from_sa,
                                       system_0_burst_17_upstream_waitrequest_from_sa,
                                       system_0_burst_18_upstream_readdata_from_sa,
                                       system_0_burst_18_upstream_waitrequest_from_sa,
                                       system_0_burst_19_upstream_readdata_from_sa,
                                       system_0_burst_19_upstream_waitrequest_from_sa,
                                       system_0_burst_1_upstream_readdata_from_sa,
                                       system_0_burst_1_upstream_waitrequest_from_sa,
                                       system_0_burst_20_upstream_readdata_from_sa,
                                       system_0_burst_20_upstream_waitrequest_from_sa,
                                       system_0_burst_21_upstream_readdata_from_sa,
                                       system_0_burst_21_upstream_waitrequest_from_sa,
                                       system_0_burst_22_upstream_readdata_from_sa,
                                       system_0_burst_22_upstream_waitrequest_from_sa,
                                       system_0_burst_23_upstream_readdata_from_sa,
                                       system_0_burst_23_upstream_waitrequest_from_sa,
                                       system_0_burst_24_upstream_readdata_from_sa,
                                       system_0_burst_24_upstream_waitrequest_from_sa,
                                       system_0_burst_25_upstream_readdata_from_sa,
                                       system_0_burst_25_upstream_waitrequest_from_sa,
                                       system_0_burst_26_upstream_readdata_from_sa,
                                       system_0_burst_26_upstream_waitrequest_from_sa,
                                       system_0_burst_27_upstream_readdata_from_sa,
                                       system_0_burst_27_upstream_waitrequest_from_sa,
                                       system_0_burst_28_upstream_readdata_from_sa,
                                       system_0_burst_28_upstream_waitrequest_from_sa,
                                       system_0_burst_29_upstream_readdata_from_sa,
                                       system_0_burst_29_upstream_waitrequest_from_sa,
                                       system_0_burst_30_upstream_readdata_from_sa,
                                       system_0_burst_30_upstream_waitrequest_from_sa,
                                       system_0_burst_31_upstream_readdata_from_sa,
                                       system_0_burst_31_upstream_waitrequest_from_sa,
                                       system_0_burst_32_upstream_readdata_from_sa,
                                       system_0_burst_32_upstream_waitrequest_from_sa,
                                       system_0_burst_34_upstream_readdata_from_sa,
                                       system_0_burst_34_upstream_waitrequest_from_sa,
                                       system_0_burst_35_upstream_readdata_from_sa,
                                       system_0_burst_35_upstream_waitrequest_from_sa,
                                       system_0_burst_3_upstream_readdata_from_sa,
                                       system_0_burst_3_upstream_waitrequest_from_sa,
                                       system_0_burst_5_upstream_readdata_from_sa,
                                       system_0_burst_5_upstream_waitrequest_from_sa,
                                       system_0_burst_7_upstream_readdata_from_sa,
                                       system_0_burst_7_upstream_waitrequest_from_sa,
                                       system_0_burst_8_upstream_readdata_from_sa,
                                       system_0_burst_8_upstream_waitrequest_from_sa,
                                       system_0_burst_9_upstream_readdata_from_sa,
                                       system_0_burst_9_upstream_waitrequest_from_sa,
                                       timer_0_s1_irq_from_sa,
                                       timer_1_s1_irq_from_sa,
                                       uart_0_s1_irq_from_sa,

                                      // outputs:
                                       cpu_0_data_master_address_to_slave,
                                       cpu_0_data_master_dbs_address,
                                       cpu_0_data_master_dbs_write_16,
                                       cpu_0_data_master_dbs_write_8,
                                       cpu_0_data_master_irq,
                                       cpu_0_data_master_latency_counter,
                                       cpu_0_data_master_readdata,
                                       cpu_0_data_master_readdatavalid,
                                       cpu_0_data_master_waitrequest
                                    )
;

  output  [ 24: 0] cpu_0_data_master_address_to_slave;
  output  [  1: 0] cpu_0_data_master_dbs_address;
  output  [ 15: 0] cpu_0_data_master_dbs_write_16;
  output  [  7: 0] cpu_0_data_master_dbs_write_8;
  output  [ 31: 0] cpu_0_data_master_irq;
  output           cpu_0_data_master_latency_counter;
  output  [ 31: 0] cpu_0_data_master_readdata;
  output           cpu_0_data_master_readdatavalid;
  output           cpu_0_data_master_waitrequest;
  input            MS_s1_irq_from_sa;
  input            Oct_DOWN_s1_irq_from_sa;
  input            Oct_UP_s1_irq_from_sa;
  input            RST_s1_irq_from_sa;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input   [  1: 0] cpu_0_data_master_byteenable_system_0_burst_15_upstream;
  input            cpu_0_data_master_byteenable_system_0_burst_3_upstream;
  input   [  1: 0] cpu_0_data_master_byteenable_system_0_burst_5_upstream;
  input            cpu_0_data_master_granted_system_0_burst_10_upstream;
  input            cpu_0_data_master_granted_system_0_burst_11_upstream;
  input            cpu_0_data_master_granted_system_0_burst_12_upstream;
  input            cpu_0_data_master_granted_system_0_burst_13_upstream;
  input            cpu_0_data_master_granted_system_0_burst_15_upstream;
  input            cpu_0_data_master_granted_system_0_burst_16_upstream;
  input            cpu_0_data_master_granted_system_0_burst_17_upstream;
  input            cpu_0_data_master_granted_system_0_burst_18_upstream;
  input            cpu_0_data_master_granted_system_0_burst_19_upstream;
  input            cpu_0_data_master_granted_system_0_burst_1_upstream;
  input            cpu_0_data_master_granted_system_0_burst_20_upstream;
  input            cpu_0_data_master_granted_system_0_burst_21_upstream;
  input            cpu_0_data_master_granted_system_0_burst_22_upstream;
  input            cpu_0_data_master_granted_system_0_burst_23_upstream;
  input            cpu_0_data_master_granted_system_0_burst_24_upstream;
  input            cpu_0_data_master_granted_system_0_burst_25_upstream;
  input            cpu_0_data_master_granted_system_0_burst_26_upstream;
  input            cpu_0_data_master_granted_system_0_burst_27_upstream;
  input            cpu_0_data_master_granted_system_0_burst_28_upstream;
  input            cpu_0_data_master_granted_system_0_burst_29_upstream;
  input            cpu_0_data_master_granted_system_0_burst_30_upstream;
  input            cpu_0_data_master_granted_system_0_burst_31_upstream;
  input            cpu_0_data_master_granted_system_0_burst_32_upstream;
  input            cpu_0_data_master_granted_system_0_burst_34_upstream;
  input            cpu_0_data_master_granted_system_0_burst_35_upstream;
  input            cpu_0_data_master_granted_system_0_burst_3_upstream;
  input            cpu_0_data_master_granted_system_0_burst_5_upstream;
  input            cpu_0_data_master_granted_system_0_burst_7_upstream;
  input            cpu_0_data_master_granted_system_0_burst_8_upstream;
  input            cpu_0_data_master_granted_system_0_burst_9_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_10_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_11_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_12_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_13_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_15_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_16_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_17_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_18_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_19_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_1_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_20_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_21_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_22_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_23_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_24_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_25_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_26_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_27_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_28_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_29_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_30_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_31_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_32_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_34_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_35_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_3_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_5_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_7_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_8_upstream;
  input            cpu_0_data_master_qualified_request_system_0_burst_9_upstream;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_requests_system_0_burst_10_upstream;
  input            cpu_0_data_master_requests_system_0_burst_11_upstream;
  input            cpu_0_data_master_requests_system_0_burst_12_upstream;
  input            cpu_0_data_master_requests_system_0_burst_13_upstream;
  input            cpu_0_data_master_requests_system_0_burst_15_upstream;
  input            cpu_0_data_master_requests_system_0_burst_16_upstream;
  input            cpu_0_data_master_requests_system_0_burst_17_upstream;
  input            cpu_0_data_master_requests_system_0_burst_18_upstream;
  input            cpu_0_data_master_requests_system_0_burst_19_upstream;
  input            cpu_0_data_master_requests_system_0_burst_1_upstream;
  input            cpu_0_data_master_requests_system_0_burst_20_upstream;
  input            cpu_0_data_master_requests_system_0_burst_21_upstream;
  input            cpu_0_data_master_requests_system_0_burst_22_upstream;
  input            cpu_0_data_master_requests_system_0_burst_23_upstream;
  input            cpu_0_data_master_requests_system_0_burst_24_upstream;
  input            cpu_0_data_master_requests_system_0_burst_25_upstream;
  input            cpu_0_data_master_requests_system_0_burst_26_upstream;
  input            cpu_0_data_master_requests_system_0_burst_27_upstream;
  input            cpu_0_data_master_requests_system_0_burst_28_upstream;
  input            cpu_0_data_master_requests_system_0_burst_29_upstream;
  input            cpu_0_data_master_requests_system_0_burst_30_upstream;
  input            cpu_0_data_master_requests_system_0_burst_31_upstream;
  input            cpu_0_data_master_requests_system_0_burst_32_upstream;
  input            cpu_0_data_master_requests_system_0_burst_34_upstream;
  input            cpu_0_data_master_requests_system_0_burst_35_upstream;
  input            cpu_0_data_master_requests_system_0_burst_3_upstream;
  input            cpu_0_data_master_requests_system_0_burst_5_upstream;
  input            cpu_0_data_master_requests_system_0_burst_7_upstream;
  input            cpu_0_data_master_requests_system_0_burst_8_upstream;
  input            cpu_0_data_master_requests_system_0_burst_9_upstream;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            d1_system_0_burst_10_upstream_end_xfer;
  input            d1_system_0_burst_11_upstream_end_xfer;
  input            d1_system_0_burst_12_upstream_end_xfer;
  input            d1_system_0_burst_13_upstream_end_xfer;
  input            d1_system_0_burst_15_upstream_end_xfer;
  input            d1_system_0_burst_16_upstream_end_xfer;
  input            d1_system_0_burst_17_upstream_end_xfer;
  input            d1_system_0_burst_18_upstream_end_xfer;
  input            d1_system_0_burst_19_upstream_end_xfer;
  input            d1_system_0_burst_1_upstream_end_xfer;
  input            d1_system_0_burst_20_upstream_end_xfer;
  input            d1_system_0_burst_21_upstream_end_xfer;
  input            d1_system_0_burst_22_upstream_end_xfer;
  input            d1_system_0_burst_23_upstream_end_xfer;
  input            d1_system_0_burst_24_upstream_end_xfer;
  input            d1_system_0_burst_25_upstream_end_xfer;
  input            d1_system_0_burst_26_upstream_end_xfer;
  input            d1_system_0_burst_27_upstream_end_xfer;
  input            d1_system_0_burst_28_upstream_end_xfer;
  input            d1_system_0_burst_29_upstream_end_xfer;
  input            d1_system_0_burst_30_upstream_end_xfer;
  input            d1_system_0_burst_31_upstream_end_xfer;
  input            d1_system_0_burst_32_upstream_end_xfer;
  input            d1_system_0_burst_34_upstream_end_xfer;
  input            d1_system_0_burst_35_upstream_end_xfer;
  input            d1_system_0_burst_3_upstream_end_xfer;
  input            d1_system_0_burst_5_upstream_end_xfer;
  input            d1_system_0_burst_7_upstream_end_xfer;
  input            d1_system_0_burst_8_upstream_end_xfer;
  input            d1_system_0_burst_9_upstream_end_xfer;
  input            dist_sensor_s1_irq_from_sa;
  input            epcs_controller_epcs_control_port_irq_from_sa;
  input            i2c_master_avalon_slave_0_irq_from_sa;
  input            jtag_uart_0_avalon_jtag_slave_irq_from_sa;
  input            reset_n;
  input   [ 15: 0] system_0_burst_10_upstream_readdata_from_sa;
  input            system_0_burst_10_upstream_waitrequest_from_sa;
  input   [ 15: 0] system_0_burst_11_upstream_readdata_from_sa;
  input            system_0_burst_11_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_12_upstream_readdata_from_sa;
  input            system_0_burst_12_upstream_waitrequest_from_sa;
  input   [ 31: 0] system_0_burst_13_upstream_readdata_from_sa;
  input            system_0_burst_13_upstream_waitrequest_from_sa;
  input   [ 15: 0] system_0_burst_15_upstream_readdata_from_sa;
  input            system_0_burst_15_upstream_waitrequest_from_sa;
  input   [ 15: 0] system_0_burst_16_upstream_readdata_from_sa;
  input            system_0_burst_16_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_17_upstream_readdata_from_sa;
  input            system_0_burst_17_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_18_upstream_readdata_from_sa;
  input            system_0_burst_18_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_19_upstream_readdata_from_sa;
  input            system_0_burst_19_upstream_waitrequest_from_sa;
  input   [ 31: 0] system_0_burst_1_upstream_readdata_from_sa;
  input            system_0_burst_1_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_20_upstream_readdata_from_sa;
  input            system_0_burst_20_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_21_upstream_readdata_from_sa;
  input            system_0_burst_21_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_22_upstream_readdata_from_sa;
  input            system_0_burst_22_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_23_upstream_readdata_from_sa;
  input            system_0_burst_23_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_24_upstream_readdata_from_sa;
  input            system_0_burst_24_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_25_upstream_readdata_from_sa;
  input            system_0_burst_25_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_26_upstream_readdata_from_sa;
  input            system_0_burst_26_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_27_upstream_readdata_from_sa;
  input            system_0_burst_27_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_28_upstream_readdata_from_sa;
  input            system_0_burst_28_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_29_upstream_readdata_from_sa;
  input            system_0_burst_29_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_30_upstream_readdata_from_sa;
  input            system_0_burst_30_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_31_upstream_readdata_from_sa;
  input            system_0_burst_31_upstream_waitrequest_from_sa;
  input   [ 31: 0] system_0_burst_32_upstream_readdata_from_sa;
  input            system_0_burst_32_upstream_waitrequest_from_sa;
  input   [ 31: 0] system_0_burst_34_upstream_readdata_from_sa;
  input            system_0_burst_34_upstream_waitrequest_from_sa;
  input   [ 31: 0] system_0_burst_35_upstream_readdata_from_sa;
  input            system_0_burst_35_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_3_upstream_readdata_from_sa;
  input            system_0_burst_3_upstream_waitrequest_from_sa;
  input   [ 15: 0] system_0_burst_5_upstream_readdata_from_sa;
  input            system_0_burst_5_upstream_waitrequest_from_sa;
  input   [ 31: 0] system_0_burst_7_upstream_readdata_from_sa;
  input            system_0_burst_7_upstream_waitrequest_from_sa;
  input   [ 31: 0] system_0_burst_8_upstream_readdata_from_sa;
  input            system_0_burst_8_upstream_waitrequest_from_sa;
  input   [ 15: 0] system_0_burst_9_upstream_readdata_from_sa;
  input            system_0_burst_9_upstream_waitrequest_from_sa;
  input            timer_0_s1_irq_from_sa;
  input            timer_1_s1_irq_from_sa;
  input            uart_0_s1_irq_from_sa;

  reg              active_and_waiting_last_time;
  reg     [ 24: 0] cpu_0_data_master_address_last_time;
  wire    [ 24: 0] cpu_0_data_master_address_to_slave;
  reg     [  3: 0] cpu_0_data_master_burstcount_last_time;
  reg     [  3: 0] cpu_0_data_master_byteenable_last_time;
  reg     [  1: 0] cpu_0_data_master_dbs_address;
  wire    [  1: 0] cpu_0_data_master_dbs_increment;
  reg     [  1: 0] cpu_0_data_master_dbs_rdv_counter;
  wire    [  1: 0] cpu_0_data_master_dbs_rdv_counter_inc;
  wire    [ 15: 0] cpu_0_data_master_dbs_write_16;
  wire    [  7: 0] cpu_0_data_master_dbs_write_8;
  wire    [ 31: 0] cpu_0_data_master_irq;
  wire             cpu_0_data_master_is_granted_some_slave;
  reg              cpu_0_data_master_latency_counter;
  wire    [  1: 0] cpu_0_data_master_next_dbs_rdv_counter;
  reg              cpu_0_data_master_read_but_no_slave_selected;
  reg              cpu_0_data_master_read_last_time;
  wire    [ 31: 0] cpu_0_data_master_readdata;
  wire             cpu_0_data_master_readdatavalid;
  wire             cpu_0_data_master_run;
  wire             cpu_0_data_master_waitrequest;
  reg              cpu_0_data_master_write_last_time;
  reg     [ 31: 0] cpu_0_data_master_writedata_last_time;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  reg     [ 15: 0] dbs_latent_16_reg_segment_0;
  reg     [  7: 0] dbs_latent_8_reg_segment_0;
  reg     [  7: 0] dbs_latent_8_reg_segment_1;
  reg     [  7: 0] dbs_latent_8_reg_segment_2;
  wire             dbs_rdv_count_enable;
  wire             dbs_rdv_counter_overflow;
  wire             latency_load_value;
  wire    [  1: 0] next_dbs_address;
  wire             p1_cpu_0_data_master_latency_counter;
  wire    [ 15: 0] p1_dbs_latent_16_reg_segment_0;
  wire    [  7: 0] p1_dbs_latent_8_reg_segment_0;
  wire    [  7: 0] p1_dbs_latent_8_reg_segment_1;
  wire    [  7: 0] p1_dbs_latent_8_reg_segment_2;
  wire             pre_dbs_count_enable;
  wire             pre_flush_cpu_0_data_master_readdatavalid;
  wire             r_0;
  wire             r_1;
  wire             r_2;
  wire             r_3;
  wire             r_4;
  wire             r_5;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (cpu_0_data_master_qualified_request_system_0_burst_1_upstream | ~cpu_0_data_master_requests_system_0_burst_1_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_1_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_1_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_1_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_1_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_10_upstream | ~cpu_0_data_master_requests_system_0_burst_10_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_10_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_10_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_10_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_10_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_11_upstream | ~cpu_0_data_master_requests_system_0_burst_11_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_11_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_11_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_11_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_11_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_12_upstream | ~cpu_0_data_master_requests_system_0_burst_12_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_12_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_12_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_12_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_12_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_13_upstream | ~cpu_0_data_master_requests_system_0_burst_13_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_13_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_13_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_13_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_13_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write))));

  //cascaded wait assignment, which is an e_assign
  assign cpu_0_data_master_run = r_0 & r_1 & r_2 & r_3 & r_4 & r_5;

  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = 1 & (cpu_0_data_master_qualified_request_system_0_burst_15_upstream | ~cpu_0_data_master_requests_system_0_burst_15_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_15_upstream | ~cpu_0_data_master_read | (1 & ~system_0_burst_15_upstream_waitrequest_from_sa & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_system_0_burst_15_upstream | ~cpu_0_data_master_write | (1 & ~system_0_burst_15_upstream_waitrequest_from_sa & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_16_upstream | ~cpu_0_data_master_requests_system_0_burst_16_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_16_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_16_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_16_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_16_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_17_upstream | ~cpu_0_data_master_requests_system_0_burst_17_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_17_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_17_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_17_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_17_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_18_upstream | ~cpu_0_data_master_requests_system_0_burst_18_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_18_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_18_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_18_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_18_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_19_upstream | ~cpu_0_data_master_requests_system_0_burst_19_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_19_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_19_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_19_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_19_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write))));

  //r_2 master_run cascaded wait assignment, which is an e_assign
  assign r_2 = 1 & (cpu_0_data_master_qualified_request_system_0_burst_20_upstream | ~cpu_0_data_master_requests_system_0_burst_20_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_20_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_20_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_20_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_20_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_21_upstream | ~cpu_0_data_master_requests_system_0_burst_21_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_21_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_21_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_21_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_21_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_22_upstream | ~cpu_0_data_master_requests_system_0_burst_22_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_22_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_22_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_22_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_22_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_23_upstream | ~cpu_0_data_master_requests_system_0_burst_23_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_23_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_23_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_23_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_23_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_24_upstream | ~cpu_0_data_master_requests_system_0_burst_24_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_24_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_24_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_24_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_24_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write))));

  //r_3 master_run cascaded wait assignment, which is an e_assign
  assign r_3 = 1 & (cpu_0_data_master_qualified_request_system_0_burst_25_upstream | ~cpu_0_data_master_requests_system_0_burst_25_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_25_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_25_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_25_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_25_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_26_upstream | ~cpu_0_data_master_requests_system_0_burst_26_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_26_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_26_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_26_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_26_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_27_upstream | ~cpu_0_data_master_requests_system_0_burst_27_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_27_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_27_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_27_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_27_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_28_upstream | ~cpu_0_data_master_requests_system_0_burst_28_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_28_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_28_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_28_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_28_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_29_upstream | ~cpu_0_data_master_requests_system_0_burst_29_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_29_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_29_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_29_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_29_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write))));

  //r_4 master_run cascaded wait assignment, which is an e_assign
  assign r_4 = 1 & (cpu_0_data_master_qualified_request_system_0_burst_3_upstream | ~cpu_0_data_master_requests_system_0_burst_3_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_3_upstream | ~cpu_0_data_master_read | (1 & ~system_0_burst_3_upstream_waitrequest_from_sa & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_system_0_burst_3_upstream | ~cpu_0_data_master_write | (1 & ~system_0_burst_3_upstream_waitrequest_from_sa & (cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0]) & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_30_upstream | ~cpu_0_data_master_requests_system_0_burst_30_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_30_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_30_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_30_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_30_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_31_upstream | ~cpu_0_data_master_requests_system_0_burst_31_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_31_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_31_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_31_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_31_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_32_upstream | ~cpu_0_data_master_requests_system_0_burst_32_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_32_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_32_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_32_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_32_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_34_upstream | ~cpu_0_data_master_requests_system_0_burst_34_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_34_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_34_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_34_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_34_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write))));

  //r_5 master_run cascaded wait assignment, which is an e_assign
  assign r_5 = 1 & (cpu_0_data_master_qualified_request_system_0_burst_35_upstream | ~cpu_0_data_master_requests_system_0_burst_35_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_35_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_35_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_35_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_35_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_5_upstream | ~cpu_0_data_master_requests_system_0_burst_5_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_5_upstream | ~cpu_0_data_master_read | (1 & ~system_0_burst_5_upstream_waitrequest_from_sa & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_system_0_burst_5_upstream | ~cpu_0_data_master_write | (1 & ~system_0_burst_5_upstream_waitrequest_from_sa & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_7_upstream | ~cpu_0_data_master_requests_system_0_burst_7_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_7_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_7_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_7_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_7_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_8_upstream | ~cpu_0_data_master_requests_system_0_burst_8_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_8_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_8_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_8_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_8_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_system_0_burst_9_upstream | ~cpu_0_data_master_requests_system_0_burst_9_upstream) & ((~cpu_0_data_master_qualified_request_system_0_burst_9_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_9_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_system_0_burst_9_upstream | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~system_0_burst_9_upstream_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write))));

  //irq assign, which is an e_assign
  assign cpu_0_data_master_irq = {1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    i2c_master_avalon_slave_0_irq_from_sa,
    dist_sensor_s1_irq_from_sa,
    Oct_DOWN_s1_irq_from_sa,
    Oct_UP_s1_irq_from_sa,
    RST_s1_irq_from_sa,
    MS_s1_irq_from_sa,
    timer_1_s1_irq_from_sa,
    timer_0_s1_irq_from_sa,
    uart_0_s1_irq_from_sa,
    jtag_uart_0_avalon_jtag_slave_irq_from_sa,
    epcs_controller_epcs_control_port_irq_from_sa};

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_0_data_master_address_to_slave = cpu_0_data_master_address[24 : 0];

  //cpu_0_data_master_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_read_but_no_slave_selected <= 0;
      else 
        cpu_0_data_master_read_but_no_slave_selected <= cpu_0_data_master_read & cpu_0_data_master_run & ~cpu_0_data_master_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign cpu_0_data_master_is_granted_some_slave = cpu_0_data_master_granted_system_0_burst_1_upstream |
    cpu_0_data_master_granted_system_0_burst_10_upstream |
    cpu_0_data_master_granted_system_0_burst_11_upstream |
    cpu_0_data_master_granted_system_0_burst_12_upstream |
    cpu_0_data_master_granted_system_0_burst_13_upstream |
    cpu_0_data_master_granted_system_0_burst_15_upstream |
    cpu_0_data_master_granted_system_0_burst_16_upstream |
    cpu_0_data_master_granted_system_0_burst_17_upstream |
    cpu_0_data_master_granted_system_0_burst_18_upstream |
    cpu_0_data_master_granted_system_0_burst_19_upstream |
    cpu_0_data_master_granted_system_0_burst_20_upstream |
    cpu_0_data_master_granted_system_0_burst_21_upstream |
    cpu_0_data_master_granted_system_0_burst_22_upstream |
    cpu_0_data_master_granted_system_0_burst_23_upstream |
    cpu_0_data_master_granted_system_0_burst_24_upstream |
    cpu_0_data_master_granted_system_0_burst_25_upstream |
    cpu_0_data_master_granted_system_0_burst_26_upstream |
    cpu_0_data_master_granted_system_0_burst_27_upstream |
    cpu_0_data_master_granted_system_0_burst_28_upstream |
    cpu_0_data_master_granted_system_0_burst_29_upstream |
    cpu_0_data_master_granted_system_0_burst_3_upstream |
    cpu_0_data_master_granted_system_0_burst_30_upstream |
    cpu_0_data_master_granted_system_0_burst_31_upstream |
    cpu_0_data_master_granted_system_0_burst_32_upstream |
    cpu_0_data_master_granted_system_0_burst_34_upstream |
    cpu_0_data_master_granted_system_0_burst_35_upstream |
    cpu_0_data_master_granted_system_0_burst_5_upstream |
    cpu_0_data_master_granted_system_0_burst_7_upstream |
    cpu_0_data_master_granted_system_0_burst_8_upstream |
    cpu_0_data_master_granted_system_0_burst_9_upstream;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_cpu_0_data_master_readdatavalid = cpu_0_data_master_read_data_valid_system_0_burst_1_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_10_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_11_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_12_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_13_upstream |
    (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream & dbs_rdv_counter_overflow) |
    cpu_0_data_master_read_data_valid_system_0_burst_16_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_17_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_18_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_19_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_20_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_21_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_22_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_23_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_24_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_25_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_26_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_27_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_28_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_29_upstream |
    (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream & dbs_rdv_counter_overflow) |
    cpu_0_data_master_read_data_valid_system_0_burst_30_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_31_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_32_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_34_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_35_upstream |
    (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream & dbs_rdv_counter_overflow) |
    cpu_0_data_master_read_data_valid_system_0_burst_7_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_8_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_9_upstream;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign cpu_0_data_master_readdatavalid = cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid |
    cpu_0_data_master_read_but_no_slave_selected |
    pre_flush_cpu_0_data_master_readdatavalid;

  //cpu_0/data_master readdata mux, which is an e_mux
  assign cpu_0_data_master_readdata = ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_1_upstream}} | system_0_burst_1_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_10_upstream}} | system_0_burst_10_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_11_upstream}} | system_0_burst_11_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_12_upstream}} | system_0_burst_12_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_13_upstream}} | system_0_burst_13_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_15_upstream}} | {system_0_burst_15_upstream_readdata_from_sa[15 : 0],
    dbs_latent_16_reg_segment_0}) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_16_upstream}} | system_0_burst_16_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_17_upstream}} | system_0_burst_17_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_18_upstream}} | system_0_burst_18_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_19_upstream}} | system_0_burst_19_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_20_upstream}} | system_0_burst_20_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_21_upstream}} | system_0_burst_21_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_22_upstream}} | system_0_burst_22_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_23_upstream}} | system_0_burst_23_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_24_upstream}} | system_0_burst_24_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_25_upstream}} | system_0_burst_25_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_26_upstream}} | system_0_burst_26_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_27_upstream}} | system_0_burst_27_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_28_upstream}} | system_0_burst_28_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_29_upstream}} | system_0_burst_29_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_3_upstream}} | {system_0_burst_3_upstream_readdata_from_sa[7 : 0],
    dbs_latent_8_reg_segment_2,
    dbs_latent_8_reg_segment_1,
    dbs_latent_8_reg_segment_0}) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_30_upstream}} | system_0_burst_30_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_31_upstream}} | system_0_burst_31_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_32_upstream}} | system_0_burst_32_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_34_upstream}} | system_0_burst_34_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_35_upstream}} | system_0_burst_35_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_5_upstream}} | {system_0_burst_5_upstream_readdata_from_sa[15 : 0],
    dbs_latent_16_reg_segment_0}) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_7_upstream}} | system_0_burst_7_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_8_upstream}} | system_0_burst_8_upstream_readdata_from_sa) &
    ({32 {~cpu_0_data_master_read_data_valid_system_0_burst_9_upstream}} | system_0_burst_9_upstream_readdata_from_sa);

  //actual waitrequest port, which is an e_assign
  assign cpu_0_data_master_waitrequest = ~cpu_0_data_master_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_latency_counter <= 0;
      else 
        cpu_0_data_master_latency_counter <= p1_cpu_0_data_master_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_cpu_0_data_master_latency_counter = ((cpu_0_data_master_run & cpu_0_data_master_read))? latency_load_value :
    (cpu_0_data_master_latency_counter)? cpu_0_data_master_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = 0;

  //input to latent dbs-16 stored 0, which is an e_mux
  assign p1_dbs_latent_16_reg_segment_0 = (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream)? system_0_burst_15_upstream_readdata_from_sa :
    system_0_burst_5_upstream_readdata_from_sa;

  //dbs register for latent dbs-16 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_16_reg_segment_0 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_0_data_master_dbs_rdv_counter[1]) == 0))
          dbs_latent_16_reg_segment_0 <= p1_dbs_latent_16_reg_segment_0;
    end


  //mux write dbs 1, which is an e_mux
  assign cpu_0_data_master_dbs_write_16 = (cpu_0_data_master_dbs_address[1])? cpu_0_data_master_writedata[31 : 16] :
    (~(cpu_0_data_master_dbs_address[1]))? cpu_0_data_master_writedata[15 : 0] :
    (cpu_0_data_master_dbs_address[1])? cpu_0_data_master_writedata[31 : 16] :
    cpu_0_data_master_writedata[15 : 0];

  //dbs count increment, which is an e_mux
  assign cpu_0_data_master_dbs_increment = (cpu_0_data_master_requests_system_0_burst_15_upstream)? 2 :
    (cpu_0_data_master_requests_system_0_burst_3_upstream)? 1 :
    (cpu_0_data_master_requests_system_0_burst_5_upstream)? 2 :
    0;

  //dbs counter overflow, which is an e_assign
  assign dbs_counter_overflow = cpu_0_data_master_dbs_address[1] & !(next_dbs_address[1]);

  //next master address, which is an e_assign
  assign next_dbs_address = cpu_0_data_master_dbs_address + cpu_0_data_master_dbs_increment;

  //dbs count enable, which is an e_mux
  assign dbs_count_enable = pre_dbs_count_enable;

  //dbs counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_dbs_address <= 0;
      else if (dbs_count_enable)
          cpu_0_data_master_dbs_address <= next_dbs_address;
    end


  //p1 dbs rdv counter, which is an e_assign
  assign cpu_0_data_master_next_dbs_rdv_counter = cpu_0_data_master_dbs_rdv_counter + cpu_0_data_master_dbs_rdv_counter_inc;

  //cpu_0_data_master_rdv_inc_mux, which is an e_mux
  assign cpu_0_data_master_dbs_rdv_counter_inc = (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream)? 2 :
    (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream)? 1 :
    2;

  //master any slave rdv, which is an e_mux
  assign dbs_rdv_count_enable = cpu_0_data_master_read_data_valid_system_0_burst_15_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_3_upstream |
    cpu_0_data_master_read_data_valid_system_0_burst_5_upstream;

  //dbs rdv counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_dbs_rdv_counter <= 0;
      else if (dbs_rdv_count_enable)
          cpu_0_data_master_dbs_rdv_counter <= cpu_0_data_master_next_dbs_rdv_counter;
    end


  //dbs rdv counter overflow, which is an e_assign
  assign dbs_rdv_counter_overflow = cpu_0_data_master_dbs_rdv_counter[1] & ~cpu_0_data_master_next_dbs_rdv_counter[1];

  //pre dbs count enable, which is an e_mux
  assign pre_dbs_count_enable = (cpu_0_data_master_granted_system_0_burst_15_upstream & cpu_0_data_master_read & 0 & 1 & ~system_0_burst_15_upstream_waitrequest_from_sa) |
    (cpu_0_data_master_granted_system_0_burst_15_upstream & cpu_0_data_master_write & 1 & 1 & ~system_0_burst_15_upstream_waitrequest_from_sa) |
    (cpu_0_data_master_granted_system_0_burst_3_upstream & cpu_0_data_master_read & 0 & 1 & ~system_0_burst_3_upstream_waitrequest_from_sa) |
    (cpu_0_data_master_granted_system_0_burst_3_upstream & cpu_0_data_master_write & 1 & 1 & ~system_0_burst_3_upstream_waitrequest_from_sa) |
    (cpu_0_data_master_granted_system_0_burst_5_upstream & cpu_0_data_master_read & 0 & 1 & ~system_0_burst_5_upstream_waitrequest_from_sa) |
    (cpu_0_data_master_granted_system_0_burst_5_upstream & cpu_0_data_master_write & 1 & 1 & ~system_0_burst_5_upstream_waitrequest_from_sa);

  //input to latent dbs-8 stored 0, which is an e_mux
  assign p1_dbs_latent_8_reg_segment_0 = system_0_burst_3_upstream_readdata_from_sa;

  //dbs register for latent dbs-8 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_8_reg_segment_0 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_0_data_master_dbs_rdv_counter[1 : 0]) == 0))
          dbs_latent_8_reg_segment_0 <= p1_dbs_latent_8_reg_segment_0;
    end


  //input to latent dbs-8 stored 1, which is an e_mux
  assign p1_dbs_latent_8_reg_segment_1 = system_0_burst_3_upstream_readdata_from_sa;

  //dbs register for latent dbs-8 segment 1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_8_reg_segment_1 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_0_data_master_dbs_rdv_counter[1 : 0]) == 1))
          dbs_latent_8_reg_segment_1 <= p1_dbs_latent_8_reg_segment_1;
    end


  //input to latent dbs-8 stored 2, which is an e_mux
  assign p1_dbs_latent_8_reg_segment_2 = system_0_burst_3_upstream_readdata_from_sa;

  //dbs register for latent dbs-8 segment 2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_8_reg_segment_2 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_0_data_master_dbs_rdv_counter[1 : 0]) == 2))
          dbs_latent_8_reg_segment_2 <= p1_dbs_latent_8_reg_segment_2;
    end


  //mux write dbs 2, which is an e_mux
  assign cpu_0_data_master_dbs_write_8 = ((cpu_0_data_master_dbs_address[1 : 0] == 0))? cpu_0_data_master_writedata[7 : 0] :
    ((cpu_0_data_master_dbs_address[1 : 0] == 1))? cpu_0_data_master_writedata[15 : 8] :
    ((cpu_0_data_master_dbs_address[1 : 0] == 2))? cpu_0_data_master_writedata[23 : 16] :
    cpu_0_data_master_writedata[31 : 24];


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu_0_data_master_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_address_last_time <= 0;
      else 
        cpu_0_data_master_address_last_time <= cpu_0_data_master_address;
    end


  //cpu_0/data_master waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= cpu_0_data_master_waitrequest & (cpu_0_data_master_read | cpu_0_data_master_write);
    end


  //cpu_0_data_master_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_0_data_master_address != cpu_0_data_master_address_last_time))
        begin
          $write("%0d ns: cpu_0_data_master_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_0_data_master_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_burstcount_last_time <= 0;
      else 
        cpu_0_data_master_burstcount_last_time <= cpu_0_data_master_burstcount;
    end


  //cpu_0_data_master_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_0_data_master_burstcount != cpu_0_data_master_burstcount_last_time))
        begin
          $write("%0d ns: cpu_0_data_master_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_0_data_master_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_byteenable_last_time <= 0;
      else 
        cpu_0_data_master_byteenable_last_time <= cpu_0_data_master_byteenable;
    end


  //cpu_0_data_master_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_0_data_master_byteenable != cpu_0_data_master_byteenable_last_time))
        begin
          $write("%0d ns: cpu_0_data_master_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_0_data_master_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_read_last_time <= 0;
      else 
        cpu_0_data_master_read_last_time <= cpu_0_data_master_read;
    end


  //cpu_0_data_master_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_0_data_master_read != cpu_0_data_master_read_last_time))
        begin
          $write("%0d ns: cpu_0_data_master_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_0_data_master_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_write_last_time <= 0;
      else 
        cpu_0_data_master_write_last_time <= cpu_0_data_master_write;
    end


  //cpu_0_data_master_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_0_data_master_write != cpu_0_data_master_write_last_time))
        begin
          $write("%0d ns: cpu_0_data_master_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_0_data_master_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_writedata_last_time <= 0;
      else 
        cpu_0_data_master_writedata_last_time <= cpu_0_data_master_writedata;
    end


  //cpu_0_data_master_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_0_data_master_writedata != cpu_0_data_master_writedata_last_time) & cpu_0_data_master_write)
        begin
          $write("%0d ns: cpu_0_data_master_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_0_instruction_master_arbitrator (
                                             // inputs:
                                              clk,
                                              cpu_0_instruction_master_address,
                                              cpu_0_instruction_master_burstcount,
                                              cpu_0_instruction_master_granted_system_0_burst_0_upstream,
                                              cpu_0_instruction_master_granted_system_0_burst_14_upstream,
                                              cpu_0_instruction_master_granted_system_0_burst_2_upstream,
                                              cpu_0_instruction_master_granted_system_0_burst_33_upstream,
                                              cpu_0_instruction_master_granted_system_0_burst_4_upstream,
                                              cpu_0_instruction_master_granted_system_0_burst_6_upstream,
                                              cpu_0_instruction_master_qualified_request_system_0_burst_0_upstream,
                                              cpu_0_instruction_master_qualified_request_system_0_burst_14_upstream,
                                              cpu_0_instruction_master_qualified_request_system_0_burst_2_upstream,
                                              cpu_0_instruction_master_qualified_request_system_0_burst_33_upstream,
                                              cpu_0_instruction_master_qualified_request_system_0_burst_4_upstream,
                                              cpu_0_instruction_master_qualified_request_system_0_burst_6_upstream,
                                              cpu_0_instruction_master_read,
                                              cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream,
                                              cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register,
                                              cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream,
                                              cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register,
                                              cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream,
                                              cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register,
                                              cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream,
                                              cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register,
                                              cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream,
                                              cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register,
                                              cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream,
                                              cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register,
                                              cpu_0_instruction_master_requests_system_0_burst_0_upstream,
                                              cpu_0_instruction_master_requests_system_0_burst_14_upstream,
                                              cpu_0_instruction_master_requests_system_0_burst_2_upstream,
                                              cpu_0_instruction_master_requests_system_0_burst_33_upstream,
                                              cpu_0_instruction_master_requests_system_0_burst_4_upstream,
                                              cpu_0_instruction_master_requests_system_0_burst_6_upstream,
                                              d1_system_0_burst_0_upstream_end_xfer,
                                              d1_system_0_burst_14_upstream_end_xfer,
                                              d1_system_0_burst_2_upstream_end_xfer,
                                              d1_system_0_burst_33_upstream_end_xfer,
                                              d1_system_0_burst_4_upstream_end_xfer,
                                              d1_system_0_burst_6_upstream_end_xfer,
                                              reset_n,
                                              system_0_burst_0_upstream_readdata_from_sa,
                                              system_0_burst_0_upstream_waitrequest_from_sa,
                                              system_0_burst_14_upstream_readdata_from_sa,
                                              system_0_burst_14_upstream_waitrequest_from_sa,
                                              system_0_burst_2_upstream_readdata_from_sa,
                                              system_0_burst_2_upstream_waitrequest_from_sa,
                                              system_0_burst_33_upstream_readdata_from_sa,
                                              system_0_burst_33_upstream_waitrequest_from_sa,
                                              system_0_burst_4_upstream_readdata_from_sa,
                                              system_0_burst_4_upstream_waitrequest_from_sa,
                                              system_0_burst_6_upstream_readdata_from_sa,
                                              system_0_burst_6_upstream_waitrequest_from_sa,

                                             // outputs:
                                              cpu_0_instruction_master_address_to_slave,
                                              cpu_0_instruction_master_dbs_address,
                                              cpu_0_instruction_master_latency_counter,
                                              cpu_0_instruction_master_readdata,
                                              cpu_0_instruction_master_readdatavalid,
                                              cpu_0_instruction_master_waitrequest
                                           )
;

  output  [ 24: 0] cpu_0_instruction_master_address_to_slave;
  output  [  1: 0] cpu_0_instruction_master_dbs_address;
  output           cpu_0_instruction_master_latency_counter;
  output  [ 31: 0] cpu_0_instruction_master_readdata;
  output           cpu_0_instruction_master_readdatavalid;
  output           cpu_0_instruction_master_waitrequest;
  input            clk;
  input   [ 24: 0] cpu_0_instruction_master_address;
  input   [  3: 0] cpu_0_instruction_master_burstcount;
  input            cpu_0_instruction_master_granted_system_0_burst_0_upstream;
  input            cpu_0_instruction_master_granted_system_0_burst_14_upstream;
  input            cpu_0_instruction_master_granted_system_0_burst_2_upstream;
  input            cpu_0_instruction_master_granted_system_0_burst_33_upstream;
  input            cpu_0_instruction_master_granted_system_0_burst_4_upstream;
  input            cpu_0_instruction_master_granted_system_0_burst_6_upstream;
  input            cpu_0_instruction_master_qualified_request_system_0_burst_0_upstream;
  input            cpu_0_instruction_master_qualified_request_system_0_burst_14_upstream;
  input            cpu_0_instruction_master_qualified_request_system_0_burst_2_upstream;
  input            cpu_0_instruction_master_qualified_request_system_0_burst_33_upstream;
  input            cpu_0_instruction_master_qualified_request_system_0_burst_4_upstream;
  input            cpu_0_instruction_master_qualified_request_system_0_burst_6_upstream;
  input            cpu_0_instruction_master_read;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register;
  input            cpu_0_instruction_master_requests_system_0_burst_0_upstream;
  input            cpu_0_instruction_master_requests_system_0_burst_14_upstream;
  input            cpu_0_instruction_master_requests_system_0_burst_2_upstream;
  input            cpu_0_instruction_master_requests_system_0_burst_33_upstream;
  input            cpu_0_instruction_master_requests_system_0_burst_4_upstream;
  input            cpu_0_instruction_master_requests_system_0_burst_6_upstream;
  input            d1_system_0_burst_0_upstream_end_xfer;
  input            d1_system_0_burst_14_upstream_end_xfer;
  input            d1_system_0_burst_2_upstream_end_xfer;
  input            d1_system_0_burst_33_upstream_end_xfer;
  input            d1_system_0_burst_4_upstream_end_xfer;
  input            d1_system_0_burst_6_upstream_end_xfer;
  input            reset_n;
  input   [ 31: 0] system_0_burst_0_upstream_readdata_from_sa;
  input            system_0_burst_0_upstream_waitrequest_from_sa;
  input   [ 15: 0] system_0_burst_14_upstream_readdata_from_sa;
  input            system_0_burst_14_upstream_waitrequest_from_sa;
  input   [  7: 0] system_0_burst_2_upstream_readdata_from_sa;
  input            system_0_burst_2_upstream_waitrequest_from_sa;
  input   [ 31: 0] system_0_burst_33_upstream_readdata_from_sa;
  input            system_0_burst_33_upstream_waitrequest_from_sa;
  input   [ 15: 0] system_0_burst_4_upstream_readdata_from_sa;
  input            system_0_burst_4_upstream_waitrequest_from_sa;
  input   [ 31: 0] system_0_burst_6_upstream_readdata_from_sa;
  input            system_0_burst_6_upstream_waitrequest_from_sa;

  reg              active_and_waiting_last_time;
  reg     [ 24: 0] cpu_0_instruction_master_address_last_time;
  wire    [ 24: 0] cpu_0_instruction_master_address_to_slave;
  reg     [  3: 0] cpu_0_instruction_master_burstcount_last_time;
  reg     [  1: 0] cpu_0_instruction_master_dbs_address;
  wire    [  1: 0] cpu_0_instruction_master_dbs_increment;
  reg     [  1: 0] cpu_0_instruction_master_dbs_rdv_counter;
  wire    [  1: 0] cpu_0_instruction_master_dbs_rdv_counter_inc;
  wire             cpu_0_instruction_master_is_granted_some_slave;
  reg              cpu_0_instruction_master_latency_counter;
  wire    [  1: 0] cpu_0_instruction_master_next_dbs_rdv_counter;
  reg              cpu_0_instruction_master_read_but_no_slave_selected;
  reg              cpu_0_instruction_master_read_last_time;
  wire    [ 31: 0] cpu_0_instruction_master_readdata;
  wire             cpu_0_instruction_master_readdatavalid;
  wire             cpu_0_instruction_master_run;
  wire             cpu_0_instruction_master_waitrequest;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  reg     [ 15: 0] dbs_latent_16_reg_segment_0;
  reg     [  7: 0] dbs_latent_8_reg_segment_0;
  reg     [  7: 0] dbs_latent_8_reg_segment_1;
  reg     [  7: 0] dbs_latent_8_reg_segment_2;
  wire             dbs_rdv_count_enable;
  wire             dbs_rdv_counter_overflow;
  wire             latency_load_value;
  wire    [  1: 0] next_dbs_address;
  wire             p1_cpu_0_instruction_master_latency_counter;
  wire    [ 15: 0] p1_dbs_latent_16_reg_segment_0;
  wire    [  7: 0] p1_dbs_latent_8_reg_segment_0;
  wire    [  7: 0] p1_dbs_latent_8_reg_segment_1;
  wire    [  7: 0] p1_dbs_latent_8_reg_segment_2;
  wire             pre_dbs_count_enable;
  wire             pre_flush_cpu_0_instruction_master_readdatavalid;
  wire             r_0;
  wire             r_1;
  wire             r_2;
  wire             r_4;
  wire             r_5;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (cpu_0_instruction_master_qualified_request_system_0_burst_0_upstream | ~cpu_0_instruction_master_requests_system_0_burst_0_upstream) & ((~cpu_0_instruction_master_qualified_request_system_0_burst_0_upstream | ~(cpu_0_instruction_master_read) | (1 & ~system_0_burst_0_upstream_waitrequest_from_sa & (cpu_0_instruction_master_read))));

  //cascaded wait assignment, which is an e_assign
  assign cpu_0_instruction_master_run = r_0 & r_1 & r_2 & r_4 & r_5;

  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = 1 & (cpu_0_instruction_master_qualified_request_system_0_burst_14_upstream | ~cpu_0_instruction_master_requests_system_0_burst_14_upstream) & ((~cpu_0_instruction_master_qualified_request_system_0_burst_14_upstream | ~cpu_0_instruction_master_read | (1 & ~system_0_burst_14_upstream_waitrequest_from_sa & cpu_0_instruction_master_read)));

  //r_2 master_run cascaded wait assignment, which is an e_assign
  assign r_2 = 1 & (cpu_0_instruction_master_qualified_request_system_0_burst_2_upstream | ~cpu_0_instruction_master_requests_system_0_burst_2_upstream) & ((~cpu_0_instruction_master_qualified_request_system_0_burst_2_upstream | ~cpu_0_instruction_master_read | (1 & ~system_0_burst_2_upstream_waitrequest_from_sa & cpu_0_instruction_master_read)));

  //r_4 master_run cascaded wait assignment, which is an e_assign
  assign r_4 = 1 & (cpu_0_instruction_master_qualified_request_system_0_burst_33_upstream | ~cpu_0_instruction_master_requests_system_0_burst_33_upstream) & ((~cpu_0_instruction_master_qualified_request_system_0_burst_33_upstream | ~(cpu_0_instruction_master_read) | (1 & ~system_0_burst_33_upstream_waitrequest_from_sa & (cpu_0_instruction_master_read))));

  //r_5 master_run cascaded wait assignment, which is an e_assign
  assign r_5 = 1 & (cpu_0_instruction_master_qualified_request_system_0_burst_4_upstream | ~cpu_0_instruction_master_requests_system_0_burst_4_upstream) & ((~cpu_0_instruction_master_qualified_request_system_0_burst_4_upstream | ~cpu_0_instruction_master_read | (1 & ~system_0_burst_4_upstream_waitrequest_from_sa & cpu_0_instruction_master_read))) & 1 & (cpu_0_instruction_master_qualified_request_system_0_burst_6_upstream | ~cpu_0_instruction_master_requests_system_0_burst_6_upstream) & ((~cpu_0_instruction_master_qualified_request_system_0_burst_6_upstream | ~(cpu_0_instruction_master_read) | (1 & ~system_0_burst_6_upstream_waitrequest_from_sa & (cpu_0_instruction_master_read))));

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_0_instruction_master_address_to_slave = cpu_0_instruction_master_address[24 : 0];

  //cpu_0_instruction_master_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_read_but_no_slave_selected <= 0;
      else 
        cpu_0_instruction_master_read_but_no_slave_selected <= cpu_0_instruction_master_read & cpu_0_instruction_master_run & ~cpu_0_instruction_master_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign cpu_0_instruction_master_is_granted_some_slave = cpu_0_instruction_master_granted_system_0_burst_0_upstream |
    cpu_0_instruction_master_granted_system_0_burst_14_upstream |
    cpu_0_instruction_master_granted_system_0_burst_2_upstream |
    cpu_0_instruction_master_granted_system_0_burst_33_upstream |
    cpu_0_instruction_master_granted_system_0_burst_4_upstream |
    cpu_0_instruction_master_granted_system_0_burst_6_upstream;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_cpu_0_instruction_master_readdatavalid = cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream |
    (cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream & dbs_rdv_counter_overflow) |
    (cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream & dbs_rdv_counter_overflow) |
    cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream |
    (cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream & dbs_rdv_counter_overflow) |
    cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign cpu_0_instruction_master_readdatavalid = cpu_0_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_0_instruction_master_readdatavalid |
    cpu_0_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_0_instruction_master_readdatavalid |
    cpu_0_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_0_instruction_master_readdatavalid |
    cpu_0_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_0_instruction_master_readdatavalid |
    cpu_0_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_0_instruction_master_readdatavalid |
    cpu_0_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_0_instruction_master_readdatavalid;

  //cpu_0/instruction_master readdata mux, which is an e_mux
  assign cpu_0_instruction_master_readdata = ({32 {~cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream}} | system_0_burst_0_upstream_readdata_from_sa) &
    ({32 {~cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream}} | {system_0_burst_14_upstream_readdata_from_sa[15 : 0],
    dbs_latent_16_reg_segment_0}) &
    ({32 {~cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream}} | {system_0_burst_2_upstream_readdata_from_sa[7 : 0],
    dbs_latent_8_reg_segment_2,
    dbs_latent_8_reg_segment_1,
    dbs_latent_8_reg_segment_0}) &
    ({32 {~cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream}} | system_0_burst_33_upstream_readdata_from_sa) &
    ({32 {~cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream}} | {system_0_burst_4_upstream_readdata_from_sa[15 : 0],
    dbs_latent_16_reg_segment_0}) &
    ({32 {~cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream}} | system_0_burst_6_upstream_readdata_from_sa);

  //actual waitrequest port, which is an e_assign
  assign cpu_0_instruction_master_waitrequest = ~cpu_0_instruction_master_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_latency_counter <= 0;
      else 
        cpu_0_instruction_master_latency_counter <= p1_cpu_0_instruction_master_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_cpu_0_instruction_master_latency_counter = ((cpu_0_instruction_master_run & cpu_0_instruction_master_read))? latency_load_value :
    (cpu_0_instruction_master_latency_counter)? cpu_0_instruction_master_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = 0;

  //input to latent dbs-16 stored 0, which is an e_mux
  assign p1_dbs_latent_16_reg_segment_0 = (cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream)? system_0_burst_14_upstream_readdata_from_sa :
    system_0_burst_4_upstream_readdata_from_sa;

  //dbs register for latent dbs-16 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_16_reg_segment_0 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_0_instruction_master_dbs_rdv_counter[1]) == 0))
          dbs_latent_16_reg_segment_0 <= p1_dbs_latent_16_reg_segment_0;
    end


  //dbs count increment, which is an e_mux
  assign cpu_0_instruction_master_dbs_increment = (cpu_0_instruction_master_requests_system_0_burst_14_upstream)? 2 :
    (cpu_0_instruction_master_requests_system_0_burst_2_upstream)? 1 :
    (cpu_0_instruction_master_requests_system_0_burst_4_upstream)? 2 :
    0;

  //dbs counter overflow, which is an e_assign
  assign dbs_counter_overflow = cpu_0_instruction_master_dbs_address[1] & !(next_dbs_address[1]);

  //next master address, which is an e_assign
  assign next_dbs_address = cpu_0_instruction_master_dbs_address + cpu_0_instruction_master_dbs_increment;

  //dbs count enable, which is an e_mux
  assign dbs_count_enable = pre_dbs_count_enable;

  //dbs counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_dbs_address <= 0;
      else if (dbs_count_enable)
          cpu_0_instruction_master_dbs_address <= next_dbs_address;
    end


  //p1 dbs rdv counter, which is an e_assign
  assign cpu_0_instruction_master_next_dbs_rdv_counter = cpu_0_instruction_master_dbs_rdv_counter + cpu_0_instruction_master_dbs_rdv_counter_inc;

  //cpu_0_instruction_master_rdv_inc_mux, which is an e_mux
  assign cpu_0_instruction_master_dbs_rdv_counter_inc = (cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream)? 2 :
    (cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream)? 1 :
    2;

  //master any slave rdv, which is an e_mux
  assign dbs_rdv_count_enable = cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream |
    cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream |
    cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream;

  //dbs rdv counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_dbs_rdv_counter <= 0;
      else if (dbs_rdv_count_enable)
          cpu_0_instruction_master_dbs_rdv_counter <= cpu_0_instruction_master_next_dbs_rdv_counter;
    end


  //dbs rdv counter overflow, which is an e_assign
  assign dbs_rdv_counter_overflow = cpu_0_instruction_master_dbs_rdv_counter[1] & ~cpu_0_instruction_master_next_dbs_rdv_counter[1];

  //pre dbs count enable, which is an e_mux
  assign pre_dbs_count_enable = (cpu_0_instruction_master_granted_system_0_burst_14_upstream & cpu_0_instruction_master_read & 0 & 1 & ~system_0_burst_14_upstream_waitrequest_from_sa) |
    (cpu_0_instruction_master_granted_system_0_burst_2_upstream & cpu_0_instruction_master_read & 0 & 1 & ~system_0_burst_2_upstream_waitrequest_from_sa) |
    (cpu_0_instruction_master_granted_system_0_burst_4_upstream & cpu_0_instruction_master_read & 0 & 1 & ~system_0_burst_4_upstream_waitrequest_from_sa);

  //input to latent dbs-8 stored 0, which is an e_mux
  assign p1_dbs_latent_8_reg_segment_0 = system_0_burst_2_upstream_readdata_from_sa;

  //dbs register for latent dbs-8 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_8_reg_segment_0 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_0_instruction_master_dbs_rdv_counter[1 : 0]) == 0))
          dbs_latent_8_reg_segment_0 <= p1_dbs_latent_8_reg_segment_0;
    end


  //input to latent dbs-8 stored 1, which is an e_mux
  assign p1_dbs_latent_8_reg_segment_1 = system_0_burst_2_upstream_readdata_from_sa;

  //dbs register for latent dbs-8 segment 1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_8_reg_segment_1 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_0_instruction_master_dbs_rdv_counter[1 : 0]) == 1))
          dbs_latent_8_reg_segment_1 <= p1_dbs_latent_8_reg_segment_1;
    end


  //input to latent dbs-8 stored 2, which is an e_mux
  assign p1_dbs_latent_8_reg_segment_2 = system_0_burst_2_upstream_readdata_from_sa;

  //dbs register for latent dbs-8 segment 2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_8_reg_segment_2 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_0_instruction_master_dbs_rdv_counter[1 : 0]) == 2))
          dbs_latent_8_reg_segment_2 <= p1_dbs_latent_8_reg_segment_2;
    end



//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu_0_instruction_master_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_address_last_time <= 0;
      else 
        cpu_0_instruction_master_address_last_time <= cpu_0_instruction_master_address;
    end


  //cpu_0/instruction_master waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= cpu_0_instruction_master_waitrequest & (cpu_0_instruction_master_read);
    end


  //cpu_0_instruction_master_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_0_instruction_master_address != cpu_0_instruction_master_address_last_time))
        begin
          $write("%0d ns: cpu_0_instruction_master_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_0_instruction_master_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_burstcount_last_time <= 0;
      else 
        cpu_0_instruction_master_burstcount_last_time <= cpu_0_instruction_master_burstcount;
    end


  //cpu_0_instruction_master_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_0_instruction_master_burstcount != cpu_0_instruction_master_burstcount_last_time))
        begin
          $write("%0d ns: cpu_0_instruction_master_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_0_instruction_master_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_read_last_time <= 0;
      else 
        cpu_0_instruction_master_read_last_time <= cpu_0_instruction_master_read;
    end


  //cpu_0_instruction_master_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_0_instruction_master_read != cpu_0_instruction_master_read_last_time))
        begin
          $write("%0d ns: cpu_0_instruction_master_read did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module dist_sensor_s1_arbitrator (
                                   // inputs:
                                    clk,
                                    dist_sensor_s1_irq,
                                    dist_sensor_s1_readdata,
                                    reset_n,
                                    system_0_burst_28_downstream_address_to_slave,
                                    system_0_burst_28_downstream_arbitrationshare,
                                    system_0_burst_28_downstream_burstcount,
                                    system_0_burst_28_downstream_latency_counter,
                                    system_0_burst_28_downstream_nativeaddress,
                                    system_0_burst_28_downstream_read,
                                    system_0_burst_28_downstream_write,
                                    system_0_burst_28_downstream_writedata,

                                   // outputs:
                                    d1_dist_sensor_s1_end_xfer,
                                    dist_sensor_s1_address,
                                    dist_sensor_s1_chipselect,
                                    dist_sensor_s1_irq_from_sa,
                                    dist_sensor_s1_readdata_from_sa,
                                    dist_sensor_s1_reset_n,
                                    dist_sensor_s1_write_n,
                                    dist_sensor_s1_writedata,
                                    system_0_burst_28_downstream_granted_dist_sensor_s1,
                                    system_0_burst_28_downstream_qualified_request_dist_sensor_s1,
                                    system_0_burst_28_downstream_read_data_valid_dist_sensor_s1,
                                    system_0_burst_28_downstream_requests_dist_sensor_s1
                                 )
;

  output           d1_dist_sensor_s1_end_xfer;
  output  [  1: 0] dist_sensor_s1_address;
  output           dist_sensor_s1_chipselect;
  output           dist_sensor_s1_irq_from_sa;
  output           dist_sensor_s1_readdata_from_sa;
  output           dist_sensor_s1_reset_n;
  output           dist_sensor_s1_write_n;
  output           dist_sensor_s1_writedata;
  output           system_0_burst_28_downstream_granted_dist_sensor_s1;
  output           system_0_burst_28_downstream_qualified_request_dist_sensor_s1;
  output           system_0_burst_28_downstream_read_data_valid_dist_sensor_s1;
  output           system_0_burst_28_downstream_requests_dist_sensor_s1;
  input            clk;
  input            dist_sensor_s1_irq;
  input            dist_sensor_s1_readdata;
  input            reset_n;
  input   [  1: 0] system_0_burst_28_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_28_downstream_arbitrationshare;
  input            system_0_burst_28_downstream_burstcount;
  input            system_0_burst_28_downstream_latency_counter;
  input   [  1: 0] system_0_burst_28_downstream_nativeaddress;
  input            system_0_burst_28_downstream_read;
  input            system_0_burst_28_downstream_write;
  input   [  7: 0] system_0_burst_28_downstream_writedata;

  reg              d1_dist_sensor_s1_end_xfer;
  reg              d1_reasons_to_wait;
  wire    [  1: 0] dist_sensor_s1_address;
  wire             dist_sensor_s1_allgrants;
  wire             dist_sensor_s1_allow_new_arb_cycle;
  wire             dist_sensor_s1_any_bursting_master_saved_grant;
  wire             dist_sensor_s1_any_continuerequest;
  wire             dist_sensor_s1_arb_counter_enable;
  reg     [  5: 0] dist_sensor_s1_arb_share_counter;
  wire    [  5: 0] dist_sensor_s1_arb_share_counter_next_value;
  wire    [  5: 0] dist_sensor_s1_arb_share_set_values;
  wire             dist_sensor_s1_beginbursttransfer_internal;
  wire             dist_sensor_s1_begins_xfer;
  wire             dist_sensor_s1_chipselect;
  wire             dist_sensor_s1_end_xfer;
  wire             dist_sensor_s1_firsttransfer;
  wire             dist_sensor_s1_grant_vector;
  wire             dist_sensor_s1_in_a_read_cycle;
  wire             dist_sensor_s1_in_a_write_cycle;
  wire             dist_sensor_s1_irq_from_sa;
  wire             dist_sensor_s1_master_qreq_vector;
  wire             dist_sensor_s1_non_bursting_master_requests;
  wire             dist_sensor_s1_readdata_from_sa;
  reg              dist_sensor_s1_reg_firsttransfer;
  wire             dist_sensor_s1_reset_n;
  reg              dist_sensor_s1_slavearbiterlockenable;
  wire             dist_sensor_s1_slavearbiterlockenable2;
  wire             dist_sensor_s1_unreg_firsttransfer;
  wire             dist_sensor_s1_waits_for_read;
  wire             dist_sensor_s1_waits_for_write;
  wire             dist_sensor_s1_write_n;
  wire             dist_sensor_s1_writedata;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_dist_sensor_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             system_0_burst_28_downstream_arbiterlock;
  wire             system_0_burst_28_downstream_arbiterlock2;
  wire             system_0_burst_28_downstream_continuerequest;
  wire             system_0_burst_28_downstream_granted_dist_sensor_s1;
  wire             system_0_burst_28_downstream_qualified_request_dist_sensor_s1;
  wire             system_0_burst_28_downstream_read_data_valid_dist_sensor_s1;
  wire             system_0_burst_28_downstream_requests_dist_sensor_s1;
  wire             system_0_burst_28_downstream_saved_grant_dist_sensor_s1;
  wire             wait_for_dist_sensor_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~dist_sensor_s1_end_xfer;
    end


  assign dist_sensor_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_28_downstream_qualified_request_dist_sensor_s1));
  //assign dist_sensor_s1_readdata_from_sa = dist_sensor_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign dist_sensor_s1_readdata_from_sa = dist_sensor_s1_readdata;

  assign system_0_burst_28_downstream_requests_dist_sensor_s1 = (1) & (system_0_burst_28_downstream_read | system_0_burst_28_downstream_write);
  //dist_sensor_s1_arb_share_counter set values, which is an e_mux
  assign dist_sensor_s1_arb_share_set_values = (system_0_burst_28_downstream_granted_dist_sensor_s1)? system_0_burst_28_downstream_arbitrationshare :
    1;

  //dist_sensor_s1_non_bursting_master_requests mux, which is an e_mux
  assign dist_sensor_s1_non_bursting_master_requests = 0;

  //dist_sensor_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign dist_sensor_s1_any_bursting_master_saved_grant = system_0_burst_28_downstream_saved_grant_dist_sensor_s1;

  //dist_sensor_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign dist_sensor_s1_arb_share_counter_next_value = dist_sensor_s1_firsttransfer ? (dist_sensor_s1_arb_share_set_values - 1) : |dist_sensor_s1_arb_share_counter ? (dist_sensor_s1_arb_share_counter - 1) : 0;

  //dist_sensor_s1_allgrants all slave grants, which is an e_mux
  assign dist_sensor_s1_allgrants = |dist_sensor_s1_grant_vector;

  //dist_sensor_s1_end_xfer assignment, which is an e_assign
  assign dist_sensor_s1_end_xfer = ~(dist_sensor_s1_waits_for_read | dist_sensor_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_dist_sensor_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_dist_sensor_s1 = dist_sensor_s1_end_xfer & (~dist_sensor_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //dist_sensor_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign dist_sensor_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_dist_sensor_s1 & dist_sensor_s1_allgrants) | (end_xfer_arb_share_counter_term_dist_sensor_s1 & ~dist_sensor_s1_non_bursting_master_requests);

  //dist_sensor_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dist_sensor_s1_arb_share_counter <= 0;
      else if (dist_sensor_s1_arb_counter_enable)
          dist_sensor_s1_arb_share_counter <= dist_sensor_s1_arb_share_counter_next_value;
    end


  //dist_sensor_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dist_sensor_s1_slavearbiterlockenable <= 0;
      else if ((|dist_sensor_s1_master_qreq_vector & end_xfer_arb_share_counter_term_dist_sensor_s1) | (end_xfer_arb_share_counter_term_dist_sensor_s1 & ~dist_sensor_s1_non_bursting_master_requests))
          dist_sensor_s1_slavearbiterlockenable <= |dist_sensor_s1_arb_share_counter_next_value;
    end


  //system_0_burst_28/downstream dist_sensor/s1 arbiterlock, which is an e_assign
  assign system_0_burst_28_downstream_arbiterlock = dist_sensor_s1_slavearbiterlockenable & system_0_burst_28_downstream_continuerequest;

  //dist_sensor_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign dist_sensor_s1_slavearbiterlockenable2 = |dist_sensor_s1_arb_share_counter_next_value;

  //system_0_burst_28/downstream dist_sensor/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_28_downstream_arbiterlock2 = dist_sensor_s1_slavearbiterlockenable2 & system_0_burst_28_downstream_continuerequest;

  //dist_sensor_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign dist_sensor_s1_any_continuerequest = 1;

  //system_0_burst_28_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_28_downstream_continuerequest = 1;

  assign system_0_burst_28_downstream_qualified_request_dist_sensor_s1 = system_0_burst_28_downstream_requests_dist_sensor_s1 & ~((system_0_burst_28_downstream_read & ((system_0_burst_28_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_28_downstream_read_data_valid_dist_sensor_s1, which is an e_mux
  assign system_0_burst_28_downstream_read_data_valid_dist_sensor_s1 = system_0_burst_28_downstream_granted_dist_sensor_s1 & system_0_burst_28_downstream_read & ~dist_sensor_s1_waits_for_read;

  //dist_sensor_s1_writedata mux, which is an e_mux
  assign dist_sensor_s1_writedata = system_0_burst_28_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_28_downstream_granted_dist_sensor_s1 = system_0_burst_28_downstream_qualified_request_dist_sensor_s1;

  //system_0_burst_28/downstream saved-grant dist_sensor/s1, which is an e_assign
  assign system_0_burst_28_downstream_saved_grant_dist_sensor_s1 = system_0_burst_28_downstream_requests_dist_sensor_s1;

  //allow new arb cycle for dist_sensor/s1, which is an e_assign
  assign dist_sensor_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign dist_sensor_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign dist_sensor_s1_master_qreq_vector = 1;

  //dist_sensor_s1_reset_n assignment, which is an e_assign
  assign dist_sensor_s1_reset_n = reset_n;

  assign dist_sensor_s1_chipselect = system_0_burst_28_downstream_granted_dist_sensor_s1;
  //dist_sensor_s1_firsttransfer first transaction, which is an e_assign
  assign dist_sensor_s1_firsttransfer = dist_sensor_s1_begins_xfer ? dist_sensor_s1_unreg_firsttransfer : dist_sensor_s1_reg_firsttransfer;

  //dist_sensor_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign dist_sensor_s1_unreg_firsttransfer = ~(dist_sensor_s1_slavearbiterlockenable & dist_sensor_s1_any_continuerequest);

  //dist_sensor_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dist_sensor_s1_reg_firsttransfer <= 1'b1;
      else if (dist_sensor_s1_begins_xfer)
          dist_sensor_s1_reg_firsttransfer <= dist_sensor_s1_unreg_firsttransfer;
    end


  //dist_sensor_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign dist_sensor_s1_beginbursttransfer_internal = dist_sensor_s1_begins_xfer;

  //~dist_sensor_s1_write_n assignment, which is an e_mux
  assign dist_sensor_s1_write_n = ~(system_0_burst_28_downstream_granted_dist_sensor_s1 & system_0_burst_28_downstream_write);

  //dist_sensor_s1_address mux, which is an e_mux
  assign dist_sensor_s1_address = system_0_burst_28_downstream_nativeaddress;

  //d1_dist_sensor_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_dist_sensor_s1_end_xfer <= 1;
      else 
        d1_dist_sensor_s1_end_xfer <= dist_sensor_s1_end_xfer;
    end


  //dist_sensor_s1_waits_for_read in a cycle, which is an e_mux
  assign dist_sensor_s1_waits_for_read = dist_sensor_s1_in_a_read_cycle & dist_sensor_s1_begins_xfer;

  //dist_sensor_s1_in_a_read_cycle assignment, which is an e_assign
  assign dist_sensor_s1_in_a_read_cycle = system_0_burst_28_downstream_granted_dist_sensor_s1 & system_0_burst_28_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = dist_sensor_s1_in_a_read_cycle;

  //dist_sensor_s1_waits_for_write in a cycle, which is an e_mux
  assign dist_sensor_s1_waits_for_write = dist_sensor_s1_in_a_write_cycle & 0;

  //dist_sensor_s1_in_a_write_cycle assignment, which is an e_assign
  assign dist_sensor_s1_in_a_write_cycle = system_0_burst_28_downstream_granted_dist_sensor_s1 & system_0_burst_28_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = dist_sensor_s1_in_a_write_cycle;

  assign wait_for_dist_sensor_s1_counter = 0;
  //assign dist_sensor_s1_irq_from_sa = dist_sensor_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign dist_sensor_s1_irq_from_sa = dist_sensor_s1_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //dist_sensor/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_28/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_28_downstream_requests_dist_sensor_s1 && (system_0_burst_28_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_28/downstream drove 0 on its 'arbitrationshare' port while accessing slave dist_sensor/s1", $time);
          $stop;
        end
    end


  //system_0_burst_28/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_28_downstream_requests_dist_sensor_s1 && (system_0_burst_28_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_28/downstream drove 0 on its 'burstcount' port while accessing slave dist_sensor/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module epcs_controller_epcs_control_port_arbitrator (
                                                      // inputs:
                                                       clk,
                                                       epcs_controller_epcs_control_port_dataavailable,
                                                       epcs_controller_epcs_control_port_endofpacket,
                                                       epcs_controller_epcs_control_port_irq,
                                                       epcs_controller_epcs_control_port_readdata,
                                                       epcs_controller_epcs_control_port_readyfordata,
                                                       reset_n,
                                                       system_0_burst_6_downstream_address_to_slave,
                                                       system_0_burst_6_downstream_arbitrationshare,
                                                       system_0_burst_6_downstream_burstcount,
                                                       system_0_burst_6_downstream_latency_counter,
                                                       system_0_burst_6_downstream_read,
                                                       system_0_burst_6_downstream_write,
                                                       system_0_burst_6_downstream_writedata,
                                                       system_0_burst_7_downstream_address_to_slave,
                                                       system_0_burst_7_downstream_arbitrationshare,
                                                       system_0_burst_7_downstream_burstcount,
                                                       system_0_burst_7_downstream_latency_counter,
                                                       system_0_burst_7_downstream_read,
                                                       system_0_burst_7_downstream_write,
                                                       system_0_burst_7_downstream_writedata,

                                                      // outputs:
                                                       d1_epcs_controller_epcs_control_port_end_xfer,
                                                       epcs_controller_epcs_control_port_address,
                                                       epcs_controller_epcs_control_port_chipselect,
                                                       epcs_controller_epcs_control_port_dataavailable_from_sa,
                                                       epcs_controller_epcs_control_port_endofpacket_from_sa,
                                                       epcs_controller_epcs_control_port_irq_from_sa,
                                                       epcs_controller_epcs_control_port_read_n,
                                                       epcs_controller_epcs_control_port_readdata_from_sa,
                                                       epcs_controller_epcs_control_port_readyfordata_from_sa,
                                                       epcs_controller_epcs_control_port_reset_n,
                                                       epcs_controller_epcs_control_port_write_n,
                                                       epcs_controller_epcs_control_port_writedata,
                                                       system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port,
                                                       system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port,
                                                       system_0_burst_6_downstream_read_data_valid_epcs_controller_epcs_control_port,
                                                       system_0_burst_6_downstream_requests_epcs_controller_epcs_control_port,
                                                       system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port,
                                                       system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port,
                                                       system_0_burst_7_downstream_read_data_valid_epcs_controller_epcs_control_port,
                                                       system_0_burst_7_downstream_requests_epcs_controller_epcs_control_port
                                                    )
;

  output           d1_epcs_controller_epcs_control_port_end_xfer;
  output  [  8: 0] epcs_controller_epcs_control_port_address;
  output           epcs_controller_epcs_control_port_chipselect;
  output           epcs_controller_epcs_control_port_dataavailable_from_sa;
  output           epcs_controller_epcs_control_port_endofpacket_from_sa;
  output           epcs_controller_epcs_control_port_irq_from_sa;
  output           epcs_controller_epcs_control_port_read_n;
  output  [ 31: 0] epcs_controller_epcs_control_port_readdata_from_sa;
  output           epcs_controller_epcs_control_port_readyfordata_from_sa;
  output           epcs_controller_epcs_control_port_reset_n;
  output           epcs_controller_epcs_control_port_write_n;
  output  [ 31: 0] epcs_controller_epcs_control_port_writedata;
  output           system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port;
  output           system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port;
  output           system_0_burst_6_downstream_read_data_valid_epcs_controller_epcs_control_port;
  output           system_0_burst_6_downstream_requests_epcs_controller_epcs_control_port;
  output           system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port;
  output           system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port;
  output           system_0_burst_7_downstream_read_data_valid_epcs_controller_epcs_control_port;
  output           system_0_burst_7_downstream_requests_epcs_controller_epcs_control_port;
  input            clk;
  input            epcs_controller_epcs_control_port_dataavailable;
  input            epcs_controller_epcs_control_port_endofpacket;
  input            epcs_controller_epcs_control_port_irq;
  input   [ 31: 0] epcs_controller_epcs_control_port_readdata;
  input            epcs_controller_epcs_control_port_readyfordata;
  input            reset_n;
  input   [ 10: 0] system_0_burst_6_downstream_address_to_slave;
  input   [  3: 0] system_0_burst_6_downstream_arbitrationshare;
  input            system_0_burst_6_downstream_burstcount;
  input            system_0_burst_6_downstream_latency_counter;
  input            system_0_burst_6_downstream_read;
  input            system_0_burst_6_downstream_write;
  input   [ 31: 0] system_0_burst_6_downstream_writedata;
  input   [ 10: 0] system_0_burst_7_downstream_address_to_slave;
  input   [  3: 0] system_0_burst_7_downstream_arbitrationshare;
  input            system_0_burst_7_downstream_burstcount;
  input            system_0_burst_7_downstream_latency_counter;
  input            system_0_burst_7_downstream_read;
  input            system_0_burst_7_downstream_write;
  input   [ 31: 0] system_0_burst_7_downstream_writedata;

  reg              d1_epcs_controller_epcs_control_port_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_epcs_controller_epcs_control_port;
  wire    [  8: 0] epcs_controller_epcs_control_port_address;
  wire             epcs_controller_epcs_control_port_allgrants;
  wire             epcs_controller_epcs_control_port_allow_new_arb_cycle;
  wire             epcs_controller_epcs_control_port_any_bursting_master_saved_grant;
  wire             epcs_controller_epcs_control_port_any_continuerequest;
  reg     [  1: 0] epcs_controller_epcs_control_port_arb_addend;
  wire             epcs_controller_epcs_control_port_arb_counter_enable;
  reg     [  3: 0] epcs_controller_epcs_control_port_arb_share_counter;
  wire    [  3: 0] epcs_controller_epcs_control_port_arb_share_counter_next_value;
  wire    [  3: 0] epcs_controller_epcs_control_port_arb_share_set_values;
  wire    [  1: 0] epcs_controller_epcs_control_port_arb_winner;
  wire             epcs_controller_epcs_control_port_arbitration_holdoff_internal;
  wire             epcs_controller_epcs_control_port_beginbursttransfer_internal;
  wire             epcs_controller_epcs_control_port_begins_xfer;
  wire             epcs_controller_epcs_control_port_chipselect;
  wire    [  3: 0] epcs_controller_epcs_control_port_chosen_master_double_vector;
  wire    [  1: 0] epcs_controller_epcs_control_port_chosen_master_rot_left;
  wire             epcs_controller_epcs_control_port_dataavailable_from_sa;
  wire             epcs_controller_epcs_control_port_end_xfer;
  wire             epcs_controller_epcs_control_port_endofpacket_from_sa;
  wire             epcs_controller_epcs_control_port_firsttransfer;
  wire    [  1: 0] epcs_controller_epcs_control_port_grant_vector;
  wire             epcs_controller_epcs_control_port_in_a_read_cycle;
  wire             epcs_controller_epcs_control_port_in_a_write_cycle;
  wire             epcs_controller_epcs_control_port_irq_from_sa;
  wire    [  1: 0] epcs_controller_epcs_control_port_master_qreq_vector;
  wire             epcs_controller_epcs_control_port_non_bursting_master_requests;
  wire             epcs_controller_epcs_control_port_read_n;
  wire    [ 31: 0] epcs_controller_epcs_control_port_readdata_from_sa;
  wire             epcs_controller_epcs_control_port_readyfordata_from_sa;
  reg              epcs_controller_epcs_control_port_reg_firsttransfer;
  wire             epcs_controller_epcs_control_port_reset_n;
  reg     [  1: 0] epcs_controller_epcs_control_port_saved_chosen_master_vector;
  reg              epcs_controller_epcs_control_port_slavearbiterlockenable;
  wire             epcs_controller_epcs_control_port_slavearbiterlockenable2;
  wire             epcs_controller_epcs_control_port_unreg_firsttransfer;
  wire             epcs_controller_epcs_control_port_waits_for_read;
  wire             epcs_controller_epcs_control_port_waits_for_write;
  wire             epcs_controller_epcs_control_port_write_n;
  wire    [ 31: 0] epcs_controller_epcs_control_port_writedata;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_system_0_burst_6_downstream_granted_slave_epcs_controller_epcs_control_port;
  reg              last_cycle_system_0_burst_7_downstream_granted_slave_epcs_controller_epcs_control_port;
  wire    [ 10: 0] shifted_address_to_epcs_controller_epcs_control_port_from_system_0_burst_6_downstream;
  wire    [ 10: 0] shifted_address_to_epcs_controller_epcs_control_port_from_system_0_burst_7_downstream;
  wire             system_0_burst_6_downstream_arbiterlock;
  wire             system_0_burst_6_downstream_arbiterlock2;
  wire             system_0_burst_6_downstream_continuerequest;
  wire             system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port;
  wire             system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port;
  wire             system_0_burst_6_downstream_read_data_valid_epcs_controller_epcs_control_port;
  wire             system_0_burst_6_downstream_requests_epcs_controller_epcs_control_port;
  wire             system_0_burst_6_downstream_saved_grant_epcs_controller_epcs_control_port;
  wire             system_0_burst_7_downstream_arbiterlock;
  wire             system_0_burst_7_downstream_arbiterlock2;
  wire             system_0_burst_7_downstream_continuerequest;
  wire             system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port;
  wire             system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port;
  wire             system_0_burst_7_downstream_read_data_valid_epcs_controller_epcs_control_port;
  wire             system_0_burst_7_downstream_requests_epcs_controller_epcs_control_port;
  wire             system_0_burst_7_downstream_saved_grant_epcs_controller_epcs_control_port;
  wire             wait_for_epcs_controller_epcs_control_port_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~epcs_controller_epcs_control_port_end_xfer;
    end


  assign epcs_controller_epcs_control_port_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port | system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port));
  //assign epcs_controller_epcs_control_port_readdata_from_sa = epcs_controller_epcs_control_port_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign epcs_controller_epcs_control_port_readdata_from_sa = epcs_controller_epcs_control_port_readdata;

  assign system_0_burst_6_downstream_requests_epcs_controller_epcs_control_port = (1) & (system_0_burst_6_downstream_read | system_0_burst_6_downstream_write);
  //assign epcs_controller_epcs_control_port_dataavailable_from_sa = epcs_controller_epcs_control_port_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign epcs_controller_epcs_control_port_dataavailable_from_sa = epcs_controller_epcs_control_port_dataavailable;

  //assign epcs_controller_epcs_control_port_readyfordata_from_sa = epcs_controller_epcs_control_port_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign epcs_controller_epcs_control_port_readyfordata_from_sa = epcs_controller_epcs_control_port_readyfordata;

  //epcs_controller_epcs_control_port_arb_share_counter set values, which is an e_mux
  assign epcs_controller_epcs_control_port_arb_share_set_values = (system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port)? system_0_burst_6_downstream_arbitrationshare :
    (system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port)? system_0_burst_7_downstream_arbitrationshare :
    (system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port)? system_0_burst_6_downstream_arbitrationshare :
    (system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port)? system_0_burst_7_downstream_arbitrationshare :
    1;

  //epcs_controller_epcs_control_port_non_bursting_master_requests mux, which is an e_mux
  assign epcs_controller_epcs_control_port_non_bursting_master_requests = 0;

  //epcs_controller_epcs_control_port_any_bursting_master_saved_grant mux, which is an e_mux
  assign epcs_controller_epcs_control_port_any_bursting_master_saved_grant = system_0_burst_6_downstream_saved_grant_epcs_controller_epcs_control_port |
    system_0_burst_7_downstream_saved_grant_epcs_controller_epcs_control_port |
    system_0_burst_6_downstream_saved_grant_epcs_controller_epcs_control_port |
    system_0_burst_7_downstream_saved_grant_epcs_controller_epcs_control_port;

  //epcs_controller_epcs_control_port_arb_share_counter_next_value assignment, which is an e_assign
  assign epcs_controller_epcs_control_port_arb_share_counter_next_value = epcs_controller_epcs_control_port_firsttransfer ? (epcs_controller_epcs_control_port_arb_share_set_values - 1) : |epcs_controller_epcs_control_port_arb_share_counter ? (epcs_controller_epcs_control_port_arb_share_counter - 1) : 0;

  //epcs_controller_epcs_control_port_allgrants all slave grants, which is an e_mux
  assign epcs_controller_epcs_control_port_allgrants = (|epcs_controller_epcs_control_port_grant_vector) |
    (|epcs_controller_epcs_control_port_grant_vector) |
    (|epcs_controller_epcs_control_port_grant_vector) |
    (|epcs_controller_epcs_control_port_grant_vector);

  //epcs_controller_epcs_control_port_end_xfer assignment, which is an e_assign
  assign epcs_controller_epcs_control_port_end_xfer = ~(epcs_controller_epcs_control_port_waits_for_read | epcs_controller_epcs_control_port_waits_for_write);

  //end_xfer_arb_share_counter_term_epcs_controller_epcs_control_port arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_epcs_controller_epcs_control_port = epcs_controller_epcs_control_port_end_xfer & (~epcs_controller_epcs_control_port_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //epcs_controller_epcs_control_port_arb_share_counter arbitration counter enable, which is an e_assign
  assign epcs_controller_epcs_control_port_arb_counter_enable = (end_xfer_arb_share_counter_term_epcs_controller_epcs_control_port & epcs_controller_epcs_control_port_allgrants) | (end_xfer_arb_share_counter_term_epcs_controller_epcs_control_port & ~epcs_controller_epcs_control_port_non_bursting_master_requests);

  //epcs_controller_epcs_control_port_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          epcs_controller_epcs_control_port_arb_share_counter <= 0;
      else if (epcs_controller_epcs_control_port_arb_counter_enable)
          epcs_controller_epcs_control_port_arb_share_counter <= epcs_controller_epcs_control_port_arb_share_counter_next_value;
    end


  //epcs_controller_epcs_control_port_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          epcs_controller_epcs_control_port_slavearbiterlockenable <= 0;
      else if ((|epcs_controller_epcs_control_port_master_qreq_vector & end_xfer_arb_share_counter_term_epcs_controller_epcs_control_port) | (end_xfer_arb_share_counter_term_epcs_controller_epcs_control_port & ~epcs_controller_epcs_control_port_non_bursting_master_requests))
          epcs_controller_epcs_control_port_slavearbiterlockenable <= |epcs_controller_epcs_control_port_arb_share_counter_next_value;
    end


  //system_0_burst_6/downstream epcs_controller/epcs_control_port arbiterlock, which is an e_assign
  assign system_0_burst_6_downstream_arbiterlock = epcs_controller_epcs_control_port_slavearbiterlockenable & system_0_burst_6_downstream_continuerequest;

  //epcs_controller_epcs_control_port_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign epcs_controller_epcs_control_port_slavearbiterlockenable2 = |epcs_controller_epcs_control_port_arb_share_counter_next_value;

  //system_0_burst_6/downstream epcs_controller/epcs_control_port arbiterlock2, which is an e_assign
  assign system_0_burst_6_downstream_arbiterlock2 = epcs_controller_epcs_control_port_slavearbiterlockenable2 & system_0_burst_6_downstream_continuerequest;

  //system_0_burst_7/downstream epcs_controller/epcs_control_port arbiterlock, which is an e_assign
  assign system_0_burst_7_downstream_arbiterlock = epcs_controller_epcs_control_port_slavearbiterlockenable & system_0_burst_7_downstream_continuerequest;

  //system_0_burst_7/downstream epcs_controller/epcs_control_port arbiterlock2, which is an e_assign
  assign system_0_burst_7_downstream_arbiterlock2 = epcs_controller_epcs_control_port_slavearbiterlockenable2 & system_0_burst_7_downstream_continuerequest;

  //system_0_burst_7/downstream granted epcs_controller/epcs_control_port last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_system_0_burst_7_downstream_granted_slave_epcs_controller_epcs_control_port <= 0;
      else 
        last_cycle_system_0_burst_7_downstream_granted_slave_epcs_controller_epcs_control_port <= system_0_burst_7_downstream_saved_grant_epcs_controller_epcs_control_port ? 1 : (epcs_controller_epcs_control_port_arbitration_holdoff_internal | 0) ? 0 : last_cycle_system_0_burst_7_downstream_granted_slave_epcs_controller_epcs_control_port;
    end


  //system_0_burst_7_downstream_continuerequest continued request, which is an e_mux
  assign system_0_burst_7_downstream_continuerequest = last_cycle_system_0_burst_7_downstream_granted_slave_epcs_controller_epcs_control_port & 1;

  //epcs_controller_epcs_control_port_any_continuerequest at least one master continues requesting, which is an e_mux
  assign epcs_controller_epcs_control_port_any_continuerequest = system_0_burst_7_downstream_continuerequest |
    system_0_burst_6_downstream_continuerequest;

  assign system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port = system_0_burst_6_downstream_requests_epcs_controller_epcs_control_port & ~((system_0_burst_6_downstream_read & ((system_0_burst_6_downstream_latency_counter != 0))) | system_0_burst_7_downstream_arbiterlock);
  //local readdatavalid system_0_burst_6_downstream_read_data_valid_epcs_controller_epcs_control_port, which is an e_mux
  assign system_0_burst_6_downstream_read_data_valid_epcs_controller_epcs_control_port = system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port & system_0_burst_6_downstream_read & ~epcs_controller_epcs_control_port_waits_for_read;

  //epcs_controller_epcs_control_port_writedata mux, which is an e_mux
  assign epcs_controller_epcs_control_port_writedata = (system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port)? system_0_burst_6_downstream_writedata :
    system_0_burst_7_downstream_writedata;

  //assign epcs_controller_epcs_control_port_endofpacket_from_sa = epcs_controller_epcs_control_port_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign epcs_controller_epcs_control_port_endofpacket_from_sa = epcs_controller_epcs_control_port_endofpacket;

  assign system_0_burst_7_downstream_requests_epcs_controller_epcs_control_port = (1) & (system_0_burst_7_downstream_read | system_0_burst_7_downstream_write);
  //system_0_burst_6/downstream granted epcs_controller/epcs_control_port last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_system_0_burst_6_downstream_granted_slave_epcs_controller_epcs_control_port <= 0;
      else 
        last_cycle_system_0_burst_6_downstream_granted_slave_epcs_controller_epcs_control_port <= system_0_burst_6_downstream_saved_grant_epcs_controller_epcs_control_port ? 1 : (epcs_controller_epcs_control_port_arbitration_holdoff_internal | 0) ? 0 : last_cycle_system_0_burst_6_downstream_granted_slave_epcs_controller_epcs_control_port;
    end


  //system_0_burst_6_downstream_continuerequest continued request, which is an e_mux
  assign system_0_burst_6_downstream_continuerequest = last_cycle_system_0_burst_6_downstream_granted_slave_epcs_controller_epcs_control_port & 1;

  assign system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port = system_0_burst_7_downstream_requests_epcs_controller_epcs_control_port & ~((system_0_burst_7_downstream_read & ((system_0_burst_7_downstream_latency_counter != 0))) | system_0_burst_6_downstream_arbiterlock);
  //local readdatavalid system_0_burst_7_downstream_read_data_valid_epcs_controller_epcs_control_port, which is an e_mux
  assign system_0_burst_7_downstream_read_data_valid_epcs_controller_epcs_control_port = system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port & system_0_burst_7_downstream_read & ~epcs_controller_epcs_control_port_waits_for_read;

  //allow new arb cycle for epcs_controller/epcs_control_port, which is an e_assign
  assign epcs_controller_epcs_control_port_allow_new_arb_cycle = ~system_0_burst_6_downstream_arbiterlock & ~system_0_burst_7_downstream_arbiterlock;

  //system_0_burst_7/downstream assignment into master qualified-requests vector for epcs_controller/epcs_control_port, which is an e_assign
  assign epcs_controller_epcs_control_port_master_qreq_vector[0] = system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port;

  //system_0_burst_7/downstream grant epcs_controller/epcs_control_port, which is an e_assign
  assign system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port = epcs_controller_epcs_control_port_grant_vector[0];

  //system_0_burst_7/downstream saved-grant epcs_controller/epcs_control_port, which is an e_assign
  assign system_0_burst_7_downstream_saved_grant_epcs_controller_epcs_control_port = epcs_controller_epcs_control_port_arb_winner[0];

  //system_0_burst_6/downstream assignment into master qualified-requests vector for epcs_controller/epcs_control_port, which is an e_assign
  assign epcs_controller_epcs_control_port_master_qreq_vector[1] = system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port;

  //system_0_burst_6/downstream grant epcs_controller/epcs_control_port, which is an e_assign
  assign system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port = epcs_controller_epcs_control_port_grant_vector[1];

  //system_0_burst_6/downstream saved-grant epcs_controller/epcs_control_port, which is an e_assign
  assign system_0_burst_6_downstream_saved_grant_epcs_controller_epcs_control_port = epcs_controller_epcs_control_port_arb_winner[1];

  //epcs_controller/epcs_control_port chosen-master double-vector, which is an e_assign
  assign epcs_controller_epcs_control_port_chosen_master_double_vector = {epcs_controller_epcs_control_port_master_qreq_vector, epcs_controller_epcs_control_port_master_qreq_vector} & ({~epcs_controller_epcs_control_port_master_qreq_vector, ~epcs_controller_epcs_control_port_master_qreq_vector} + epcs_controller_epcs_control_port_arb_addend);

  //stable onehot encoding of arb winner
  assign epcs_controller_epcs_control_port_arb_winner = (epcs_controller_epcs_control_port_allow_new_arb_cycle & | epcs_controller_epcs_control_port_grant_vector) ? epcs_controller_epcs_control_port_grant_vector : epcs_controller_epcs_control_port_saved_chosen_master_vector;

  //saved epcs_controller_epcs_control_port_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          epcs_controller_epcs_control_port_saved_chosen_master_vector <= 0;
      else if (epcs_controller_epcs_control_port_allow_new_arb_cycle)
          epcs_controller_epcs_control_port_saved_chosen_master_vector <= |epcs_controller_epcs_control_port_grant_vector ? epcs_controller_epcs_control_port_grant_vector : epcs_controller_epcs_control_port_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign epcs_controller_epcs_control_port_grant_vector = {(epcs_controller_epcs_control_port_chosen_master_double_vector[1] | epcs_controller_epcs_control_port_chosen_master_double_vector[3]),
    (epcs_controller_epcs_control_port_chosen_master_double_vector[0] | epcs_controller_epcs_control_port_chosen_master_double_vector[2])};

  //epcs_controller/epcs_control_port chosen master rotated left, which is an e_assign
  assign epcs_controller_epcs_control_port_chosen_master_rot_left = (epcs_controller_epcs_control_port_arb_winner << 1) ? (epcs_controller_epcs_control_port_arb_winner << 1) : 1;

  //epcs_controller/epcs_control_port's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          epcs_controller_epcs_control_port_arb_addend <= 1;
      else if (|epcs_controller_epcs_control_port_grant_vector)
          epcs_controller_epcs_control_port_arb_addend <= epcs_controller_epcs_control_port_end_xfer? epcs_controller_epcs_control_port_chosen_master_rot_left : epcs_controller_epcs_control_port_grant_vector;
    end


  //epcs_controller_epcs_control_port_reset_n assignment, which is an e_assign
  assign epcs_controller_epcs_control_port_reset_n = reset_n;

  assign epcs_controller_epcs_control_port_chipselect = system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port | system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port;
  //epcs_controller_epcs_control_port_firsttransfer first transaction, which is an e_assign
  assign epcs_controller_epcs_control_port_firsttransfer = epcs_controller_epcs_control_port_begins_xfer ? epcs_controller_epcs_control_port_unreg_firsttransfer : epcs_controller_epcs_control_port_reg_firsttransfer;

  //epcs_controller_epcs_control_port_unreg_firsttransfer first transaction, which is an e_assign
  assign epcs_controller_epcs_control_port_unreg_firsttransfer = ~(epcs_controller_epcs_control_port_slavearbiterlockenable & epcs_controller_epcs_control_port_any_continuerequest);

  //epcs_controller_epcs_control_port_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          epcs_controller_epcs_control_port_reg_firsttransfer <= 1'b1;
      else if (epcs_controller_epcs_control_port_begins_xfer)
          epcs_controller_epcs_control_port_reg_firsttransfer <= epcs_controller_epcs_control_port_unreg_firsttransfer;
    end


  //epcs_controller_epcs_control_port_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign epcs_controller_epcs_control_port_beginbursttransfer_internal = epcs_controller_epcs_control_port_begins_xfer;

  //epcs_controller_epcs_control_port_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign epcs_controller_epcs_control_port_arbitration_holdoff_internal = epcs_controller_epcs_control_port_begins_xfer & epcs_controller_epcs_control_port_firsttransfer;

  //~epcs_controller_epcs_control_port_read_n assignment, which is an e_mux
  assign epcs_controller_epcs_control_port_read_n = ~((system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port & system_0_burst_6_downstream_read) | (system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port & system_0_burst_7_downstream_read));

  //~epcs_controller_epcs_control_port_write_n assignment, which is an e_mux
  assign epcs_controller_epcs_control_port_write_n = ~((system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port & system_0_burst_6_downstream_write) | (system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port & system_0_burst_7_downstream_write));

  assign shifted_address_to_epcs_controller_epcs_control_port_from_system_0_burst_6_downstream = system_0_burst_6_downstream_address_to_slave;
  //epcs_controller_epcs_control_port_address mux, which is an e_mux
  assign epcs_controller_epcs_control_port_address = (system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port)? (shifted_address_to_epcs_controller_epcs_control_port_from_system_0_burst_6_downstream >> 2) :
    (shifted_address_to_epcs_controller_epcs_control_port_from_system_0_burst_7_downstream >> 2);

  assign shifted_address_to_epcs_controller_epcs_control_port_from_system_0_burst_7_downstream = system_0_burst_7_downstream_address_to_slave;
  //d1_epcs_controller_epcs_control_port_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_epcs_controller_epcs_control_port_end_xfer <= 1;
      else 
        d1_epcs_controller_epcs_control_port_end_xfer <= epcs_controller_epcs_control_port_end_xfer;
    end


  //epcs_controller_epcs_control_port_waits_for_read in a cycle, which is an e_mux
  assign epcs_controller_epcs_control_port_waits_for_read = epcs_controller_epcs_control_port_in_a_read_cycle & epcs_controller_epcs_control_port_begins_xfer;

  //epcs_controller_epcs_control_port_in_a_read_cycle assignment, which is an e_assign
  assign epcs_controller_epcs_control_port_in_a_read_cycle = (system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port & system_0_burst_6_downstream_read) | (system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port & system_0_burst_7_downstream_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = epcs_controller_epcs_control_port_in_a_read_cycle;

  //epcs_controller_epcs_control_port_waits_for_write in a cycle, which is an e_mux
  assign epcs_controller_epcs_control_port_waits_for_write = epcs_controller_epcs_control_port_in_a_write_cycle & epcs_controller_epcs_control_port_begins_xfer;

  //epcs_controller_epcs_control_port_in_a_write_cycle assignment, which is an e_assign
  assign epcs_controller_epcs_control_port_in_a_write_cycle = (system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port & system_0_burst_6_downstream_write) | (system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port & system_0_burst_7_downstream_write);

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = epcs_controller_epcs_control_port_in_a_write_cycle;

  assign wait_for_epcs_controller_epcs_control_port_counter = 0;
  //assign epcs_controller_epcs_control_port_irq_from_sa = epcs_controller_epcs_control_port_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign epcs_controller_epcs_control_port_irq_from_sa = epcs_controller_epcs_control_port_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //epcs_controller/epcs_control_port enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_6/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_6_downstream_requests_epcs_controller_epcs_control_port && (system_0_burst_6_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_6/downstream drove 0 on its 'arbitrationshare' port while accessing slave epcs_controller/epcs_control_port", $time);
          $stop;
        end
    end


  //system_0_burst_6/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_6_downstream_requests_epcs_controller_epcs_control_port && (system_0_burst_6_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_6/downstream drove 0 on its 'burstcount' port while accessing slave epcs_controller/epcs_control_port", $time);
          $stop;
        end
    end


  //system_0_burst_7/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_7_downstream_requests_epcs_controller_epcs_control_port && (system_0_burst_7_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_7/downstream drove 0 on its 'arbitrationshare' port while accessing slave epcs_controller/epcs_control_port", $time);
          $stop;
        end
    end


  //system_0_burst_7/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_7_downstream_requests_epcs_controller_epcs_control_port && (system_0_burst_7_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_7/downstream drove 0 on its 'burstcount' port while accessing slave epcs_controller/epcs_control_port", $time);
          $stop;
        end
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port + system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_6_downstream_saved_grant_epcs_controller_epcs_control_port + system_0_burst_7_downstream_saved_grant_epcs_controller_epcs_control_port > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module i2c_master_avalon_slave_0_arbitrator (
                                              // inputs:
                                               clk,
                                               i2c_master_avalon_slave_0_irq,
                                               i2c_master_avalon_slave_0_readdata,
                                               i2c_master_avalon_slave_0_waitrequest_n,
                                               reset_n,
                                               system_0_burst_33_downstream_address_to_slave,
                                               system_0_burst_33_downstream_arbitrationshare,
                                               system_0_burst_33_downstream_burstcount,
                                               system_0_burst_33_downstream_latency_counter,
                                               system_0_burst_33_downstream_read,
                                               system_0_burst_33_downstream_write,
                                               system_0_burst_33_downstream_writedata,
                                               system_0_burst_34_downstream_address_to_slave,
                                               system_0_burst_34_downstream_arbitrationshare,
                                               system_0_burst_34_downstream_burstcount,
                                               system_0_burst_34_downstream_latency_counter,
                                               system_0_burst_34_downstream_read,
                                               system_0_burst_34_downstream_write,
                                               system_0_burst_34_downstream_writedata,

                                              // outputs:
                                               d1_i2c_master_avalon_slave_0_end_xfer,
                                               i2c_master_avalon_slave_0_address,
                                               i2c_master_avalon_slave_0_chipselect,
                                               i2c_master_avalon_slave_0_irq_from_sa,
                                               i2c_master_avalon_slave_0_readdata_from_sa,
                                               i2c_master_avalon_slave_0_reset,
                                               i2c_master_avalon_slave_0_waitrequest_n_from_sa,
                                               i2c_master_avalon_slave_0_write,
                                               i2c_master_avalon_slave_0_writedata,
                                               system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0,
                                               system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0,
                                               system_0_burst_33_downstream_read_data_valid_i2c_master_avalon_slave_0,
                                               system_0_burst_33_downstream_requests_i2c_master_avalon_slave_0,
                                               system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0,
                                               system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0,
                                               system_0_burst_34_downstream_read_data_valid_i2c_master_avalon_slave_0,
                                               system_0_burst_34_downstream_requests_i2c_master_avalon_slave_0
                                            )
;

  output           d1_i2c_master_avalon_slave_0_end_xfer;
  output  [  2: 0] i2c_master_avalon_slave_0_address;
  output           i2c_master_avalon_slave_0_chipselect;
  output           i2c_master_avalon_slave_0_irq_from_sa;
  output  [ 31: 0] i2c_master_avalon_slave_0_readdata_from_sa;
  output           i2c_master_avalon_slave_0_reset;
  output           i2c_master_avalon_slave_0_waitrequest_n_from_sa;
  output           i2c_master_avalon_slave_0_write;
  output  [ 31: 0] i2c_master_avalon_slave_0_writedata;
  output           system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0;
  output           system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0;
  output           system_0_burst_33_downstream_read_data_valid_i2c_master_avalon_slave_0;
  output           system_0_burst_33_downstream_requests_i2c_master_avalon_slave_0;
  output           system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0;
  output           system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0;
  output           system_0_burst_34_downstream_read_data_valid_i2c_master_avalon_slave_0;
  output           system_0_burst_34_downstream_requests_i2c_master_avalon_slave_0;
  input            clk;
  input            i2c_master_avalon_slave_0_irq;
  input   [ 31: 0] i2c_master_avalon_slave_0_readdata;
  input            i2c_master_avalon_slave_0_waitrequest_n;
  input            reset_n;
  input   [  4: 0] system_0_burst_33_downstream_address_to_slave;
  input   [  3: 0] system_0_burst_33_downstream_arbitrationshare;
  input            system_0_burst_33_downstream_burstcount;
  input            system_0_burst_33_downstream_latency_counter;
  input            system_0_burst_33_downstream_read;
  input            system_0_burst_33_downstream_write;
  input   [ 31: 0] system_0_burst_33_downstream_writedata;
  input   [  4: 0] system_0_burst_34_downstream_address_to_slave;
  input   [  3: 0] system_0_burst_34_downstream_arbitrationshare;
  input            system_0_burst_34_downstream_burstcount;
  input            system_0_burst_34_downstream_latency_counter;
  input            system_0_burst_34_downstream_read;
  input            system_0_burst_34_downstream_write;
  input   [ 31: 0] system_0_burst_34_downstream_writedata;

  reg              d1_i2c_master_avalon_slave_0_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_i2c_master_avalon_slave_0;
  wire    [  2: 0] i2c_master_avalon_slave_0_address;
  wire             i2c_master_avalon_slave_0_allgrants;
  wire             i2c_master_avalon_slave_0_allow_new_arb_cycle;
  wire             i2c_master_avalon_slave_0_any_bursting_master_saved_grant;
  wire             i2c_master_avalon_slave_0_any_continuerequest;
  reg     [  1: 0] i2c_master_avalon_slave_0_arb_addend;
  wire             i2c_master_avalon_slave_0_arb_counter_enable;
  reg     [  3: 0] i2c_master_avalon_slave_0_arb_share_counter;
  wire    [  3: 0] i2c_master_avalon_slave_0_arb_share_counter_next_value;
  wire    [  3: 0] i2c_master_avalon_slave_0_arb_share_set_values;
  wire    [  1: 0] i2c_master_avalon_slave_0_arb_winner;
  wire             i2c_master_avalon_slave_0_arbitration_holdoff_internal;
  wire             i2c_master_avalon_slave_0_beginbursttransfer_internal;
  wire             i2c_master_avalon_slave_0_begins_xfer;
  wire             i2c_master_avalon_slave_0_chipselect;
  wire    [  3: 0] i2c_master_avalon_slave_0_chosen_master_double_vector;
  wire    [  1: 0] i2c_master_avalon_slave_0_chosen_master_rot_left;
  wire             i2c_master_avalon_slave_0_end_xfer;
  wire             i2c_master_avalon_slave_0_firsttransfer;
  wire    [  1: 0] i2c_master_avalon_slave_0_grant_vector;
  wire             i2c_master_avalon_slave_0_in_a_read_cycle;
  wire             i2c_master_avalon_slave_0_in_a_write_cycle;
  wire             i2c_master_avalon_slave_0_irq_from_sa;
  wire    [  1: 0] i2c_master_avalon_slave_0_master_qreq_vector;
  wire             i2c_master_avalon_slave_0_non_bursting_master_requests;
  wire    [ 31: 0] i2c_master_avalon_slave_0_readdata_from_sa;
  reg              i2c_master_avalon_slave_0_reg_firsttransfer;
  wire             i2c_master_avalon_slave_0_reset;
  reg     [  1: 0] i2c_master_avalon_slave_0_saved_chosen_master_vector;
  reg              i2c_master_avalon_slave_0_slavearbiterlockenable;
  wire             i2c_master_avalon_slave_0_slavearbiterlockenable2;
  wire             i2c_master_avalon_slave_0_unreg_firsttransfer;
  wire             i2c_master_avalon_slave_0_waitrequest_n_from_sa;
  wire             i2c_master_avalon_slave_0_waits_for_read;
  wire             i2c_master_avalon_slave_0_waits_for_write;
  wire             i2c_master_avalon_slave_0_write;
  wire    [ 31: 0] i2c_master_avalon_slave_0_writedata;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_system_0_burst_33_downstream_granted_slave_i2c_master_avalon_slave_0;
  reg              last_cycle_system_0_burst_34_downstream_granted_slave_i2c_master_avalon_slave_0;
  wire    [  4: 0] shifted_address_to_i2c_master_avalon_slave_0_from_system_0_burst_33_downstream;
  wire    [  4: 0] shifted_address_to_i2c_master_avalon_slave_0_from_system_0_burst_34_downstream;
  wire             system_0_burst_33_downstream_arbiterlock;
  wire             system_0_burst_33_downstream_arbiterlock2;
  wire             system_0_burst_33_downstream_continuerequest;
  wire             system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0;
  wire             system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0;
  wire             system_0_burst_33_downstream_read_data_valid_i2c_master_avalon_slave_0;
  wire             system_0_burst_33_downstream_requests_i2c_master_avalon_slave_0;
  wire             system_0_burst_33_downstream_saved_grant_i2c_master_avalon_slave_0;
  wire             system_0_burst_34_downstream_arbiterlock;
  wire             system_0_burst_34_downstream_arbiterlock2;
  wire             system_0_burst_34_downstream_continuerequest;
  wire             system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0;
  wire             system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0;
  wire             system_0_burst_34_downstream_read_data_valid_i2c_master_avalon_slave_0;
  wire             system_0_burst_34_downstream_requests_i2c_master_avalon_slave_0;
  wire             system_0_burst_34_downstream_saved_grant_i2c_master_avalon_slave_0;
  wire             wait_for_i2c_master_avalon_slave_0_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~i2c_master_avalon_slave_0_end_xfer;
    end


  assign i2c_master_avalon_slave_0_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0 | system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0));
  //assign i2c_master_avalon_slave_0_readdata_from_sa = i2c_master_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign i2c_master_avalon_slave_0_readdata_from_sa = i2c_master_avalon_slave_0_readdata;

  assign system_0_burst_33_downstream_requests_i2c_master_avalon_slave_0 = (1) & (system_0_burst_33_downstream_read | system_0_burst_33_downstream_write);
  //assign i2c_master_avalon_slave_0_waitrequest_n_from_sa = i2c_master_avalon_slave_0_waitrequest_n so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign i2c_master_avalon_slave_0_waitrequest_n_from_sa = i2c_master_avalon_slave_0_waitrequest_n;

  //i2c_master_avalon_slave_0_arb_share_counter set values, which is an e_mux
  assign i2c_master_avalon_slave_0_arb_share_set_values = (system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0)? system_0_burst_33_downstream_arbitrationshare :
    (system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0)? system_0_burst_34_downstream_arbitrationshare :
    (system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0)? system_0_burst_33_downstream_arbitrationshare :
    (system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0)? system_0_burst_34_downstream_arbitrationshare :
    1;

  //i2c_master_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
  assign i2c_master_avalon_slave_0_non_bursting_master_requests = 0;

  //i2c_master_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
  assign i2c_master_avalon_slave_0_any_bursting_master_saved_grant = system_0_burst_33_downstream_saved_grant_i2c_master_avalon_slave_0 |
    system_0_burst_34_downstream_saved_grant_i2c_master_avalon_slave_0 |
    system_0_burst_33_downstream_saved_grant_i2c_master_avalon_slave_0 |
    system_0_burst_34_downstream_saved_grant_i2c_master_avalon_slave_0;

  //i2c_master_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
  assign i2c_master_avalon_slave_0_arb_share_counter_next_value = i2c_master_avalon_slave_0_firsttransfer ? (i2c_master_avalon_slave_0_arb_share_set_values - 1) : |i2c_master_avalon_slave_0_arb_share_counter ? (i2c_master_avalon_slave_0_arb_share_counter - 1) : 0;

  //i2c_master_avalon_slave_0_allgrants all slave grants, which is an e_mux
  assign i2c_master_avalon_slave_0_allgrants = (|i2c_master_avalon_slave_0_grant_vector) |
    (|i2c_master_avalon_slave_0_grant_vector) |
    (|i2c_master_avalon_slave_0_grant_vector) |
    (|i2c_master_avalon_slave_0_grant_vector);

  //i2c_master_avalon_slave_0_end_xfer assignment, which is an e_assign
  assign i2c_master_avalon_slave_0_end_xfer = ~(i2c_master_avalon_slave_0_waits_for_read | i2c_master_avalon_slave_0_waits_for_write);

  //end_xfer_arb_share_counter_term_i2c_master_avalon_slave_0 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_i2c_master_avalon_slave_0 = i2c_master_avalon_slave_0_end_xfer & (~i2c_master_avalon_slave_0_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //i2c_master_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
  assign i2c_master_avalon_slave_0_arb_counter_enable = (end_xfer_arb_share_counter_term_i2c_master_avalon_slave_0 & i2c_master_avalon_slave_0_allgrants) | (end_xfer_arb_share_counter_term_i2c_master_avalon_slave_0 & ~i2c_master_avalon_slave_0_non_bursting_master_requests);

  //i2c_master_avalon_slave_0_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          i2c_master_avalon_slave_0_arb_share_counter <= 0;
      else if (i2c_master_avalon_slave_0_arb_counter_enable)
          i2c_master_avalon_slave_0_arb_share_counter <= i2c_master_avalon_slave_0_arb_share_counter_next_value;
    end


  //i2c_master_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          i2c_master_avalon_slave_0_slavearbiterlockenable <= 0;
      else if ((|i2c_master_avalon_slave_0_master_qreq_vector & end_xfer_arb_share_counter_term_i2c_master_avalon_slave_0) | (end_xfer_arb_share_counter_term_i2c_master_avalon_slave_0 & ~i2c_master_avalon_slave_0_non_bursting_master_requests))
          i2c_master_avalon_slave_0_slavearbiterlockenable <= |i2c_master_avalon_slave_0_arb_share_counter_next_value;
    end


  //system_0_burst_33/downstream i2c_master/avalon_slave_0 arbiterlock, which is an e_assign
  assign system_0_burst_33_downstream_arbiterlock = i2c_master_avalon_slave_0_slavearbiterlockenable & system_0_burst_33_downstream_continuerequest;

  //i2c_master_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign i2c_master_avalon_slave_0_slavearbiterlockenable2 = |i2c_master_avalon_slave_0_arb_share_counter_next_value;

  //system_0_burst_33/downstream i2c_master/avalon_slave_0 arbiterlock2, which is an e_assign
  assign system_0_burst_33_downstream_arbiterlock2 = i2c_master_avalon_slave_0_slavearbiterlockenable2 & system_0_burst_33_downstream_continuerequest;

  //system_0_burst_34/downstream i2c_master/avalon_slave_0 arbiterlock, which is an e_assign
  assign system_0_burst_34_downstream_arbiterlock = i2c_master_avalon_slave_0_slavearbiterlockenable & system_0_burst_34_downstream_continuerequest;

  //system_0_burst_34/downstream i2c_master/avalon_slave_0 arbiterlock2, which is an e_assign
  assign system_0_burst_34_downstream_arbiterlock2 = i2c_master_avalon_slave_0_slavearbiterlockenable2 & system_0_burst_34_downstream_continuerequest;

  //system_0_burst_34/downstream granted i2c_master/avalon_slave_0 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_system_0_burst_34_downstream_granted_slave_i2c_master_avalon_slave_0 <= 0;
      else 
        last_cycle_system_0_burst_34_downstream_granted_slave_i2c_master_avalon_slave_0 <= system_0_burst_34_downstream_saved_grant_i2c_master_avalon_slave_0 ? 1 : (i2c_master_avalon_slave_0_arbitration_holdoff_internal | 0) ? 0 : last_cycle_system_0_burst_34_downstream_granted_slave_i2c_master_avalon_slave_0;
    end


  //system_0_burst_34_downstream_continuerequest continued request, which is an e_mux
  assign system_0_burst_34_downstream_continuerequest = last_cycle_system_0_burst_34_downstream_granted_slave_i2c_master_avalon_slave_0 & 1;

  //i2c_master_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_mux
  assign i2c_master_avalon_slave_0_any_continuerequest = system_0_burst_34_downstream_continuerequest |
    system_0_burst_33_downstream_continuerequest;

  assign system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0 = system_0_burst_33_downstream_requests_i2c_master_avalon_slave_0 & ~((system_0_burst_33_downstream_read & ((system_0_burst_33_downstream_latency_counter != 0))) | system_0_burst_34_downstream_arbiterlock);
  //local readdatavalid system_0_burst_33_downstream_read_data_valid_i2c_master_avalon_slave_0, which is an e_mux
  assign system_0_burst_33_downstream_read_data_valid_i2c_master_avalon_slave_0 = system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0 & system_0_burst_33_downstream_read & ~i2c_master_avalon_slave_0_waits_for_read;

  //i2c_master_avalon_slave_0_writedata mux, which is an e_mux
  assign i2c_master_avalon_slave_0_writedata = (system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0)? system_0_burst_33_downstream_writedata :
    system_0_burst_34_downstream_writedata;

  assign system_0_burst_34_downstream_requests_i2c_master_avalon_slave_0 = (1) & (system_0_burst_34_downstream_read | system_0_burst_34_downstream_write);
  //system_0_burst_33/downstream granted i2c_master/avalon_slave_0 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_system_0_burst_33_downstream_granted_slave_i2c_master_avalon_slave_0 <= 0;
      else 
        last_cycle_system_0_burst_33_downstream_granted_slave_i2c_master_avalon_slave_0 <= system_0_burst_33_downstream_saved_grant_i2c_master_avalon_slave_0 ? 1 : (i2c_master_avalon_slave_0_arbitration_holdoff_internal | 0) ? 0 : last_cycle_system_0_burst_33_downstream_granted_slave_i2c_master_avalon_slave_0;
    end


  //system_0_burst_33_downstream_continuerequest continued request, which is an e_mux
  assign system_0_burst_33_downstream_continuerequest = last_cycle_system_0_burst_33_downstream_granted_slave_i2c_master_avalon_slave_0 & 1;

  assign system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0 = system_0_burst_34_downstream_requests_i2c_master_avalon_slave_0 & ~((system_0_burst_34_downstream_read & ((system_0_burst_34_downstream_latency_counter != 0))) | system_0_burst_33_downstream_arbiterlock);
  //local readdatavalid system_0_burst_34_downstream_read_data_valid_i2c_master_avalon_slave_0, which is an e_mux
  assign system_0_burst_34_downstream_read_data_valid_i2c_master_avalon_slave_0 = system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0 & system_0_burst_34_downstream_read & ~i2c_master_avalon_slave_0_waits_for_read;

  //allow new arb cycle for i2c_master/avalon_slave_0, which is an e_assign
  assign i2c_master_avalon_slave_0_allow_new_arb_cycle = ~system_0_burst_33_downstream_arbiterlock & ~system_0_burst_34_downstream_arbiterlock;

  //system_0_burst_34/downstream assignment into master qualified-requests vector for i2c_master/avalon_slave_0, which is an e_assign
  assign i2c_master_avalon_slave_0_master_qreq_vector[0] = system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0;

  //system_0_burst_34/downstream grant i2c_master/avalon_slave_0, which is an e_assign
  assign system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0 = i2c_master_avalon_slave_0_grant_vector[0];

  //system_0_burst_34/downstream saved-grant i2c_master/avalon_slave_0, which is an e_assign
  assign system_0_burst_34_downstream_saved_grant_i2c_master_avalon_slave_0 = i2c_master_avalon_slave_0_arb_winner[0];

  //system_0_burst_33/downstream assignment into master qualified-requests vector for i2c_master/avalon_slave_0, which is an e_assign
  assign i2c_master_avalon_slave_0_master_qreq_vector[1] = system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0;

  //system_0_burst_33/downstream grant i2c_master/avalon_slave_0, which is an e_assign
  assign system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0 = i2c_master_avalon_slave_0_grant_vector[1];

  //system_0_burst_33/downstream saved-grant i2c_master/avalon_slave_0, which is an e_assign
  assign system_0_burst_33_downstream_saved_grant_i2c_master_avalon_slave_0 = i2c_master_avalon_slave_0_arb_winner[1];

  //i2c_master/avalon_slave_0 chosen-master double-vector, which is an e_assign
  assign i2c_master_avalon_slave_0_chosen_master_double_vector = {i2c_master_avalon_slave_0_master_qreq_vector, i2c_master_avalon_slave_0_master_qreq_vector} & ({~i2c_master_avalon_slave_0_master_qreq_vector, ~i2c_master_avalon_slave_0_master_qreq_vector} + i2c_master_avalon_slave_0_arb_addend);

  //stable onehot encoding of arb winner
  assign i2c_master_avalon_slave_0_arb_winner = (i2c_master_avalon_slave_0_allow_new_arb_cycle & | i2c_master_avalon_slave_0_grant_vector) ? i2c_master_avalon_slave_0_grant_vector : i2c_master_avalon_slave_0_saved_chosen_master_vector;

  //saved i2c_master_avalon_slave_0_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          i2c_master_avalon_slave_0_saved_chosen_master_vector <= 0;
      else if (i2c_master_avalon_slave_0_allow_new_arb_cycle)
          i2c_master_avalon_slave_0_saved_chosen_master_vector <= |i2c_master_avalon_slave_0_grant_vector ? i2c_master_avalon_slave_0_grant_vector : i2c_master_avalon_slave_0_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign i2c_master_avalon_slave_0_grant_vector = {(i2c_master_avalon_slave_0_chosen_master_double_vector[1] | i2c_master_avalon_slave_0_chosen_master_double_vector[3]),
    (i2c_master_avalon_slave_0_chosen_master_double_vector[0] | i2c_master_avalon_slave_0_chosen_master_double_vector[2])};

  //i2c_master/avalon_slave_0 chosen master rotated left, which is an e_assign
  assign i2c_master_avalon_slave_0_chosen_master_rot_left = (i2c_master_avalon_slave_0_arb_winner << 1) ? (i2c_master_avalon_slave_0_arb_winner << 1) : 1;

  //i2c_master/avalon_slave_0's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          i2c_master_avalon_slave_0_arb_addend <= 1;
      else if (|i2c_master_avalon_slave_0_grant_vector)
          i2c_master_avalon_slave_0_arb_addend <= i2c_master_avalon_slave_0_end_xfer? i2c_master_avalon_slave_0_chosen_master_rot_left : i2c_master_avalon_slave_0_grant_vector;
    end


  //~i2c_master_avalon_slave_0_reset assignment, which is an e_assign
  assign i2c_master_avalon_slave_0_reset = ~reset_n;

  assign i2c_master_avalon_slave_0_chipselect = system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0 | system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0;
  //i2c_master_avalon_slave_0_firsttransfer first transaction, which is an e_assign
  assign i2c_master_avalon_slave_0_firsttransfer = i2c_master_avalon_slave_0_begins_xfer ? i2c_master_avalon_slave_0_unreg_firsttransfer : i2c_master_avalon_slave_0_reg_firsttransfer;

  //i2c_master_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
  assign i2c_master_avalon_slave_0_unreg_firsttransfer = ~(i2c_master_avalon_slave_0_slavearbiterlockenable & i2c_master_avalon_slave_0_any_continuerequest);

  //i2c_master_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          i2c_master_avalon_slave_0_reg_firsttransfer <= 1'b1;
      else if (i2c_master_avalon_slave_0_begins_xfer)
          i2c_master_avalon_slave_0_reg_firsttransfer <= i2c_master_avalon_slave_0_unreg_firsttransfer;
    end


  //i2c_master_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign i2c_master_avalon_slave_0_beginbursttransfer_internal = i2c_master_avalon_slave_0_begins_xfer;

  //i2c_master_avalon_slave_0_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign i2c_master_avalon_slave_0_arbitration_holdoff_internal = i2c_master_avalon_slave_0_begins_xfer & i2c_master_avalon_slave_0_firsttransfer;

  //i2c_master_avalon_slave_0_write assignment, which is an e_mux
  assign i2c_master_avalon_slave_0_write = (system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0 & system_0_burst_33_downstream_write) | (system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0 & system_0_burst_34_downstream_write);

  assign shifted_address_to_i2c_master_avalon_slave_0_from_system_0_burst_33_downstream = system_0_burst_33_downstream_address_to_slave;
  //i2c_master_avalon_slave_0_address mux, which is an e_mux
  assign i2c_master_avalon_slave_0_address = (system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0)? (shifted_address_to_i2c_master_avalon_slave_0_from_system_0_burst_33_downstream >> 2) :
    (shifted_address_to_i2c_master_avalon_slave_0_from_system_0_burst_34_downstream >> 2);

  assign shifted_address_to_i2c_master_avalon_slave_0_from_system_0_burst_34_downstream = system_0_burst_34_downstream_address_to_slave;
  //d1_i2c_master_avalon_slave_0_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_i2c_master_avalon_slave_0_end_xfer <= 1;
      else 
        d1_i2c_master_avalon_slave_0_end_xfer <= i2c_master_avalon_slave_0_end_xfer;
    end


  //i2c_master_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
  assign i2c_master_avalon_slave_0_waits_for_read = i2c_master_avalon_slave_0_in_a_read_cycle & ~i2c_master_avalon_slave_0_waitrequest_n_from_sa;

  //i2c_master_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
  assign i2c_master_avalon_slave_0_in_a_read_cycle = (system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0 & system_0_burst_33_downstream_read) | (system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0 & system_0_burst_34_downstream_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = i2c_master_avalon_slave_0_in_a_read_cycle;

  //i2c_master_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
  assign i2c_master_avalon_slave_0_waits_for_write = i2c_master_avalon_slave_0_in_a_write_cycle & ~i2c_master_avalon_slave_0_waitrequest_n_from_sa;

  //i2c_master_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
  assign i2c_master_avalon_slave_0_in_a_write_cycle = (system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0 & system_0_burst_33_downstream_write) | (system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0 & system_0_burst_34_downstream_write);

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = i2c_master_avalon_slave_0_in_a_write_cycle;

  assign wait_for_i2c_master_avalon_slave_0_counter = 0;
  //assign i2c_master_avalon_slave_0_irq_from_sa = i2c_master_avalon_slave_0_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign i2c_master_avalon_slave_0_irq_from_sa = i2c_master_avalon_slave_0_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //i2c_master/avalon_slave_0 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_33/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_33_downstream_requests_i2c_master_avalon_slave_0 && (system_0_burst_33_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_33/downstream drove 0 on its 'arbitrationshare' port while accessing slave i2c_master/avalon_slave_0", $time);
          $stop;
        end
    end


  //system_0_burst_33/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_33_downstream_requests_i2c_master_avalon_slave_0 && (system_0_burst_33_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_33/downstream drove 0 on its 'burstcount' port while accessing slave i2c_master/avalon_slave_0", $time);
          $stop;
        end
    end


  //system_0_burst_34/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_34_downstream_requests_i2c_master_avalon_slave_0 && (system_0_burst_34_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_34/downstream drove 0 on its 'arbitrationshare' port while accessing slave i2c_master/avalon_slave_0", $time);
          $stop;
        end
    end


  //system_0_burst_34/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_34_downstream_requests_i2c_master_avalon_slave_0 && (system_0_burst_34_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_34/downstream drove 0 on its 'burstcount' port while accessing slave i2c_master/avalon_slave_0", $time);
          $stop;
        end
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0 + system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0 > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_33_downstream_saved_grant_i2c_master_avalon_slave_0 + system_0_burst_34_downstream_saved_grant_i2c_master_avalon_slave_0 > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module jtag_uart_0_avalon_jtag_slave_arbitrator (
                                                  // inputs:
                                                   clk,
                                                   jtag_uart_0_avalon_jtag_slave_dataavailable,
                                                   jtag_uart_0_avalon_jtag_slave_irq,
                                                   jtag_uart_0_avalon_jtag_slave_readdata,
                                                   jtag_uart_0_avalon_jtag_slave_readyfordata,
                                                   jtag_uart_0_avalon_jtag_slave_waitrequest,
                                                   reset_n,
                                                   system_0_burst_8_downstream_address_to_slave,
                                                   system_0_burst_8_downstream_arbitrationshare,
                                                   system_0_burst_8_downstream_burstcount,
                                                   system_0_burst_8_downstream_latency_counter,
                                                   system_0_burst_8_downstream_nativeaddress,
                                                   system_0_burst_8_downstream_read,
                                                   system_0_burst_8_downstream_write,
                                                   system_0_burst_8_downstream_writedata,

                                                  // outputs:
                                                   d1_jtag_uart_0_avalon_jtag_slave_end_xfer,
                                                   jtag_uart_0_avalon_jtag_slave_address,
                                                   jtag_uart_0_avalon_jtag_slave_chipselect,
                                                   jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa,
                                                   jtag_uart_0_avalon_jtag_slave_irq_from_sa,
                                                   jtag_uart_0_avalon_jtag_slave_read_n,
                                                   jtag_uart_0_avalon_jtag_slave_readdata_from_sa,
                                                   jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa,
                                                   jtag_uart_0_avalon_jtag_slave_reset_n,
                                                   jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa,
                                                   jtag_uart_0_avalon_jtag_slave_write_n,
                                                   jtag_uart_0_avalon_jtag_slave_writedata,
                                                   system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave,
                                                   system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave,
                                                   system_0_burst_8_downstream_read_data_valid_jtag_uart_0_avalon_jtag_slave,
                                                   system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave
                                                )
;

  output           d1_jtag_uart_0_avalon_jtag_slave_end_xfer;
  output           jtag_uart_0_avalon_jtag_slave_address;
  output           jtag_uart_0_avalon_jtag_slave_chipselect;
  output           jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa;
  output           jtag_uart_0_avalon_jtag_slave_irq_from_sa;
  output           jtag_uart_0_avalon_jtag_slave_read_n;
  output  [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
  output           jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa;
  output           jtag_uart_0_avalon_jtag_slave_reset_n;
  output           jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
  output           jtag_uart_0_avalon_jtag_slave_write_n;
  output  [ 31: 0] jtag_uart_0_avalon_jtag_slave_writedata;
  output           system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave;
  output           system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave;
  output           system_0_burst_8_downstream_read_data_valid_jtag_uart_0_avalon_jtag_slave;
  output           system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave;
  input            clk;
  input            jtag_uart_0_avalon_jtag_slave_dataavailable;
  input            jtag_uart_0_avalon_jtag_slave_irq;
  input   [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata;
  input            jtag_uart_0_avalon_jtag_slave_readyfordata;
  input            jtag_uart_0_avalon_jtag_slave_waitrequest;
  input            reset_n;
  input   [  2: 0] system_0_burst_8_downstream_address_to_slave;
  input   [  3: 0] system_0_burst_8_downstream_arbitrationshare;
  input            system_0_burst_8_downstream_burstcount;
  input            system_0_burst_8_downstream_latency_counter;
  input   [  2: 0] system_0_burst_8_downstream_nativeaddress;
  input            system_0_burst_8_downstream_read;
  input            system_0_burst_8_downstream_write;
  input   [ 31: 0] system_0_burst_8_downstream_writedata;

  reg              d1_jtag_uart_0_avalon_jtag_slave_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             jtag_uart_0_avalon_jtag_slave_address;
  wire             jtag_uart_0_avalon_jtag_slave_allgrants;
  wire             jtag_uart_0_avalon_jtag_slave_allow_new_arb_cycle;
  wire             jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant;
  wire             jtag_uart_0_avalon_jtag_slave_any_continuerequest;
  wire             jtag_uart_0_avalon_jtag_slave_arb_counter_enable;
  reg     [  3: 0] jtag_uart_0_avalon_jtag_slave_arb_share_counter;
  wire    [  3: 0] jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value;
  wire    [  3: 0] jtag_uart_0_avalon_jtag_slave_arb_share_set_values;
  wire             jtag_uart_0_avalon_jtag_slave_beginbursttransfer_internal;
  wire             jtag_uart_0_avalon_jtag_slave_begins_xfer;
  wire             jtag_uart_0_avalon_jtag_slave_chipselect;
  wire             jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_0_avalon_jtag_slave_end_xfer;
  wire             jtag_uart_0_avalon_jtag_slave_firsttransfer;
  wire             jtag_uart_0_avalon_jtag_slave_grant_vector;
  wire             jtag_uart_0_avalon_jtag_slave_in_a_read_cycle;
  wire             jtag_uart_0_avalon_jtag_slave_in_a_write_cycle;
  wire             jtag_uart_0_avalon_jtag_slave_irq_from_sa;
  wire             jtag_uart_0_avalon_jtag_slave_master_qreq_vector;
  wire             jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests;
  wire             jtag_uart_0_avalon_jtag_slave_read_n;
  wire    [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
  wire             jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa;
  reg              jtag_uart_0_avalon_jtag_slave_reg_firsttransfer;
  wire             jtag_uart_0_avalon_jtag_slave_reset_n;
  reg              jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable;
  wire             jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2;
  wire             jtag_uart_0_avalon_jtag_slave_unreg_firsttransfer;
  wire             jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
  wire             jtag_uart_0_avalon_jtag_slave_waits_for_read;
  wire             jtag_uart_0_avalon_jtag_slave_waits_for_write;
  wire             jtag_uart_0_avalon_jtag_slave_write_n;
  wire    [ 31: 0] jtag_uart_0_avalon_jtag_slave_writedata;
  wire             system_0_burst_8_downstream_arbiterlock;
  wire             system_0_burst_8_downstream_arbiterlock2;
  wire             system_0_burst_8_downstream_continuerequest;
  wire             system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave;
  wire             system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave;
  wire             system_0_burst_8_downstream_read_data_valid_jtag_uart_0_avalon_jtag_slave;
  wire             system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave;
  wire             system_0_burst_8_downstream_saved_grant_jtag_uart_0_avalon_jtag_slave;
  wire             wait_for_jtag_uart_0_avalon_jtag_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~jtag_uart_0_avalon_jtag_slave_end_xfer;
    end


  assign jtag_uart_0_avalon_jtag_slave_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave));
  //assign jtag_uart_0_avalon_jtag_slave_readdata_from_sa = jtag_uart_0_avalon_jtag_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_readdata_from_sa = jtag_uart_0_avalon_jtag_slave_readdata;

  assign system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave = (1) & (system_0_burst_8_downstream_read | system_0_burst_8_downstream_write);
  //assign jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_0_avalon_jtag_slave_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_0_avalon_jtag_slave_dataavailable;

  //assign jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_0_avalon_jtag_slave_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_0_avalon_jtag_slave_readyfordata;

  //assign jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_0_avalon_jtag_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_0_avalon_jtag_slave_waitrequest;

  //jtag_uart_0_avalon_jtag_slave_arb_share_counter set values, which is an e_mux
  assign jtag_uart_0_avalon_jtag_slave_arb_share_set_values = (system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave)? system_0_burst_8_downstream_arbitrationshare :
    1;

  //jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests mux, which is an e_mux
  assign jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests = 0;

  //jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant = system_0_burst_8_downstream_saved_grant_jtag_uart_0_avalon_jtag_slave;

  //jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value = jtag_uart_0_avalon_jtag_slave_firsttransfer ? (jtag_uart_0_avalon_jtag_slave_arb_share_set_values - 1) : |jtag_uart_0_avalon_jtag_slave_arb_share_counter ? (jtag_uart_0_avalon_jtag_slave_arb_share_counter - 1) : 0;

  //jtag_uart_0_avalon_jtag_slave_allgrants all slave grants, which is an e_mux
  assign jtag_uart_0_avalon_jtag_slave_allgrants = |jtag_uart_0_avalon_jtag_slave_grant_vector;

  //jtag_uart_0_avalon_jtag_slave_end_xfer assignment, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_end_xfer = ~(jtag_uart_0_avalon_jtag_slave_waits_for_read | jtag_uart_0_avalon_jtag_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave = jtag_uart_0_avalon_jtag_slave_end_xfer & (~jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //jtag_uart_0_avalon_jtag_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave & jtag_uart_0_avalon_jtag_slave_allgrants) | (end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave & ~jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests);

  //jtag_uart_0_avalon_jtag_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_0_avalon_jtag_slave_arb_share_counter <= 0;
      else if (jtag_uart_0_avalon_jtag_slave_arb_counter_enable)
          jtag_uart_0_avalon_jtag_slave_arb_share_counter <= jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value;
    end


  //jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable <= 0;
      else if ((|jtag_uart_0_avalon_jtag_slave_master_qreq_vector & end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave) | (end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave & ~jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests))
          jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable <= |jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value;
    end


  //system_0_burst_8/downstream jtag_uart_0/avalon_jtag_slave arbiterlock, which is an e_assign
  assign system_0_burst_8_downstream_arbiterlock = jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable & system_0_burst_8_downstream_continuerequest;

  //jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2 = |jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value;

  //system_0_burst_8/downstream jtag_uart_0/avalon_jtag_slave arbiterlock2, which is an e_assign
  assign system_0_burst_8_downstream_arbiterlock2 = jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2 & system_0_burst_8_downstream_continuerequest;

  //jtag_uart_0_avalon_jtag_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_any_continuerequest = 1;

  //system_0_burst_8_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_8_downstream_continuerequest = 1;

  assign system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave = system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave & ~((system_0_burst_8_downstream_read & ((system_0_burst_8_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_8_downstream_read_data_valid_jtag_uart_0_avalon_jtag_slave, which is an e_mux
  assign system_0_burst_8_downstream_read_data_valid_jtag_uart_0_avalon_jtag_slave = system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave & system_0_burst_8_downstream_read & ~jtag_uart_0_avalon_jtag_slave_waits_for_read;

  //jtag_uart_0_avalon_jtag_slave_writedata mux, which is an e_mux
  assign jtag_uart_0_avalon_jtag_slave_writedata = system_0_burst_8_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave = system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave;

  //system_0_burst_8/downstream saved-grant jtag_uart_0/avalon_jtag_slave, which is an e_assign
  assign system_0_burst_8_downstream_saved_grant_jtag_uart_0_avalon_jtag_slave = system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave;

  //allow new arb cycle for jtag_uart_0/avalon_jtag_slave, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign jtag_uart_0_avalon_jtag_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign jtag_uart_0_avalon_jtag_slave_master_qreq_vector = 1;

  //jtag_uart_0_avalon_jtag_slave_reset_n assignment, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_reset_n = reset_n;

  assign jtag_uart_0_avalon_jtag_slave_chipselect = system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave;
  //jtag_uart_0_avalon_jtag_slave_firsttransfer first transaction, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_firsttransfer = jtag_uart_0_avalon_jtag_slave_begins_xfer ? jtag_uart_0_avalon_jtag_slave_unreg_firsttransfer : jtag_uart_0_avalon_jtag_slave_reg_firsttransfer;

  //jtag_uart_0_avalon_jtag_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_unreg_firsttransfer = ~(jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable & jtag_uart_0_avalon_jtag_slave_any_continuerequest);

  //jtag_uart_0_avalon_jtag_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_0_avalon_jtag_slave_reg_firsttransfer <= 1'b1;
      else if (jtag_uart_0_avalon_jtag_slave_begins_xfer)
          jtag_uart_0_avalon_jtag_slave_reg_firsttransfer <= jtag_uart_0_avalon_jtag_slave_unreg_firsttransfer;
    end


  //jtag_uart_0_avalon_jtag_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_beginbursttransfer_internal = jtag_uart_0_avalon_jtag_slave_begins_xfer;

  //~jtag_uart_0_avalon_jtag_slave_read_n assignment, which is an e_mux
  assign jtag_uart_0_avalon_jtag_slave_read_n = ~(system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave & system_0_burst_8_downstream_read);

  //~jtag_uart_0_avalon_jtag_slave_write_n assignment, which is an e_mux
  assign jtag_uart_0_avalon_jtag_slave_write_n = ~(system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave & system_0_burst_8_downstream_write);

  //jtag_uart_0_avalon_jtag_slave_address mux, which is an e_mux
  assign jtag_uart_0_avalon_jtag_slave_address = system_0_burst_8_downstream_nativeaddress;

  //d1_jtag_uart_0_avalon_jtag_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_jtag_uart_0_avalon_jtag_slave_end_xfer <= 1;
      else 
        d1_jtag_uart_0_avalon_jtag_slave_end_xfer <= jtag_uart_0_avalon_jtag_slave_end_xfer;
    end


  //jtag_uart_0_avalon_jtag_slave_waits_for_read in a cycle, which is an e_mux
  assign jtag_uart_0_avalon_jtag_slave_waits_for_read = jtag_uart_0_avalon_jtag_slave_in_a_read_cycle & jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;

  //jtag_uart_0_avalon_jtag_slave_in_a_read_cycle assignment, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_in_a_read_cycle = system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave & system_0_burst_8_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = jtag_uart_0_avalon_jtag_slave_in_a_read_cycle;

  //jtag_uart_0_avalon_jtag_slave_waits_for_write in a cycle, which is an e_mux
  assign jtag_uart_0_avalon_jtag_slave_waits_for_write = jtag_uart_0_avalon_jtag_slave_in_a_write_cycle & jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;

  //jtag_uart_0_avalon_jtag_slave_in_a_write_cycle assignment, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_in_a_write_cycle = system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave & system_0_burst_8_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = jtag_uart_0_avalon_jtag_slave_in_a_write_cycle;

  assign wait_for_jtag_uart_0_avalon_jtag_slave_counter = 0;
  //assign jtag_uart_0_avalon_jtag_slave_irq_from_sa = jtag_uart_0_avalon_jtag_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_0_avalon_jtag_slave_irq_from_sa = jtag_uart_0_avalon_jtag_slave_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //jtag_uart_0/avalon_jtag_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_8/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave && (system_0_burst_8_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_8/downstream drove 0 on its 'arbitrationshare' port while accessing slave jtag_uart_0/avalon_jtag_slave", $time);
          $stop;
        end
    end


  //system_0_burst_8/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave && (system_0_burst_8_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_8/downstream drove 0 on its 'burstcount' port while accessing slave jtag_uart_0/avalon_jtag_slave", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module lcd_16207_0_control_slave_arbitrator (
                                              // inputs:
                                               clk,
                                               lcd_16207_0_control_slave_readdata,
                                               reset_n,
                                               system_0_burst_12_downstream_address_to_slave,
                                               system_0_burst_12_downstream_arbitrationshare,
                                               system_0_burst_12_downstream_burstcount,
                                               system_0_burst_12_downstream_byteenable,
                                               system_0_burst_12_downstream_latency_counter,
                                               system_0_burst_12_downstream_nativeaddress,
                                               system_0_burst_12_downstream_read,
                                               system_0_burst_12_downstream_write,
                                               system_0_burst_12_downstream_writedata,

                                              // outputs:
                                               d1_lcd_16207_0_control_slave_end_xfer,
                                               lcd_16207_0_control_slave_address,
                                               lcd_16207_0_control_slave_begintransfer,
                                               lcd_16207_0_control_slave_read,
                                               lcd_16207_0_control_slave_readdata_from_sa,
                                               lcd_16207_0_control_slave_wait_counter_eq_0,
                                               lcd_16207_0_control_slave_write,
                                               lcd_16207_0_control_slave_writedata,
                                               system_0_burst_12_downstream_granted_lcd_16207_0_control_slave,
                                               system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave,
                                               system_0_burst_12_downstream_read_data_valid_lcd_16207_0_control_slave,
                                               system_0_burst_12_downstream_requests_lcd_16207_0_control_slave
                                            )
;

  output           d1_lcd_16207_0_control_slave_end_xfer;
  output  [  1: 0] lcd_16207_0_control_slave_address;
  output           lcd_16207_0_control_slave_begintransfer;
  output           lcd_16207_0_control_slave_read;
  output  [  7: 0] lcd_16207_0_control_slave_readdata_from_sa;
  output           lcd_16207_0_control_slave_wait_counter_eq_0;
  output           lcd_16207_0_control_slave_write;
  output  [  7: 0] lcd_16207_0_control_slave_writedata;
  output           system_0_burst_12_downstream_granted_lcd_16207_0_control_slave;
  output           system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave;
  output           system_0_burst_12_downstream_read_data_valid_lcd_16207_0_control_slave;
  output           system_0_burst_12_downstream_requests_lcd_16207_0_control_slave;
  input            clk;
  input   [  7: 0] lcd_16207_0_control_slave_readdata;
  input            reset_n;
  input   [  1: 0] system_0_burst_12_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_12_downstream_arbitrationshare;
  input            system_0_burst_12_downstream_burstcount;
  input            system_0_burst_12_downstream_byteenable;
  input            system_0_burst_12_downstream_latency_counter;
  input   [  1: 0] system_0_burst_12_downstream_nativeaddress;
  input            system_0_burst_12_downstream_read;
  input            system_0_burst_12_downstream_write;
  input   [  7: 0] system_0_burst_12_downstream_writedata;

  reg              d1_lcd_16207_0_control_slave_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_lcd_16207_0_control_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] lcd_16207_0_control_slave_address;
  wire             lcd_16207_0_control_slave_allgrants;
  wire             lcd_16207_0_control_slave_allow_new_arb_cycle;
  wire             lcd_16207_0_control_slave_any_bursting_master_saved_grant;
  wire             lcd_16207_0_control_slave_any_continuerequest;
  wire             lcd_16207_0_control_slave_arb_counter_enable;
  reg     [  5: 0] lcd_16207_0_control_slave_arb_share_counter;
  wire    [  5: 0] lcd_16207_0_control_slave_arb_share_counter_next_value;
  wire    [  5: 0] lcd_16207_0_control_slave_arb_share_set_values;
  wire             lcd_16207_0_control_slave_beginbursttransfer_internal;
  wire             lcd_16207_0_control_slave_begins_xfer;
  wire             lcd_16207_0_control_slave_begintransfer;
  wire    [  6: 0] lcd_16207_0_control_slave_counter_load_value;
  wire             lcd_16207_0_control_slave_end_xfer;
  wire             lcd_16207_0_control_slave_firsttransfer;
  wire             lcd_16207_0_control_slave_grant_vector;
  wire             lcd_16207_0_control_slave_in_a_read_cycle;
  wire             lcd_16207_0_control_slave_in_a_write_cycle;
  wire             lcd_16207_0_control_slave_master_qreq_vector;
  wire             lcd_16207_0_control_slave_non_bursting_master_requests;
  wire             lcd_16207_0_control_slave_pretend_byte_enable;
  wire             lcd_16207_0_control_slave_read;
  wire    [  7: 0] lcd_16207_0_control_slave_readdata_from_sa;
  reg              lcd_16207_0_control_slave_reg_firsttransfer;
  reg              lcd_16207_0_control_slave_slavearbiterlockenable;
  wire             lcd_16207_0_control_slave_slavearbiterlockenable2;
  wire             lcd_16207_0_control_slave_unreg_firsttransfer;
  reg     [  6: 0] lcd_16207_0_control_slave_wait_counter;
  wire             lcd_16207_0_control_slave_wait_counter_eq_0;
  wire             lcd_16207_0_control_slave_waits_for_read;
  wire             lcd_16207_0_control_slave_waits_for_write;
  wire             lcd_16207_0_control_slave_write;
  wire    [  7: 0] lcd_16207_0_control_slave_writedata;
  wire             system_0_burst_12_downstream_arbiterlock;
  wire             system_0_burst_12_downstream_arbiterlock2;
  wire             system_0_burst_12_downstream_continuerequest;
  wire             system_0_burst_12_downstream_granted_lcd_16207_0_control_slave;
  wire             system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave;
  wire             system_0_burst_12_downstream_read_data_valid_lcd_16207_0_control_slave;
  wire             system_0_burst_12_downstream_requests_lcd_16207_0_control_slave;
  wire             system_0_burst_12_downstream_saved_grant_lcd_16207_0_control_slave;
  wire             wait_for_lcd_16207_0_control_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~lcd_16207_0_control_slave_end_xfer;
    end


  assign lcd_16207_0_control_slave_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave));
  //assign lcd_16207_0_control_slave_readdata_from_sa = lcd_16207_0_control_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign lcd_16207_0_control_slave_readdata_from_sa = lcd_16207_0_control_slave_readdata;

  assign system_0_burst_12_downstream_requests_lcd_16207_0_control_slave = (1) & (system_0_burst_12_downstream_read | system_0_burst_12_downstream_write);
  //lcd_16207_0_control_slave_arb_share_counter set values, which is an e_mux
  assign lcd_16207_0_control_slave_arb_share_set_values = (system_0_burst_12_downstream_granted_lcd_16207_0_control_slave)? system_0_burst_12_downstream_arbitrationshare :
    1;

  //lcd_16207_0_control_slave_non_bursting_master_requests mux, which is an e_mux
  assign lcd_16207_0_control_slave_non_bursting_master_requests = 0;

  //lcd_16207_0_control_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign lcd_16207_0_control_slave_any_bursting_master_saved_grant = system_0_burst_12_downstream_saved_grant_lcd_16207_0_control_slave;

  //lcd_16207_0_control_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign lcd_16207_0_control_slave_arb_share_counter_next_value = lcd_16207_0_control_slave_firsttransfer ? (lcd_16207_0_control_slave_arb_share_set_values - 1) : |lcd_16207_0_control_slave_arb_share_counter ? (lcd_16207_0_control_slave_arb_share_counter - 1) : 0;

  //lcd_16207_0_control_slave_allgrants all slave grants, which is an e_mux
  assign lcd_16207_0_control_slave_allgrants = |lcd_16207_0_control_slave_grant_vector;

  //lcd_16207_0_control_slave_end_xfer assignment, which is an e_assign
  assign lcd_16207_0_control_slave_end_xfer = ~(lcd_16207_0_control_slave_waits_for_read | lcd_16207_0_control_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_lcd_16207_0_control_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_lcd_16207_0_control_slave = lcd_16207_0_control_slave_end_xfer & (~lcd_16207_0_control_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //lcd_16207_0_control_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign lcd_16207_0_control_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_lcd_16207_0_control_slave & lcd_16207_0_control_slave_allgrants) | (end_xfer_arb_share_counter_term_lcd_16207_0_control_slave & ~lcd_16207_0_control_slave_non_bursting_master_requests);

  //lcd_16207_0_control_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_16207_0_control_slave_arb_share_counter <= 0;
      else if (lcd_16207_0_control_slave_arb_counter_enable)
          lcd_16207_0_control_slave_arb_share_counter <= lcd_16207_0_control_slave_arb_share_counter_next_value;
    end


  //lcd_16207_0_control_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_16207_0_control_slave_slavearbiterlockenable <= 0;
      else if ((|lcd_16207_0_control_slave_master_qreq_vector & end_xfer_arb_share_counter_term_lcd_16207_0_control_slave) | (end_xfer_arb_share_counter_term_lcd_16207_0_control_slave & ~lcd_16207_0_control_slave_non_bursting_master_requests))
          lcd_16207_0_control_slave_slavearbiterlockenable <= |lcd_16207_0_control_slave_arb_share_counter_next_value;
    end


  //system_0_burst_12/downstream lcd_16207_0/control_slave arbiterlock, which is an e_assign
  assign system_0_burst_12_downstream_arbiterlock = lcd_16207_0_control_slave_slavearbiterlockenable & system_0_burst_12_downstream_continuerequest;

  //lcd_16207_0_control_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign lcd_16207_0_control_slave_slavearbiterlockenable2 = |lcd_16207_0_control_slave_arb_share_counter_next_value;

  //system_0_burst_12/downstream lcd_16207_0/control_slave arbiterlock2, which is an e_assign
  assign system_0_burst_12_downstream_arbiterlock2 = lcd_16207_0_control_slave_slavearbiterlockenable2 & system_0_burst_12_downstream_continuerequest;

  //lcd_16207_0_control_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign lcd_16207_0_control_slave_any_continuerequest = 1;

  //system_0_burst_12_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_12_downstream_continuerequest = 1;

  assign system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave = system_0_burst_12_downstream_requests_lcd_16207_0_control_slave & ~((system_0_burst_12_downstream_read & ((system_0_burst_12_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_12_downstream_read_data_valid_lcd_16207_0_control_slave, which is an e_mux
  assign system_0_burst_12_downstream_read_data_valid_lcd_16207_0_control_slave = system_0_burst_12_downstream_granted_lcd_16207_0_control_slave & system_0_burst_12_downstream_read & ~lcd_16207_0_control_slave_waits_for_read;

  //lcd_16207_0_control_slave_writedata mux, which is an e_mux
  assign lcd_16207_0_control_slave_writedata = system_0_burst_12_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_12_downstream_granted_lcd_16207_0_control_slave = system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave;

  //system_0_burst_12/downstream saved-grant lcd_16207_0/control_slave, which is an e_assign
  assign system_0_burst_12_downstream_saved_grant_lcd_16207_0_control_slave = system_0_burst_12_downstream_requests_lcd_16207_0_control_slave;

  //allow new arb cycle for lcd_16207_0/control_slave, which is an e_assign
  assign lcd_16207_0_control_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign lcd_16207_0_control_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign lcd_16207_0_control_slave_master_qreq_vector = 1;

  assign lcd_16207_0_control_slave_begintransfer = lcd_16207_0_control_slave_begins_xfer;
  //lcd_16207_0_control_slave_firsttransfer first transaction, which is an e_assign
  assign lcd_16207_0_control_slave_firsttransfer = lcd_16207_0_control_slave_begins_xfer ? lcd_16207_0_control_slave_unreg_firsttransfer : lcd_16207_0_control_slave_reg_firsttransfer;

  //lcd_16207_0_control_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign lcd_16207_0_control_slave_unreg_firsttransfer = ~(lcd_16207_0_control_slave_slavearbiterlockenable & lcd_16207_0_control_slave_any_continuerequest);

  //lcd_16207_0_control_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_16207_0_control_slave_reg_firsttransfer <= 1'b1;
      else if (lcd_16207_0_control_slave_begins_xfer)
          lcd_16207_0_control_slave_reg_firsttransfer <= lcd_16207_0_control_slave_unreg_firsttransfer;
    end


  //lcd_16207_0_control_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign lcd_16207_0_control_slave_beginbursttransfer_internal = lcd_16207_0_control_slave_begins_xfer;

  //lcd_16207_0_control_slave_read assignment, which is an e_mux
  assign lcd_16207_0_control_slave_read = ((system_0_burst_12_downstream_granted_lcd_16207_0_control_slave & system_0_burst_12_downstream_read))& ~lcd_16207_0_control_slave_begins_xfer & (lcd_16207_0_control_slave_wait_counter < 25);

  //lcd_16207_0_control_slave_write assignment, which is an e_mux
  assign lcd_16207_0_control_slave_write = ((system_0_burst_12_downstream_granted_lcd_16207_0_control_slave & system_0_burst_12_downstream_write)) & ~lcd_16207_0_control_slave_begins_xfer & (lcd_16207_0_control_slave_wait_counter >= 25) & (lcd_16207_0_control_slave_wait_counter < 50) & lcd_16207_0_control_slave_pretend_byte_enable;

  //lcd_16207_0_control_slave_address mux, which is an e_mux
  assign lcd_16207_0_control_slave_address = system_0_burst_12_downstream_nativeaddress;

  //d1_lcd_16207_0_control_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_lcd_16207_0_control_slave_end_xfer <= 1;
      else 
        d1_lcd_16207_0_control_slave_end_xfer <= lcd_16207_0_control_slave_end_xfer;
    end


  //lcd_16207_0_control_slave_waits_for_read in a cycle, which is an e_mux
  assign lcd_16207_0_control_slave_waits_for_read = lcd_16207_0_control_slave_in_a_read_cycle & wait_for_lcd_16207_0_control_slave_counter;

  //lcd_16207_0_control_slave_in_a_read_cycle assignment, which is an e_assign
  assign lcd_16207_0_control_slave_in_a_read_cycle = system_0_burst_12_downstream_granted_lcd_16207_0_control_slave & system_0_burst_12_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = lcd_16207_0_control_slave_in_a_read_cycle;

  //lcd_16207_0_control_slave_waits_for_write in a cycle, which is an e_mux
  assign lcd_16207_0_control_slave_waits_for_write = lcd_16207_0_control_slave_in_a_write_cycle & wait_for_lcd_16207_0_control_slave_counter;

  //lcd_16207_0_control_slave_in_a_write_cycle assignment, which is an e_assign
  assign lcd_16207_0_control_slave_in_a_write_cycle = system_0_burst_12_downstream_granted_lcd_16207_0_control_slave & system_0_burst_12_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = lcd_16207_0_control_slave_in_a_write_cycle;

  assign lcd_16207_0_control_slave_wait_counter_eq_0 = lcd_16207_0_control_slave_wait_counter == 0;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_16207_0_control_slave_wait_counter <= 0;
      else 
        lcd_16207_0_control_slave_wait_counter <= lcd_16207_0_control_slave_counter_load_value;
    end


  assign lcd_16207_0_control_slave_counter_load_value = ((lcd_16207_0_control_slave_in_a_read_cycle & lcd_16207_0_control_slave_begins_xfer))? 48 :
    ((lcd_16207_0_control_slave_in_a_write_cycle & lcd_16207_0_control_slave_begins_xfer))? 73 :
    (~lcd_16207_0_control_slave_wait_counter_eq_0)? lcd_16207_0_control_slave_wait_counter - 1 :
    0;

  assign wait_for_lcd_16207_0_control_slave_counter = lcd_16207_0_control_slave_begins_xfer | ~lcd_16207_0_control_slave_wait_counter_eq_0;
  //lcd_16207_0_control_slave_pretend_byte_enable byte enable port mux, which is an e_mux
  assign lcd_16207_0_control_slave_pretend_byte_enable = (system_0_burst_12_downstream_granted_lcd_16207_0_control_slave)? system_0_burst_12_downstream_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //lcd_16207_0/control_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_12/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_12_downstream_requests_lcd_16207_0_control_slave && (system_0_burst_12_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_12/downstream drove 0 on its 'arbitrationshare' port while accessing slave lcd_16207_0/control_slave", $time);
          $stop;
        end
    end


  //system_0_burst_12/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_12_downstream_requests_lcd_16207_0_control_slave && (system_0_burst_12_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_12/downstream drove 0 on its 'burstcount' port while accessing slave lcd_16207_0/control_slave", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module noteA_s1_arbitrator (
                             // inputs:
                              clk,
                              noteA_s1_readdata,
                              reset_n,
                              system_0_burst_20_downstream_address_to_slave,
                              system_0_burst_20_downstream_arbitrationshare,
                              system_0_burst_20_downstream_burstcount,
                              system_0_burst_20_downstream_latency_counter,
                              system_0_burst_20_downstream_nativeaddress,
                              system_0_burst_20_downstream_read,
                              system_0_burst_20_downstream_write,

                             // outputs:
                              d1_noteA_s1_end_xfer,
                              noteA_s1_address,
                              noteA_s1_readdata_from_sa,
                              noteA_s1_reset_n,
                              system_0_burst_20_downstream_granted_noteA_s1,
                              system_0_burst_20_downstream_qualified_request_noteA_s1,
                              system_0_burst_20_downstream_read_data_valid_noteA_s1,
                              system_0_burst_20_downstream_requests_noteA_s1
                           )
;

  output           d1_noteA_s1_end_xfer;
  output  [  1: 0] noteA_s1_address;
  output           noteA_s1_readdata_from_sa;
  output           noteA_s1_reset_n;
  output           system_0_burst_20_downstream_granted_noteA_s1;
  output           system_0_burst_20_downstream_qualified_request_noteA_s1;
  output           system_0_burst_20_downstream_read_data_valid_noteA_s1;
  output           system_0_burst_20_downstream_requests_noteA_s1;
  input            clk;
  input            noteA_s1_readdata;
  input            reset_n;
  input   [  1: 0] system_0_burst_20_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_20_downstream_arbitrationshare;
  input            system_0_burst_20_downstream_burstcount;
  input            system_0_burst_20_downstream_latency_counter;
  input   [  1: 0] system_0_burst_20_downstream_nativeaddress;
  input            system_0_burst_20_downstream_read;
  input            system_0_burst_20_downstream_write;

  reg              d1_noteA_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_noteA_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] noteA_s1_address;
  wire             noteA_s1_allgrants;
  wire             noteA_s1_allow_new_arb_cycle;
  wire             noteA_s1_any_bursting_master_saved_grant;
  wire             noteA_s1_any_continuerequest;
  wire             noteA_s1_arb_counter_enable;
  reg     [  5: 0] noteA_s1_arb_share_counter;
  wire    [  5: 0] noteA_s1_arb_share_counter_next_value;
  wire    [  5: 0] noteA_s1_arb_share_set_values;
  wire             noteA_s1_beginbursttransfer_internal;
  wire             noteA_s1_begins_xfer;
  wire             noteA_s1_end_xfer;
  wire             noteA_s1_firsttransfer;
  wire             noteA_s1_grant_vector;
  wire             noteA_s1_in_a_read_cycle;
  wire             noteA_s1_in_a_write_cycle;
  wire             noteA_s1_master_qreq_vector;
  wire             noteA_s1_non_bursting_master_requests;
  wire             noteA_s1_readdata_from_sa;
  reg              noteA_s1_reg_firsttransfer;
  wire             noteA_s1_reset_n;
  reg              noteA_s1_slavearbiterlockenable;
  wire             noteA_s1_slavearbiterlockenable2;
  wire             noteA_s1_unreg_firsttransfer;
  wire             noteA_s1_waits_for_read;
  wire             noteA_s1_waits_for_write;
  wire             system_0_burst_20_downstream_arbiterlock;
  wire             system_0_burst_20_downstream_arbiterlock2;
  wire             system_0_burst_20_downstream_continuerequest;
  wire             system_0_burst_20_downstream_granted_noteA_s1;
  wire             system_0_burst_20_downstream_qualified_request_noteA_s1;
  wire             system_0_burst_20_downstream_read_data_valid_noteA_s1;
  wire             system_0_burst_20_downstream_requests_noteA_s1;
  wire             system_0_burst_20_downstream_saved_grant_noteA_s1;
  wire             wait_for_noteA_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~noteA_s1_end_xfer;
    end


  assign noteA_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_20_downstream_qualified_request_noteA_s1));
  //assign noteA_s1_readdata_from_sa = noteA_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign noteA_s1_readdata_from_sa = noteA_s1_readdata;

  assign system_0_burst_20_downstream_requests_noteA_s1 = ((1) & (system_0_burst_20_downstream_read | system_0_burst_20_downstream_write)) & system_0_burst_20_downstream_read;
  //noteA_s1_arb_share_counter set values, which is an e_mux
  assign noteA_s1_arb_share_set_values = (system_0_burst_20_downstream_granted_noteA_s1)? system_0_burst_20_downstream_arbitrationshare :
    1;

  //noteA_s1_non_bursting_master_requests mux, which is an e_mux
  assign noteA_s1_non_bursting_master_requests = 0;

  //noteA_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign noteA_s1_any_bursting_master_saved_grant = system_0_burst_20_downstream_saved_grant_noteA_s1;

  //noteA_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign noteA_s1_arb_share_counter_next_value = noteA_s1_firsttransfer ? (noteA_s1_arb_share_set_values - 1) : |noteA_s1_arb_share_counter ? (noteA_s1_arb_share_counter - 1) : 0;

  //noteA_s1_allgrants all slave grants, which is an e_mux
  assign noteA_s1_allgrants = |noteA_s1_grant_vector;

  //noteA_s1_end_xfer assignment, which is an e_assign
  assign noteA_s1_end_xfer = ~(noteA_s1_waits_for_read | noteA_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_noteA_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_noteA_s1 = noteA_s1_end_xfer & (~noteA_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //noteA_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign noteA_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_noteA_s1 & noteA_s1_allgrants) | (end_xfer_arb_share_counter_term_noteA_s1 & ~noteA_s1_non_bursting_master_requests);

  //noteA_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteA_s1_arb_share_counter <= 0;
      else if (noteA_s1_arb_counter_enable)
          noteA_s1_arb_share_counter <= noteA_s1_arb_share_counter_next_value;
    end


  //noteA_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteA_s1_slavearbiterlockenable <= 0;
      else if ((|noteA_s1_master_qreq_vector & end_xfer_arb_share_counter_term_noteA_s1) | (end_xfer_arb_share_counter_term_noteA_s1 & ~noteA_s1_non_bursting_master_requests))
          noteA_s1_slavearbiterlockenable <= |noteA_s1_arb_share_counter_next_value;
    end


  //system_0_burst_20/downstream noteA/s1 arbiterlock, which is an e_assign
  assign system_0_burst_20_downstream_arbiterlock = noteA_s1_slavearbiterlockenable & system_0_burst_20_downstream_continuerequest;

  //noteA_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign noteA_s1_slavearbiterlockenable2 = |noteA_s1_arb_share_counter_next_value;

  //system_0_burst_20/downstream noteA/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_20_downstream_arbiterlock2 = noteA_s1_slavearbiterlockenable2 & system_0_burst_20_downstream_continuerequest;

  //noteA_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign noteA_s1_any_continuerequest = 1;

  //system_0_burst_20_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_20_downstream_continuerequest = 1;

  assign system_0_burst_20_downstream_qualified_request_noteA_s1 = system_0_burst_20_downstream_requests_noteA_s1 & ~((system_0_burst_20_downstream_read & ((system_0_burst_20_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_20_downstream_read_data_valid_noteA_s1, which is an e_mux
  assign system_0_burst_20_downstream_read_data_valid_noteA_s1 = system_0_burst_20_downstream_granted_noteA_s1 & system_0_burst_20_downstream_read & ~noteA_s1_waits_for_read;

  //master is always granted when requested
  assign system_0_burst_20_downstream_granted_noteA_s1 = system_0_burst_20_downstream_qualified_request_noteA_s1;

  //system_0_burst_20/downstream saved-grant noteA/s1, which is an e_assign
  assign system_0_burst_20_downstream_saved_grant_noteA_s1 = system_0_burst_20_downstream_requests_noteA_s1;

  //allow new arb cycle for noteA/s1, which is an e_assign
  assign noteA_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign noteA_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign noteA_s1_master_qreq_vector = 1;

  //noteA_s1_reset_n assignment, which is an e_assign
  assign noteA_s1_reset_n = reset_n;

  //noteA_s1_firsttransfer first transaction, which is an e_assign
  assign noteA_s1_firsttransfer = noteA_s1_begins_xfer ? noteA_s1_unreg_firsttransfer : noteA_s1_reg_firsttransfer;

  //noteA_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign noteA_s1_unreg_firsttransfer = ~(noteA_s1_slavearbiterlockenable & noteA_s1_any_continuerequest);

  //noteA_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteA_s1_reg_firsttransfer <= 1'b1;
      else if (noteA_s1_begins_xfer)
          noteA_s1_reg_firsttransfer <= noteA_s1_unreg_firsttransfer;
    end


  //noteA_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign noteA_s1_beginbursttransfer_internal = noteA_s1_begins_xfer;

  //noteA_s1_address mux, which is an e_mux
  assign noteA_s1_address = system_0_burst_20_downstream_nativeaddress;

  //d1_noteA_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_noteA_s1_end_xfer <= 1;
      else 
        d1_noteA_s1_end_xfer <= noteA_s1_end_xfer;
    end


  //noteA_s1_waits_for_read in a cycle, which is an e_mux
  assign noteA_s1_waits_for_read = noteA_s1_in_a_read_cycle & noteA_s1_begins_xfer;

  //noteA_s1_in_a_read_cycle assignment, which is an e_assign
  assign noteA_s1_in_a_read_cycle = system_0_burst_20_downstream_granted_noteA_s1 & system_0_burst_20_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = noteA_s1_in_a_read_cycle;

  //noteA_s1_waits_for_write in a cycle, which is an e_mux
  assign noteA_s1_waits_for_write = noteA_s1_in_a_write_cycle & 0;

  //noteA_s1_in_a_write_cycle assignment, which is an e_assign
  assign noteA_s1_in_a_write_cycle = system_0_burst_20_downstream_granted_noteA_s1 & system_0_burst_20_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = noteA_s1_in_a_write_cycle;

  assign wait_for_noteA_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //noteA/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_20/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_20_downstream_requests_noteA_s1 && (system_0_burst_20_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_20/downstream drove 0 on its 'arbitrationshare' port while accessing slave noteA/s1", $time);
          $stop;
        end
    end


  //system_0_burst_20/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_20_downstream_requests_noteA_s1 && (system_0_burst_20_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_20/downstream drove 0 on its 'burstcount' port while accessing slave noteA/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module noteB_s1_arbitrator (
                             // inputs:
                              clk,
                              noteB_s1_readdata,
                              reset_n,
                              system_0_burst_21_downstream_address_to_slave,
                              system_0_burst_21_downstream_arbitrationshare,
                              system_0_burst_21_downstream_burstcount,
                              system_0_burst_21_downstream_latency_counter,
                              system_0_burst_21_downstream_nativeaddress,
                              system_0_burst_21_downstream_read,
                              system_0_burst_21_downstream_write,

                             // outputs:
                              d1_noteB_s1_end_xfer,
                              noteB_s1_address,
                              noteB_s1_readdata_from_sa,
                              noteB_s1_reset_n,
                              system_0_burst_21_downstream_granted_noteB_s1,
                              system_0_burst_21_downstream_qualified_request_noteB_s1,
                              system_0_burst_21_downstream_read_data_valid_noteB_s1,
                              system_0_burst_21_downstream_requests_noteB_s1
                           )
;

  output           d1_noteB_s1_end_xfer;
  output  [  1: 0] noteB_s1_address;
  output           noteB_s1_readdata_from_sa;
  output           noteB_s1_reset_n;
  output           system_0_burst_21_downstream_granted_noteB_s1;
  output           system_0_burst_21_downstream_qualified_request_noteB_s1;
  output           system_0_burst_21_downstream_read_data_valid_noteB_s1;
  output           system_0_burst_21_downstream_requests_noteB_s1;
  input            clk;
  input            noteB_s1_readdata;
  input            reset_n;
  input   [  1: 0] system_0_burst_21_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_21_downstream_arbitrationshare;
  input            system_0_burst_21_downstream_burstcount;
  input            system_0_burst_21_downstream_latency_counter;
  input   [  1: 0] system_0_burst_21_downstream_nativeaddress;
  input            system_0_burst_21_downstream_read;
  input            system_0_burst_21_downstream_write;

  reg              d1_noteB_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_noteB_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] noteB_s1_address;
  wire             noteB_s1_allgrants;
  wire             noteB_s1_allow_new_arb_cycle;
  wire             noteB_s1_any_bursting_master_saved_grant;
  wire             noteB_s1_any_continuerequest;
  wire             noteB_s1_arb_counter_enable;
  reg     [  5: 0] noteB_s1_arb_share_counter;
  wire    [  5: 0] noteB_s1_arb_share_counter_next_value;
  wire    [  5: 0] noteB_s1_arb_share_set_values;
  wire             noteB_s1_beginbursttransfer_internal;
  wire             noteB_s1_begins_xfer;
  wire             noteB_s1_end_xfer;
  wire             noteB_s1_firsttransfer;
  wire             noteB_s1_grant_vector;
  wire             noteB_s1_in_a_read_cycle;
  wire             noteB_s1_in_a_write_cycle;
  wire             noteB_s1_master_qreq_vector;
  wire             noteB_s1_non_bursting_master_requests;
  wire             noteB_s1_readdata_from_sa;
  reg              noteB_s1_reg_firsttransfer;
  wire             noteB_s1_reset_n;
  reg              noteB_s1_slavearbiterlockenable;
  wire             noteB_s1_slavearbiterlockenable2;
  wire             noteB_s1_unreg_firsttransfer;
  wire             noteB_s1_waits_for_read;
  wire             noteB_s1_waits_for_write;
  wire             system_0_burst_21_downstream_arbiterlock;
  wire             system_0_burst_21_downstream_arbiterlock2;
  wire             system_0_burst_21_downstream_continuerequest;
  wire             system_0_burst_21_downstream_granted_noteB_s1;
  wire             system_0_burst_21_downstream_qualified_request_noteB_s1;
  wire             system_0_burst_21_downstream_read_data_valid_noteB_s1;
  wire             system_0_burst_21_downstream_requests_noteB_s1;
  wire             system_0_burst_21_downstream_saved_grant_noteB_s1;
  wire             wait_for_noteB_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~noteB_s1_end_xfer;
    end


  assign noteB_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_21_downstream_qualified_request_noteB_s1));
  //assign noteB_s1_readdata_from_sa = noteB_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign noteB_s1_readdata_from_sa = noteB_s1_readdata;

  assign system_0_burst_21_downstream_requests_noteB_s1 = ((1) & (system_0_burst_21_downstream_read | system_0_burst_21_downstream_write)) & system_0_burst_21_downstream_read;
  //noteB_s1_arb_share_counter set values, which is an e_mux
  assign noteB_s1_arb_share_set_values = (system_0_burst_21_downstream_granted_noteB_s1)? system_0_burst_21_downstream_arbitrationshare :
    1;

  //noteB_s1_non_bursting_master_requests mux, which is an e_mux
  assign noteB_s1_non_bursting_master_requests = 0;

  //noteB_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign noteB_s1_any_bursting_master_saved_grant = system_0_burst_21_downstream_saved_grant_noteB_s1;

  //noteB_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign noteB_s1_arb_share_counter_next_value = noteB_s1_firsttransfer ? (noteB_s1_arb_share_set_values - 1) : |noteB_s1_arb_share_counter ? (noteB_s1_arb_share_counter - 1) : 0;

  //noteB_s1_allgrants all slave grants, which is an e_mux
  assign noteB_s1_allgrants = |noteB_s1_grant_vector;

  //noteB_s1_end_xfer assignment, which is an e_assign
  assign noteB_s1_end_xfer = ~(noteB_s1_waits_for_read | noteB_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_noteB_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_noteB_s1 = noteB_s1_end_xfer & (~noteB_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //noteB_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign noteB_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_noteB_s1 & noteB_s1_allgrants) | (end_xfer_arb_share_counter_term_noteB_s1 & ~noteB_s1_non_bursting_master_requests);

  //noteB_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteB_s1_arb_share_counter <= 0;
      else if (noteB_s1_arb_counter_enable)
          noteB_s1_arb_share_counter <= noteB_s1_arb_share_counter_next_value;
    end


  //noteB_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteB_s1_slavearbiterlockenable <= 0;
      else if ((|noteB_s1_master_qreq_vector & end_xfer_arb_share_counter_term_noteB_s1) | (end_xfer_arb_share_counter_term_noteB_s1 & ~noteB_s1_non_bursting_master_requests))
          noteB_s1_slavearbiterlockenable <= |noteB_s1_arb_share_counter_next_value;
    end


  //system_0_burst_21/downstream noteB/s1 arbiterlock, which is an e_assign
  assign system_0_burst_21_downstream_arbiterlock = noteB_s1_slavearbiterlockenable & system_0_burst_21_downstream_continuerequest;

  //noteB_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign noteB_s1_slavearbiterlockenable2 = |noteB_s1_arb_share_counter_next_value;

  //system_0_burst_21/downstream noteB/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_21_downstream_arbiterlock2 = noteB_s1_slavearbiterlockenable2 & system_0_burst_21_downstream_continuerequest;

  //noteB_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign noteB_s1_any_continuerequest = 1;

  //system_0_burst_21_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_21_downstream_continuerequest = 1;

  assign system_0_burst_21_downstream_qualified_request_noteB_s1 = system_0_burst_21_downstream_requests_noteB_s1 & ~((system_0_burst_21_downstream_read & ((system_0_burst_21_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_21_downstream_read_data_valid_noteB_s1, which is an e_mux
  assign system_0_burst_21_downstream_read_data_valid_noteB_s1 = system_0_burst_21_downstream_granted_noteB_s1 & system_0_burst_21_downstream_read & ~noteB_s1_waits_for_read;

  //master is always granted when requested
  assign system_0_burst_21_downstream_granted_noteB_s1 = system_0_burst_21_downstream_qualified_request_noteB_s1;

  //system_0_burst_21/downstream saved-grant noteB/s1, which is an e_assign
  assign system_0_burst_21_downstream_saved_grant_noteB_s1 = system_0_burst_21_downstream_requests_noteB_s1;

  //allow new arb cycle for noteB/s1, which is an e_assign
  assign noteB_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign noteB_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign noteB_s1_master_qreq_vector = 1;

  //noteB_s1_reset_n assignment, which is an e_assign
  assign noteB_s1_reset_n = reset_n;

  //noteB_s1_firsttransfer first transaction, which is an e_assign
  assign noteB_s1_firsttransfer = noteB_s1_begins_xfer ? noteB_s1_unreg_firsttransfer : noteB_s1_reg_firsttransfer;

  //noteB_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign noteB_s1_unreg_firsttransfer = ~(noteB_s1_slavearbiterlockenable & noteB_s1_any_continuerequest);

  //noteB_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteB_s1_reg_firsttransfer <= 1'b1;
      else if (noteB_s1_begins_xfer)
          noteB_s1_reg_firsttransfer <= noteB_s1_unreg_firsttransfer;
    end


  //noteB_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign noteB_s1_beginbursttransfer_internal = noteB_s1_begins_xfer;

  //noteB_s1_address mux, which is an e_mux
  assign noteB_s1_address = system_0_burst_21_downstream_nativeaddress;

  //d1_noteB_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_noteB_s1_end_xfer <= 1;
      else 
        d1_noteB_s1_end_xfer <= noteB_s1_end_xfer;
    end


  //noteB_s1_waits_for_read in a cycle, which is an e_mux
  assign noteB_s1_waits_for_read = noteB_s1_in_a_read_cycle & noteB_s1_begins_xfer;

  //noteB_s1_in_a_read_cycle assignment, which is an e_assign
  assign noteB_s1_in_a_read_cycle = system_0_burst_21_downstream_granted_noteB_s1 & system_0_burst_21_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = noteB_s1_in_a_read_cycle;

  //noteB_s1_waits_for_write in a cycle, which is an e_mux
  assign noteB_s1_waits_for_write = noteB_s1_in_a_write_cycle & 0;

  //noteB_s1_in_a_write_cycle assignment, which is an e_assign
  assign noteB_s1_in_a_write_cycle = system_0_burst_21_downstream_granted_noteB_s1 & system_0_burst_21_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = noteB_s1_in_a_write_cycle;

  assign wait_for_noteB_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //noteB/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_21/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_21_downstream_requests_noteB_s1 && (system_0_burst_21_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_21/downstream drove 0 on its 'arbitrationshare' port while accessing slave noteB/s1", $time);
          $stop;
        end
    end


  //system_0_burst_21/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_21_downstream_requests_noteB_s1 && (system_0_burst_21_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_21/downstream drove 0 on its 'burstcount' port while accessing slave noteB/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module noteC_s1_arbitrator (
                             // inputs:
                              clk,
                              noteC_s1_readdata,
                              reset_n,
                              system_0_burst_22_downstream_address_to_slave,
                              system_0_burst_22_downstream_arbitrationshare,
                              system_0_burst_22_downstream_burstcount,
                              system_0_burst_22_downstream_latency_counter,
                              system_0_burst_22_downstream_nativeaddress,
                              system_0_burst_22_downstream_read,
                              system_0_burst_22_downstream_write,

                             // outputs:
                              d1_noteC_s1_end_xfer,
                              noteC_s1_address,
                              noteC_s1_readdata_from_sa,
                              noteC_s1_reset_n,
                              system_0_burst_22_downstream_granted_noteC_s1,
                              system_0_burst_22_downstream_qualified_request_noteC_s1,
                              system_0_burst_22_downstream_read_data_valid_noteC_s1,
                              system_0_burst_22_downstream_requests_noteC_s1
                           )
;

  output           d1_noteC_s1_end_xfer;
  output  [  1: 0] noteC_s1_address;
  output           noteC_s1_readdata_from_sa;
  output           noteC_s1_reset_n;
  output           system_0_burst_22_downstream_granted_noteC_s1;
  output           system_0_burst_22_downstream_qualified_request_noteC_s1;
  output           system_0_burst_22_downstream_read_data_valid_noteC_s1;
  output           system_0_burst_22_downstream_requests_noteC_s1;
  input            clk;
  input            noteC_s1_readdata;
  input            reset_n;
  input   [  1: 0] system_0_burst_22_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_22_downstream_arbitrationshare;
  input            system_0_burst_22_downstream_burstcount;
  input            system_0_burst_22_downstream_latency_counter;
  input   [  1: 0] system_0_burst_22_downstream_nativeaddress;
  input            system_0_burst_22_downstream_read;
  input            system_0_burst_22_downstream_write;

  reg              d1_noteC_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_noteC_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] noteC_s1_address;
  wire             noteC_s1_allgrants;
  wire             noteC_s1_allow_new_arb_cycle;
  wire             noteC_s1_any_bursting_master_saved_grant;
  wire             noteC_s1_any_continuerequest;
  wire             noteC_s1_arb_counter_enable;
  reg     [  5: 0] noteC_s1_arb_share_counter;
  wire    [  5: 0] noteC_s1_arb_share_counter_next_value;
  wire    [  5: 0] noteC_s1_arb_share_set_values;
  wire             noteC_s1_beginbursttransfer_internal;
  wire             noteC_s1_begins_xfer;
  wire             noteC_s1_end_xfer;
  wire             noteC_s1_firsttransfer;
  wire             noteC_s1_grant_vector;
  wire             noteC_s1_in_a_read_cycle;
  wire             noteC_s1_in_a_write_cycle;
  wire             noteC_s1_master_qreq_vector;
  wire             noteC_s1_non_bursting_master_requests;
  wire             noteC_s1_readdata_from_sa;
  reg              noteC_s1_reg_firsttransfer;
  wire             noteC_s1_reset_n;
  reg              noteC_s1_slavearbiterlockenable;
  wire             noteC_s1_slavearbiterlockenable2;
  wire             noteC_s1_unreg_firsttransfer;
  wire             noteC_s1_waits_for_read;
  wire             noteC_s1_waits_for_write;
  wire             system_0_burst_22_downstream_arbiterlock;
  wire             system_0_burst_22_downstream_arbiterlock2;
  wire             system_0_burst_22_downstream_continuerequest;
  wire             system_0_burst_22_downstream_granted_noteC_s1;
  wire             system_0_burst_22_downstream_qualified_request_noteC_s1;
  wire             system_0_burst_22_downstream_read_data_valid_noteC_s1;
  wire             system_0_burst_22_downstream_requests_noteC_s1;
  wire             system_0_burst_22_downstream_saved_grant_noteC_s1;
  wire             wait_for_noteC_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~noteC_s1_end_xfer;
    end


  assign noteC_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_22_downstream_qualified_request_noteC_s1));
  //assign noteC_s1_readdata_from_sa = noteC_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign noteC_s1_readdata_from_sa = noteC_s1_readdata;

  assign system_0_burst_22_downstream_requests_noteC_s1 = ((1) & (system_0_burst_22_downstream_read | system_0_burst_22_downstream_write)) & system_0_burst_22_downstream_read;
  //noteC_s1_arb_share_counter set values, which is an e_mux
  assign noteC_s1_arb_share_set_values = (system_0_burst_22_downstream_granted_noteC_s1)? system_0_burst_22_downstream_arbitrationshare :
    1;

  //noteC_s1_non_bursting_master_requests mux, which is an e_mux
  assign noteC_s1_non_bursting_master_requests = 0;

  //noteC_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign noteC_s1_any_bursting_master_saved_grant = system_0_burst_22_downstream_saved_grant_noteC_s1;

  //noteC_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign noteC_s1_arb_share_counter_next_value = noteC_s1_firsttransfer ? (noteC_s1_arb_share_set_values - 1) : |noteC_s1_arb_share_counter ? (noteC_s1_arb_share_counter - 1) : 0;

  //noteC_s1_allgrants all slave grants, which is an e_mux
  assign noteC_s1_allgrants = |noteC_s1_grant_vector;

  //noteC_s1_end_xfer assignment, which is an e_assign
  assign noteC_s1_end_xfer = ~(noteC_s1_waits_for_read | noteC_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_noteC_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_noteC_s1 = noteC_s1_end_xfer & (~noteC_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //noteC_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign noteC_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_noteC_s1 & noteC_s1_allgrants) | (end_xfer_arb_share_counter_term_noteC_s1 & ~noteC_s1_non_bursting_master_requests);

  //noteC_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteC_s1_arb_share_counter <= 0;
      else if (noteC_s1_arb_counter_enable)
          noteC_s1_arb_share_counter <= noteC_s1_arb_share_counter_next_value;
    end


  //noteC_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteC_s1_slavearbiterlockenable <= 0;
      else if ((|noteC_s1_master_qreq_vector & end_xfer_arb_share_counter_term_noteC_s1) | (end_xfer_arb_share_counter_term_noteC_s1 & ~noteC_s1_non_bursting_master_requests))
          noteC_s1_slavearbiterlockenable <= |noteC_s1_arb_share_counter_next_value;
    end


  //system_0_burst_22/downstream noteC/s1 arbiterlock, which is an e_assign
  assign system_0_burst_22_downstream_arbiterlock = noteC_s1_slavearbiterlockenable & system_0_burst_22_downstream_continuerequest;

  //noteC_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign noteC_s1_slavearbiterlockenable2 = |noteC_s1_arb_share_counter_next_value;

  //system_0_burst_22/downstream noteC/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_22_downstream_arbiterlock2 = noteC_s1_slavearbiterlockenable2 & system_0_burst_22_downstream_continuerequest;

  //noteC_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign noteC_s1_any_continuerequest = 1;

  //system_0_burst_22_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_22_downstream_continuerequest = 1;

  assign system_0_burst_22_downstream_qualified_request_noteC_s1 = system_0_burst_22_downstream_requests_noteC_s1 & ~((system_0_burst_22_downstream_read & ((system_0_burst_22_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_22_downstream_read_data_valid_noteC_s1, which is an e_mux
  assign system_0_burst_22_downstream_read_data_valid_noteC_s1 = system_0_burst_22_downstream_granted_noteC_s1 & system_0_burst_22_downstream_read & ~noteC_s1_waits_for_read;

  //master is always granted when requested
  assign system_0_burst_22_downstream_granted_noteC_s1 = system_0_burst_22_downstream_qualified_request_noteC_s1;

  //system_0_burst_22/downstream saved-grant noteC/s1, which is an e_assign
  assign system_0_burst_22_downstream_saved_grant_noteC_s1 = system_0_burst_22_downstream_requests_noteC_s1;

  //allow new arb cycle for noteC/s1, which is an e_assign
  assign noteC_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign noteC_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign noteC_s1_master_qreq_vector = 1;

  //noteC_s1_reset_n assignment, which is an e_assign
  assign noteC_s1_reset_n = reset_n;

  //noteC_s1_firsttransfer first transaction, which is an e_assign
  assign noteC_s1_firsttransfer = noteC_s1_begins_xfer ? noteC_s1_unreg_firsttransfer : noteC_s1_reg_firsttransfer;

  //noteC_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign noteC_s1_unreg_firsttransfer = ~(noteC_s1_slavearbiterlockenable & noteC_s1_any_continuerequest);

  //noteC_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteC_s1_reg_firsttransfer <= 1'b1;
      else if (noteC_s1_begins_xfer)
          noteC_s1_reg_firsttransfer <= noteC_s1_unreg_firsttransfer;
    end


  //noteC_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign noteC_s1_beginbursttransfer_internal = noteC_s1_begins_xfer;

  //noteC_s1_address mux, which is an e_mux
  assign noteC_s1_address = system_0_burst_22_downstream_nativeaddress;

  //d1_noteC_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_noteC_s1_end_xfer <= 1;
      else 
        d1_noteC_s1_end_xfer <= noteC_s1_end_xfer;
    end


  //noteC_s1_waits_for_read in a cycle, which is an e_mux
  assign noteC_s1_waits_for_read = noteC_s1_in_a_read_cycle & noteC_s1_begins_xfer;

  //noteC_s1_in_a_read_cycle assignment, which is an e_assign
  assign noteC_s1_in_a_read_cycle = system_0_burst_22_downstream_granted_noteC_s1 & system_0_burst_22_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = noteC_s1_in_a_read_cycle;

  //noteC_s1_waits_for_write in a cycle, which is an e_mux
  assign noteC_s1_waits_for_write = noteC_s1_in_a_write_cycle & 0;

  //noteC_s1_in_a_write_cycle assignment, which is an e_assign
  assign noteC_s1_in_a_write_cycle = system_0_burst_22_downstream_granted_noteC_s1 & system_0_burst_22_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = noteC_s1_in_a_write_cycle;

  assign wait_for_noteC_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //noteC/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_22/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_22_downstream_requests_noteC_s1 && (system_0_burst_22_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_22/downstream drove 0 on its 'arbitrationshare' port while accessing slave noteC/s1", $time);
          $stop;
        end
    end


  //system_0_burst_22/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_22_downstream_requests_noteC_s1 && (system_0_burst_22_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_22/downstream drove 0 on its 'burstcount' port while accessing slave noteC/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module noteD_s1_arbitrator (
                             // inputs:
                              clk,
                              noteD_s1_readdata,
                              reset_n,
                              system_0_burst_23_downstream_address_to_slave,
                              system_0_burst_23_downstream_arbitrationshare,
                              system_0_burst_23_downstream_burstcount,
                              system_0_burst_23_downstream_latency_counter,
                              system_0_burst_23_downstream_nativeaddress,
                              system_0_burst_23_downstream_read,
                              system_0_burst_23_downstream_write,

                             // outputs:
                              d1_noteD_s1_end_xfer,
                              noteD_s1_address,
                              noteD_s1_readdata_from_sa,
                              noteD_s1_reset_n,
                              system_0_burst_23_downstream_granted_noteD_s1,
                              system_0_burst_23_downstream_qualified_request_noteD_s1,
                              system_0_burst_23_downstream_read_data_valid_noteD_s1,
                              system_0_burst_23_downstream_requests_noteD_s1
                           )
;

  output           d1_noteD_s1_end_xfer;
  output  [  1: 0] noteD_s1_address;
  output           noteD_s1_readdata_from_sa;
  output           noteD_s1_reset_n;
  output           system_0_burst_23_downstream_granted_noteD_s1;
  output           system_0_burst_23_downstream_qualified_request_noteD_s1;
  output           system_0_burst_23_downstream_read_data_valid_noteD_s1;
  output           system_0_burst_23_downstream_requests_noteD_s1;
  input            clk;
  input            noteD_s1_readdata;
  input            reset_n;
  input   [  1: 0] system_0_burst_23_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_23_downstream_arbitrationshare;
  input            system_0_burst_23_downstream_burstcount;
  input            system_0_burst_23_downstream_latency_counter;
  input   [  1: 0] system_0_burst_23_downstream_nativeaddress;
  input            system_0_burst_23_downstream_read;
  input            system_0_burst_23_downstream_write;

  reg              d1_noteD_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_noteD_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] noteD_s1_address;
  wire             noteD_s1_allgrants;
  wire             noteD_s1_allow_new_arb_cycle;
  wire             noteD_s1_any_bursting_master_saved_grant;
  wire             noteD_s1_any_continuerequest;
  wire             noteD_s1_arb_counter_enable;
  reg     [  5: 0] noteD_s1_arb_share_counter;
  wire    [  5: 0] noteD_s1_arb_share_counter_next_value;
  wire    [  5: 0] noteD_s1_arb_share_set_values;
  wire             noteD_s1_beginbursttransfer_internal;
  wire             noteD_s1_begins_xfer;
  wire             noteD_s1_end_xfer;
  wire             noteD_s1_firsttransfer;
  wire             noteD_s1_grant_vector;
  wire             noteD_s1_in_a_read_cycle;
  wire             noteD_s1_in_a_write_cycle;
  wire             noteD_s1_master_qreq_vector;
  wire             noteD_s1_non_bursting_master_requests;
  wire             noteD_s1_readdata_from_sa;
  reg              noteD_s1_reg_firsttransfer;
  wire             noteD_s1_reset_n;
  reg              noteD_s1_slavearbiterlockenable;
  wire             noteD_s1_slavearbiterlockenable2;
  wire             noteD_s1_unreg_firsttransfer;
  wire             noteD_s1_waits_for_read;
  wire             noteD_s1_waits_for_write;
  wire             system_0_burst_23_downstream_arbiterlock;
  wire             system_0_burst_23_downstream_arbiterlock2;
  wire             system_0_burst_23_downstream_continuerequest;
  wire             system_0_burst_23_downstream_granted_noteD_s1;
  wire             system_0_burst_23_downstream_qualified_request_noteD_s1;
  wire             system_0_burst_23_downstream_read_data_valid_noteD_s1;
  wire             system_0_burst_23_downstream_requests_noteD_s1;
  wire             system_0_burst_23_downstream_saved_grant_noteD_s1;
  wire             wait_for_noteD_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~noteD_s1_end_xfer;
    end


  assign noteD_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_23_downstream_qualified_request_noteD_s1));
  //assign noteD_s1_readdata_from_sa = noteD_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign noteD_s1_readdata_from_sa = noteD_s1_readdata;

  assign system_0_burst_23_downstream_requests_noteD_s1 = ((1) & (system_0_burst_23_downstream_read | system_0_burst_23_downstream_write)) & system_0_burst_23_downstream_read;
  //noteD_s1_arb_share_counter set values, which is an e_mux
  assign noteD_s1_arb_share_set_values = (system_0_burst_23_downstream_granted_noteD_s1)? system_0_burst_23_downstream_arbitrationshare :
    1;

  //noteD_s1_non_bursting_master_requests mux, which is an e_mux
  assign noteD_s1_non_bursting_master_requests = 0;

  //noteD_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign noteD_s1_any_bursting_master_saved_grant = system_0_burst_23_downstream_saved_grant_noteD_s1;

  //noteD_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign noteD_s1_arb_share_counter_next_value = noteD_s1_firsttransfer ? (noteD_s1_arb_share_set_values - 1) : |noteD_s1_arb_share_counter ? (noteD_s1_arb_share_counter - 1) : 0;

  //noteD_s1_allgrants all slave grants, which is an e_mux
  assign noteD_s1_allgrants = |noteD_s1_grant_vector;

  //noteD_s1_end_xfer assignment, which is an e_assign
  assign noteD_s1_end_xfer = ~(noteD_s1_waits_for_read | noteD_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_noteD_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_noteD_s1 = noteD_s1_end_xfer & (~noteD_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //noteD_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign noteD_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_noteD_s1 & noteD_s1_allgrants) | (end_xfer_arb_share_counter_term_noteD_s1 & ~noteD_s1_non_bursting_master_requests);

  //noteD_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteD_s1_arb_share_counter <= 0;
      else if (noteD_s1_arb_counter_enable)
          noteD_s1_arb_share_counter <= noteD_s1_arb_share_counter_next_value;
    end


  //noteD_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteD_s1_slavearbiterlockenable <= 0;
      else if ((|noteD_s1_master_qreq_vector & end_xfer_arb_share_counter_term_noteD_s1) | (end_xfer_arb_share_counter_term_noteD_s1 & ~noteD_s1_non_bursting_master_requests))
          noteD_s1_slavearbiterlockenable <= |noteD_s1_arb_share_counter_next_value;
    end


  //system_0_burst_23/downstream noteD/s1 arbiterlock, which is an e_assign
  assign system_0_burst_23_downstream_arbiterlock = noteD_s1_slavearbiterlockenable & system_0_burst_23_downstream_continuerequest;

  //noteD_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign noteD_s1_slavearbiterlockenable2 = |noteD_s1_arb_share_counter_next_value;

  //system_0_burst_23/downstream noteD/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_23_downstream_arbiterlock2 = noteD_s1_slavearbiterlockenable2 & system_0_burst_23_downstream_continuerequest;

  //noteD_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign noteD_s1_any_continuerequest = 1;

  //system_0_burst_23_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_23_downstream_continuerequest = 1;

  assign system_0_burst_23_downstream_qualified_request_noteD_s1 = system_0_burst_23_downstream_requests_noteD_s1 & ~((system_0_burst_23_downstream_read & ((system_0_burst_23_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_23_downstream_read_data_valid_noteD_s1, which is an e_mux
  assign system_0_burst_23_downstream_read_data_valid_noteD_s1 = system_0_burst_23_downstream_granted_noteD_s1 & system_0_burst_23_downstream_read & ~noteD_s1_waits_for_read;

  //master is always granted when requested
  assign system_0_burst_23_downstream_granted_noteD_s1 = system_0_burst_23_downstream_qualified_request_noteD_s1;

  //system_0_burst_23/downstream saved-grant noteD/s1, which is an e_assign
  assign system_0_burst_23_downstream_saved_grant_noteD_s1 = system_0_burst_23_downstream_requests_noteD_s1;

  //allow new arb cycle for noteD/s1, which is an e_assign
  assign noteD_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign noteD_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign noteD_s1_master_qreq_vector = 1;

  //noteD_s1_reset_n assignment, which is an e_assign
  assign noteD_s1_reset_n = reset_n;

  //noteD_s1_firsttransfer first transaction, which is an e_assign
  assign noteD_s1_firsttransfer = noteD_s1_begins_xfer ? noteD_s1_unreg_firsttransfer : noteD_s1_reg_firsttransfer;

  //noteD_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign noteD_s1_unreg_firsttransfer = ~(noteD_s1_slavearbiterlockenable & noteD_s1_any_continuerequest);

  //noteD_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteD_s1_reg_firsttransfer <= 1'b1;
      else if (noteD_s1_begins_xfer)
          noteD_s1_reg_firsttransfer <= noteD_s1_unreg_firsttransfer;
    end


  //noteD_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign noteD_s1_beginbursttransfer_internal = noteD_s1_begins_xfer;

  //noteD_s1_address mux, which is an e_mux
  assign noteD_s1_address = system_0_burst_23_downstream_nativeaddress;

  //d1_noteD_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_noteD_s1_end_xfer <= 1;
      else 
        d1_noteD_s1_end_xfer <= noteD_s1_end_xfer;
    end


  //noteD_s1_waits_for_read in a cycle, which is an e_mux
  assign noteD_s1_waits_for_read = noteD_s1_in_a_read_cycle & noteD_s1_begins_xfer;

  //noteD_s1_in_a_read_cycle assignment, which is an e_assign
  assign noteD_s1_in_a_read_cycle = system_0_burst_23_downstream_granted_noteD_s1 & system_0_burst_23_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = noteD_s1_in_a_read_cycle;

  //noteD_s1_waits_for_write in a cycle, which is an e_mux
  assign noteD_s1_waits_for_write = noteD_s1_in_a_write_cycle & 0;

  //noteD_s1_in_a_write_cycle assignment, which is an e_assign
  assign noteD_s1_in_a_write_cycle = system_0_burst_23_downstream_granted_noteD_s1 & system_0_burst_23_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = noteD_s1_in_a_write_cycle;

  assign wait_for_noteD_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //noteD/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_23/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_23_downstream_requests_noteD_s1 && (system_0_burst_23_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_23/downstream drove 0 on its 'arbitrationshare' port while accessing slave noteD/s1", $time);
          $stop;
        end
    end


  //system_0_burst_23/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_23_downstream_requests_noteD_s1 && (system_0_burst_23_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_23/downstream drove 0 on its 'burstcount' port while accessing slave noteD/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module noteE_s1_arbitrator (
                             // inputs:
                              clk,
                              noteE_s1_readdata,
                              reset_n,
                              system_0_burst_24_downstream_address_to_slave,
                              system_0_burst_24_downstream_arbitrationshare,
                              system_0_burst_24_downstream_burstcount,
                              system_0_burst_24_downstream_latency_counter,
                              system_0_burst_24_downstream_nativeaddress,
                              system_0_burst_24_downstream_read,
                              system_0_burst_24_downstream_write,

                             // outputs:
                              d1_noteE_s1_end_xfer,
                              noteE_s1_address,
                              noteE_s1_readdata_from_sa,
                              noteE_s1_reset_n,
                              system_0_burst_24_downstream_granted_noteE_s1,
                              system_0_burst_24_downstream_qualified_request_noteE_s1,
                              system_0_burst_24_downstream_read_data_valid_noteE_s1,
                              system_0_burst_24_downstream_requests_noteE_s1
                           )
;

  output           d1_noteE_s1_end_xfer;
  output  [  1: 0] noteE_s1_address;
  output           noteE_s1_readdata_from_sa;
  output           noteE_s1_reset_n;
  output           system_0_burst_24_downstream_granted_noteE_s1;
  output           system_0_burst_24_downstream_qualified_request_noteE_s1;
  output           system_0_burst_24_downstream_read_data_valid_noteE_s1;
  output           system_0_burst_24_downstream_requests_noteE_s1;
  input            clk;
  input            noteE_s1_readdata;
  input            reset_n;
  input   [  1: 0] system_0_burst_24_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_24_downstream_arbitrationshare;
  input            system_0_burst_24_downstream_burstcount;
  input            system_0_burst_24_downstream_latency_counter;
  input   [  1: 0] system_0_burst_24_downstream_nativeaddress;
  input            system_0_burst_24_downstream_read;
  input            system_0_burst_24_downstream_write;

  reg              d1_noteE_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_noteE_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] noteE_s1_address;
  wire             noteE_s1_allgrants;
  wire             noteE_s1_allow_new_arb_cycle;
  wire             noteE_s1_any_bursting_master_saved_grant;
  wire             noteE_s1_any_continuerequest;
  wire             noteE_s1_arb_counter_enable;
  reg     [  5: 0] noteE_s1_arb_share_counter;
  wire    [  5: 0] noteE_s1_arb_share_counter_next_value;
  wire    [  5: 0] noteE_s1_arb_share_set_values;
  wire             noteE_s1_beginbursttransfer_internal;
  wire             noteE_s1_begins_xfer;
  wire             noteE_s1_end_xfer;
  wire             noteE_s1_firsttransfer;
  wire             noteE_s1_grant_vector;
  wire             noteE_s1_in_a_read_cycle;
  wire             noteE_s1_in_a_write_cycle;
  wire             noteE_s1_master_qreq_vector;
  wire             noteE_s1_non_bursting_master_requests;
  wire             noteE_s1_readdata_from_sa;
  reg              noteE_s1_reg_firsttransfer;
  wire             noteE_s1_reset_n;
  reg              noteE_s1_slavearbiterlockenable;
  wire             noteE_s1_slavearbiterlockenable2;
  wire             noteE_s1_unreg_firsttransfer;
  wire             noteE_s1_waits_for_read;
  wire             noteE_s1_waits_for_write;
  wire             system_0_burst_24_downstream_arbiterlock;
  wire             system_0_burst_24_downstream_arbiterlock2;
  wire             system_0_burst_24_downstream_continuerequest;
  wire             system_0_burst_24_downstream_granted_noteE_s1;
  wire             system_0_burst_24_downstream_qualified_request_noteE_s1;
  wire             system_0_burst_24_downstream_read_data_valid_noteE_s1;
  wire             system_0_burst_24_downstream_requests_noteE_s1;
  wire             system_0_burst_24_downstream_saved_grant_noteE_s1;
  wire             wait_for_noteE_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~noteE_s1_end_xfer;
    end


  assign noteE_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_24_downstream_qualified_request_noteE_s1));
  //assign noteE_s1_readdata_from_sa = noteE_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign noteE_s1_readdata_from_sa = noteE_s1_readdata;

  assign system_0_burst_24_downstream_requests_noteE_s1 = ((1) & (system_0_burst_24_downstream_read | system_0_burst_24_downstream_write)) & system_0_burst_24_downstream_read;
  //noteE_s1_arb_share_counter set values, which is an e_mux
  assign noteE_s1_arb_share_set_values = (system_0_burst_24_downstream_granted_noteE_s1)? system_0_burst_24_downstream_arbitrationshare :
    1;

  //noteE_s1_non_bursting_master_requests mux, which is an e_mux
  assign noteE_s1_non_bursting_master_requests = 0;

  //noteE_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign noteE_s1_any_bursting_master_saved_grant = system_0_burst_24_downstream_saved_grant_noteE_s1;

  //noteE_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign noteE_s1_arb_share_counter_next_value = noteE_s1_firsttransfer ? (noteE_s1_arb_share_set_values - 1) : |noteE_s1_arb_share_counter ? (noteE_s1_arb_share_counter - 1) : 0;

  //noteE_s1_allgrants all slave grants, which is an e_mux
  assign noteE_s1_allgrants = |noteE_s1_grant_vector;

  //noteE_s1_end_xfer assignment, which is an e_assign
  assign noteE_s1_end_xfer = ~(noteE_s1_waits_for_read | noteE_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_noteE_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_noteE_s1 = noteE_s1_end_xfer & (~noteE_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //noteE_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign noteE_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_noteE_s1 & noteE_s1_allgrants) | (end_xfer_arb_share_counter_term_noteE_s1 & ~noteE_s1_non_bursting_master_requests);

  //noteE_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteE_s1_arb_share_counter <= 0;
      else if (noteE_s1_arb_counter_enable)
          noteE_s1_arb_share_counter <= noteE_s1_arb_share_counter_next_value;
    end


  //noteE_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteE_s1_slavearbiterlockenable <= 0;
      else if ((|noteE_s1_master_qreq_vector & end_xfer_arb_share_counter_term_noteE_s1) | (end_xfer_arb_share_counter_term_noteE_s1 & ~noteE_s1_non_bursting_master_requests))
          noteE_s1_slavearbiterlockenable <= |noteE_s1_arb_share_counter_next_value;
    end


  //system_0_burst_24/downstream noteE/s1 arbiterlock, which is an e_assign
  assign system_0_burst_24_downstream_arbiterlock = noteE_s1_slavearbiterlockenable & system_0_burst_24_downstream_continuerequest;

  //noteE_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign noteE_s1_slavearbiterlockenable2 = |noteE_s1_arb_share_counter_next_value;

  //system_0_burst_24/downstream noteE/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_24_downstream_arbiterlock2 = noteE_s1_slavearbiterlockenable2 & system_0_burst_24_downstream_continuerequest;

  //noteE_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign noteE_s1_any_continuerequest = 1;

  //system_0_burst_24_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_24_downstream_continuerequest = 1;

  assign system_0_burst_24_downstream_qualified_request_noteE_s1 = system_0_burst_24_downstream_requests_noteE_s1 & ~((system_0_burst_24_downstream_read & ((system_0_burst_24_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_24_downstream_read_data_valid_noteE_s1, which is an e_mux
  assign system_0_burst_24_downstream_read_data_valid_noteE_s1 = system_0_burst_24_downstream_granted_noteE_s1 & system_0_burst_24_downstream_read & ~noteE_s1_waits_for_read;

  //master is always granted when requested
  assign system_0_burst_24_downstream_granted_noteE_s1 = system_0_burst_24_downstream_qualified_request_noteE_s1;

  //system_0_burst_24/downstream saved-grant noteE/s1, which is an e_assign
  assign system_0_burst_24_downstream_saved_grant_noteE_s1 = system_0_burst_24_downstream_requests_noteE_s1;

  //allow new arb cycle for noteE/s1, which is an e_assign
  assign noteE_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign noteE_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign noteE_s1_master_qreq_vector = 1;

  //noteE_s1_reset_n assignment, which is an e_assign
  assign noteE_s1_reset_n = reset_n;

  //noteE_s1_firsttransfer first transaction, which is an e_assign
  assign noteE_s1_firsttransfer = noteE_s1_begins_xfer ? noteE_s1_unreg_firsttransfer : noteE_s1_reg_firsttransfer;

  //noteE_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign noteE_s1_unreg_firsttransfer = ~(noteE_s1_slavearbiterlockenable & noteE_s1_any_continuerequest);

  //noteE_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteE_s1_reg_firsttransfer <= 1'b1;
      else if (noteE_s1_begins_xfer)
          noteE_s1_reg_firsttransfer <= noteE_s1_unreg_firsttransfer;
    end


  //noteE_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign noteE_s1_beginbursttransfer_internal = noteE_s1_begins_xfer;

  //noteE_s1_address mux, which is an e_mux
  assign noteE_s1_address = system_0_burst_24_downstream_nativeaddress;

  //d1_noteE_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_noteE_s1_end_xfer <= 1;
      else 
        d1_noteE_s1_end_xfer <= noteE_s1_end_xfer;
    end


  //noteE_s1_waits_for_read in a cycle, which is an e_mux
  assign noteE_s1_waits_for_read = noteE_s1_in_a_read_cycle & noteE_s1_begins_xfer;

  //noteE_s1_in_a_read_cycle assignment, which is an e_assign
  assign noteE_s1_in_a_read_cycle = system_0_burst_24_downstream_granted_noteE_s1 & system_0_burst_24_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = noteE_s1_in_a_read_cycle;

  //noteE_s1_waits_for_write in a cycle, which is an e_mux
  assign noteE_s1_waits_for_write = noteE_s1_in_a_write_cycle & 0;

  //noteE_s1_in_a_write_cycle assignment, which is an e_assign
  assign noteE_s1_in_a_write_cycle = system_0_burst_24_downstream_granted_noteE_s1 & system_0_burst_24_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = noteE_s1_in_a_write_cycle;

  assign wait_for_noteE_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //noteE/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_24/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_24_downstream_requests_noteE_s1 && (system_0_burst_24_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_24/downstream drove 0 on its 'arbitrationshare' port while accessing slave noteE/s1", $time);
          $stop;
        end
    end


  //system_0_burst_24/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_24_downstream_requests_noteE_s1 && (system_0_burst_24_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_24/downstream drove 0 on its 'burstcount' port while accessing slave noteE/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module noteF_s1_arbitrator (
                             // inputs:
                              clk,
                              noteF_s1_readdata,
                              reset_n,
                              system_0_burst_25_downstream_address_to_slave,
                              system_0_burst_25_downstream_arbitrationshare,
                              system_0_burst_25_downstream_burstcount,
                              system_0_burst_25_downstream_latency_counter,
                              system_0_burst_25_downstream_nativeaddress,
                              system_0_burst_25_downstream_read,
                              system_0_burst_25_downstream_write,

                             // outputs:
                              d1_noteF_s1_end_xfer,
                              noteF_s1_address,
                              noteF_s1_readdata_from_sa,
                              noteF_s1_reset_n,
                              system_0_burst_25_downstream_granted_noteF_s1,
                              system_0_burst_25_downstream_qualified_request_noteF_s1,
                              system_0_burst_25_downstream_read_data_valid_noteF_s1,
                              system_0_burst_25_downstream_requests_noteF_s1
                           )
;

  output           d1_noteF_s1_end_xfer;
  output  [  1: 0] noteF_s1_address;
  output           noteF_s1_readdata_from_sa;
  output           noteF_s1_reset_n;
  output           system_0_burst_25_downstream_granted_noteF_s1;
  output           system_0_burst_25_downstream_qualified_request_noteF_s1;
  output           system_0_burst_25_downstream_read_data_valid_noteF_s1;
  output           system_0_burst_25_downstream_requests_noteF_s1;
  input            clk;
  input            noteF_s1_readdata;
  input            reset_n;
  input   [  1: 0] system_0_burst_25_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_25_downstream_arbitrationshare;
  input            system_0_burst_25_downstream_burstcount;
  input            system_0_burst_25_downstream_latency_counter;
  input   [  1: 0] system_0_burst_25_downstream_nativeaddress;
  input            system_0_burst_25_downstream_read;
  input            system_0_burst_25_downstream_write;

  reg              d1_noteF_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_noteF_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] noteF_s1_address;
  wire             noteF_s1_allgrants;
  wire             noteF_s1_allow_new_arb_cycle;
  wire             noteF_s1_any_bursting_master_saved_grant;
  wire             noteF_s1_any_continuerequest;
  wire             noteF_s1_arb_counter_enable;
  reg     [  5: 0] noteF_s1_arb_share_counter;
  wire    [  5: 0] noteF_s1_arb_share_counter_next_value;
  wire    [  5: 0] noteF_s1_arb_share_set_values;
  wire             noteF_s1_beginbursttransfer_internal;
  wire             noteF_s1_begins_xfer;
  wire             noteF_s1_end_xfer;
  wire             noteF_s1_firsttransfer;
  wire             noteF_s1_grant_vector;
  wire             noteF_s1_in_a_read_cycle;
  wire             noteF_s1_in_a_write_cycle;
  wire             noteF_s1_master_qreq_vector;
  wire             noteF_s1_non_bursting_master_requests;
  wire             noteF_s1_readdata_from_sa;
  reg              noteF_s1_reg_firsttransfer;
  wire             noteF_s1_reset_n;
  reg              noteF_s1_slavearbiterlockenable;
  wire             noteF_s1_slavearbiterlockenable2;
  wire             noteF_s1_unreg_firsttransfer;
  wire             noteF_s1_waits_for_read;
  wire             noteF_s1_waits_for_write;
  wire             system_0_burst_25_downstream_arbiterlock;
  wire             system_0_burst_25_downstream_arbiterlock2;
  wire             system_0_burst_25_downstream_continuerequest;
  wire             system_0_burst_25_downstream_granted_noteF_s1;
  wire             system_0_burst_25_downstream_qualified_request_noteF_s1;
  wire             system_0_burst_25_downstream_read_data_valid_noteF_s1;
  wire             system_0_burst_25_downstream_requests_noteF_s1;
  wire             system_0_burst_25_downstream_saved_grant_noteF_s1;
  wire             wait_for_noteF_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~noteF_s1_end_xfer;
    end


  assign noteF_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_25_downstream_qualified_request_noteF_s1));
  //assign noteF_s1_readdata_from_sa = noteF_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign noteF_s1_readdata_from_sa = noteF_s1_readdata;

  assign system_0_burst_25_downstream_requests_noteF_s1 = ((1) & (system_0_burst_25_downstream_read | system_0_burst_25_downstream_write)) & system_0_burst_25_downstream_read;
  //noteF_s1_arb_share_counter set values, which is an e_mux
  assign noteF_s1_arb_share_set_values = (system_0_burst_25_downstream_granted_noteF_s1)? system_0_burst_25_downstream_arbitrationshare :
    1;

  //noteF_s1_non_bursting_master_requests mux, which is an e_mux
  assign noteF_s1_non_bursting_master_requests = 0;

  //noteF_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign noteF_s1_any_bursting_master_saved_grant = system_0_burst_25_downstream_saved_grant_noteF_s1;

  //noteF_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign noteF_s1_arb_share_counter_next_value = noteF_s1_firsttransfer ? (noteF_s1_arb_share_set_values - 1) : |noteF_s1_arb_share_counter ? (noteF_s1_arb_share_counter - 1) : 0;

  //noteF_s1_allgrants all slave grants, which is an e_mux
  assign noteF_s1_allgrants = |noteF_s1_grant_vector;

  //noteF_s1_end_xfer assignment, which is an e_assign
  assign noteF_s1_end_xfer = ~(noteF_s1_waits_for_read | noteF_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_noteF_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_noteF_s1 = noteF_s1_end_xfer & (~noteF_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //noteF_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign noteF_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_noteF_s1 & noteF_s1_allgrants) | (end_xfer_arb_share_counter_term_noteF_s1 & ~noteF_s1_non_bursting_master_requests);

  //noteF_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteF_s1_arb_share_counter <= 0;
      else if (noteF_s1_arb_counter_enable)
          noteF_s1_arb_share_counter <= noteF_s1_arb_share_counter_next_value;
    end


  //noteF_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteF_s1_slavearbiterlockenable <= 0;
      else if ((|noteF_s1_master_qreq_vector & end_xfer_arb_share_counter_term_noteF_s1) | (end_xfer_arb_share_counter_term_noteF_s1 & ~noteF_s1_non_bursting_master_requests))
          noteF_s1_slavearbiterlockenable <= |noteF_s1_arb_share_counter_next_value;
    end


  //system_0_burst_25/downstream noteF/s1 arbiterlock, which is an e_assign
  assign system_0_burst_25_downstream_arbiterlock = noteF_s1_slavearbiterlockenable & system_0_burst_25_downstream_continuerequest;

  //noteF_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign noteF_s1_slavearbiterlockenable2 = |noteF_s1_arb_share_counter_next_value;

  //system_0_burst_25/downstream noteF/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_25_downstream_arbiterlock2 = noteF_s1_slavearbiterlockenable2 & system_0_burst_25_downstream_continuerequest;

  //noteF_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign noteF_s1_any_continuerequest = 1;

  //system_0_burst_25_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_25_downstream_continuerequest = 1;

  assign system_0_burst_25_downstream_qualified_request_noteF_s1 = system_0_burst_25_downstream_requests_noteF_s1 & ~((system_0_burst_25_downstream_read & ((system_0_burst_25_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_25_downstream_read_data_valid_noteF_s1, which is an e_mux
  assign system_0_burst_25_downstream_read_data_valid_noteF_s1 = system_0_burst_25_downstream_granted_noteF_s1 & system_0_burst_25_downstream_read & ~noteF_s1_waits_for_read;

  //master is always granted when requested
  assign system_0_burst_25_downstream_granted_noteF_s1 = system_0_burst_25_downstream_qualified_request_noteF_s1;

  //system_0_burst_25/downstream saved-grant noteF/s1, which is an e_assign
  assign system_0_burst_25_downstream_saved_grant_noteF_s1 = system_0_burst_25_downstream_requests_noteF_s1;

  //allow new arb cycle for noteF/s1, which is an e_assign
  assign noteF_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign noteF_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign noteF_s1_master_qreq_vector = 1;

  //noteF_s1_reset_n assignment, which is an e_assign
  assign noteF_s1_reset_n = reset_n;

  //noteF_s1_firsttransfer first transaction, which is an e_assign
  assign noteF_s1_firsttransfer = noteF_s1_begins_xfer ? noteF_s1_unreg_firsttransfer : noteF_s1_reg_firsttransfer;

  //noteF_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign noteF_s1_unreg_firsttransfer = ~(noteF_s1_slavearbiterlockenable & noteF_s1_any_continuerequest);

  //noteF_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteF_s1_reg_firsttransfer <= 1'b1;
      else if (noteF_s1_begins_xfer)
          noteF_s1_reg_firsttransfer <= noteF_s1_unreg_firsttransfer;
    end


  //noteF_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign noteF_s1_beginbursttransfer_internal = noteF_s1_begins_xfer;

  //noteF_s1_address mux, which is an e_mux
  assign noteF_s1_address = system_0_burst_25_downstream_nativeaddress;

  //d1_noteF_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_noteF_s1_end_xfer <= 1;
      else 
        d1_noteF_s1_end_xfer <= noteF_s1_end_xfer;
    end


  //noteF_s1_waits_for_read in a cycle, which is an e_mux
  assign noteF_s1_waits_for_read = noteF_s1_in_a_read_cycle & noteF_s1_begins_xfer;

  //noteF_s1_in_a_read_cycle assignment, which is an e_assign
  assign noteF_s1_in_a_read_cycle = system_0_burst_25_downstream_granted_noteF_s1 & system_0_burst_25_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = noteF_s1_in_a_read_cycle;

  //noteF_s1_waits_for_write in a cycle, which is an e_mux
  assign noteF_s1_waits_for_write = noteF_s1_in_a_write_cycle & 0;

  //noteF_s1_in_a_write_cycle assignment, which is an e_assign
  assign noteF_s1_in_a_write_cycle = system_0_burst_25_downstream_granted_noteF_s1 & system_0_burst_25_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = noteF_s1_in_a_write_cycle;

  assign wait_for_noteF_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //noteF/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_25/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_25_downstream_requests_noteF_s1 && (system_0_burst_25_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_25/downstream drove 0 on its 'arbitrationshare' port while accessing slave noteF/s1", $time);
          $stop;
        end
    end


  //system_0_burst_25/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_25_downstream_requests_noteF_s1 && (system_0_burst_25_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_25/downstream drove 0 on its 'burstcount' port while accessing slave noteF/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module noteG_s1_arbitrator (
                             // inputs:
                              clk,
                              noteG_s1_readdata,
                              reset_n,
                              system_0_burst_26_downstream_address_to_slave,
                              system_0_burst_26_downstream_arbitrationshare,
                              system_0_burst_26_downstream_burstcount,
                              system_0_burst_26_downstream_latency_counter,
                              system_0_burst_26_downstream_nativeaddress,
                              system_0_burst_26_downstream_read,
                              system_0_burst_26_downstream_write,

                             // outputs:
                              d1_noteG_s1_end_xfer,
                              noteG_s1_address,
                              noteG_s1_readdata_from_sa,
                              noteG_s1_reset_n,
                              system_0_burst_26_downstream_granted_noteG_s1,
                              system_0_burst_26_downstream_qualified_request_noteG_s1,
                              system_0_burst_26_downstream_read_data_valid_noteG_s1,
                              system_0_burst_26_downstream_requests_noteG_s1
                           )
;

  output           d1_noteG_s1_end_xfer;
  output  [  1: 0] noteG_s1_address;
  output           noteG_s1_readdata_from_sa;
  output           noteG_s1_reset_n;
  output           system_0_burst_26_downstream_granted_noteG_s1;
  output           system_0_burst_26_downstream_qualified_request_noteG_s1;
  output           system_0_burst_26_downstream_read_data_valid_noteG_s1;
  output           system_0_burst_26_downstream_requests_noteG_s1;
  input            clk;
  input            noteG_s1_readdata;
  input            reset_n;
  input   [  1: 0] system_0_burst_26_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_26_downstream_arbitrationshare;
  input            system_0_burst_26_downstream_burstcount;
  input            system_0_burst_26_downstream_latency_counter;
  input   [  1: 0] system_0_burst_26_downstream_nativeaddress;
  input            system_0_burst_26_downstream_read;
  input            system_0_burst_26_downstream_write;

  reg              d1_noteG_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_noteG_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] noteG_s1_address;
  wire             noteG_s1_allgrants;
  wire             noteG_s1_allow_new_arb_cycle;
  wire             noteG_s1_any_bursting_master_saved_grant;
  wire             noteG_s1_any_continuerequest;
  wire             noteG_s1_arb_counter_enable;
  reg     [  5: 0] noteG_s1_arb_share_counter;
  wire    [  5: 0] noteG_s1_arb_share_counter_next_value;
  wire    [  5: 0] noteG_s1_arb_share_set_values;
  wire             noteG_s1_beginbursttransfer_internal;
  wire             noteG_s1_begins_xfer;
  wire             noteG_s1_end_xfer;
  wire             noteG_s1_firsttransfer;
  wire             noteG_s1_grant_vector;
  wire             noteG_s1_in_a_read_cycle;
  wire             noteG_s1_in_a_write_cycle;
  wire             noteG_s1_master_qreq_vector;
  wire             noteG_s1_non_bursting_master_requests;
  wire             noteG_s1_readdata_from_sa;
  reg              noteG_s1_reg_firsttransfer;
  wire             noteG_s1_reset_n;
  reg              noteG_s1_slavearbiterlockenable;
  wire             noteG_s1_slavearbiterlockenable2;
  wire             noteG_s1_unreg_firsttransfer;
  wire             noteG_s1_waits_for_read;
  wire             noteG_s1_waits_for_write;
  wire             system_0_burst_26_downstream_arbiterlock;
  wire             system_0_burst_26_downstream_arbiterlock2;
  wire             system_0_burst_26_downstream_continuerequest;
  wire             system_0_burst_26_downstream_granted_noteG_s1;
  wire             system_0_burst_26_downstream_qualified_request_noteG_s1;
  wire             system_0_burst_26_downstream_read_data_valid_noteG_s1;
  wire             system_0_burst_26_downstream_requests_noteG_s1;
  wire             system_0_burst_26_downstream_saved_grant_noteG_s1;
  wire             wait_for_noteG_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~noteG_s1_end_xfer;
    end


  assign noteG_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_26_downstream_qualified_request_noteG_s1));
  //assign noteG_s1_readdata_from_sa = noteG_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign noteG_s1_readdata_from_sa = noteG_s1_readdata;

  assign system_0_burst_26_downstream_requests_noteG_s1 = ((1) & (system_0_burst_26_downstream_read | system_0_burst_26_downstream_write)) & system_0_burst_26_downstream_read;
  //noteG_s1_arb_share_counter set values, which is an e_mux
  assign noteG_s1_arb_share_set_values = (system_0_burst_26_downstream_granted_noteG_s1)? system_0_burst_26_downstream_arbitrationshare :
    1;

  //noteG_s1_non_bursting_master_requests mux, which is an e_mux
  assign noteG_s1_non_bursting_master_requests = 0;

  //noteG_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign noteG_s1_any_bursting_master_saved_grant = system_0_burst_26_downstream_saved_grant_noteG_s1;

  //noteG_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign noteG_s1_arb_share_counter_next_value = noteG_s1_firsttransfer ? (noteG_s1_arb_share_set_values - 1) : |noteG_s1_arb_share_counter ? (noteG_s1_arb_share_counter - 1) : 0;

  //noteG_s1_allgrants all slave grants, which is an e_mux
  assign noteG_s1_allgrants = |noteG_s1_grant_vector;

  //noteG_s1_end_xfer assignment, which is an e_assign
  assign noteG_s1_end_xfer = ~(noteG_s1_waits_for_read | noteG_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_noteG_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_noteG_s1 = noteG_s1_end_xfer & (~noteG_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //noteG_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign noteG_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_noteG_s1 & noteG_s1_allgrants) | (end_xfer_arb_share_counter_term_noteG_s1 & ~noteG_s1_non_bursting_master_requests);

  //noteG_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteG_s1_arb_share_counter <= 0;
      else if (noteG_s1_arb_counter_enable)
          noteG_s1_arb_share_counter <= noteG_s1_arb_share_counter_next_value;
    end


  //noteG_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteG_s1_slavearbiterlockenable <= 0;
      else if ((|noteG_s1_master_qreq_vector & end_xfer_arb_share_counter_term_noteG_s1) | (end_xfer_arb_share_counter_term_noteG_s1 & ~noteG_s1_non_bursting_master_requests))
          noteG_s1_slavearbiterlockenable <= |noteG_s1_arb_share_counter_next_value;
    end


  //system_0_burst_26/downstream noteG/s1 arbiterlock, which is an e_assign
  assign system_0_burst_26_downstream_arbiterlock = noteG_s1_slavearbiterlockenable & system_0_burst_26_downstream_continuerequest;

  //noteG_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign noteG_s1_slavearbiterlockenable2 = |noteG_s1_arb_share_counter_next_value;

  //system_0_burst_26/downstream noteG/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_26_downstream_arbiterlock2 = noteG_s1_slavearbiterlockenable2 & system_0_burst_26_downstream_continuerequest;

  //noteG_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign noteG_s1_any_continuerequest = 1;

  //system_0_burst_26_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_26_downstream_continuerequest = 1;

  assign system_0_burst_26_downstream_qualified_request_noteG_s1 = system_0_burst_26_downstream_requests_noteG_s1 & ~((system_0_burst_26_downstream_read & ((system_0_burst_26_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_26_downstream_read_data_valid_noteG_s1, which is an e_mux
  assign system_0_burst_26_downstream_read_data_valid_noteG_s1 = system_0_burst_26_downstream_granted_noteG_s1 & system_0_burst_26_downstream_read & ~noteG_s1_waits_for_read;

  //master is always granted when requested
  assign system_0_burst_26_downstream_granted_noteG_s1 = system_0_burst_26_downstream_qualified_request_noteG_s1;

  //system_0_burst_26/downstream saved-grant noteG/s1, which is an e_assign
  assign system_0_burst_26_downstream_saved_grant_noteG_s1 = system_0_burst_26_downstream_requests_noteG_s1;

  //allow new arb cycle for noteG/s1, which is an e_assign
  assign noteG_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign noteG_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign noteG_s1_master_qreq_vector = 1;

  //noteG_s1_reset_n assignment, which is an e_assign
  assign noteG_s1_reset_n = reset_n;

  //noteG_s1_firsttransfer first transaction, which is an e_assign
  assign noteG_s1_firsttransfer = noteG_s1_begins_xfer ? noteG_s1_unreg_firsttransfer : noteG_s1_reg_firsttransfer;

  //noteG_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign noteG_s1_unreg_firsttransfer = ~(noteG_s1_slavearbiterlockenable & noteG_s1_any_continuerequest);

  //noteG_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          noteG_s1_reg_firsttransfer <= 1'b1;
      else if (noteG_s1_begins_xfer)
          noteG_s1_reg_firsttransfer <= noteG_s1_unreg_firsttransfer;
    end


  //noteG_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign noteG_s1_beginbursttransfer_internal = noteG_s1_begins_xfer;

  //noteG_s1_address mux, which is an e_mux
  assign noteG_s1_address = system_0_burst_26_downstream_nativeaddress;

  //d1_noteG_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_noteG_s1_end_xfer <= 1;
      else 
        d1_noteG_s1_end_xfer <= noteG_s1_end_xfer;
    end


  //noteG_s1_waits_for_read in a cycle, which is an e_mux
  assign noteG_s1_waits_for_read = noteG_s1_in_a_read_cycle & noteG_s1_begins_xfer;

  //noteG_s1_in_a_read_cycle assignment, which is an e_assign
  assign noteG_s1_in_a_read_cycle = system_0_burst_26_downstream_granted_noteG_s1 & system_0_burst_26_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = noteG_s1_in_a_read_cycle;

  //noteG_s1_waits_for_write in a cycle, which is an e_mux
  assign noteG_s1_waits_for_write = noteG_s1_in_a_write_cycle & 0;

  //noteG_s1_in_a_write_cycle assignment, which is an e_assign
  assign noteG_s1_in_a_write_cycle = system_0_burst_26_downstream_granted_noteG_s1 & system_0_burst_26_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = noteG_s1_in_a_write_cycle;

  assign wait_for_noteG_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //noteG/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_26/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_26_downstream_requests_noteG_s1 && (system_0_burst_26_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_26/downstream drove 0 on its 'arbitrationshare' port while accessing slave noteG/s1", $time);
          $stop;
        end
    end


  //system_0_burst_26/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_26_downstream_requests_noteG_s1 && (system_0_burst_26_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_26/downstream drove 0 on its 'burstcount' port while accessing slave noteG/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_system_0_burst_4_downstream_to_sdram_0_s1_module (
                                                                       // inputs:
                                                                        clear_fifo,
                                                                        clk,
                                                                        data_in,
                                                                        read,
                                                                        reset_n,
                                                                        sync_reset,
                                                                        write,

                                                                       // outputs:
                                                                        data_out,
                                                                        empty,
                                                                        fifo_contains_ones_n,
                                                                        full
                                                                     )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  reg              full_2;
  reg              full_3;
  reg              full_4;
  reg              full_5;
  reg              full_6;
  wire             full_7;
  reg     [  3: 0] how_many_ones;
  wire    [  3: 0] one_count_minus_one;
  wire    [  3: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  wire             p2_full_2;
  wire             p2_stage_2;
  wire             p3_full_3;
  wire             p3_stage_3;
  wire             p4_full_4;
  wire             p4_stage_4;
  wire             p5_full_5;
  wire             p5_stage_5;
  wire             p6_full_6;
  wire             p6_stage_6;
  reg              stage_0;
  reg              stage_1;
  reg              stage_2;
  reg              stage_3;
  reg              stage_4;
  reg              stage_5;
  reg              stage_6;
  wire    [  3: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_6;
  assign empty = !full_0;
  assign full_7 = 0;
  //data_6, which is an e_mux
  assign p6_stage_6 = ((full_7 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_6 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_6))
          if (sync_reset & full_6 & !((full_7 == 0) & read & write))
              stage_6 <= 0;
          else 
            stage_6 <= p6_stage_6;
    end


  //control_6, which is an e_mux
  assign p6_full_6 = ((read & !write) == 0)? full_5 :
    0;

  //control_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_6 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_6 <= 0;
          else 
            full_6 <= p6_full_6;
    end


  //data_5, which is an e_mux
  assign p5_stage_5 = ((full_6 & ~clear_fifo) == 0)? data_in :
    stage_6;

  //data_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_5 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_5))
          if (sync_reset & full_5 & !((full_6 == 0) & read & write))
              stage_5 <= 0;
          else 
            stage_5 <= p5_stage_5;
    end


  //control_5, which is an e_mux
  assign p5_full_5 = ((read & !write) == 0)? full_4 :
    full_6;

  //control_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_5 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_5 <= 0;
          else 
            full_5 <= p5_full_5;
    end


  //data_4, which is an e_mux
  assign p4_stage_4 = ((full_5 & ~clear_fifo) == 0)? data_in :
    stage_5;

  //data_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_4 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_4))
          if (sync_reset & full_4 & !((full_5 == 0) & read & write))
              stage_4 <= 0;
          else 
            stage_4 <= p4_stage_4;
    end


  //control_4, which is an e_mux
  assign p4_full_4 = ((read & !write) == 0)? full_3 :
    full_5;

  //control_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_4 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_4 <= 0;
          else 
            full_4 <= p4_full_4;
    end


  //data_3, which is an e_mux
  assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
    stage_4;

  //data_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_3 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_3))
          if (sync_reset & full_3 & !((full_4 == 0) & read & write))
              stage_3 <= 0;
          else 
            stage_3 <= p3_stage_3;
    end


  //control_3, which is an e_mux
  assign p3_full_3 = ((read & !write) == 0)? full_2 :
    full_4;

  //control_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_system_0_burst_5_downstream_to_sdram_0_s1_module (
                                                                       // inputs:
                                                                        clear_fifo,
                                                                        clk,
                                                                        data_in,
                                                                        read,
                                                                        reset_n,
                                                                        sync_reset,
                                                                        write,

                                                                       // outputs:
                                                                        data_out,
                                                                        empty,
                                                                        fifo_contains_ones_n,
                                                                        full
                                                                     )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  reg              full_2;
  reg              full_3;
  reg              full_4;
  reg              full_5;
  reg              full_6;
  wire             full_7;
  reg     [  3: 0] how_many_ones;
  wire    [  3: 0] one_count_minus_one;
  wire    [  3: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  wire             p2_full_2;
  wire             p2_stage_2;
  wire             p3_full_3;
  wire             p3_stage_3;
  wire             p4_full_4;
  wire             p4_stage_4;
  wire             p5_full_5;
  wire             p5_stage_5;
  wire             p6_full_6;
  wire             p6_stage_6;
  reg              stage_0;
  reg              stage_1;
  reg              stage_2;
  reg              stage_3;
  reg              stage_4;
  reg              stage_5;
  reg              stage_6;
  wire    [  3: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_6;
  assign empty = !full_0;
  assign full_7 = 0;
  //data_6, which is an e_mux
  assign p6_stage_6 = ((full_7 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_6 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_6))
          if (sync_reset & full_6 & !((full_7 == 0) & read & write))
              stage_6 <= 0;
          else 
            stage_6 <= p6_stage_6;
    end


  //control_6, which is an e_mux
  assign p6_full_6 = ((read & !write) == 0)? full_5 :
    0;

  //control_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_6 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_6 <= 0;
          else 
            full_6 <= p6_full_6;
    end


  //data_5, which is an e_mux
  assign p5_stage_5 = ((full_6 & ~clear_fifo) == 0)? data_in :
    stage_6;

  //data_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_5 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_5))
          if (sync_reset & full_5 & !((full_6 == 0) & read & write))
              stage_5 <= 0;
          else 
            stage_5 <= p5_stage_5;
    end


  //control_5, which is an e_mux
  assign p5_full_5 = ((read & !write) == 0)? full_4 :
    full_6;

  //control_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_5 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_5 <= 0;
          else 
            full_5 <= p5_full_5;
    end


  //data_4, which is an e_mux
  assign p4_stage_4 = ((full_5 & ~clear_fifo) == 0)? data_in :
    stage_5;

  //data_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_4 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_4))
          if (sync_reset & full_4 & !((full_5 == 0) & read & write))
              stage_4 <= 0;
          else 
            stage_4 <= p4_stage_4;
    end


  //control_4, which is an e_mux
  assign p4_full_4 = ((read & !write) == 0)? full_3 :
    full_5;

  //control_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_4 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_4 <= 0;
          else 
            full_4 <= p4_full_4;
    end


  //data_3, which is an e_mux
  assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
    stage_4;

  //data_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_3 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_3))
          if (sync_reset & full_3 & !((full_4 == 0) & read & write))
              stage_3 <= 0;
          else 
            stage_3 <= p3_stage_3;
    end


  //control_3, which is an e_mux
  assign p3_full_3 = ((read & !write) == 0)? full_2 :
    full_4;

  //control_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module sdram_0_s1_arbitrator (
                               // inputs:
                                clk,
                                reset_n,
                                sdram_0_s1_readdata,
                                sdram_0_s1_readdatavalid,
                                sdram_0_s1_waitrequest,
                                system_0_burst_4_downstream_address_to_slave,
                                system_0_burst_4_downstream_arbitrationshare,
                                system_0_burst_4_downstream_burstcount,
                                system_0_burst_4_downstream_byteenable,
                                system_0_burst_4_downstream_latency_counter,
                                system_0_burst_4_downstream_read,
                                system_0_burst_4_downstream_write,
                                system_0_burst_4_downstream_writedata,
                                system_0_burst_5_downstream_address_to_slave,
                                system_0_burst_5_downstream_arbitrationshare,
                                system_0_burst_5_downstream_burstcount,
                                system_0_burst_5_downstream_byteenable,
                                system_0_burst_5_downstream_latency_counter,
                                system_0_burst_5_downstream_read,
                                system_0_burst_5_downstream_write,
                                system_0_burst_5_downstream_writedata,

                               // outputs:
                                d1_sdram_0_s1_end_xfer,
                                sdram_0_s1_address,
                                sdram_0_s1_byteenable_n,
                                sdram_0_s1_chipselect,
                                sdram_0_s1_read_n,
                                sdram_0_s1_readdata_from_sa,
                                sdram_0_s1_reset_n,
                                sdram_0_s1_waitrequest_from_sa,
                                sdram_0_s1_write_n,
                                sdram_0_s1_writedata,
                                system_0_burst_4_downstream_granted_sdram_0_s1,
                                system_0_burst_4_downstream_qualified_request_sdram_0_s1,
                                system_0_burst_4_downstream_read_data_valid_sdram_0_s1,
                                system_0_burst_4_downstream_read_data_valid_sdram_0_s1_shift_register,
                                system_0_burst_4_downstream_requests_sdram_0_s1,
                                system_0_burst_5_downstream_granted_sdram_0_s1,
                                system_0_burst_5_downstream_qualified_request_sdram_0_s1,
                                system_0_burst_5_downstream_read_data_valid_sdram_0_s1,
                                system_0_burst_5_downstream_read_data_valid_sdram_0_s1_shift_register,
                                system_0_burst_5_downstream_requests_sdram_0_s1
                             )
;

  output           d1_sdram_0_s1_end_xfer;
  output  [ 21: 0] sdram_0_s1_address;
  output  [  1: 0] sdram_0_s1_byteenable_n;
  output           sdram_0_s1_chipselect;
  output           sdram_0_s1_read_n;
  output  [ 15: 0] sdram_0_s1_readdata_from_sa;
  output           sdram_0_s1_reset_n;
  output           sdram_0_s1_waitrequest_from_sa;
  output           sdram_0_s1_write_n;
  output  [ 15: 0] sdram_0_s1_writedata;
  output           system_0_burst_4_downstream_granted_sdram_0_s1;
  output           system_0_burst_4_downstream_qualified_request_sdram_0_s1;
  output           system_0_burst_4_downstream_read_data_valid_sdram_0_s1;
  output           system_0_burst_4_downstream_read_data_valid_sdram_0_s1_shift_register;
  output           system_0_burst_4_downstream_requests_sdram_0_s1;
  output           system_0_burst_5_downstream_granted_sdram_0_s1;
  output           system_0_burst_5_downstream_qualified_request_sdram_0_s1;
  output           system_0_burst_5_downstream_read_data_valid_sdram_0_s1;
  output           system_0_burst_5_downstream_read_data_valid_sdram_0_s1_shift_register;
  output           system_0_burst_5_downstream_requests_sdram_0_s1;
  input            clk;
  input            reset_n;
  input   [ 15: 0] sdram_0_s1_readdata;
  input            sdram_0_s1_readdatavalid;
  input            sdram_0_s1_waitrequest;
  input   [ 22: 0] system_0_burst_4_downstream_address_to_slave;
  input   [  4: 0] system_0_burst_4_downstream_arbitrationshare;
  input            system_0_burst_4_downstream_burstcount;
  input   [  1: 0] system_0_burst_4_downstream_byteenable;
  input            system_0_burst_4_downstream_latency_counter;
  input            system_0_burst_4_downstream_read;
  input            system_0_burst_4_downstream_write;
  input   [ 15: 0] system_0_burst_4_downstream_writedata;
  input   [ 22: 0] system_0_burst_5_downstream_address_to_slave;
  input   [  4: 0] system_0_burst_5_downstream_arbitrationshare;
  input            system_0_burst_5_downstream_burstcount;
  input   [  1: 0] system_0_burst_5_downstream_byteenable;
  input            system_0_burst_5_downstream_latency_counter;
  input            system_0_burst_5_downstream_read;
  input            system_0_burst_5_downstream_write;
  input   [ 15: 0] system_0_burst_5_downstream_writedata;

  reg              d1_reasons_to_wait;
  reg              d1_sdram_0_s1_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_sdram_0_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_system_0_burst_4_downstream_granted_slave_sdram_0_s1;
  reg              last_cycle_system_0_burst_5_downstream_granted_slave_sdram_0_s1;
  wire    [ 21: 0] sdram_0_s1_address;
  wire             sdram_0_s1_allgrants;
  wire             sdram_0_s1_allow_new_arb_cycle;
  wire             sdram_0_s1_any_bursting_master_saved_grant;
  wire             sdram_0_s1_any_continuerequest;
  reg     [  1: 0] sdram_0_s1_arb_addend;
  wire             sdram_0_s1_arb_counter_enable;
  reg     [  4: 0] sdram_0_s1_arb_share_counter;
  wire    [  4: 0] sdram_0_s1_arb_share_counter_next_value;
  wire    [  4: 0] sdram_0_s1_arb_share_set_values;
  wire    [  1: 0] sdram_0_s1_arb_winner;
  wire             sdram_0_s1_arbitration_holdoff_internal;
  wire             sdram_0_s1_beginbursttransfer_internal;
  wire             sdram_0_s1_begins_xfer;
  wire    [  1: 0] sdram_0_s1_byteenable_n;
  wire             sdram_0_s1_chipselect;
  wire    [  3: 0] sdram_0_s1_chosen_master_double_vector;
  wire    [  1: 0] sdram_0_s1_chosen_master_rot_left;
  wire             sdram_0_s1_end_xfer;
  wire             sdram_0_s1_firsttransfer;
  wire    [  1: 0] sdram_0_s1_grant_vector;
  wire             sdram_0_s1_in_a_read_cycle;
  wire             sdram_0_s1_in_a_write_cycle;
  wire    [  1: 0] sdram_0_s1_master_qreq_vector;
  wire             sdram_0_s1_move_on_to_next_transaction;
  wire             sdram_0_s1_non_bursting_master_requests;
  wire             sdram_0_s1_read_n;
  wire    [ 15: 0] sdram_0_s1_readdata_from_sa;
  wire             sdram_0_s1_readdatavalid_from_sa;
  reg              sdram_0_s1_reg_firsttransfer;
  wire             sdram_0_s1_reset_n;
  reg     [  1: 0] sdram_0_s1_saved_chosen_master_vector;
  reg              sdram_0_s1_slavearbiterlockenable;
  wire             sdram_0_s1_slavearbiterlockenable2;
  wire             sdram_0_s1_unreg_firsttransfer;
  wire             sdram_0_s1_waitrequest_from_sa;
  wire             sdram_0_s1_waits_for_read;
  wire             sdram_0_s1_waits_for_write;
  wire             sdram_0_s1_write_n;
  wire    [ 15: 0] sdram_0_s1_writedata;
  wire    [ 22: 0] shifted_address_to_sdram_0_s1_from_system_0_burst_4_downstream;
  wire    [ 22: 0] shifted_address_to_sdram_0_s1_from_system_0_burst_5_downstream;
  wire             system_0_burst_4_downstream_arbiterlock;
  wire             system_0_burst_4_downstream_arbiterlock2;
  wire             system_0_burst_4_downstream_continuerequest;
  wire             system_0_burst_4_downstream_granted_sdram_0_s1;
  wire             system_0_burst_4_downstream_qualified_request_sdram_0_s1;
  wire             system_0_burst_4_downstream_rdv_fifo_empty_sdram_0_s1;
  wire             system_0_burst_4_downstream_rdv_fifo_output_from_sdram_0_s1;
  wire             system_0_burst_4_downstream_read_data_valid_sdram_0_s1;
  wire             system_0_burst_4_downstream_read_data_valid_sdram_0_s1_shift_register;
  wire             system_0_burst_4_downstream_requests_sdram_0_s1;
  wire             system_0_burst_4_downstream_saved_grant_sdram_0_s1;
  wire             system_0_burst_5_downstream_arbiterlock;
  wire             system_0_burst_5_downstream_arbiterlock2;
  wire             system_0_burst_5_downstream_continuerequest;
  wire             system_0_burst_5_downstream_granted_sdram_0_s1;
  wire             system_0_burst_5_downstream_qualified_request_sdram_0_s1;
  wire             system_0_burst_5_downstream_rdv_fifo_empty_sdram_0_s1;
  wire             system_0_burst_5_downstream_rdv_fifo_output_from_sdram_0_s1;
  wire             system_0_burst_5_downstream_read_data_valid_sdram_0_s1;
  wire             system_0_burst_5_downstream_read_data_valid_sdram_0_s1_shift_register;
  wire             system_0_burst_5_downstream_requests_sdram_0_s1;
  wire             system_0_burst_5_downstream_saved_grant_sdram_0_s1;
  wire             wait_for_sdram_0_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~sdram_0_s1_end_xfer;
    end


  assign sdram_0_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_4_downstream_qualified_request_sdram_0_s1 | system_0_burst_5_downstream_qualified_request_sdram_0_s1));
  //assign sdram_0_s1_readdata_from_sa = sdram_0_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sdram_0_s1_readdata_from_sa = sdram_0_s1_readdata;

  assign system_0_burst_4_downstream_requests_sdram_0_s1 = (1) & (system_0_burst_4_downstream_read | system_0_burst_4_downstream_write);
  //assign sdram_0_s1_waitrequest_from_sa = sdram_0_s1_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sdram_0_s1_waitrequest_from_sa = sdram_0_s1_waitrequest;

  //assign sdram_0_s1_readdatavalid_from_sa = sdram_0_s1_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sdram_0_s1_readdatavalid_from_sa = sdram_0_s1_readdatavalid;

  //sdram_0_s1_arb_share_counter set values, which is an e_mux
  assign sdram_0_s1_arb_share_set_values = (system_0_burst_4_downstream_granted_sdram_0_s1)? system_0_burst_4_downstream_arbitrationshare :
    (system_0_burst_5_downstream_granted_sdram_0_s1)? system_0_burst_5_downstream_arbitrationshare :
    (system_0_burst_4_downstream_granted_sdram_0_s1)? system_0_burst_4_downstream_arbitrationshare :
    (system_0_burst_5_downstream_granted_sdram_0_s1)? system_0_burst_5_downstream_arbitrationshare :
    1;

  //sdram_0_s1_non_bursting_master_requests mux, which is an e_mux
  assign sdram_0_s1_non_bursting_master_requests = 0;

  //sdram_0_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign sdram_0_s1_any_bursting_master_saved_grant = system_0_burst_4_downstream_saved_grant_sdram_0_s1 |
    system_0_burst_5_downstream_saved_grant_sdram_0_s1 |
    system_0_burst_4_downstream_saved_grant_sdram_0_s1 |
    system_0_burst_5_downstream_saved_grant_sdram_0_s1;

  //sdram_0_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign sdram_0_s1_arb_share_counter_next_value = sdram_0_s1_firsttransfer ? (sdram_0_s1_arb_share_set_values - 1) : |sdram_0_s1_arb_share_counter ? (sdram_0_s1_arb_share_counter - 1) : 0;

  //sdram_0_s1_allgrants all slave grants, which is an e_mux
  assign sdram_0_s1_allgrants = (|sdram_0_s1_grant_vector) |
    (|sdram_0_s1_grant_vector) |
    (|sdram_0_s1_grant_vector) |
    (|sdram_0_s1_grant_vector);

  //sdram_0_s1_end_xfer assignment, which is an e_assign
  assign sdram_0_s1_end_xfer = ~(sdram_0_s1_waits_for_read | sdram_0_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_sdram_0_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_sdram_0_s1 = sdram_0_s1_end_xfer & (~sdram_0_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //sdram_0_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign sdram_0_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_sdram_0_s1 & sdram_0_s1_allgrants) | (end_xfer_arb_share_counter_term_sdram_0_s1 & ~sdram_0_s1_non_bursting_master_requests);

  //sdram_0_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sdram_0_s1_arb_share_counter <= 0;
      else if (sdram_0_s1_arb_counter_enable)
          sdram_0_s1_arb_share_counter <= sdram_0_s1_arb_share_counter_next_value;
    end


  //sdram_0_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sdram_0_s1_slavearbiterlockenable <= 0;
      else if ((|sdram_0_s1_master_qreq_vector & end_xfer_arb_share_counter_term_sdram_0_s1) | (end_xfer_arb_share_counter_term_sdram_0_s1 & ~sdram_0_s1_non_bursting_master_requests))
          sdram_0_s1_slavearbiterlockenable <= |sdram_0_s1_arb_share_counter_next_value;
    end


  //system_0_burst_4/downstream sdram_0/s1 arbiterlock, which is an e_assign
  assign system_0_burst_4_downstream_arbiterlock = sdram_0_s1_slavearbiterlockenable & system_0_burst_4_downstream_continuerequest;

  //sdram_0_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign sdram_0_s1_slavearbiterlockenable2 = |sdram_0_s1_arb_share_counter_next_value;

  //system_0_burst_4/downstream sdram_0/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_4_downstream_arbiterlock2 = sdram_0_s1_slavearbiterlockenable2 & system_0_burst_4_downstream_continuerequest;

  //system_0_burst_5/downstream sdram_0/s1 arbiterlock, which is an e_assign
  assign system_0_burst_5_downstream_arbiterlock = sdram_0_s1_slavearbiterlockenable & system_0_burst_5_downstream_continuerequest;

  //system_0_burst_5/downstream sdram_0/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_5_downstream_arbiterlock2 = sdram_0_s1_slavearbiterlockenable2 & system_0_burst_5_downstream_continuerequest;

  //system_0_burst_5/downstream granted sdram_0/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_system_0_burst_5_downstream_granted_slave_sdram_0_s1 <= 0;
      else 
        last_cycle_system_0_burst_5_downstream_granted_slave_sdram_0_s1 <= system_0_burst_5_downstream_saved_grant_sdram_0_s1 ? 1 : (sdram_0_s1_arbitration_holdoff_internal | 0) ? 0 : last_cycle_system_0_burst_5_downstream_granted_slave_sdram_0_s1;
    end


  //system_0_burst_5_downstream_continuerequest continued request, which is an e_mux
  assign system_0_burst_5_downstream_continuerequest = last_cycle_system_0_burst_5_downstream_granted_slave_sdram_0_s1 & 1;

  //sdram_0_s1_any_continuerequest at least one master continues requesting, which is an e_mux
  assign sdram_0_s1_any_continuerequest = system_0_burst_5_downstream_continuerequest |
    system_0_burst_4_downstream_continuerequest;

  assign system_0_burst_4_downstream_qualified_request_sdram_0_s1 = system_0_burst_4_downstream_requests_sdram_0_s1 & ~((system_0_burst_4_downstream_read & ((system_0_burst_4_downstream_latency_counter != 0) | (1 < system_0_burst_4_downstream_latency_counter))) | system_0_burst_5_downstream_arbiterlock);
  //unique name for sdram_0_s1_move_on_to_next_transaction, which is an e_assign
  assign sdram_0_s1_move_on_to_next_transaction = sdram_0_s1_readdatavalid_from_sa;

  //rdv_fifo_for_system_0_burst_4_downstream_to_sdram_0_s1, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_system_0_burst_4_downstream_to_sdram_0_s1_module rdv_fifo_for_system_0_burst_4_downstream_to_sdram_0_s1
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_4_downstream_granted_sdram_0_s1),
      .data_out             (system_0_burst_4_downstream_rdv_fifo_output_from_sdram_0_s1),
      .empty                (),
      .fifo_contains_ones_n (system_0_burst_4_downstream_rdv_fifo_empty_sdram_0_s1),
      .full                 (),
      .read                 (sdram_0_s1_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~sdram_0_s1_waits_for_read)
    );

  assign system_0_burst_4_downstream_read_data_valid_sdram_0_s1_shift_register = ~system_0_burst_4_downstream_rdv_fifo_empty_sdram_0_s1;
  //local readdatavalid system_0_burst_4_downstream_read_data_valid_sdram_0_s1, which is an e_mux
  assign system_0_burst_4_downstream_read_data_valid_sdram_0_s1 = (sdram_0_s1_readdatavalid_from_sa & system_0_burst_4_downstream_rdv_fifo_output_from_sdram_0_s1) & ~ system_0_burst_4_downstream_rdv_fifo_empty_sdram_0_s1;

  //sdram_0_s1_writedata mux, which is an e_mux
  assign sdram_0_s1_writedata = (system_0_burst_4_downstream_granted_sdram_0_s1)? system_0_burst_4_downstream_writedata :
    system_0_burst_5_downstream_writedata;

  assign system_0_burst_5_downstream_requests_sdram_0_s1 = (1) & (system_0_burst_5_downstream_read | system_0_burst_5_downstream_write);
  //system_0_burst_4/downstream granted sdram_0/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_system_0_burst_4_downstream_granted_slave_sdram_0_s1 <= 0;
      else 
        last_cycle_system_0_burst_4_downstream_granted_slave_sdram_0_s1 <= system_0_burst_4_downstream_saved_grant_sdram_0_s1 ? 1 : (sdram_0_s1_arbitration_holdoff_internal | 0) ? 0 : last_cycle_system_0_burst_4_downstream_granted_slave_sdram_0_s1;
    end


  //system_0_burst_4_downstream_continuerequest continued request, which is an e_mux
  assign system_0_burst_4_downstream_continuerequest = last_cycle_system_0_burst_4_downstream_granted_slave_sdram_0_s1 & 1;

  assign system_0_burst_5_downstream_qualified_request_sdram_0_s1 = system_0_burst_5_downstream_requests_sdram_0_s1 & ~((system_0_burst_5_downstream_read & ((system_0_burst_5_downstream_latency_counter != 0) | (1 < system_0_burst_5_downstream_latency_counter))) | system_0_burst_4_downstream_arbiterlock);
  //rdv_fifo_for_system_0_burst_5_downstream_to_sdram_0_s1, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_system_0_burst_5_downstream_to_sdram_0_s1_module rdv_fifo_for_system_0_burst_5_downstream_to_sdram_0_s1
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_5_downstream_granted_sdram_0_s1),
      .data_out             (system_0_burst_5_downstream_rdv_fifo_output_from_sdram_0_s1),
      .empty                (),
      .fifo_contains_ones_n (system_0_burst_5_downstream_rdv_fifo_empty_sdram_0_s1),
      .full                 (),
      .read                 (sdram_0_s1_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~sdram_0_s1_waits_for_read)
    );

  assign system_0_burst_5_downstream_read_data_valid_sdram_0_s1_shift_register = ~system_0_burst_5_downstream_rdv_fifo_empty_sdram_0_s1;
  //local readdatavalid system_0_burst_5_downstream_read_data_valid_sdram_0_s1, which is an e_mux
  assign system_0_burst_5_downstream_read_data_valid_sdram_0_s1 = (sdram_0_s1_readdatavalid_from_sa & system_0_burst_5_downstream_rdv_fifo_output_from_sdram_0_s1) & ~ system_0_burst_5_downstream_rdv_fifo_empty_sdram_0_s1;

  //allow new arb cycle for sdram_0/s1, which is an e_assign
  assign sdram_0_s1_allow_new_arb_cycle = ~system_0_burst_4_downstream_arbiterlock & ~system_0_burst_5_downstream_arbiterlock;

  //system_0_burst_5/downstream assignment into master qualified-requests vector for sdram_0/s1, which is an e_assign
  assign sdram_0_s1_master_qreq_vector[0] = system_0_burst_5_downstream_qualified_request_sdram_0_s1;

  //system_0_burst_5/downstream grant sdram_0/s1, which is an e_assign
  assign system_0_burst_5_downstream_granted_sdram_0_s1 = sdram_0_s1_grant_vector[0];

  //system_0_burst_5/downstream saved-grant sdram_0/s1, which is an e_assign
  assign system_0_burst_5_downstream_saved_grant_sdram_0_s1 = sdram_0_s1_arb_winner[0];

  //system_0_burst_4/downstream assignment into master qualified-requests vector for sdram_0/s1, which is an e_assign
  assign sdram_0_s1_master_qreq_vector[1] = system_0_burst_4_downstream_qualified_request_sdram_0_s1;

  //system_0_burst_4/downstream grant sdram_0/s1, which is an e_assign
  assign system_0_burst_4_downstream_granted_sdram_0_s1 = sdram_0_s1_grant_vector[1];

  //system_0_burst_4/downstream saved-grant sdram_0/s1, which is an e_assign
  assign system_0_burst_4_downstream_saved_grant_sdram_0_s1 = sdram_0_s1_arb_winner[1];

  //sdram_0/s1 chosen-master double-vector, which is an e_assign
  assign sdram_0_s1_chosen_master_double_vector = {sdram_0_s1_master_qreq_vector, sdram_0_s1_master_qreq_vector} & ({~sdram_0_s1_master_qreq_vector, ~sdram_0_s1_master_qreq_vector} + sdram_0_s1_arb_addend);

  //stable onehot encoding of arb winner
  assign sdram_0_s1_arb_winner = (sdram_0_s1_allow_new_arb_cycle & | sdram_0_s1_grant_vector) ? sdram_0_s1_grant_vector : sdram_0_s1_saved_chosen_master_vector;

  //saved sdram_0_s1_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sdram_0_s1_saved_chosen_master_vector <= 0;
      else if (sdram_0_s1_allow_new_arb_cycle)
          sdram_0_s1_saved_chosen_master_vector <= |sdram_0_s1_grant_vector ? sdram_0_s1_grant_vector : sdram_0_s1_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign sdram_0_s1_grant_vector = {(sdram_0_s1_chosen_master_double_vector[1] | sdram_0_s1_chosen_master_double_vector[3]),
    (sdram_0_s1_chosen_master_double_vector[0] | sdram_0_s1_chosen_master_double_vector[2])};

  //sdram_0/s1 chosen master rotated left, which is an e_assign
  assign sdram_0_s1_chosen_master_rot_left = (sdram_0_s1_arb_winner << 1) ? (sdram_0_s1_arb_winner << 1) : 1;

  //sdram_0/s1's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sdram_0_s1_arb_addend <= 1;
      else if (|sdram_0_s1_grant_vector)
          sdram_0_s1_arb_addend <= sdram_0_s1_end_xfer? sdram_0_s1_chosen_master_rot_left : sdram_0_s1_grant_vector;
    end


  //sdram_0_s1_reset_n assignment, which is an e_assign
  assign sdram_0_s1_reset_n = reset_n;

  assign sdram_0_s1_chipselect = system_0_burst_4_downstream_granted_sdram_0_s1 | system_0_burst_5_downstream_granted_sdram_0_s1;
  //sdram_0_s1_firsttransfer first transaction, which is an e_assign
  assign sdram_0_s1_firsttransfer = sdram_0_s1_begins_xfer ? sdram_0_s1_unreg_firsttransfer : sdram_0_s1_reg_firsttransfer;

  //sdram_0_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign sdram_0_s1_unreg_firsttransfer = ~(sdram_0_s1_slavearbiterlockenable & sdram_0_s1_any_continuerequest);

  //sdram_0_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sdram_0_s1_reg_firsttransfer <= 1'b1;
      else if (sdram_0_s1_begins_xfer)
          sdram_0_s1_reg_firsttransfer <= sdram_0_s1_unreg_firsttransfer;
    end


  //sdram_0_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign sdram_0_s1_beginbursttransfer_internal = sdram_0_s1_begins_xfer;

  //sdram_0_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign sdram_0_s1_arbitration_holdoff_internal = sdram_0_s1_begins_xfer & sdram_0_s1_firsttransfer;

  //~sdram_0_s1_read_n assignment, which is an e_mux
  assign sdram_0_s1_read_n = ~((system_0_burst_4_downstream_granted_sdram_0_s1 & system_0_burst_4_downstream_read) | (system_0_burst_5_downstream_granted_sdram_0_s1 & system_0_burst_5_downstream_read));

  //~sdram_0_s1_write_n assignment, which is an e_mux
  assign sdram_0_s1_write_n = ~((system_0_burst_4_downstream_granted_sdram_0_s1 & system_0_burst_4_downstream_write) | (system_0_burst_5_downstream_granted_sdram_0_s1 & system_0_burst_5_downstream_write));

  assign shifted_address_to_sdram_0_s1_from_system_0_burst_4_downstream = system_0_burst_4_downstream_address_to_slave;
  //sdram_0_s1_address mux, which is an e_mux
  assign sdram_0_s1_address = (system_0_burst_4_downstream_granted_sdram_0_s1)? (shifted_address_to_sdram_0_s1_from_system_0_burst_4_downstream >> 1) :
    (shifted_address_to_sdram_0_s1_from_system_0_burst_5_downstream >> 1);

  assign shifted_address_to_sdram_0_s1_from_system_0_burst_5_downstream = system_0_burst_5_downstream_address_to_slave;
  //d1_sdram_0_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_sdram_0_s1_end_xfer <= 1;
      else 
        d1_sdram_0_s1_end_xfer <= sdram_0_s1_end_xfer;
    end


  //sdram_0_s1_waits_for_read in a cycle, which is an e_mux
  assign sdram_0_s1_waits_for_read = sdram_0_s1_in_a_read_cycle & sdram_0_s1_waitrequest_from_sa;

  //sdram_0_s1_in_a_read_cycle assignment, which is an e_assign
  assign sdram_0_s1_in_a_read_cycle = (system_0_burst_4_downstream_granted_sdram_0_s1 & system_0_burst_4_downstream_read) | (system_0_burst_5_downstream_granted_sdram_0_s1 & system_0_burst_5_downstream_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = sdram_0_s1_in_a_read_cycle;

  //sdram_0_s1_waits_for_write in a cycle, which is an e_mux
  assign sdram_0_s1_waits_for_write = sdram_0_s1_in_a_write_cycle & sdram_0_s1_waitrequest_from_sa;

  //sdram_0_s1_in_a_write_cycle assignment, which is an e_assign
  assign sdram_0_s1_in_a_write_cycle = (system_0_burst_4_downstream_granted_sdram_0_s1 & system_0_burst_4_downstream_write) | (system_0_burst_5_downstream_granted_sdram_0_s1 & system_0_burst_5_downstream_write);

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = sdram_0_s1_in_a_write_cycle;

  assign wait_for_sdram_0_s1_counter = 0;
  //~sdram_0_s1_byteenable_n byte enable port mux, which is an e_mux
  assign sdram_0_s1_byteenable_n = ~((system_0_burst_4_downstream_granted_sdram_0_s1)? system_0_burst_4_downstream_byteenable :
    (system_0_burst_5_downstream_granted_sdram_0_s1)? system_0_burst_5_downstream_byteenable :
    -1);


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //sdram_0/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_4/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_4_downstream_requests_sdram_0_s1 && (system_0_burst_4_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_4/downstream drove 0 on its 'arbitrationshare' port while accessing slave sdram_0/s1", $time);
          $stop;
        end
    end


  //system_0_burst_4/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_4_downstream_requests_sdram_0_s1 && (system_0_burst_4_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_4/downstream drove 0 on its 'burstcount' port while accessing slave sdram_0/s1", $time);
          $stop;
        end
    end


  //system_0_burst_5/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_5_downstream_requests_sdram_0_s1 && (system_0_burst_5_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_5/downstream drove 0 on its 'arbitrationshare' port while accessing slave sdram_0/s1", $time);
          $stop;
        end
    end


  //system_0_burst_5/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_5_downstream_requests_sdram_0_s1 && (system_0_burst_5_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_5/downstream drove 0 on its 'burstcount' port while accessing slave sdram_0/s1", $time);
          $stop;
        end
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_4_downstream_granted_sdram_0_s1 + system_0_burst_5_downstream_granted_sdram_0_s1 > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_4_downstream_saved_grant_sdram_0_s1 + system_0_burst_5_downstream_saved_grant_sdram_0_s1 > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module sram_0_avalon_slave_0_arbitrator (
                                          // inputs:
                                           clk,
                                           reset_n,
                                           sram_0_avalon_slave_0_readdata,
                                           system_0_burst_14_downstream_address_to_slave,
                                           system_0_burst_14_downstream_arbitrationshare,
                                           system_0_burst_14_downstream_burstcount,
                                           system_0_burst_14_downstream_byteenable,
                                           system_0_burst_14_downstream_latency_counter,
                                           system_0_burst_14_downstream_read,
                                           system_0_burst_14_downstream_write,
                                           system_0_burst_14_downstream_writedata,
                                           system_0_burst_15_downstream_address_to_slave,
                                           system_0_burst_15_downstream_arbitrationshare,
                                           system_0_burst_15_downstream_burstcount,
                                           system_0_burst_15_downstream_byteenable,
                                           system_0_burst_15_downstream_latency_counter,
                                           system_0_burst_15_downstream_read,
                                           system_0_burst_15_downstream_write,
                                           system_0_burst_15_downstream_writedata,

                                          // outputs:
                                           d1_sram_0_avalon_slave_0_end_xfer,
                                           sram_0_avalon_slave_0_address,
                                           sram_0_avalon_slave_0_byteenable_n,
                                           sram_0_avalon_slave_0_chipselect_n,
                                           sram_0_avalon_slave_0_read_n,
                                           sram_0_avalon_slave_0_readdata_from_sa,
                                           sram_0_avalon_slave_0_wait_counter_eq_0,
                                           sram_0_avalon_slave_0_write_n,
                                           sram_0_avalon_slave_0_writedata,
                                           system_0_burst_14_downstream_granted_sram_0_avalon_slave_0,
                                           system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0,
                                           system_0_burst_14_downstream_read_data_valid_sram_0_avalon_slave_0,
                                           system_0_burst_14_downstream_requests_sram_0_avalon_slave_0,
                                           system_0_burst_15_downstream_granted_sram_0_avalon_slave_0,
                                           system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0,
                                           system_0_burst_15_downstream_read_data_valid_sram_0_avalon_slave_0,
                                           system_0_burst_15_downstream_requests_sram_0_avalon_slave_0
                                        )
;

  output           d1_sram_0_avalon_slave_0_end_xfer;
  output  [ 17: 0] sram_0_avalon_slave_0_address;
  output  [  1: 0] sram_0_avalon_slave_0_byteenable_n;
  output           sram_0_avalon_slave_0_chipselect_n;
  output           sram_0_avalon_slave_0_read_n;
  output  [ 15: 0] sram_0_avalon_slave_0_readdata_from_sa;
  output           sram_0_avalon_slave_0_wait_counter_eq_0;
  output           sram_0_avalon_slave_0_write_n;
  output  [ 15: 0] sram_0_avalon_slave_0_writedata;
  output           system_0_burst_14_downstream_granted_sram_0_avalon_slave_0;
  output           system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0;
  output           system_0_burst_14_downstream_read_data_valid_sram_0_avalon_slave_0;
  output           system_0_burst_14_downstream_requests_sram_0_avalon_slave_0;
  output           system_0_burst_15_downstream_granted_sram_0_avalon_slave_0;
  output           system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0;
  output           system_0_burst_15_downstream_read_data_valid_sram_0_avalon_slave_0;
  output           system_0_burst_15_downstream_requests_sram_0_avalon_slave_0;
  input            clk;
  input            reset_n;
  input   [ 15: 0] sram_0_avalon_slave_0_readdata;
  input   [ 18: 0] system_0_burst_14_downstream_address_to_slave;
  input   [  4: 0] system_0_burst_14_downstream_arbitrationshare;
  input            system_0_burst_14_downstream_burstcount;
  input   [  1: 0] system_0_burst_14_downstream_byteenable;
  input            system_0_burst_14_downstream_latency_counter;
  input            system_0_burst_14_downstream_read;
  input            system_0_burst_14_downstream_write;
  input   [ 15: 0] system_0_burst_14_downstream_writedata;
  input   [ 18: 0] system_0_burst_15_downstream_address_to_slave;
  input   [  4: 0] system_0_burst_15_downstream_arbitrationshare;
  input            system_0_burst_15_downstream_burstcount;
  input   [  1: 0] system_0_burst_15_downstream_byteenable;
  input            system_0_burst_15_downstream_latency_counter;
  input            system_0_burst_15_downstream_read;
  input            system_0_burst_15_downstream_write;
  input   [ 15: 0] system_0_burst_15_downstream_writedata;

  reg              d1_reasons_to_wait;
  reg              d1_sram_0_avalon_slave_0_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_sram_0_avalon_slave_0;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_system_0_burst_14_downstream_granted_slave_sram_0_avalon_slave_0;
  reg              last_cycle_system_0_burst_15_downstream_granted_slave_sram_0_avalon_slave_0;
  wire    [ 18: 0] shifted_address_to_sram_0_avalon_slave_0_from_system_0_burst_14_downstream;
  wire    [ 18: 0] shifted_address_to_sram_0_avalon_slave_0_from_system_0_burst_15_downstream;
  wire    [ 17: 0] sram_0_avalon_slave_0_address;
  wire             sram_0_avalon_slave_0_allgrants;
  wire             sram_0_avalon_slave_0_allow_new_arb_cycle;
  wire             sram_0_avalon_slave_0_any_bursting_master_saved_grant;
  wire             sram_0_avalon_slave_0_any_continuerequest;
  reg     [  1: 0] sram_0_avalon_slave_0_arb_addend;
  wire             sram_0_avalon_slave_0_arb_counter_enable;
  reg     [  4: 0] sram_0_avalon_slave_0_arb_share_counter;
  wire    [  4: 0] sram_0_avalon_slave_0_arb_share_counter_next_value;
  wire    [  4: 0] sram_0_avalon_slave_0_arb_share_set_values;
  wire    [  1: 0] sram_0_avalon_slave_0_arb_winner;
  wire             sram_0_avalon_slave_0_arbitration_holdoff_internal;
  wire             sram_0_avalon_slave_0_beginbursttransfer_internal;
  wire             sram_0_avalon_slave_0_begins_xfer;
  wire    [  1: 0] sram_0_avalon_slave_0_byteenable_n;
  wire             sram_0_avalon_slave_0_chipselect_n;
  wire    [  3: 0] sram_0_avalon_slave_0_chosen_master_double_vector;
  wire    [  1: 0] sram_0_avalon_slave_0_chosen_master_rot_left;
  wire    [  2: 0] sram_0_avalon_slave_0_counter_load_value;
  wire             sram_0_avalon_slave_0_end_xfer;
  wire             sram_0_avalon_slave_0_firsttransfer;
  wire    [  1: 0] sram_0_avalon_slave_0_grant_vector;
  wire             sram_0_avalon_slave_0_in_a_read_cycle;
  wire             sram_0_avalon_slave_0_in_a_write_cycle;
  wire    [  1: 0] sram_0_avalon_slave_0_master_qreq_vector;
  wire             sram_0_avalon_slave_0_non_bursting_master_requests;
  wire             sram_0_avalon_slave_0_read_n;
  wire    [ 15: 0] sram_0_avalon_slave_0_readdata_from_sa;
  reg              sram_0_avalon_slave_0_reg_firsttransfer;
  reg     [  1: 0] sram_0_avalon_slave_0_saved_chosen_master_vector;
  reg              sram_0_avalon_slave_0_slavearbiterlockenable;
  wire             sram_0_avalon_slave_0_slavearbiterlockenable2;
  wire             sram_0_avalon_slave_0_unreg_firsttransfer;
  reg     [  2: 0] sram_0_avalon_slave_0_wait_counter;
  wire             sram_0_avalon_slave_0_wait_counter_eq_0;
  wire             sram_0_avalon_slave_0_waits_for_read;
  wire             sram_0_avalon_slave_0_waits_for_write;
  wire             sram_0_avalon_slave_0_write_n;
  wire    [ 15: 0] sram_0_avalon_slave_0_writedata;
  wire             system_0_burst_14_downstream_arbiterlock;
  wire             system_0_burst_14_downstream_arbiterlock2;
  wire             system_0_burst_14_downstream_continuerequest;
  wire             system_0_burst_14_downstream_granted_sram_0_avalon_slave_0;
  wire             system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0;
  wire             system_0_burst_14_downstream_read_data_valid_sram_0_avalon_slave_0;
  wire             system_0_burst_14_downstream_requests_sram_0_avalon_slave_0;
  wire             system_0_burst_14_downstream_saved_grant_sram_0_avalon_slave_0;
  wire             system_0_burst_15_downstream_arbiterlock;
  wire             system_0_burst_15_downstream_arbiterlock2;
  wire             system_0_burst_15_downstream_continuerequest;
  wire             system_0_burst_15_downstream_granted_sram_0_avalon_slave_0;
  wire             system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0;
  wire             system_0_burst_15_downstream_read_data_valid_sram_0_avalon_slave_0;
  wire             system_0_burst_15_downstream_requests_sram_0_avalon_slave_0;
  wire             system_0_burst_15_downstream_saved_grant_sram_0_avalon_slave_0;
  wire             wait_for_sram_0_avalon_slave_0_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~sram_0_avalon_slave_0_end_xfer;
    end


  assign sram_0_avalon_slave_0_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0 | system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0));
  //assign sram_0_avalon_slave_0_readdata_from_sa = sram_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sram_0_avalon_slave_0_readdata_from_sa = sram_0_avalon_slave_0_readdata;

  assign system_0_burst_14_downstream_requests_sram_0_avalon_slave_0 = (1) & (system_0_burst_14_downstream_read | system_0_burst_14_downstream_write);
  //sram_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
  assign sram_0_avalon_slave_0_arb_share_set_values = (system_0_burst_14_downstream_granted_sram_0_avalon_slave_0)? system_0_burst_14_downstream_arbitrationshare :
    (system_0_burst_15_downstream_granted_sram_0_avalon_slave_0)? system_0_burst_15_downstream_arbitrationshare :
    (system_0_burst_14_downstream_granted_sram_0_avalon_slave_0)? system_0_burst_14_downstream_arbitrationshare :
    (system_0_burst_15_downstream_granted_sram_0_avalon_slave_0)? system_0_burst_15_downstream_arbitrationshare :
    1;

  //sram_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
  assign sram_0_avalon_slave_0_non_bursting_master_requests = 0;

  //sram_0_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
  assign sram_0_avalon_slave_0_any_bursting_master_saved_grant = system_0_burst_14_downstream_saved_grant_sram_0_avalon_slave_0 |
    system_0_burst_15_downstream_saved_grant_sram_0_avalon_slave_0 |
    system_0_burst_14_downstream_saved_grant_sram_0_avalon_slave_0 |
    system_0_burst_15_downstream_saved_grant_sram_0_avalon_slave_0;

  //sram_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
  assign sram_0_avalon_slave_0_arb_share_counter_next_value = sram_0_avalon_slave_0_firsttransfer ? (sram_0_avalon_slave_0_arb_share_set_values - 1) : |sram_0_avalon_slave_0_arb_share_counter ? (sram_0_avalon_slave_0_arb_share_counter - 1) : 0;

  //sram_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
  assign sram_0_avalon_slave_0_allgrants = (|sram_0_avalon_slave_0_grant_vector) |
    (|sram_0_avalon_slave_0_grant_vector) |
    (|sram_0_avalon_slave_0_grant_vector) |
    (|sram_0_avalon_slave_0_grant_vector);

  //sram_0_avalon_slave_0_end_xfer assignment, which is an e_assign
  assign sram_0_avalon_slave_0_end_xfer = ~(sram_0_avalon_slave_0_waits_for_read | sram_0_avalon_slave_0_waits_for_write);

  //end_xfer_arb_share_counter_term_sram_0_avalon_slave_0 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_sram_0_avalon_slave_0 = sram_0_avalon_slave_0_end_xfer & (~sram_0_avalon_slave_0_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //sram_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
  assign sram_0_avalon_slave_0_arb_counter_enable = (end_xfer_arb_share_counter_term_sram_0_avalon_slave_0 & sram_0_avalon_slave_0_allgrants) | (end_xfer_arb_share_counter_term_sram_0_avalon_slave_0 & ~sram_0_avalon_slave_0_non_bursting_master_requests);

  //sram_0_avalon_slave_0_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_0_avalon_slave_0_arb_share_counter <= 0;
      else if (sram_0_avalon_slave_0_arb_counter_enable)
          sram_0_avalon_slave_0_arb_share_counter <= sram_0_avalon_slave_0_arb_share_counter_next_value;
    end


  //sram_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_0_avalon_slave_0_slavearbiterlockenable <= 0;
      else if ((|sram_0_avalon_slave_0_master_qreq_vector & end_xfer_arb_share_counter_term_sram_0_avalon_slave_0) | (end_xfer_arb_share_counter_term_sram_0_avalon_slave_0 & ~sram_0_avalon_slave_0_non_bursting_master_requests))
          sram_0_avalon_slave_0_slavearbiterlockenable <= |sram_0_avalon_slave_0_arb_share_counter_next_value;
    end


  //system_0_burst_14/downstream sram_0/avalon_slave_0 arbiterlock, which is an e_assign
  assign system_0_burst_14_downstream_arbiterlock = sram_0_avalon_slave_0_slavearbiterlockenable & system_0_burst_14_downstream_continuerequest;

  //sram_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign sram_0_avalon_slave_0_slavearbiterlockenable2 = |sram_0_avalon_slave_0_arb_share_counter_next_value;

  //system_0_burst_14/downstream sram_0/avalon_slave_0 arbiterlock2, which is an e_assign
  assign system_0_burst_14_downstream_arbiterlock2 = sram_0_avalon_slave_0_slavearbiterlockenable2 & system_0_burst_14_downstream_continuerequest;

  //system_0_burst_15/downstream sram_0/avalon_slave_0 arbiterlock, which is an e_assign
  assign system_0_burst_15_downstream_arbiterlock = sram_0_avalon_slave_0_slavearbiterlockenable & system_0_burst_15_downstream_continuerequest;

  //system_0_burst_15/downstream sram_0/avalon_slave_0 arbiterlock2, which is an e_assign
  assign system_0_burst_15_downstream_arbiterlock2 = sram_0_avalon_slave_0_slavearbiterlockenable2 & system_0_burst_15_downstream_continuerequest;

  //system_0_burst_15/downstream granted sram_0/avalon_slave_0 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_system_0_burst_15_downstream_granted_slave_sram_0_avalon_slave_0 <= 0;
      else 
        last_cycle_system_0_burst_15_downstream_granted_slave_sram_0_avalon_slave_0 <= system_0_burst_15_downstream_saved_grant_sram_0_avalon_slave_0 ? 1 : (sram_0_avalon_slave_0_arbitration_holdoff_internal | 0) ? 0 : last_cycle_system_0_burst_15_downstream_granted_slave_sram_0_avalon_slave_0;
    end


  //system_0_burst_15_downstream_continuerequest continued request, which is an e_mux
  assign system_0_burst_15_downstream_continuerequest = last_cycle_system_0_burst_15_downstream_granted_slave_sram_0_avalon_slave_0 & 1;

  //sram_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_mux
  assign sram_0_avalon_slave_0_any_continuerequest = system_0_burst_15_downstream_continuerequest |
    system_0_burst_14_downstream_continuerequest;

  assign system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0 = system_0_burst_14_downstream_requests_sram_0_avalon_slave_0 & ~((system_0_burst_14_downstream_read & ((system_0_burst_14_downstream_latency_counter != 0))) | system_0_burst_15_downstream_arbiterlock);
  //local readdatavalid system_0_burst_14_downstream_read_data_valid_sram_0_avalon_slave_0, which is an e_mux
  assign system_0_burst_14_downstream_read_data_valid_sram_0_avalon_slave_0 = system_0_burst_14_downstream_granted_sram_0_avalon_slave_0 & system_0_burst_14_downstream_read & ~sram_0_avalon_slave_0_waits_for_read;

  //sram_0_avalon_slave_0_writedata mux, which is an e_mux
  assign sram_0_avalon_slave_0_writedata = (system_0_burst_14_downstream_granted_sram_0_avalon_slave_0)? system_0_burst_14_downstream_writedata :
    system_0_burst_15_downstream_writedata;

  assign system_0_burst_15_downstream_requests_sram_0_avalon_slave_0 = (1) & (system_0_burst_15_downstream_read | system_0_burst_15_downstream_write);
  //system_0_burst_14/downstream granted sram_0/avalon_slave_0 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_system_0_burst_14_downstream_granted_slave_sram_0_avalon_slave_0 <= 0;
      else 
        last_cycle_system_0_burst_14_downstream_granted_slave_sram_0_avalon_slave_0 <= system_0_burst_14_downstream_saved_grant_sram_0_avalon_slave_0 ? 1 : (sram_0_avalon_slave_0_arbitration_holdoff_internal | 0) ? 0 : last_cycle_system_0_burst_14_downstream_granted_slave_sram_0_avalon_slave_0;
    end


  //system_0_burst_14_downstream_continuerequest continued request, which is an e_mux
  assign system_0_burst_14_downstream_continuerequest = last_cycle_system_0_burst_14_downstream_granted_slave_sram_0_avalon_slave_0 & 1;

  assign system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0 = system_0_burst_15_downstream_requests_sram_0_avalon_slave_0 & ~((system_0_burst_15_downstream_read & ((system_0_burst_15_downstream_latency_counter != 0))) | system_0_burst_14_downstream_arbiterlock);
  //local readdatavalid system_0_burst_15_downstream_read_data_valid_sram_0_avalon_slave_0, which is an e_mux
  assign system_0_burst_15_downstream_read_data_valid_sram_0_avalon_slave_0 = system_0_burst_15_downstream_granted_sram_0_avalon_slave_0 & system_0_burst_15_downstream_read & ~sram_0_avalon_slave_0_waits_for_read;

  //allow new arb cycle for sram_0/avalon_slave_0, which is an e_assign
  assign sram_0_avalon_slave_0_allow_new_arb_cycle = ~system_0_burst_14_downstream_arbiterlock & ~system_0_burst_15_downstream_arbiterlock;

  //system_0_burst_15/downstream assignment into master qualified-requests vector for sram_0/avalon_slave_0, which is an e_assign
  assign sram_0_avalon_slave_0_master_qreq_vector[0] = system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0;

  //system_0_burst_15/downstream grant sram_0/avalon_slave_0, which is an e_assign
  assign system_0_burst_15_downstream_granted_sram_0_avalon_slave_0 = sram_0_avalon_slave_0_grant_vector[0];

  //system_0_burst_15/downstream saved-grant sram_0/avalon_slave_0, which is an e_assign
  assign system_0_burst_15_downstream_saved_grant_sram_0_avalon_slave_0 = sram_0_avalon_slave_0_arb_winner[0];

  //system_0_burst_14/downstream assignment into master qualified-requests vector for sram_0/avalon_slave_0, which is an e_assign
  assign sram_0_avalon_slave_0_master_qreq_vector[1] = system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0;

  //system_0_burst_14/downstream grant sram_0/avalon_slave_0, which is an e_assign
  assign system_0_burst_14_downstream_granted_sram_0_avalon_slave_0 = sram_0_avalon_slave_0_grant_vector[1];

  //system_0_burst_14/downstream saved-grant sram_0/avalon_slave_0, which is an e_assign
  assign system_0_burst_14_downstream_saved_grant_sram_0_avalon_slave_0 = sram_0_avalon_slave_0_arb_winner[1];

  //sram_0/avalon_slave_0 chosen-master double-vector, which is an e_assign
  assign sram_0_avalon_slave_0_chosen_master_double_vector = {sram_0_avalon_slave_0_master_qreq_vector, sram_0_avalon_slave_0_master_qreq_vector} & ({~sram_0_avalon_slave_0_master_qreq_vector, ~sram_0_avalon_slave_0_master_qreq_vector} + sram_0_avalon_slave_0_arb_addend);

  //stable onehot encoding of arb winner
  assign sram_0_avalon_slave_0_arb_winner = (sram_0_avalon_slave_0_allow_new_arb_cycle & | sram_0_avalon_slave_0_grant_vector) ? sram_0_avalon_slave_0_grant_vector : sram_0_avalon_slave_0_saved_chosen_master_vector;

  //saved sram_0_avalon_slave_0_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_0_avalon_slave_0_saved_chosen_master_vector <= 0;
      else if (sram_0_avalon_slave_0_allow_new_arb_cycle)
          sram_0_avalon_slave_0_saved_chosen_master_vector <= |sram_0_avalon_slave_0_grant_vector ? sram_0_avalon_slave_0_grant_vector : sram_0_avalon_slave_0_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign sram_0_avalon_slave_0_grant_vector = {(sram_0_avalon_slave_0_chosen_master_double_vector[1] | sram_0_avalon_slave_0_chosen_master_double_vector[3]),
    (sram_0_avalon_slave_0_chosen_master_double_vector[0] | sram_0_avalon_slave_0_chosen_master_double_vector[2])};

  //sram_0/avalon_slave_0 chosen master rotated left, which is an e_assign
  assign sram_0_avalon_slave_0_chosen_master_rot_left = (sram_0_avalon_slave_0_arb_winner << 1) ? (sram_0_avalon_slave_0_arb_winner << 1) : 1;

  //sram_0/avalon_slave_0's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_0_avalon_slave_0_arb_addend <= 1;
      else if (|sram_0_avalon_slave_0_grant_vector)
          sram_0_avalon_slave_0_arb_addend <= sram_0_avalon_slave_0_end_xfer? sram_0_avalon_slave_0_chosen_master_rot_left : sram_0_avalon_slave_0_grant_vector;
    end


  assign sram_0_avalon_slave_0_chipselect_n = ~(system_0_burst_14_downstream_granted_sram_0_avalon_slave_0 | system_0_burst_15_downstream_granted_sram_0_avalon_slave_0);
  //sram_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
  assign sram_0_avalon_slave_0_firsttransfer = sram_0_avalon_slave_0_begins_xfer ? sram_0_avalon_slave_0_unreg_firsttransfer : sram_0_avalon_slave_0_reg_firsttransfer;

  //sram_0_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
  assign sram_0_avalon_slave_0_unreg_firsttransfer = ~(sram_0_avalon_slave_0_slavearbiterlockenable & sram_0_avalon_slave_0_any_continuerequest);

  //sram_0_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_0_avalon_slave_0_reg_firsttransfer <= 1'b1;
      else if (sram_0_avalon_slave_0_begins_xfer)
          sram_0_avalon_slave_0_reg_firsttransfer <= sram_0_avalon_slave_0_unreg_firsttransfer;
    end


  //sram_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign sram_0_avalon_slave_0_beginbursttransfer_internal = sram_0_avalon_slave_0_begins_xfer;

  //sram_0_avalon_slave_0_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign sram_0_avalon_slave_0_arbitration_holdoff_internal = sram_0_avalon_slave_0_begins_xfer & sram_0_avalon_slave_0_firsttransfer;

  //~sram_0_avalon_slave_0_read_n assignment, which is an e_mux
  assign sram_0_avalon_slave_0_read_n = ~(((system_0_burst_14_downstream_granted_sram_0_avalon_slave_0 & system_0_burst_14_downstream_read) | (system_0_burst_15_downstream_granted_sram_0_avalon_slave_0 & system_0_burst_15_downstream_read))& ~sram_0_avalon_slave_0_begins_xfer & (sram_0_avalon_slave_0_wait_counter < 2));

  //~sram_0_avalon_slave_0_write_n assignment, which is an e_mux
  assign sram_0_avalon_slave_0_write_n = ~(((system_0_burst_14_downstream_granted_sram_0_avalon_slave_0 & system_0_burst_14_downstream_write) | (system_0_burst_15_downstream_granted_sram_0_avalon_slave_0 & system_0_burst_15_downstream_write)) & ~sram_0_avalon_slave_0_begins_xfer & (sram_0_avalon_slave_0_wait_counter >= 2) & (sram_0_avalon_slave_0_wait_counter < 4));

  assign shifted_address_to_sram_0_avalon_slave_0_from_system_0_burst_14_downstream = system_0_burst_14_downstream_address_to_slave;
  //sram_0_avalon_slave_0_address mux, which is an e_mux
  assign sram_0_avalon_slave_0_address = (system_0_burst_14_downstream_granted_sram_0_avalon_slave_0)? (shifted_address_to_sram_0_avalon_slave_0_from_system_0_burst_14_downstream >> 1) :
    (shifted_address_to_sram_0_avalon_slave_0_from_system_0_burst_15_downstream >> 1);

  assign shifted_address_to_sram_0_avalon_slave_0_from_system_0_burst_15_downstream = system_0_burst_15_downstream_address_to_slave;
  //d1_sram_0_avalon_slave_0_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_sram_0_avalon_slave_0_end_xfer <= 1;
      else 
        d1_sram_0_avalon_slave_0_end_xfer <= sram_0_avalon_slave_0_end_xfer;
    end


  //sram_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
  assign sram_0_avalon_slave_0_waits_for_read = sram_0_avalon_slave_0_in_a_read_cycle & wait_for_sram_0_avalon_slave_0_counter;

  //sram_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
  assign sram_0_avalon_slave_0_in_a_read_cycle = (system_0_burst_14_downstream_granted_sram_0_avalon_slave_0 & system_0_burst_14_downstream_read) | (system_0_burst_15_downstream_granted_sram_0_avalon_slave_0 & system_0_burst_15_downstream_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = sram_0_avalon_slave_0_in_a_read_cycle;

  //sram_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
  assign sram_0_avalon_slave_0_waits_for_write = sram_0_avalon_slave_0_in_a_write_cycle & wait_for_sram_0_avalon_slave_0_counter;

  //sram_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
  assign sram_0_avalon_slave_0_in_a_write_cycle = (system_0_burst_14_downstream_granted_sram_0_avalon_slave_0 & system_0_burst_14_downstream_write) | (system_0_burst_15_downstream_granted_sram_0_avalon_slave_0 & system_0_burst_15_downstream_write);

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = sram_0_avalon_slave_0_in_a_write_cycle;

  assign sram_0_avalon_slave_0_wait_counter_eq_0 = sram_0_avalon_slave_0_wait_counter == 0;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_0_avalon_slave_0_wait_counter <= 0;
      else 
        sram_0_avalon_slave_0_wait_counter <= sram_0_avalon_slave_0_counter_load_value;
    end


  assign sram_0_avalon_slave_0_counter_load_value = ((sram_0_avalon_slave_0_in_a_write_cycle & sram_0_avalon_slave_0_begins_xfer))? 4 :
    ((sram_0_avalon_slave_0_in_a_read_cycle & sram_0_avalon_slave_0_begins_xfer))? 2 :
    (~sram_0_avalon_slave_0_wait_counter_eq_0)? sram_0_avalon_slave_0_wait_counter - 1 :
    0;

  assign wait_for_sram_0_avalon_slave_0_counter = sram_0_avalon_slave_0_begins_xfer | ~sram_0_avalon_slave_0_wait_counter_eq_0;
  //~sram_0_avalon_slave_0_byteenable_n byte enable port mux, which is an e_mux
  assign sram_0_avalon_slave_0_byteenable_n = ~((system_0_burst_14_downstream_granted_sram_0_avalon_slave_0)? system_0_burst_14_downstream_byteenable :
    (system_0_burst_15_downstream_granted_sram_0_avalon_slave_0)? system_0_burst_15_downstream_byteenable :
    -1);


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //sram_0/avalon_slave_0 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_14/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_14_downstream_requests_sram_0_avalon_slave_0 && (system_0_burst_14_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_14/downstream drove 0 on its 'arbitrationshare' port while accessing slave sram_0/avalon_slave_0", $time);
          $stop;
        end
    end


  //system_0_burst_14/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_14_downstream_requests_sram_0_avalon_slave_0 && (system_0_burst_14_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_14/downstream drove 0 on its 'burstcount' port while accessing slave sram_0/avalon_slave_0", $time);
          $stop;
        end
    end


  //system_0_burst_15/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_15_downstream_requests_sram_0_avalon_slave_0 && (system_0_burst_15_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_15/downstream drove 0 on its 'arbitrationshare' port while accessing slave sram_0/avalon_slave_0", $time);
          $stop;
        end
    end


  //system_0_burst_15/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_15_downstream_requests_sram_0_avalon_slave_0 && (system_0_burst_15_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_15/downstream drove 0 on its 'burstcount' port while accessing slave sram_0/avalon_slave_0", $time);
          $stop;
        end
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_14_downstream_granted_sram_0_avalon_slave_0 + system_0_burst_15_downstream_granted_sram_0_avalon_slave_0 > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_14_downstream_saved_grant_sram_0_avalon_slave_0 + system_0_burst_15_downstream_saved_grant_sram_0_avalon_slave_0 > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_0_upstream_module (
                                                              // inputs:
                                                               clear_fifo,
                                                               clk,
                                                               data_in,
                                                               read,
                                                               reset_n,
                                                               sync_reset,
                                                               write,

                                                              // outputs:
                                                               data_out,
                                                               empty,
                                                               fifo_contains_ones_n,
                                                               full
                                                            )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_0_upstream_module (
                                                                                   // inputs:
                                                                                    clear_fifo,
                                                                                    clk,
                                                                                    data_in,
                                                                                    read,
                                                                                    reset_n,
                                                                                    sync_reset,
                                                                                    write,

                                                                                   // outputs:
                                                                                    data_out,
                                                                                    empty,
                                                                                    fifo_contains_ones_n,
                                                                                    full
                                                                                 )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_0_upstream_arbitrator (
                                              // inputs:
                                               clk,
                                               cpu_0_instruction_master_address_to_slave,
                                               cpu_0_instruction_master_burstcount,
                                               cpu_0_instruction_master_latency_counter,
                                               cpu_0_instruction_master_read,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register,
                                               reset_n,
                                               system_0_burst_0_upstream_readdata,
                                               system_0_burst_0_upstream_readdatavalid,
                                               system_0_burst_0_upstream_waitrequest,

                                              // outputs:
                                               cpu_0_instruction_master_granted_system_0_burst_0_upstream,
                                               cpu_0_instruction_master_qualified_request_system_0_burst_0_upstream,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register,
                                               cpu_0_instruction_master_requests_system_0_burst_0_upstream,
                                               d1_system_0_burst_0_upstream_end_xfer,
                                               system_0_burst_0_upstream_address,
                                               system_0_burst_0_upstream_byteaddress,
                                               system_0_burst_0_upstream_byteenable,
                                               system_0_burst_0_upstream_debugaccess,
                                               system_0_burst_0_upstream_read,
                                               system_0_burst_0_upstream_readdata_from_sa,
                                               system_0_burst_0_upstream_waitrequest_from_sa,
                                               system_0_burst_0_upstream_write
                                            )
;

  output           cpu_0_instruction_master_granted_system_0_burst_0_upstream;
  output           cpu_0_instruction_master_qualified_request_system_0_burst_0_upstream;
  output           cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream;
  output           cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register;
  output           cpu_0_instruction_master_requests_system_0_burst_0_upstream;
  output           d1_system_0_burst_0_upstream_end_xfer;
  output  [ 10: 0] system_0_burst_0_upstream_address;
  output  [ 12: 0] system_0_burst_0_upstream_byteaddress;
  output  [  3: 0] system_0_burst_0_upstream_byteenable;
  output           system_0_burst_0_upstream_debugaccess;
  output           system_0_burst_0_upstream_read;
  output  [ 31: 0] system_0_burst_0_upstream_readdata_from_sa;
  output           system_0_burst_0_upstream_waitrequest_from_sa;
  output           system_0_burst_0_upstream_write;
  input            clk;
  input   [ 24: 0] cpu_0_instruction_master_address_to_slave;
  input   [  3: 0] cpu_0_instruction_master_burstcount;
  input            cpu_0_instruction_master_latency_counter;
  input            cpu_0_instruction_master_read;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register;
  input            reset_n;
  input   [ 31: 0] system_0_burst_0_upstream_readdata;
  input            system_0_burst_0_upstream_readdatavalid;
  input            system_0_burst_0_upstream_waitrequest;

  wire             cpu_0_instruction_master_arbiterlock;
  wire             cpu_0_instruction_master_arbiterlock2;
  wire             cpu_0_instruction_master_continuerequest;
  wire             cpu_0_instruction_master_granted_system_0_burst_0_upstream;
  wire             cpu_0_instruction_master_qualified_request_system_0_burst_0_upstream;
  wire             cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_0_upstream;
  wire             cpu_0_instruction_master_rdv_fifo_output_from_system_0_burst_0_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register;
  wire             cpu_0_instruction_master_requests_system_0_burst_0_upstream;
  wire             cpu_0_instruction_master_saved_grant_system_0_burst_0_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_0_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_0_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_0_upstream_load_fifo;
  wire    [ 10: 0] system_0_burst_0_upstream_address;
  wire             system_0_burst_0_upstream_allgrants;
  wire             system_0_burst_0_upstream_allow_new_arb_cycle;
  wire             system_0_burst_0_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_0_upstream_any_continuerequest;
  wire             system_0_burst_0_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_0_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_0_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_0_upstream_arb_share_set_values;
  wire             system_0_burst_0_upstream_beginbursttransfer_internal;
  wire             system_0_burst_0_upstream_begins_xfer;
  wire             system_0_burst_0_upstream_burstcount_fifo_empty;
  wire    [ 12: 0] system_0_burst_0_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_0_upstream_byteenable;
  reg     [  3: 0] system_0_burst_0_upstream_current_burst;
  wire    [  3: 0] system_0_burst_0_upstream_current_burst_minus_one;
  wire             system_0_burst_0_upstream_debugaccess;
  wire             system_0_burst_0_upstream_end_xfer;
  wire             system_0_burst_0_upstream_firsttransfer;
  wire             system_0_burst_0_upstream_grant_vector;
  wire             system_0_burst_0_upstream_in_a_read_cycle;
  wire             system_0_burst_0_upstream_in_a_write_cycle;
  reg              system_0_burst_0_upstream_load_fifo;
  wire             system_0_burst_0_upstream_master_qreq_vector;
  wire             system_0_burst_0_upstream_move_on_to_next_transaction;
  wire    [  3: 0] system_0_burst_0_upstream_next_burst_count;
  wire             system_0_burst_0_upstream_non_bursting_master_requests;
  wire             system_0_burst_0_upstream_read;
  wire    [ 31: 0] system_0_burst_0_upstream_readdata_from_sa;
  wire             system_0_burst_0_upstream_readdatavalid_from_sa;
  reg              system_0_burst_0_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_0_upstream_selected_burstcount;
  reg              system_0_burst_0_upstream_slavearbiterlockenable;
  wire             system_0_burst_0_upstream_slavearbiterlockenable2;
  wire             system_0_burst_0_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_0_upstream_transaction_burst_count;
  wire             system_0_burst_0_upstream_unreg_firsttransfer;
  wire             system_0_burst_0_upstream_waitrequest_from_sa;
  wire             system_0_burst_0_upstream_waits_for_read;
  wire             system_0_burst_0_upstream_waits_for_write;
  wire             system_0_burst_0_upstream_write;
  wire             wait_for_system_0_burst_0_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_0_upstream_end_xfer;
    end


  assign system_0_burst_0_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_instruction_master_qualified_request_system_0_burst_0_upstream));
  //assign system_0_burst_0_upstream_readdata_from_sa = system_0_burst_0_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_0_upstream_readdata_from_sa = system_0_burst_0_upstream_readdata;

  assign cpu_0_instruction_master_requests_system_0_burst_0_upstream = (({cpu_0_instruction_master_address_to_slave[24 : 11] , 11'b0} == 25'h1909000) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
  //assign system_0_burst_0_upstream_waitrequest_from_sa = system_0_burst_0_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_0_upstream_waitrequest_from_sa = system_0_burst_0_upstream_waitrequest;

  //assign system_0_burst_0_upstream_readdatavalid_from_sa = system_0_burst_0_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_0_upstream_readdatavalid_from_sa = system_0_burst_0_upstream_readdatavalid;

  //system_0_burst_0_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_0_upstream_arb_share_set_values = 1;

  //system_0_burst_0_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_0_upstream_non_bursting_master_requests = 0;

  //system_0_burst_0_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_0_upstream_any_bursting_master_saved_grant = cpu_0_instruction_master_saved_grant_system_0_burst_0_upstream;

  //system_0_burst_0_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_0_upstream_arb_share_counter_next_value = system_0_burst_0_upstream_firsttransfer ? (system_0_burst_0_upstream_arb_share_set_values - 1) : |system_0_burst_0_upstream_arb_share_counter ? (system_0_burst_0_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_0_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_0_upstream_allgrants = |system_0_burst_0_upstream_grant_vector;

  //system_0_burst_0_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_0_upstream_end_xfer = ~(system_0_burst_0_upstream_waits_for_read | system_0_burst_0_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_0_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_0_upstream = system_0_burst_0_upstream_end_xfer & (~system_0_burst_0_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_0_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_0_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_0_upstream & system_0_burst_0_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_0_upstream & ~system_0_burst_0_upstream_non_bursting_master_requests);

  //system_0_burst_0_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_0_upstream_arb_share_counter <= 0;
      else if (system_0_burst_0_upstream_arb_counter_enable)
          system_0_burst_0_upstream_arb_share_counter <= system_0_burst_0_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_0_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_0_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_0_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_0_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_0_upstream & ~system_0_burst_0_upstream_non_bursting_master_requests))
          system_0_burst_0_upstream_slavearbiterlockenable <= |system_0_burst_0_upstream_arb_share_counter_next_value;
    end


  //cpu_0/instruction_master system_0_burst_0/upstream arbiterlock, which is an e_assign
  assign cpu_0_instruction_master_arbiterlock = system_0_burst_0_upstream_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;

  //system_0_burst_0_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_0_upstream_slavearbiterlockenable2 = |system_0_burst_0_upstream_arb_share_counter_next_value;

  //cpu_0/instruction_master system_0_burst_0/upstream arbiterlock2, which is an e_assign
  assign cpu_0_instruction_master_arbiterlock2 = system_0_burst_0_upstream_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;

  //system_0_burst_0_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_0_upstream_any_continuerequest = 1;

  //cpu_0_instruction_master_continuerequest continued request, which is an e_assign
  assign cpu_0_instruction_master_continuerequest = 1;

  assign cpu_0_instruction_master_qualified_request_system_0_burst_0_upstream = cpu_0_instruction_master_requests_system_0_burst_0_upstream & ~((cpu_0_instruction_master_read & ((cpu_0_instruction_master_latency_counter != 0) | (1 < cpu_0_instruction_master_latency_counter) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register))));
  //unique name for system_0_burst_0_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_0_upstream_move_on_to_next_transaction = system_0_burst_0_upstream_this_cycle_is_the_last_burst & system_0_burst_0_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_0_upstream, which is an e_mux
  assign system_0_burst_0_upstream_selected_burstcount = (cpu_0_instruction_master_granted_system_0_burst_0_upstream)? cpu_0_instruction_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_0_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_0_upstream_module burstcount_fifo_for_system_0_burst_0_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_0_upstream_selected_burstcount),
      .data_out             (system_0_burst_0_upstream_transaction_burst_count),
      .empty                (system_0_burst_0_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_0_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_0_upstream_waits_for_read & system_0_burst_0_upstream_load_fifo & ~(system_0_burst_0_upstream_this_cycle_is_the_last_burst & system_0_burst_0_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_0_upstream current burst minus one, which is an e_assign
  assign system_0_burst_0_upstream_current_burst_minus_one = system_0_burst_0_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_0_upstream, which is an e_mux
  assign system_0_burst_0_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_0_upstream_waits_for_read) & ~system_0_burst_0_upstream_load_fifo))? system_0_burst_0_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_0_upstream_waits_for_read & system_0_burst_0_upstream_this_cycle_is_the_last_burst & system_0_burst_0_upstream_burstcount_fifo_empty))? system_0_burst_0_upstream_selected_burstcount :
    (system_0_burst_0_upstream_this_cycle_is_the_last_burst)? system_0_burst_0_upstream_transaction_burst_count :
    system_0_burst_0_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_0_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_0_upstream_current_burst <= 0;
      else if (system_0_burst_0_upstream_readdatavalid_from_sa | (~system_0_burst_0_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_0_upstream_waits_for_read)))
          system_0_burst_0_upstream_current_burst <= system_0_burst_0_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_0_upstream_load_fifo = (~system_0_burst_0_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_0_upstream_waits_for_read) & system_0_burst_0_upstream_load_fifo))? 1 :
    ~system_0_burst_0_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_0_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_0_upstream_waits_for_read) & ~system_0_burst_0_upstream_load_fifo | system_0_burst_0_upstream_this_cycle_is_the_last_burst)
          system_0_burst_0_upstream_load_fifo <= p0_system_0_burst_0_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_0_upstream, which is an e_assign
  assign system_0_burst_0_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_0_upstream_current_burst_minus_one) & system_0_burst_0_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_0_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_0_upstream_module rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_0_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_instruction_master_granted_system_0_burst_0_upstream),
      .data_out             (cpu_0_instruction_master_rdv_fifo_output_from_system_0_burst_0_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_0_upstream),
      .full                 (),
      .read                 (system_0_burst_0_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_0_upstream_waits_for_read)
    );

  assign cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register = ~cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_0_upstream;
  //local readdatavalid cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream, which is an e_mux
  assign cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream = system_0_burst_0_upstream_readdatavalid_from_sa;

  //byteaddress mux for system_0_burst_0/upstream, which is an e_mux
  assign system_0_burst_0_upstream_byteaddress = cpu_0_instruction_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_instruction_master_granted_system_0_burst_0_upstream = cpu_0_instruction_master_qualified_request_system_0_burst_0_upstream;

  //cpu_0/instruction_master saved-grant system_0_burst_0/upstream, which is an e_assign
  assign cpu_0_instruction_master_saved_grant_system_0_burst_0_upstream = cpu_0_instruction_master_requests_system_0_burst_0_upstream;

  //allow new arb cycle for system_0_burst_0/upstream, which is an e_assign
  assign system_0_burst_0_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_0_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_0_upstream_master_qreq_vector = 1;

  //system_0_burst_0_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_0_upstream_firsttransfer = system_0_burst_0_upstream_begins_xfer ? system_0_burst_0_upstream_unreg_firsttransfer : system_0_burst_0_upstream_reg_firsttransfer;

  //system_0_burst_0_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_0_upstream_unreg_firsttransfer = ~(system_0_burst_0_upstream_slavearbiterlockenable & system_0_burst_0_upstream_any_continuerequest);

  //system_0_burst_0_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_0_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_0_upstream_begins_xfer)
          system_0_burst_0_upstream_reg_firsttransfer <= system_0_burst_0_upstream_unreg_firsttransfer;
    end


  //system_0_burst_0_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_0_upstream_beginbursttransfer_internal = system_0_burst_0_upstream_begins_xfer;

  //system_0_burst_0_upstream_read assignment, which is an e_mux
  assign system_0_burst_0_upstream_read = cpu_0_instruction_master_granted_system_0_burst_0_upstream & cpu_0_instruction_master_read;

  //system_0_burst_0_upstream_write assignment, which is an e_mux
  assign system_0_burst_0_upstream_write = 0;

  //system_0_burst_0_upstream_address mux, which is an e_mux
  assign system_0_burst_0_upstream_address = cpu_0_instruction_master_address_to_slave;

  //d1_system_0_burst_0_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_0_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_0_upstream_end_xfer <= system_0_burst_0_upstream_end_xfer;
    end


  //system_0_burst_0_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_0_upstream_waits_for_read = system_0_burst_0_upstream_in_a_read_cycle & system_0_burst_0_upstream_waitrequest_from_sa;

  //system_0_burst_0_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_0_upstream_in_a_read_cycle = cpu_0_instruction_master_granted_system_0_burst_0_upstream & cpu_0_instruction_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_0_upstream_in_a_read_cycle;

  //system_0_burst_0_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_0_upstream_waits_for_write = system_0_burst_0_upstream_in_a_write_cycle & system_0_burst_0_upstream_waitrequest_from_sa;

  //system_0_burst_0_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_0_upstream_in_a_write_cycle = 0;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_0_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_0_upstream_counter = 0;
  //system_0_burst_0_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_0_upstream_byteenable = -1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_0_upstream_debugaccess = 0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_0/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/instruction_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_instruction_master_requests_system_0_burst_0_upstream && (cpu_0_instruction_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/instruction_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_0/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_0_downstream_arbitrator (
                                                // inputs:
                                                 clk,
                                                 cpu_0_jtag_debug_module_readdata_from_sa,
                                                 d1_cpu_0_jtag_debug_module_end_xfer,
                                                 reset_n,
                                                 system_0_burst_0_downstream_address,
                                                 system_0_burst_0_downstream_burstcount,
                                                 system_0_burst_0_downstream_byteenable,
                                                 system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module,
                                                 system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module,
                                                 system_0_burst_0_downstream_read,
                                                 system_0_burst_0_downstream_read_data_valid_cpu_0_jtag_debug_module,
                                                 system_0_burst_0_downstream_requests_cpu_0_jtag_debug_module,
                                                 system_0_burst_0_downstream_write,
                                                 system_0_burst_0_downstream_writedata,

                                                // outputs:
                                                 system_0_burst_0_downstream_address_to_slave,
                                                 system_0_burst_0_downstream_latency_counter,
                                                 system_0_burst_0_downstream_readdata,
                                                 system_0_burst_0_downstream_readdatavalid,
                                                 system_0_burst_0_downstream_reset_n,
                                                 system_0_burst_0_downstream_waitrequest
                                              )
;

  output  [ 10: 0] system_0_burst_0_downstream_address_to_slave;
  output           system_0_burst_0_downstream_latency_counter;
  output  [ 31: 0] system_0_burst_0_downstream_readdata;
  output           system_0_burst_0_downstream_readdatavalid;
  output           system_0_burst_0_downstream_reset_n;
  output           system_0_burst_0_downstream_waitrequest;
  input            clk;
  input   [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
  input            d1_cpu_0_jtag_debug_module_end_xfer;
  input            reset_n;
  input   [ 10: 0] system_0_burst_0_downstream_address;
  input            system_0_burst_0_downstream_burstcount;
  input   [  3: 0] system_0_burst_0_downstream_byteenable;
  input            system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module;
  input            system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module;
  input            system_0_burst_0_downstream_read;
  input            system_0_burst_0_downstream_read_data_valid_cpu_0_jtag_debug_module;
  input            system_0_burst_0_downstream_requests_cpu_0_jtag_debug_module;
  input            system_0_burst_0_downstream_write;
  input   [ 31: 0] system_0_burst_0_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             latency_load_value;
  wire             p1_system_0_burst_0_downstream_latency_counter;
  wire             pre_flush_system_0_burst_0_downstream_readdatavalid;
  wire             r_0;
  reg     [ 10: 0] system_0_burst_0_downstream_address_last_time;
  wire    [ 10: 0] system_0_burst_0_downstream_address_to_slave;
  reg              system_0_burst_0_downstream_burstcount_last_time;
  reg     [  3: 0] system_0_burst_0_downstream_byteenable_last_time;
  wire             system_0_burst_0_downstream_is_granted_some_slave;
  reg              system_0_burst_0_downstream_latency_counter;
  reg              system_0_burst_0_downstream_read_but_no_slave_selected;
  reg              system_0_burst_0_downstream_read_last_time;
  wire    [ 31: 0] system_0_burst_0_downstream_readdata;
  wire             system_0_burst_0_downstream_readdatavalid;
  wire             system_0_burst_0_downstream_reset_n;
  wire             system_0_burst_0_downstream_run;
  wire             system_0_burst_0_downstream_waitrequest;
  reg              system_0_burst_0_downstream_write_last_time;
  reg     [ 31: 0] system_0_burst_0_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module | ~system_0_burst_0_downstream_requests_cpu_0_jtag_debug_module) & (system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module | ~system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module) & ((~system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module | ~system_0_burst_0_downstream_read | (1 & ~d1_cpu_0_jtag_debug_module_end_xfer & system_0_burst_0_downstream_read))) & ((~system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module | ~system_0_burst_0_downstream_write | (1 & system_0_burst_0_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_0_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_0_downstream_address_to_slave = system_0_burst_0_downstream_address;

  //system_0_burst_0_downstream_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_0_downstream_read_but_no_slave_selected <= 0;
      else 
        system_0_burst_0_downstream_read_but_no_slave_selected <= system_0_burst_0_downstream_read & system_0_burst_0_downstream_run & ~system_0_burst_0_downstream_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign system_0_burst_0_downstream_is_granted_some_slave = system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_0_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_0_downstream_readdatavalid = system_0_burst_0_downstream_read_but_no_slave_selected |
    pre_flush_system_0_burst_0_downstream_readdatavalid |
    system_0_burst_0_downstream_read_data_valid_cpu_0_jtag_debug_module;

  //system_0_burst_0/downstream readdata mux, which is an e_mux
  assign system_0_burst_0_downstream_readdata = cpu_0_jtag_debug_module_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_0_downstream_waitrequest = ~system_0_burst_0_downstream_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_0_downstream_latency_counter <= 0;
      else 
        system_0_burst_0_downstream_latency_counter <= p1_system_0_burst_0_downstream_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_system_0_burst_0_downstream_latency_counter = ((system_0_burst_0_downstream_run & system_0_burst_0_downstream_read))? latency_load_value :
    (system_0_burst_0_downstream_latency_counter)? system_0_burst_0_downstream_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = 0;

  //system_0_burst_0_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_0_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_0_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_0_downstream_address_last_time <= 0;
      else 
        system_0_burst_0_downstream_address_last_time <= system_0_burst_0_downstream_address;
    end


  //system_0_burst_0/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_0_downstream_waitrequest & (system_0_burst_0_downstream_read | system_0_burst_0_downstream_write);
    end


  //system_0_burst_0_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_0_downstream_address != system_0_burst_0_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_0_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_0_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_0_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_0_downstream_burstcount_last_time <= system_0_burst_0_downstream_burstcount;
    end


  //system_0_burst_0_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_0_downstream_burstcount != system_0_burst_0_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_0_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_0_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_0_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_0_downstream_byteenable_last_time <= system_0_burst_0_downstream_byteenable;
    end


  //system_0_burst_0_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_0_downstream_byteenable != system_0_burst_0_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_0_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_0_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_0_downstream_read_last_time <= 0;
      else 
        system_0_burst_0_downstream_read_last_time <= system_0_burst_0_downstream_read;
    end


  //system_0_burst_0_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_0_downstream_read != system_0_burst_0_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_0_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_0_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_0_downstream_write_last_time <= 0;
      else 
        system_0_burst_0_downstream_write_last_time <= system_0_burst_0_downstream_write;
    end


  //system_0_burst_0_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_0_downstream_write != system_0_burst_0_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_0_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_0_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_0_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_0_downstream_writedata_last_time <= system_0_burst_0_downstream_writedata;
    end


  //system_0_burst_0_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_0_downstream_writedata != system_0_burst_0_downstream_writedata_last_time) & system_0_burst_0_downstream_write)
        begin
          $write("%0d ns: system_0_burst_0_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_1_upstream_module (
                                                              // inputs:
                                                               clear_fifo,
                                                               clk,
                                                               data_in,
                                                               read,
                                                               reset_n,
                                                               sync_reset,
                                                               write,

                                                              // outputs:
                                                               data_out,
                                                               empty,
                                                               fifo_contains_ones_n,
                                                               full
                                                            )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_1_upstream_module (
                                                                            // inputs:
                                                                             clear_fifo,
                                                                             clk,
                                                                             data_in,
                                                                             read,
                                                                             reset_n,
                                                                             sync_reset,
                                                                             write,

                                                                            // outputs:
                                                                             data_out,
                                                                             empty,
                                                                             fifo_contains_ones_n,
                                                                             full
                                                                          )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_1_upstream_arbitrator (
                                              // inputs:
                                               clk,
                                               cpu_0_data_master_address_to_slave,
                                               cpu_0_data_master_burstcount,
                                               cpu_0_data_master_byteenable,
                                               cpu_0_data_master_debugaccess,
                                               cpu_0_data_master_latency_counter,
                                               cpu_0_data_master_read,
                                               cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                               cpu_0_data_master_write,
                                               cpu_0_data_master_writedata,
                                               reset_n,
                                               system_0_burst_1_upstream_readdata,
                                               system_0_burst_1_upstream_readdatavalid,
                                               system_0_burst_1_upstream_waitrequest,

                                              // outputs:
                                               cpu_0_data_master_granted_system_0_burst_1_upstream,
                                               cpu_0_data_master_qualified_request_system_0_burst_1_upstream,
                                               cpu_0_data_master_read_data_valid_system_0_burst_1_upstream,
                                               cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                               cpu_0_data_master_requests_system_0_burst_1_upstream,
                                               d1_system_0_burst_1_upstream_end_xfer,
                                               system_0_burst_1_upstream_address,
                                               system_0_burst_1_upstream_burstcount,
                                               system_0_burst_1_upstream_byteaddress,
                                               system_0_burst_1_upstream_byteenable,
                                               system_0_burst_1_upstream_debugaccess,
                                               system_0_burst_1_upstream_read,
                                               system_0_burst_1_upstream_readdata_from_sa,
                                               system_0_burst_1_upstream_waitrequest_from_sa,
                                               system_0_burst_1_upstream_write,
                                               system_0_burst_1_upstream_writedata
                                            )
;

  output           cpu_0_data_master_granted_system_0_burst_1_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_1_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_1_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_1_upstream;
  output           d1_system_0_burst_1_upstream_end_xfer;
  output  [ 10: 0] system_0_burst_1_upstream_address;
  output  [  3: 0] system_0_burst_1_upstream_burstcount;
  output  [ 12: 0] system_0_burst_1_upstream_byteaddress;
  output  [  3: 0] system_0_burst_1_upstream_byteenable;
  output           system_0_burst_1_upstream_debugaccess;
  output           system_0_burst_1_upstream_read;
  output  [ 31: 0] system_0_burst_1_upstream_readdata_from_sa;
  output           system_0_burst_1_upstream_waitrequest_from_sa;
  output           system_0_burst_1_upstream_write;
  output  [ 31: 0] system_0_burst_1_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [ 31: 0] system_0_burst_1_upstream_readdata;
  input            system_0_burst_1_upstream_readdatavalid;
  input            system_0_burst_1_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_1_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_1_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_1_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_1_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_1_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_1_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_1_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_1_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_1_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_1_upstream_load_fifo;
  wire    [ 10: 0] system_0_burst_1_upstream_address;
  wire             system_0_burst_1_upstream_allgrants;
  wire             system_0_burst_1_upstream_allow_new_arb_cycle;
  wire             system_0_burst_1_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_1_upstream_any_continuerequest;
  wire             system_0_burst_1_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_1_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_1_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_1_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_1_upstream_bbt_burstcounter;
  wire             system_0_burst_1_upstream_beginbursttransfer_internal;
  wire             system_0_burst_1_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_1_upstream_burstcount;
  wire             system_0_burst_1_upstream_burstcount_fifo_empty;
  wire    [ 12: 0] system_0_burst_1_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_1_upstream_byteenable;
  reg     [  3: 0] system_0_burst_1_upstream_current_burst;
  wire    [  3: 0] system_0_burst_1_upstream_current_burst_minus_one;
  wire             system_0_burst_1_upstream_debugaccess;
  wire             system_0_burst_1_upstream_end_xfer;
  wire             system_0_burst_1_upstream_firsttransfer;
  wire             system_0_burst_1_upstream_grant_vector;
  wire             system_0_burst_1_upstream_in_a_read_cycle;
  wire             system_0_burst_1_upstream_in_a_write_cycle;
  reg              system_0_burst_1_upstream_load_fifo;
  wire             system_0_burst_1_upstream_master_qreq_vector;
  wire             system_0_burst_1_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_1_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_1_upstream_next_burst_count;
  wire             system_0_burst_1_upstream_non_bursting_master_requests;
  wire             system_0_burst_1_upstream_read;
  wire    [ 31: 0] system_0_burst_1_upstream_readdata_from_sa;
  wire             system_0_burst_1_upstream_readdatavalid_from_sa;
  reg              system_0_burst_1_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_1_upstream_selected_burstcount;
  reg              system_0_burst_1_upstream_slavearbiterlockenable;
  wire             system_0_burst_1_upstream_slavearbiterlockenable2;
  wire             system_0_burst_1_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_1_upstream_transaction_burst_count;
  wire             system_0_burst_1_upstream_unreg_firsttransfer;
  wire             system_0_burst_1_upstream_waitrequest_from_sa;
  wire             system_0_burst_1_upstream_waits_for_read;
  wire             system_0_burst_1_upstream_waits_for_write;
  wire             system_0_burst_1_upstream_write;
  wire    [ 31: 0] system_0_burst_1_upstream_writedata;
  wire             wait_for_system_0_burst_1_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_1_upstream_end_xfer;
    end


  assign system_0_burst_1_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_1_upstream));
  //assign system_0_burst_1_upstream_readdata_from_sa = system_0_burst_1_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_1_upstream_readdata_from_sa = system_0_burst_1_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_1_upstream = ({cpu_0_data_master_address_to_slave[24 : 11] , 11'b0} == 25'h1909000) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_1_upstream_waitrequest_from_sa = system_0_burst_1_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_1_upstream_waitrequest_from_sa = system_0_burst_1_upstream_waitrequest;

  //assign system_0_burst_1_upstream_readdatavalid_from_sa = system_0_burst_1_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_1_upstream_readdatavalid_from_sa = system_0_burst_1_upstream_readdatavalid;

  //system_0_burst_1_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_1_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_1_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_1_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_1_upstream_non_bursting_master_requests = 0;

  //system_0_burst_1_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_1_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_1_upstream;

  //system_0_burst_1_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_1_upstream_arb_share_counter_next_value = system_0_burst_1_upstream_firsttransfer ? (system_0_burst_1_upstream_arb_share_set_values - 1) : |system_0_burst_1_upstream_arb_share_counter ? (system_0_burst_1_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_1_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_1_upstream_allgrants = |system_0_burst_1_upstream_grant_vector;

  //system_0_burst_1_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_1_upstream_end_xfer = ~(system_0_burst_1_upstream_waits_for_read | system_0_burst_1_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_1_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_1_upstream = system_0_burst_1_upstream_end_xfer & (~system_0_burst_1_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_1_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_1_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_1_upstream & system_0_burst_1_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_1_upstream & ~system_0_burst_1_upstream_non_bursting_master_requests);

  //system_0_burst_1_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_1_upstream_arb_share_counter <= 0;
      else if (system_0_burst_1_upstream_arb_counter_enable)
          system_0_burst_1_upstream_arb_share_counter <= system_0_burst_1_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_1_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_1_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_1_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_1_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_1_upstream & ~system_0_burst_1_upstream_non_bursting_master_requests))
          system_0_burst_1_upstream_slavearbiterlockenable <= |system_0_burst_1_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_1/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_1_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_1_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_1_upstream_slavearbiterlockenable2 = |system_0_burst_1_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_1/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_1_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_1_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_1_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_1_upstream = cpu_0_data_master_requests_system_0_burst_1_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_1_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_1_upstream_move_on_to_next_transaction = system_0_burst_1_upstream_this_cycle_is_the_last_burst & system_0_burst_1_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_1_upstream, which is an e_mux
  assign system_0_burst_1_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_1_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_1_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_1_upstream_module burstcount_fifo_for_system_0_burst_1_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_1_upstream_selected_burstcount),
      .data_out             (system_0_burst_1_upstream_transaction_burst_count),
      .empty                (system_0_burst_1_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_1_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_1_upstream_waits_for_read & system_0_burst_1_upstream_load_fifo & ~(system_0_burst_1_upstream_this_cycle_is_the_last_burst & system_0_burst_1_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_1_upstream current burst minus one, which is an e_assign
  assign system_0_burst_1_upstream_current_burst_minus_one = system_0_burst_1_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_1_upstream, which is an e_mux
  assign system_0_burst_1_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_1_upstream_waits_for_read) & ~system_0_burst_1_upstream_load_fifo))? system_0_burst_1_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_1_upstream_waits_for_read & system_0_burst_1_upstream_this_cycle_is_the_last_burst & system_0_burst_1_upstream_burstcount_fifo_empty))? system_0_burst_1_upstream_selected_burstcount :
    (system_0_burst_1_upstream_this_cycle_is_the_last_burst)? system_0_burst_1_upstream_transaction_burst_count :
    system_0_burst_1_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_1_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_1_upstream_current_burst <= 0;
      else if (system_0_burst_1_upstream_readdatavalid_from_sa | (~system_0_burst_1_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_1_upstream_waits_for_read)))
          system_0_burst_1_upstream_current_burst <= system_0_burst_1_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_1_upstream_load_fifo = (~system_0_burst_1_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_1_upstream_waits_for_read) & system_0_burst_1_upstream_load_fifo))? 1 :
    ~system_0_burst_1_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_1_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_1_upstream_waits_for_read) & ~system_0_burst_1_upstream_load_fifo | system_0_burst_1_upstream_this_cycle_is_the_last_burst)
          system_0_burst_1_upstream_load_fifo <= p0_system_0_burst_1_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_1_upstream, which is an e_assign
  assign system_0_burst_1_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_1_upstream_current_burst_minus_one) & system_0_burst_1_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_1_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_1_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_1_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_1_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_1_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_1_upstream),
      .full                 (),
      .read                 (system_0_burst_1_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_1_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_1_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_1_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_1_upstream = system_0_burst_1_upstream_readdatavalid_from_sa;

  //system_0_burst_1_upstream_writedata mux, which is an e_mux
  assign system_0_burst_1_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_1/upstream, which is an e_mux
  assign system_0_burst_1_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_1_upstream = cpu_0_data_master_qualified_request_system_0_burst_1_upstream;

  //cpu_0/data_master saved-grant system_0_burst_1/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_1_upstream = cpu_0_data_master_requests_system_0_burst_1_upstream;

  //allow new arb cycle for system_0_burst_1/upstream, which is an e_assign
  assign system_0_burst_1_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_1_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_1_upstream_master_qreq_vector = 1;

  //system_0_burst_1_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_1_upstream_firsttransfer = system_0_burst_1_upstream_begins_xfer ? system_0_burst_1_upstream_unreg_firsttransfer : system_0_burst_1_upstream_reg_firsttransfer;

  //system_0_burst_1_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_1_upstream_unreg_firsttransfer = ~(system_0_burst_1_upstream_slavearbiterlockenable & system_0_burst_1_upstream_any_continuerequest);

  //system_0_burst_1_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_1_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_1_upstream_begins_xfer)
          system_0_burst_1_upstream_reg_firsttransfer <= system_0_burst_1_upstream_unreg_firsttransfer;
    end


  //system_0_burst_1_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_1_upstream_next_bbt_burstcount = ((((system_0_burst_1_upstream_write) && (system_0_burst_1_upstream_bbt_burstcounter == 0))))? (system_0_burst_1_upstream_burstcount - 1) :
    ((((system_0_burst_1_upstream_read) && (system_0_burst_1_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_1_upstream_bbt_burstcounter - 1);

  //system_0_burst_1_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_1_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_1_upstream_begins_xfer)
          system_0_burst_1_upstream_bbt_burstcounter <= system_0_burst_1_upstream_next_bbt_burstcount;
    end


  //system_0_burst_1_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_1_upstream_beginbursttransfer_internal = system_0_burst_1_upstream_begins_xfer & (system_0_burst_1_upstream_bbt_burstcounter == 0);

  //system_0_burst_1_upstream_read assignment, which is an e_mux
  assign system_0_burst_1_upstream_read = cpu_0_data_master_granted_system_0_burst_1_upstream & cpu_0_data_master_read;

  //system_0_burst_1_upstream_write assignment, which is an e_mux
  assign system_0_burst_1_upstream_write = cpu_0_data_master_granted_system_0_burst_1_upstream & cpu_0_data_master_write;

  //system_0_burst_1_upstream_address mux, which is an e_mux
  assign system_0_burst_1_upstream_address = cpu_0_data_master_address_to_slave;

  //d1_system_0_burst_1_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_1_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_1_upstream_end_xfer <= system_0_burst_1_upstream_end_xfer;
    end


  //system_0_burst_1_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_1_upstream_waits_for_read = system_0_burst_1_upstream_in_a_read_cycle & system_0_burst_1_upstream_waitrequest_from_sa;

  //system_0_burst_1_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_1_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_1_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_1_upstream_in_a_read_cycle;

  //system_0_burst_1_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_1_upstream_waits_for_write = system_0_burst_1_upstream_in_a_write_cycle & system_0_burst_1_upstream_waitrequest_from_sa;

  //system_0_burst_1_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_1_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_1_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_1_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_1_upstream_counter = 0;
  //system_0_burst_1_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_1_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_1_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_1_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_1_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_1_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_1_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_1/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_1_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_1/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_1_downstream_arbitrator (
                                                // inputs:
                                                 clk,
                                                 cpu_0_jtag_debug_module_readdata_from_sa,
                                                 d1_cpu_0_jtag_debug_module_end_xfer,
                                                 reset_n,
                                                 system_0_burst_1_downstream_address,
                                                 system_0_burst_1_downstream_burstcount,
                                                 system_0_burst_1_downstream_byteenable,
                                                 system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module,
                                                 system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module,
                                                 system_0_burst_1_downstream_read,
                                                 system_0_burst_1_downstream_read_data_valid_cpu_0_jtag_debug_module,
                                                 system_0_burst_1_downstream_requests_cpu_0_jtag_debug_module,
                                                 system_0_burst_1_downstream_write,
                                                 system_0_burst_1_downstream_writedata,

                                                // outputs:
                                                 system_0_burst_1_downstream_address_to_slave,
                                                 system_0_burst_1_downstream_latency_counter,
                                                 system_0_burst_1_downstream_readdata,
                                                 system_0_burst_1_downstream_readdatavalid,
                                                 system_0_burst_1_downstream_reset_n,
                                                 system_0_burst_1_downstream_waitrequest
                                              )
;

  output  [ 10: 0] system_0_burst_1_downstream_address_to_slave;
  output           system_0_burst_1_downstream_latency_counter;
  output  [ 31: 0] system_0_burst_1_downstream_readdata;
  output           system_0_burst_1_downstream_readdatavalid;
  output           system_0_burst_1_downstream_reset_n;
  output           system_0_burst_1_downstream_waitrequest;
  input            clk;
  input   [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
  input            d1_cpu_0_jtag_debug_module_end_xfer;
  input            reset_n;
  input   [ 10: 0] system_0_burst_1_downstream_address;
  input            system_0_burst_1_downstream_burstcount;
  input   [  3: 0] system_0_burst_1_downstream_byteenable;
  input            system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module;
  input            system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module;
  input            system_0_burst_1_downstream_read;
  input            system_0_burst_1_downstream_read_data_valid_cpu_0_jtag_debug_module;
  input            system_0_burst_1_downstream_requests_cpu_0_jtag_debug_module;
  input            system_0_burst_1_downstream_write;
  input   [ 31: 0] system_0_burst_1_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             latency_load_value;
  wire             p1_system_0_burst_1_downstream_latency_counter;
  wire             pre_flush_system_0_burst_1_downstream_readdatavalid;
  wire             r_0;
  reg     [ 10: 0] system_0_burst_1_downstream_address_last_time;
  wire    [ 10: 0] system_0_burst_1_downstream_address_to_slave;
  reg              system_0_burst_1_downstream_burstcount_last_time;
  reg     [  3: 0] system_0_burst_1_downstream_byteenable_last_time;
  wire             system_0_burst_1_downstream_is_granted_some_slave;
  reg              system_0_burst_1_downstream_latency_counter;
  reg              system_0_burst_1_downstream_read_but_no_slave_selected;
  reg              system_0_burst_1_downstream_read_last_time;
  wire    [ 31: 0] system_0_burst_1_downstream_readdata;
  wire             system_0_burst_1_downstream_readdatavalid;
  wire             system_0_burst_1_downstream_reset_n;
  wire             system_0_burst_1_downstream_run;
  wire             system_0_burst_1_downstream_waitrequest;
  reg              system_0_burst_1_downstream_write_last_time;
  reg     [ 31: 0] system_0_burst_1_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module | ~system_0_burst_1_downstream_requests_cpu_0_jtag_debug_module) & (system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module | ~system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module) & ((~system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module | ~system_0_burst_1_downstream_read | (1 & ~d1_cpu_0_jtag_debug_module_end_xfer & system_0_burst_1_downstream_read))) & ((~system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module | ~system_0_burst_1_downstream_write | (1 & system_0_burst_1_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_1_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_1_downstream_address_to_slave = system_0_burst_1_downstream_address;

  //system_0_burst_1_downstream_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_1_downstream_read_but_no_slave_selected <= 0;
      else 
        system_0_burst_1_downstream_read_but_no_slave_selected <= system_0_burst_1_downstream_read & system_0_burst_1_downstream_run & ~system_0_burst_1_downstream_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign system_0_burst_1_downstream_is_granted_some_slave = system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_1_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_1_downstream_readdatavalid = system_0_burst_1_downstream_read_but_no_slave_selected |
    pre_flush_system_0_burst_1_downstream_readdatavalid |
    system_0_burst_1_downstream_read_data_valid_cpu_0_jtag_debug_module;

  //system_0_burst_1/downstream readdata mux, which is an e_mux
  assign system_0_burst_1_downstream_readdata = cpu_0_jtag_debug_module_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_1_downstream_waitrequest = ~system_0_burst_1_downstream_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_1_downstream_latency_counter <= 0;
      else 
        system_0_burst_1_downstream_latency_counter <= p1_system_0_burst_1_downstream_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_system_0_burst_1_downstream_latency_counter = ((system_0_burst_1_downstream_run & system_0_burst_1_downstream_read))? latency_load_value :
    (system_0_burst_1_downstream_latency_counter)? system_0_burst_1_downstream_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = 0;

  //system_0_burst_1_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_1_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_1_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_1_downstream_address_last_time <= 0;
      else 
        system_0_burst_1_downstream_address_last_time <= system_0_burst_1_downstream_address;
    end


  //system_0_burst_1/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_1_downstream_waitrequest & (system_0_burst_1_downstream_read | system_0_burst_1_downstream_write);
    end


  //system_0_burst_1_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_1_downstream_address != system_0_burst_1_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_1_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_1_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_1_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_1_downstream_burstcount_last_time <= system_0_burst_1_downstream_burstcount;
    end


  //system_0_burst_1_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_1_downstream_burstcount != system_0_burst_1_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_1_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_1_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_1_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_1_downstream_byteenable_last_time <= system_0_burst_1_downstream_byteenable;
    end


  //system_0_burst_1_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_1_downstream_byteenable != system_0_burst_1_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_1_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_1_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_1_downstream_read_last_time <= 0;
      else 
        system_0_burst_1_downstream_read_last_time <= system_0_burst_1_downstream_read;
    end


  //system_0_burst_1_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_1_downstream_read != system_0_burst_1_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_1_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_1_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_1_downstream_write_last_time <= 0;
      else 
        system_0_burst_1_downstream_write_last_time <= system_0_burst_1_downstream_write;
    end


  //system_0_burst_1_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_1_downstream_write != system_0_burst_1_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_1_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_1_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_1_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_1_downstream_writedata_last_time <= system_0_burst_1_downstream_writedata;
    end


  //system_0_burst_1_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_1_downstream_writedata != system_0_burst_1_downstream_writedata_last_time) & system_0_burst_1_downstream_write)
        begin
          $write("%0d ns: system_0_burst_1_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_10_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_10_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_10_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_10_upstream_readdata,
                                                system_0_burst_10_upstream_readdatavalid,
                                                system_0_burst_10_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_10_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_10_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_10_upstream,
                                                d1_system_0_burst_10_upstream_end_xfer,
                                                system_0_burst_10_upstream_address,
                                                system_0_burst_10_upstream_burstcount,
                                                system_0_burst_10_upstream_byteaddress,
                                                system_0_burst_10_upstream_byteenable,
                                                system_0_burst_10_upstream_debugaccess,
                                                system_0_burst_10_upstream_read,
                                                system_0_burst_10_upstream_readdata_from_sa,
                                                system_0_burst_10_upstream_waitrequest_from_sa,
                                                system_0_burst_10_upstream_write,
                                                system_0_burst_10_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_10_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_10_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_10_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_10_upstream;
  output           d1_system_0_burst_10_upstream_end_xfer;
  output  [  3: 0] system_0_burst_10_upstream_address;
  output  [  3: 0] system_0_burst_10_upstream_burstcount;
  output  [  4: 0] system_0_burst_10_upstream_byteaddress;
  output  [  1: 0] system_0_burst_10_upstream_byteenable;
  output           system_0_burst_10_upstream_debugaccess;
  output           system_0_burst_10_upstream_read;
  output  [ 15: 0] system_0_burst_10_upstream_readdata_from_sa;
  output           system_0_burst_10_upstream_waitrequest_from_sa;
  output           system_0_burst_10_upstream_write;
  output  [ 15: 0] system_0_burst_10_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [ 15: 0] system_0_burst_10_upstream_readdata;
  input            system_0_burst_10_upstream_readdatavalid;
  input            system_0_burst_10_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_10_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_10_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_10_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_10_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_10_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_10_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_10_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_10_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_10_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_10_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_10_upstream_from_cpu_0_data_master;
  wire    [  3: 0] system_0_burst_10_upstream_address;
  wire             system_0_burst_10_upstream_allgrants;
  wire             system_0_burst_10_upstream_allow_new_arb_cycle;
  wire             system_0_burst_10_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_10_upstream_any_continuerequest;
  wire             system_0_burst_10_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_10_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_10_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_10_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_10_upstream_bbt_burstcounter;
  wire             system_0_burst_10_upstream_beginbursttransfer_internal;
  wire             system_0_burst_10_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_10_upstream_burstcount;
  wire             system_0_burst_10_upstream_burstcount_fifo_empty;
  wire    [  4: 0] system_0_burst_10_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_10_upstream_byteenable;
  reg     [  3: 0] system_0_burst_10_upstream_current_burst;
  wire    [  3: 0] system_0_burst_10_upstream_current_burst_minus_one;
  wire             system_0_burst_10_upstream_debugaccess;
  wire             system_0_burst_10_upstream_end_xfer;
  wire             system_0_burst_10_upstream_firsttransfer;
  wire             system_0_burst_10_upstream_grant_vector;
  wire             system_0_burst_10_upstream_in_a_read_cycle;
  wire             system_0_burst_10_upstream_in_a_write_cycle;
  reg              system_0_burst_10_upstream_load_fifo;
  wire             system_0_burst_10_upstream_master_qreq_vector;
  wire             system_0_burst_10_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_10_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_10_upstream_next_burst_count;
  wire             system_0_burst_10_upstream_non_bursting_master_requests;
  wire             system_0_burst_10_upstream_read;
  wire    [ 15: 0] system_0_burst_10_upstream_readdata_from_sa;
  wire             system_0_burst_10_upstream_readdatavalid_from_sa;
  reg              system_0_burst_10_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_10_upstream_selected_burstcount;
  reg              system_0_burst_10_upstream_slavearbiterlockenable;
  wire             system_0_burst_10_upstream_slavearbiterlockenable2;
  wire             system_0_burst_10_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_10_upstream_transaction_burst_count;
  wire             system_0_burst_10_upstream_unreg_firsttransfer;
  wire             system_0_burst_10_upstream_waitrequest_from_sa;
  wire             system_0_burst_10_upstream_waits_for_read;
  wire             system_0_burst_10_upstream_waits_for_write;
  wire             system_0_burst_10_upstream_write;
  wire    [ 15: 0] system_0_burst_10_upstream_writedata;
  wire             wait_for_system_0_burst_10_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_10_upstream_end_xfer;
    end


  assign system_0_burst_10_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_10_upstream));
  //assign system_0_burst_10_upstream_readdatavalid_from_sa = system_0_burst_10_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_10_upstream_readdatavalid_from_sa = system_0_burst_10_upstream_readdatavalid;

  //assign system_0_burst_10_upstream_readdata_from_sa = system_0_burst_10_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_10_upstream_readdata_from_sa = system_0_burst_10_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_10_upstream = ({cpu_0_data_master_address_to_slave[24 : 5] , 5'b0} == 25'h190a040) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_10_upstream_waitrequest_from_sa = system_0_burst_10_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_10_upstream_waitrequest_from_sa = system_0_burst_10_upstream_waitrequest;

  //system_0_burst_10_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_10_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_10_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_10_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_10_upstream_non_bursting_master_requests = 0;

  //system_0_burst_10_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_10_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_10_upstream;

  //system_0_burst_10_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_10_upstream_arb_share_counter_next_value = system_0_burst_10_upstream_firsttransfer ? (system_0_burst_10_upstream_arb_share_set_values - 1) : |system_0_burst_10_upstream_arb_share_counter ? (system_0_burst_10_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_10_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_10_upstream_allgrants = |system_0_burst_10_upstream_grant_vector;

  //system_0_burst_10_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_10_upstream_end_xfer = ~(system_0_burst_10_upstream_waits_for_read | system_0_burst_10_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_10_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_10_upstream = system_0_burst_10_upstream_end_xfer & (~system_0_burst_10_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_10_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_10_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_10_upstream & system_0_burst_10_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_10_upstream & ~system_0_burst_10_upstream_non_bursting_master_requests);

  //system_0_burst_10_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_10_upstream_arb_share_counter <= 0;
      else if (system_0_burst_10_upstream_arb_counter_enable)
          system_0_burst_10_upstream_arb_share_counter <= system_0_burst_10_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_10_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_10_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_10_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_10_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_10_upstream & ~system_0_burst_10_upstream_non_bursting_master_requests))
          system_0_burst_10_upstream_slavearbiterlockenable <= |system_0_burst_10_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_10/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_10_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_10_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_10_upstream_slavearbiterlockenable2 = |system_0_burst_10_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_10/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_10_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_10_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_10_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_10_upstream = cpu_0_data_master_requests_system_0_burst_10_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_10_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_10_upstream_move_on_to_next_transaction = system_0_burst_10_upstream_this_cycle_is_the_last_burst & system_0_burst_10_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_10_upstream, which is an e_mux
  assign system_0_burst_10_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_10_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_10_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_10_upstream_module burstcount_fifo_for_system_0_burst_10_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_10_upstream_selected_burstcount),
      .data_out             (system_0_burst_10_upstream_transaction_burst_count),
      .empty                (system_0_burst_10_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_10_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_10_upstream_waits_for_read & system_0_burst_10_upstream_load_fifo & ~(system_0_burst_10_upstream_this_cycle_is_the_last_burst & system_0_burst_10_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_10_upstream current burst minus one, which is an e_assign
  assign system_0_burst_10_upstream_current_burst_minus_one = system_0_burst_10_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_10_upstream, which is an e_mux
  assign system_0_burst_10_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_10_upstream_waits_for_read) & ~system_0_burst_10_upstream_load_fifo))? system_0_burst_10_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_10_upstream_waits_for_read & system_0_burst_10_upstream_this_cycle_is_the_last_burst & system_0_burst_10_upstream_burstcount_fifo_empty))? system_0_burst_10_upstream_selected_burstcount :
    (system_0_burst_10_upstream_this_cycle_is_the_last_burst)? system_0_burst_10_upstream_transaction_burst_count :
    system_0_burst_10_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_10_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_10_upstream_current_burst <= 0;
      else if (system_0_burst_10_upstream_readdatavalid_from_sa | (~system_0_burst_10_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_10_upstream_waits_for_read)))
          system_0_burst_10_upstream_current_burst <= system_0_burst_10_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_10_upstream_load_fifo = (~system_0_burst_10_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_10_upstream_waits_for_read) & system_0_burst_10_upstream_load_fifo))? 1 :
    ~system_0_burst_10_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_10_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_10_upstream_waits_for_read) & ~system_0_burst_10_upstream_load_fifo | system_0_burst_10_upstream_this_cycle_is_the_last_burst)
          system_0_burst_10_upstream_load_fifo <= p0_system_0_burst_10_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_10_upstream, which is an e_assign
  assign system_0_burst_10_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_10_upstream_current_burst_minus_one) & system_0_burst_10_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_10_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_10_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_10_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_10_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_10_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_10_upstream),
      .full                 (),
      .read                 (system_0_burst_10_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_10_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_10_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_10_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_10_upstream = system_0_burst_10_upstream_readdatavalid_from_sa;

  //system_0_burst_10_upstream_writedata mux, which is an e_mux
  assign system_0_burst_10_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_10/upstream, which is an e_mux
  assign system_0_burst_10_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_10_upstream = cpu_0_data_master_qualified_request_system_0_burst_10_upstream;

  //cpu_0/data_master saved-grant system_0_burst_10/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_10_upstream = cpu_0_data_master_requests_system_0_burst_10_upstream;

  //allow new arb cycle for system_0_burst_10/upstream, which is an e_assign
  assign system_0_burst_10_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_10_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_10_upstream_master_qreq_vector = 1;

  //system_0_burst_10_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_10_upstream_firsttransfer = system_0_burst_10_upstream_begins_xfer ? system_0_burst_10_upstream_unreg_firsttransfer : system_0_burst_10_upstream_reg_firsttransfer;

  //system_0_burst_10_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_10_upstream_unreg_firsttransfer = ~(system_0_burst_10_upstream_slavearbiterlockenable & system_0_burst_10_upstream_any_continuerequest);

  //system_0_burst_10_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_10_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_10_upstream_begins_xfer)
          system_0_burst_10_upstream_reg_firsttransfer <= system_0_burst_10_upstream_unreg_firsttransfer;
    end


  //system_0_burst_10_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_10_upstream_next_bbt_burstcount = ((((system_0_burst_10_upstream_write) && (system_0_burst_10_upstream_bbt_burstcounter == 0))))? (system_0_burst_10_upstream_burstcount - 1) :
    ((((system_0_burst_10_upstream_read) && (system_0_burst_10_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_10_upstream_bbt_burstcounter - 1);

  //system_0_burst_10_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_10_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_10_upstream_begins_xfer)
          system_0_burst_10_upstream_bbt_burstcounter <= system_0_burst_10_upstream_next_bbt_burstcount;
    end


  //system_0_burst_10_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_10_upstream_beginbursttransfer_internal = system_0_burst_10_upstream_begins_xfer & (system_0_burst_10_upstream_bbt_burstcounter == 0);

  //system_0_burst_10_upstream_read assignment, which is an e_mux
  assign system_0_burst_10_upstream_read = cpu_0_data_master_granted_system_0_burst_10_upstream & cpu_0_data_master_read;

  //system_0_burst_10_upstream_write assignment, which is an e_mux
  assign system_0_burst_10_upstream_write = cpu_0_data_master_granted_system_0_burst_10_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_10_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_10_upstream_address mux, which is an e_mux
  assign system_0_burst_10_upstream_address = shifted_address_to_system_0_burst_10_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_10_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_10_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_10_upstream_end_xfer <= system_0_burst_10_upstream_end_xfer;
    end


  //system_0_burst_10_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_10_upstream_waits_for_read = system_0_burst_10_upstream_in_a_read_cycle & system_0_burst_10_upstream_waitrequest_from_sa;

  //system_0_burst_10_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_10_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_10_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_10_upstream_in_a_read_cycle;

  //system_0_burst_10_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_10_upstream_waits_for_write = system_0_burst_10_upstream_in_a_write_cycle & system_0_burst_10_upstream_waitrequest_from_sa;

  //system_0_burst_10_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_10_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_10_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_10_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_10_upstream_counter = 0;
  //system_0_burst_10_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_10_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_10_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_10_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_10_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_10_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_10_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_10/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_10_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_10/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_10_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_timer_0_s1_end_xfer,
                                                  reset_n,
                                                  system_0_burst_10_downstream_address,
                                                  system_0_burst_10_downstream_burstcount,
                                                  system_0_burst_10_downstream_byteenable,
                                                  system_0_burst_10_downstream_granted_timer_0_s1,
                                                  system_0_burst_10_downstream_qualified_request_timer_0_s1,
                                                  system_0_burst_10_downstream_read,
                                                  system_0_burst_10_downstream_read_data_valid_timer_0_s1,
                                                  system_0_burst_10_downstream_requests_timer_0_s1,
                                                  system_0_burst_10_downstream_write,
                                                  system_0_burst_10_downstream_writedata,
                                                  timer_0_s1_readdata_from_sa,

                                                 // outputs:
                                                  system_0_burst_10_downstream_address_to_slave,
                                                  system_0_burst_10_downstream_latency_counter,
                                                  system_0_burst_10_downstream_readdata,
                                                  system_0_burst_10_downstream_readdatavalid,
                                                  system_0_burst_10_downstream_reset_n,
                                                  system_0_burst_10_downstream_waitrequest
                                               )
;

  output  [  3: 0] system_0_burst_10_downstream_address_to_slave;
  output           system_0_burst_10_downstream_latency_counter;
  output  [ 15: 0] system_0_burst_10_downstream_readdata;
  output           system_0_burst_10_downstream_readdatavalid;
  output           system_0_burst_10_downstream_reset_n;
  output           system_0_burst_10_downstream_waitrequest;
  input            clk;
  input            d1_timer_0_s1_end_xfer;
  input            reset_n;
  input   [  3: 0] system_0_burst_10_downstream_address;
  input            system_0_burst_10_downstream_burstcount;
  input   [  1: 0] system_0_burst_10_downstream_byteenable;
  input            system_0_burst_10_downstream_granted_timer_0_s1;
  input            system_0_burst_10_downstream_qualified_request_timer_0_s1;
  input            system_0_burst_10_downstream_read;
  input            system_0_burst_10_downstream_read_data_valid_timer_0_s1;
  input            system_0_burst_10_downstream_requests_timer_0_s1;
  input            system_0_burst_10_downstream_write;
  input   [ 15: 0] system_0_burst_10_downstream_writedata;
  input   [ 15: 0] timer_0_s1_readdata_from_sa;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_10_downstream_readdatavalid;
  wire             r_6;
  reg     [  3: 0] system_0_burst_10_downstream_address_last_time;
  wire    [  3: 0] system_0_burst_10_downstream_address_to_slave;
  reg              system_0_burst_10_downstream_burstcount_last_time;
  reg     [  1: 0] system_0_burst_10_downstream_byteenable_last_time;
  wire             system_0_burst_10_downstream_latency_counter;
  reg              system_0_burst_10_downstream_read_last_time;
  wire    [ 15: 0] system_0_burst_10_downstream_readdata;
  wire             system_0_burst_10_downstream_readdatavalid;
  wire             system_0_burst_10_downstream_reset_n;
  wire             system_0_burst_10_downstream_run;
  wire             system_0_burst_10_downstream_waitrequest;
  reg              system_0_burst_10_downstream_write_last_time;
  reg     [ 15: 0] system_0_burst_10_downstream_writedata_last_time;
  //r_6 master_run cascaded wait assignment, which is an e_assign
  assign r_6 = 1 & (system_0_burst_10_downstream_qualified_request_timer_0_s1 | ~system_0_burst_10_downstream_requests_timer_0_s1) & ((~system_0_burst_10_downstream_qualified_request_timer_0_s1 | ~system_0_burst_10_downstream_read | (1 & ~d1_timer_0_s1_end_xfer & system_0_burst_10_downstream_read))) & ((~system_0_burst_10_downstream_qualified_request_timer_0_s1 | ~system_0_burst_10_downstream_write | (1 & system_0_burst_10_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_10_downstream_run = r_6;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_10_downstream_address_to_slave = system_0_burst_10_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_10_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_10_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_10_downstream_readdatavalid |
    system_0_burst_10_downstream_read_data_valid_timer_0_s1;

  //system_0_burst_10/downstream readdata mux, which is an e_mux
  assign system_0_burst_10_downstream_readdata = timer_0_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_10_downstream_waitrequest = ~system_0_burst_10_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_10_downstream_latency_counter = 0;

  //system_0_burst_10_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_10_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_10_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_10_downstream_address_last_time <= 0;
      else 
        system_0_burst_10_downstream_address_last_time <= system_0_burst_10_downstream_address;
    end


  //system_0_burst_10/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_10_downstream_waitrequest & (system_0_burst_10_downstream_read | system_0_burst_10_downstream_write);
    end


  //system_0_burst_10_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_10_downstream_address != system_0_burst_10_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_10_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_10_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_10_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_10_downstream_burstcount_last_time <= system_0_burst_10_downstream_burstcount;
    end


  //system_0_burst_10_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_10_downstream_burstcount != system_0_burst_10_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_10_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_10_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_10_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_10_downstream_byteenable_last_time <= system_0_burst_10_downstream_byteenable;
    end


  //system_0_burst_10_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_10_downstream_byteenable != system_0_burst_10_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_10_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_10_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_10_downstream_read_last_time <= 0;
      else 
        system_0_burst_10_downstream_read_last_time <= system_0_burst_10_downstream_read;
    end


  //system_0_burst_10_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_10_downstream_read != system_0_burst_10_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_10_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_10_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_10_downstream_write_last_time <= 0;
      else 
        system_0_burst_10_downstream_write_last_time <= system_0_burst_10_downstream_write;
    end


  //system_0_burst_10_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_10_downstream_write != system_0_burst_10_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_10_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_10_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_10_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_10_downstream_writedata_last_time <= system_0_burst_10_downstream_writedata;
    end


  //system_0_burst_10_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_10_downstream_writedata != system_0_burst_10_downstream_writedata_last_time) & system_0_burst_10_downstream_write)
        begin
          $write("%0d ns: system_0_burst_10_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_11_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_11_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_11_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_11_upstream_readdata,
                                                system_0_burst_11_upstream_readdatavalid,
                                                system_0_burst_11_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_11_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_11_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_11_upstream,
                                                d1_system_0_burst_11_upstream_end_xfer,
                                                system_0_burst_11_upstream_address,
                                                system_0_burst_11_upstream_burstcount,
                                                system_0_burst_11_upstream_byteaddress,
                                                system_0_burst_11_upstream_byteenable,
                                                system_0_burst_11_upstream_debugaccess,
                                                system_0_burst_11_upstream_read,
                                                system_0_burst_11_upstream_readdata_from_sa,
                                                system_0_burst_11_upstream_waitrequest_from_sa,
                                                system_0_burst_11_upstream_write,
                                                system_0_burst_11_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_11_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_11_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_11_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_11_upstream;
  output           d1_system_0_burst_11_upstream_end_xfer;
  output  [  3: 0] system_0_burst_11_upstream_address;
  output  [  3: 0] system_0_burst_11_upstream_burstcount;
  output  [  4: 0] system_0_burst_11_upstream_byteaddress;
  output  [  1: 0] system_0_burst_11_upstream_byteenable;
  output           system_0_burst_11_upstream_debugaccess;
  output           system_0_burst_11_upstream_read;
  output  [ 15: 0] system_0_burst_11_upstream_readdata_from_sa;
  output           system_0_burst_11_upstream_waitrequest_from_sa;
  output           system_0_burst_11_upstream_write;
  output  [ 15: 0] system_0_burst_11_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [ 15: 0] system_0_burst_11_upstream_readdata;
  input            system_0_burst_11_upstream_readdatavalid;
  input            system_0_burst_11_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_11_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_11_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_11_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_11_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_11_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_11_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_11_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_11_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_11_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_11_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_11_upstream_from_cpu_0_data_master;
  wire    [  3: 0] system_0_burst_11_upstream_address;
  wire             system_0_burst_11_upstream_allgrants;
  wire             system_0_burst_11_upstream_allow_new_arb_cycle;
  wire             system_0_burst_11_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_11_upstream_any_continuerequest;
  wire             system_0_burst_11_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_11_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_11_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_11_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_11_upstream_bbt_burstcounter;
  wire             system_0_burst_11_upstream_beginbursttransfer_internal;
  wire             system_0_burst_11_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_11_upstream_burstcount;
  wire             system_0_burst_11_upstream_burstcount_fifo_empty;
  wire    [  4: 0] system_0_burst_11_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_11_upstream_byteenable;
  reg     [  3: 0] system_0_burst_11_upstream_current_burst;
  wire    [  3: 0] system_0_burst_11_upstream_current_burst_minus_one;
  wire             system_0_burst_11_upstream_debugaccess;
  wire             system_0_burst_11_upstream_end_xfer;
  wire             system_0_burst_11_upstream_firsttransfer;
  wire             system_0_burst_11_upstream_grant_vector;
  wire             system_0_burst_11_upstream_in_a_read_cycle;
  wire             system_0_burst_11_upstream_in_a_write_cycle;
  reg              system_0_burst_11_upstream_load_fifo;
  wire             system_0_burst_11_upstream_master_qreq_vector;
  wire             system_0_burst_11_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_11_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_11_upstream_next_burst_count;
  wire             system_0_burst_11_upstream_non_bursting_master_requests;
  wire             system_0_burst_11_upstream_read;
  wire    [ 15: 0] system_0_burst_11_upstream_readdata_from_sa;
  wire             system_0_burst_11_upstream_readdatavalid_from_sa;
  reg              system_0_burst_11_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_11_upstream_selected_burstcount;
  reg              system_0_burst_11_upstream_slavearbiterlockenable;
  wire             system_0_burst_11_upstream_slavearbiterlockenable2;
  wire             system_0_burst_11_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_11_upstream_transaction_burst_count;
  wire             system_0_burst_11_upstream_unreg_firsttransfer;
  wire             system_0_burst_11_upstream_waitrequest_from_sa;
  wire             system_0_burst_11_upstream_waits_for_read;
  wire             system_0_burst_11_upstream_waits_for_write;
  wire             system_0_burst_11_upstream_write;
  wire    [ 15: 0] system_0_burst_11_upstream_writedata;
  wire             wait_for_system_0_burst_11_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_11_upstream_end_xfer;
    end


  assign system_0_burst_11_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_11_upstream));
  //assign system_0_burst_11_upstream_readdatavalid_from_sa = system_0_burst_11_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_11_upstream_readdatavalid_from_sa = system_0_burst_11_upstream_readdatavalid;

  //assign system_0_burst_11_upstream_readdata_from_sa = system_0_burst_11_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_11_upstream_readdata_from_sa = system_0_burst_11_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_11_upstream = ({cpu_0_data_master_address_to_slave[24 : 5] , 5'b0} == 25'h190a060) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_11_upstream_waitrequest_from_sa = system_0_burst_11_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_11_upstream_waitrequest_from_sa = system_0_burst_11_upstream_waitrequest;

  //system_0_burst_11_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_11_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_11_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_11_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_11_upstream_non_bursting_master_requests = 0;

  //system_0_burst_11_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_11_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_11_upstream;

  //system_0_burst_11_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_11_upstream_arb_share_counter_next_value = system_0_burst_11_upstream_firsttransfer ? (system_0_burst_11_upstream_arb_share_set_values - 1) : |system_0_burst_11_upstream_arb_share_counter ? (system_0_burst_11_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_11_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_11_upstream_allgrants = |system_0_burst_11_upstream_grant_vector;

  //system_0_burst_11_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_11_upstream_end_xfer = ~(system_0_burst_11_upstream_waits_for_read | system_0_burst_11_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_11_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_11_upstream = system_0_burst_11_upstream_end_xfer & (~system_0_burst_11_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_11_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_11_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_11_upstream & system_0_burst_11_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_11_upstream & ~system_0_burst_11_upstream_non_bursting_master_requests);

  //system_0_burst_11_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_11_upstream_arb_share_counter <= 0;
      else if (system_0_burst_11_upstream_arb_counter_enable)
          system_0_burst_11_upstream_arb_share_counter <= system_0_burst_11_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_11_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_11_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_11_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_11_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_11_upstream & ~system_0_burst_11_upstream_non_bursting_master_requests))
          system_0_burst_11_upstream_slavearbiterlockenable <= |system_0_burst_11_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_11/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_11_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_11_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_11_upstream_slavearbiterlockenable2 = |system_0_burst_11_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_11/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_11_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_11_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_11_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_11_upstream = cpu_0_data_master_requests_system_0_burst_11_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_11_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_11_upstream_move_on_to_next_transaction = system_0_burst_11_upstream_this_cycle_is_the_last_burst & system_0_burst_11_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_11_upstream, which is an e_mux
  assign system_0_burst_11_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_11_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_11_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_11_upstream_module burstcount_fifo_for_system_0_burst_11_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_11_upstream_selected_burstcount),
      .data_out             (system_0_burst_11_upstream_transaction_burst_count),
      .empty                (system_0_burst_11_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_11_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_11_upstream_waits_for_read & system_0_burst_11_upstream_load_fifo & ~(system_0_burst_11_upstream_this_cycle_is_the_last_burst & system_0_burst_11_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_11_upstream current burst minus one, which is an e_assign
  assign system_0_burst_11_upstream_current_burst_minus_one = system_0_burst_11_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_11_upstream, which is an e_mux
  assign system_0_burst_11_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_11_upstream_waits_for_read) & ~system_0_burst_11_upstream_load_fifo))? system_0_burst_11_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_11_upstream_waits_for_read & system_0_burst_11_upstream_this_cycle_is_the_last_burst & system_0_burst_11_upstream_burstcount_fifo_empty))? system_0_burst_11_upstream_selected_burstcount :
    (system_0_burst_11_upstream_this_cycle_is_the_last_burst)? system_0_burst_11_upstream_transaction_burst_count :
    system_0_burst_11_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_11_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_11_upstream_current_burst <= 0;
      else if (system_0_burst_11_upstream_readdatavalid_from_sa | (~system_0_burst_11_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_11_upstream_waits_for_read)))
          system_0_burst_11_upstream_current_burst <= system_0_burst_11_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_11_upstream_load_fifo = (~system_0_burst_11_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_11_upstream_waits_for_read) & system_0_burst_11_upstream_load_fifo))? 1 :
    ~system_0_burst_11_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_11_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_11_upstream_waits_for_read) & ~system_0_burst_11_upstream_load_fifo | system_0_burst_11_upstream_this_cycle_is_the_last_burst)
          system_0_burst_11_upstream_load_fifo <= p0_system_0_burst_11_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_11_upstream, which is an e_assign
  assign system_0_burst_11_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_11_upstream_current_burst_minus_one) & system_0_burst_11_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_11_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_11_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_11_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_11_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_11_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_11_upstream),
      .full                 (),
      .read                 (system_0_burst_11_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_11_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_11_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_11_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_11_upstream = system_0_burst_11_upstream_readdatavalid_from_sa;

  //system_0_burst_11_upstream_writedata mux, which is an e_mux
  assign system_0_burst_11_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_11/upstream, which is an e_mux
  assign system_0_burst_11_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_11_upstream = cpu_0_data_master_qualified_request_system_0_burst_11_upstream;

  //cpu_0/data_master saved-grant system_0_burst_11/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_11_upstream = cpu_0_data_master_requests_system_0_burst_11_upstream;

  //allow new arb cycle for system_0_burst_11/upstream, which is an e_assign
  assign system_0_burst_11_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_11_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_11_upstream_master_qreq_vector = 1;

  //system_0_burst_11_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_11_upstream_firsttransfer = system_0_burst_11_upstream_begins_xfer ? system_0_burst_11_upstream_unreg_firsttransfer : system_0_burst_11_upstream_reg_firsttransfer;

  //system_0_burst_11_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_11_upstream_unreg_firsttransfer = ~(system_0_burst_11_upstream_slavearbiterlockenable & system_0_burst_11_upstream_any_continuerequest);

  //system_0_burst_11_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_11_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_11_upstream_begins_xfer)
          system_0_burst_11_upstream_reg_firsttransfer <= system_0_burst_11_upstream_unreg_firsttransfer;
    end


  //system_0_burst_11_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_11_upstream_next_bbt_burstcount = ((((system_0_burst_11_upstream_write) && (system_0_burst_11_upstream_bbt_burstcounter == 0))))? (system_0_burst_11_upstream_burstcount - 1) :
    ((((system_0_burst_11_upstream_read) && (system_0_burst_11_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_11_upstream_bbt_burstcounter - 1);

  //system_0_burst_11_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_11_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_11_upstream_begins_xfer)
          system_0_burst_11_upstream_bbt_burstcounter <= system_0_burst_11_upstream_next_bbt_burstcount;
    end


  //system_0_burst_11_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_11_upstream_beginbursttransfer_internal = system_0_burst_11_upstream_begins_xfer & (system_0_burst_11_upstream_bbt_burstcounter == 0);

  //system_0_burst_11_upstream_read assignment, which is an e_mux
  assign system_0_burst_11_upstream_read = cpu_0_data_master_granted_system_0_burst_11_upstream & cpu_0_data_master_read;

  //system_0_burst_11_upstream_write assignment, which is an e_mux
  assign system_0_burst_11_upstream_write = cpu_0_data_master_granted_system_0_burst_11_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_11_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_11_upstream_address mux, which is an e_mux
  assign system_0_burst_11_upstream_address = shifted_address_to_system_0_burst_11_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_11_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_11_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_11_upstream_end_xfer <= system_0_burst_11_upstream_end_xfer;
    end


  //system_0_burst_11_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_11_upstream_waits_for_read = system_0_burst_11_upstream_in_a_read_cycle & system_0_burst_11_upstream_waitrequest_from_sa;

  //system_0_burst_11_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_11_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_11_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_11_upstream_in_a_read_cycle;

  //system_0_burst_11_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_11_upstream_waits_for_write = system_0_burst_11_upstream_in_a_write_cycle & system_0_burst_11_upstream_waitrequest_from_sa;

  //system_0_burst_11_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_11_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_11_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_11_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_11_upstream_counter = 0;
  //system_0_burst_11_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_11_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_11_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_11_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_11_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_11_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_11_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_11/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_11_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_11/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_11_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_timer_1_s1_end_xfer,
                                                  reset_n,
                                                  system_0_burst_11_downstream_address,
                                                  system_0_burst_11_downstream_burstcount,
                                                  system_0_burst_11_downstream_byteenable,
                                                  system_0_burst_11_downstream_granted_timer_1_s1,
                                                  system_0_burst_11_downstream_qualified_request_timer_1_s1,
                                                  system_0_burst_11_downstream_read,
                                                  system_0_burst_11_downstream_read_data_valid_timer_1_s1,
                                                  system_0_burst_11_downstream_requests_timer_1_s1,
                                                  system_0_burst_11_downstream_write,
                                                  system_0_burst_11_downstream_writedata,
                                                  timer_1_s1_readdata_from_sa,

                                                 // outputs:
                                                  system_0_burst_11_downstream_address_to_slave,
                                                  system_0_burst_11_downstream_latency_counter,
                                                  system_0_burst_11_downstream_readdata,
                                                  system_0_burst_11_downstream_readdatavalid,
                                                  system_0_burst_11_downstream_reset_n,
                                                  system_0_burst_11_downstream_waitrequest
                                               )
;

  output  [  3: 0] system_0_burst_11_downstream_address_to_slave;
  output           system_0_burst_11_downstream_latency_counter;
  output  [ 15: 0] system_0_burst_11_downstream_readdata;
  output           system_0_burst_11_downstream_readdatavalid;
  output           system_0_burst_11_downstream_reset_n;
  output           system_0_burst_11_downstream_waitrequest;
  input            clk;
  input            d1_timer_1_s1_end_xfer;
  input            reset_n;
  input   [  3: 0] system_0_burst_11_downstream_address;
  input            system_0_burst_11_downstream_burstcount;
  input   [  1: 0] system_0_burst_11_downstream_byteenable;
  input            system_0_burst_11_downstream_granted_timer_1_s1;
  input            system_0_burst_11_downstream_qualified_request_timer_1_s1;
  input            system_0_burst_11_downstream_read;
  input            system_0_burst_11_downstream_read_data_valid_timer_1_s1;
  input            system_0_burst_11_downstream_requests_timer_1_s1;
  input            system_0_burst_11_downstream_write;
  input   [ 15: 0] system_0_burst_11_downstream_writedata;
  input   [ 15: 0] timer_1_s1_readdata_from_sa;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_11_downstream_readdatavalid;
  wire             r_6;
  reg     [  3: 0] system_0_burst_11_downstream_address_last_time;
  wire    [  3: 0] system_0_burst_11_downstream_address_to_slave;
  reg              system_0_burst_11_downstream_burstcount_last_time;
  reg     [  1: 0] system_0_burst_11_downstream_byteenable_last_time;
  wire             system_0_burst_11_downstream_latency_counter;
  reg              system_0_burst_11_downstream_read_last_time;
  wire    [ 15: 0] system_0_burst_11_downstream_readdata;
  wire             system_0_burst_11_downstream_readdatavalid;
  wire             system_0_burst_11_downstream_reset_n;
  wire             system_0_burst_11_downstream_run;
  wire             system_0_burst_11_downstream_waitrequest;
  reg              system_0_burst_11_downstream_write_last_time;
  reg     [ 15: 0] system_0_burst_11_downstream_writedata_last_time;
  //r_6 master_run cascaded wait assignment, which is an e_assign
  assign r_6 = 1 & (system_0_burst_11_downstream_qualified_request_timer_1_s1 | ~system_0_burst_11_downstream_requests_timer_1_s1) & ((~system_0_burst_11_downstream_qualified_request_timer_1_s1 | ~system_0_burst_11_downstream_read | (1 & ~d1_timer_1_s1_end_xfer & system_0_burst_11_downstream_read))) & ((~system_0_burst_11_downstream_qualified_request_timer_1_s1 | ~system_0_burst_11_downstream_write | (1 & system_0_burst_11_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_11_downstream_run = r_6;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_11_downstream_address_to_slave = system_0_burst_11_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_11_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_11_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_11_downstream_readdatavalid |
    system_0_burst_11_downstream_read_data_valid_timer_1_s1;

  //system_0_burst_11/downstream readdata mux, which is an e_mux
  assign system_0_burst_11_downstream_readdata = timer_1_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_11_downstream_waitrequest = ~system_0_burst_11_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_11_downstream_latency_counter = 0;

  //system_0_burst_11_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_11_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_11_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_11_downstream_address_last_time <= 0;
      else 
        system_0_burst_11_downstream_address_last_time <= system_0_burst_11_downstream_address;
    end


  //system_0_burst_11/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_11_downstream_waitrequest & (system_0_burst_11_downstream_read | system_0_burst_11_downstream_write);
    end


  //system_0_burst_11_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_11_downstream_address != system_0_burst_11_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_11_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_11_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_11_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_11_downstream_burstcount_last_time <= system_0_burst_11_downstream_burstcount;
    end


  //system_0_burst_11_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_11_downstream_burstcount != system_0_burst_11_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_11_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_11_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_11_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_11_downstream_byteenable_last_time <= system_0_burst_11_downstream_byteenable;
    end


  //system_0_burst_11_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_11_downstream_byteenable != system_0_burst_11_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_11_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_11_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_11_downstream_read_last_time <= 0;
      else 
        system_0_burst_11_downstream_read_last_time <= system_0_burst_11_downstream_read;
    end


  //system_0_burst_11_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_11_downstream_read != system_0_burst_11_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_11_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_11_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_11_downstream_write_last_time <= 0;
      else 
        system_0_burst_11_downstream_write_last_time <= system_0_burst_11_downstream_write;
    end


  //system_0_burst_11_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_11_downstream_write != system_0_burst_11_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_11_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_11_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_11_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_11_downstream_writedata_last_time <= system_0_burst_11_downstream_writedata;
    end


  //system_0_burst_11_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_11_downstream_writedata != system_0_burst_11_downstream_writedata_last_time) & system_0_burst_11_downstream_write)
        begin
          $write("%0d ns: system_0_burst_11_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_12_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_12_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_12_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_12_upstream_readdata,
                                                system_0_burst_12_upstream_readdatavalid,
                                                system_0_burst_12_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_12_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_12_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_12_upstream,
                                                d1_system_0_burst_12_upstream_end_xfer,
                                                system_0_burst_12_upstream_address,
                                                system_0_burst_12_upstream_burstcount,
                                                system_0_burst_12_upstream_byteaddress,
                                                system_0_burst_12_upstream_byteenable,
                                                system_0_burst_12_upstream_debugaccess,
                                                system_0_burst_12_upstream_read,
                                                system_0_burst_12_upstream_readdata_from_sa,
                                                system_0_burst_12_upstream_waitrequest_from_sa,
                                                system_0_burst_12_upstream_write,
                                                system_0_burst_12_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_12_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_12_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_12_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_12_upstream;
  output           d1_system_0_burst_12_upstream_end_xfer;
  output  [  1: 0] system_0_burst_12_upstream_address;
  output  [  3: 0] system_0_burst_12_upstream_burstcount;
  output  [  1: 0] system_0_burst_12_upstream_byteaddress;
  output           system_0_burst_12_upstream_byteenable;
  output           system_0_burst_12_upstream_debugaccess;
  output           system_0_burst_12_upstream_read;
  output  [  7: 0] system_0_burst_12_upstream_readdata_from_sa;
  output           system_0_burst_12_upstream_waitrequest_from_sa;
  output           system_0_burst_12_upstream_write;
  output  [  7: 0] system_0_burst_12_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_12_upstream_readdata;
  input            system_0_burst_12_upstream_readdatavalid;
  input            system_0_burst_12_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_12_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_12_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_12_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_12_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_12_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_12_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_12_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_12_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_12_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_12_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_12_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_12_upstream_address;
  wire             system_0_burst_12_upstream_allgrants;
  wire             system_0_burst_12_upstream_allow_new_arb_cycle;
  wire             system_0_burst_12_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_12_upstream_any_continuerequest;
  wire             system_0_burst_12_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_12_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_12_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_12_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_12_upstream_bbt_burstcounter;
  wire             system_0_burst_12_upstream_beginbursttransfer_internal;
  wire             system_0_burst_12_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_12_upstream_burstcount;
  wire             system_0_burst_12_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_12_upstream_byteaddress;
  wire             system_0_burst_12_upstream_byteenable;
  reg     [  3: 0] system_0_burst_12_upstream_current_burst;
  wire    [  3: 0] system_0_burst_12_upstream_current_burst_minus_one;
  wire             system_0_burst_12_upstream_debugaccess;
  wire             system_0_burst_12_upstream_end_xfer;
  wire             system_0_burst_12_upstream_firsttransfer;
  wire             system_0_burst_12_upstream_grant_vector;
  wire             system_0_burst_12_upstream_in_a_read_cycle;
  wire             system_0_burst_12_upstream_in_a_write_cycle;
  reg              system_0_burst_12_upstream_load_fifo;
  wire             system_0_burst_12_upstream_master_qreq_vector;
  wire             system_0_burst_12_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_12_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_12_upstream_next_burst_count;
  wire             system_0_burst_12_upstream_non_bursting_master_requests;
  wire             system_0_burst_12_upstream_read;
  wire    [  7: 0] system_0_burst_12_upstream_readdata_from_sa;
  wire             system_0_burst_12_upstream_readdatavalid_from_sa;
  reg              system_0_burst_12_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_12_upstream_selected_burstcount;
  reg              system_0_burst_12_upstream_slavearbiterlockenable;
  wire             system_0_burst_12_upstream_slavearbiterlockenable2;
  wire             system_0_burst_12_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_12_upstream_transaction_burst_count;
  wire             system_0_burst_12_upstream_unreg_firsttransfer;
  wire             system_0_burst_12_upstream_waitrequest_from_sa;
  wire             system_0_burst_12_upstream_waits_for_read;
  wire             system_0_burst_12_upstream_waits_for_write;
  wire             system_0_burst_12_upstream_write;
  wire    [  7: 0] system_0_burst_12_upstream_writedata;
  wire             wait_for_system_0_burst_12_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_12_upstream_end_xfer;
    end


  assign system_0_burst_12_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_12_upstream));
  //assign system_0_burst_12_upstream_readdatavalid_from_sa = system_0_burst_12_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_12_upstream_readdatavalid_from_sa = system_0_burst_12_upstream_readdatavalid;

  //assign system_0_burst_12_upstream_readdata_from_sa = system_0_burst_12_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_12_upstream_readdata_from_sa = system_0_burst_12_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_12_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a0c0) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_12_upstream_waitrequest_from_sa = system_0_burst_12_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_12_upstream_waitrequest_from_sa = system_0_burst_12_upstream_waitrequest;

  //system_0_burst_12_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_12_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_12_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_12_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_12_upstream_non_bursting_master_requests = 0;

  //system_0_burst_12_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_12_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_12_upstream;

  //system_0_burst_12_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_12_upstream_arb_share_counter_next_value = system_0_burst_12_upstream_firsttransfer ? (system_0_burst_12_upstream_arb_share_set_values - 1) : |system_0_burst_12_upstream_arb_share_counter ? (system_0_burst_12_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_12_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_12_upstream_allgrants = |system_0_burst_12_upstream_grant_vector;

  //system_0_burst_12_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_12_upstream_end_xfer = ~(system_0_burst_12_upstream_waits_for_read | system_0_burst_12_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_12_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_12_upstream = system_0_burst_12_upstream_end_xfer & (~system_0_burst_12_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_12_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_12_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_12_upstream & system_0_burst_12_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_12_upstream & ~system_0_burst_12_upstream_non_bursting_master_requests);

  //system_0_burst_12_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_12_upstream_arb_share_counter <= 0;
      else if (system_0_burst_12_upstream_arb_counter_enable)
          system_0_burst_12_upstream_arb_share_counter <= system_0_burst_12_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_12_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_12_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_12_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_12_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_12_upstream & ~system_0_burst_12_upstream_non_bursting_master_requests))
          system_0_burst_12_upstream_slavearbiterlockenable <= |system_0_burst_12_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_12/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_12_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_12_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_12_upstream_slavearbiterlockenable2 = |system_0_burst_12_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_12/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_12_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_12_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_12_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_12_upstream = cpu_0_data_master_requests_system_0_burst_12_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_12_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_12_upstream_move_on_to_next_transaction = system_0_burst_12_upstream_this_cycle_is_the_last_burst & system_0_burst_12_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_12_upstream, which is an e_mux
  assign system_0_burst_12_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_12_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_12_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_12_upstream_module burstcount_fifo_for_system_0_burst_12_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_12_upstream_selected_burstcount),
      .data_out             (system_0_burst_12_upstream_transaction_burst_count),
      .empty                (system_0_burst_12_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_12_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_12_upstream_waits_for_read & system_0_burst_12_upstream_load_fifo & ~(system_0_burst_12_upstream_this_cycle_is_the_last_burst & system_0_burst_12_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_12_upstream current burst minus one, which is an e_assign
  assign system_0_burst_12_upstream_current_burst_minus_one = system_0_burst_12_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_12_upstream, which is an e_mux
  assign system_0_burst_12_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_12_upstream_waits_for_read) & ~system_0_burst_12_upstream_load_fifo))? system_0_burst_12_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_12_upstream_waits_for_read & system_0_burst_12_upstream_this_cycle_is_the_last_burst & system_0_burst_12_upstream_burstcount_fifo_empty))? system_0_burst_12_upstream_selected_burstcount :
    (system_0_burst_12_upstream_this_cycle_is_the_last_burst)? system_0_burst_12_upstream_transaction_burst_count :
    system_0_burst_12_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_12_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_12_upstream_current_burst <= 0;
      else if (system_0_burst_12_upstream_readdatavalid_from_sa | (~system_0_burst_12_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_12_upstream_waits_for_read)))
          system_0_burst_12_upstream_current_burst <= system_0_burst_12_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_12_upstream_load_fifo = (~system_0_burst_12_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_12_upstream_waits_for_read) & system_0_burst_12_upstream_load_fifo))? 1 :
    ~system_0_burst_12_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_12_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_12_upstream_waits_for_read) & ~system_0_burst_12_upstream_load_fifo | system_0_burst_12_upstream_this_cycle_is_the_last_burst)
          system_0_burst_12_upstream_load_fifo <= p0_system_0_burst_12_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_12_upstream, which is an e_assign
  assign system_0_burst_12_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_12_upstream_current_burst_minus_one) & system_0_burst_12_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_12_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_12_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_12_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_12_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_12_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_12_upstream),
      .full                 (),
      .read                 (system_0_burst_12_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_12_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_12_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_12_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_12_upstream = system_0_burst_12_upstream_readdatavalid_from_sa;

  //system_0_burst_12_upstream_writedata mux, which is an e_mux
  assign system_0_burst_12_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_12/upstream, which is an e_mux
  assign system_0_burst_12_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_12_upstream = cpu_0_data_master_qualified_request_system_0_burst_12_upstream;

  //cpu_0/data_master saved-grant system_0_burst_12/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_12_upstream = cpu_0_data_master_requests_system_0_burst_12_upstream;

  //allow new arb cycle for system_0_burst_12/upstream, which is an e_assign
  assign system_0_burst_12_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_12_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_12_upstream_master_qreq_vector = 1;

  //system_0_burst_12_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_12_upstream_firsttransfer = system_0_burst_12_upstream_begins_xfer ? system_0_burst_12_upstream_unreg_firsttransfer : system_0_burst_12_upstream_reg_firsttransfer;

  //system_0_burst_12_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_12_upstream_unreg_firsttransfer = ~(system_0_burst_12_upstream_slavearbiterlockenable & system_0_burst_12_upstream_any_continuerequest);

  //system_0_burst_12_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_12_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_12_upstream_begins_xfer)
          system_0_burst_12_upstream_reg_firsttransfer <= system_0_burst_12_upstream_unreg_firsttransfer;
    end


  //system_0_burst_12_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_12_upstream_next_bbt_burstcount = ((((system_0_burst_12_upstream_write) && (system_0_burst_12_upstream_bbt_burstcounter == 0))))? (system_0_burst_12_upstream_burstcount - 1) :
    ((((system_0_burst_12_upstream_read) && (system_0_burst_12_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_12_upstream_bbt_burstcounter - 1);

  //system_0_burst_12_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_12_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_12_upstream_begins_xfer)
          system_0_burst_12_upstream_bbt_burstcounter <= system_0_burst_12_upstream_next_bbt_burstcount;
    end


  //system_0_burst_12_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_12_upstream_beginbursttransfer_internal = system_0_burst_12_upstream_begins_xfer & (system_0_burst_12_upstream_bbt_burstcounter == 0);

  //system_0_burst_12_upstream_read assignment, which is an e_mux
  assign system_0_burst_12_upstream_read = cpu_0_data_master_granted_system_0_burst_12_upstream & cpu_0_data_master_read;

  //system_0_burst_12_upstream_write assignment, which is an e_mux
  assign system_0_burst_12_upstream_write = cpu_0_data_master_granted_system_0_burst_12_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_12_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_12_upstream_address mux, which is an e_mux
  assign system_0_burst_12_upstream_address = shifted_address_to_system_0_burst_12_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_12_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_12_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_12_upstream_end_xfer <= system_0_burst_12_upstream_end_xfer;
    end


  //system_0_burst_12_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_12_upstream_waits_for_read = system_0_burst_12_upstream_in_a_read_cycle & system_0_burst_12_upstream_waitrequest_from_sa;

  //system_0_burst_12_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_12_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_12_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_12_upstream_in_a_read_cycle;

  //system_0_burst_12_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_12_upstream_waits_for_write = system_0_burst_12_upstream_in_a_write_cycle & system_0_burst_12_upstream_waitrequest_from_sa;

  //system_0_burst_12_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_12_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_12_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_12_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_12_upstream_counter = 0;
  //system_0_burst_12_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_12_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_12_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_12_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_12_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_12_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_12_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_12/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_12_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_12/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_12_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_lcd_16207_0_control_slave_end_xfer,
                                                  lcd_16207_0_control_slave_readdata_from_sa,
                                                  lcd_16207_0_control_slave_wait_counter_eq_0,
                                                  reset_n,
                                                  system_0_burst_12_downstream_address,
                                                  system_0_burst_12_downstream_burstcount,
                                                  system_0_burst_12_downstream_byteenable,
                                                  system_0_burst_12_downstream_granted_lcd_16207_0_control_slave,
                                                  system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave,
                                                  system_0_burst_12_downstream_read,
                                                  system_0_burst_12_downstream_read_data_valid_lcd_16207_0_control_slave,
                                                  system_0_burst_12_downstream_requests_lcd_16207_0_control_slave,
                                                  system_0_burst_12_downstream_write,
                                                  system_0_burst_12_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_12_downstream_address_to_slave,
                                                  system_0_burst_12_downstream_latency_counter,
                                                  system_0_burst_12_downstream_readdata,
                                                  system_0_burst_12_downstream_readdatavalid,
                                                  system_0_burst_12_downstream_reset_n,
                                                  system_0_burst_12_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_12_downstream_address_to_slave;
  output           system_0_burst_12_downstream_latency_counter;
  output  [  7: 0] system_0_burst_12_downstream_readdata;
  output           system_0_burst_12_downstream_readdatavalid;
  output           system_0_burst_12_downstream_reset_n;
  output           system_0_burst_12_downstream_waitrequest;
  input            clk;
  input            d1_lcd_16207_0_control_slave_end_xfer;
  input   [  7: 0] lcd_16207_0_control_slave_readdata_from_sa;
  input            lcd_16207_0_control_slave_wait_counter_eq_0;
  input            reset_n;
  input   [  1: 0] system_0_burst_12_downstream_address;
  input            system_0_burst_12_downstream_burstcount;
  input            system_0_burst_12_downstream_byteenable;
  input            system_0_burst_12_downstream_granted_lcd_16207_0_control_slave;
  input            system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave;
  input            system_0_burst_12_downstream_read;
  input            system_0_burst_12_downstream_read_data_valid_lcd_16207_0_control_slave;
  input            system_0_burst_12_downstream_requests_lcd_16207_0_control_slave;
  input            system_0_burst_12_downstream_write;
  input   [  7: 0] system_0_burst_12_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_12_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_12_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_12_downstream_address_to_slave;
  reg              system_0_burst_12_downstream_burstcount_last_time;
  reg              system_0_burst_12_downstream_byteenable_last_time;
  wire             system_0_burst_12_downstream_latency_counter;
  reg              system_0_burst_12_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_12_downstream_readdata;
  wire             system_0_burst_12_downstream_readdatavalid;
  wire             system_0_burst_12_downstream_reset_n;
  wire             system_0_burst_12_downstream_run;
  wire             system_0_burst_12_downstream_waitrequest;
  reg              system_0_burst_12_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_12_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave | ~system_0_burst_12_downstream_requests_lcd_16207_0_control_slave) & ((~system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave | ~system_0_burst_12_downstream_read | (1 & ((lcd_16207_0_control_slave_wait_counter_eq_0 & ~d1_lcd_16207_0_control_slave_end_xfer)) & system_0_burst_12_downstream_read))) & ((~system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave | ~system_0_burst_12_downstream_write | (1 & ((lcd_16207_0_control_slave_wait_counter_eq_0 & ~d1_lcd_16207_0_control_slave_end_xfer)) & system_0_burst_12_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_12_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_12_downstream_address_to_slave = system_0_burst_12_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_12_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_12_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_12_downstream_readdatavalid |
    system_0_burst_12_downstream_read_data_valid_lcd_16207_0_control_slave;

  //system_0_burst_12/downstream readdata mux, which is an e_mux
  assign system_0_burst_12_downstream_readdata = lcd_16207_0_control_slave_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_12_downstream_waitrequest = ~system_0_burst_12_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_12_downstream_latency_counter = 0;

  //system_0_burst_12_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_12_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_12_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_12_downstream_address_last_time <= 0;
      else 
        system_0_burst_12_downstream_address_last_time <= system_0_burst_12_downstream_address;
    end


  //system_0_burst_12/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_12_downstream_waitrequest & (system_0_burst_12_downstream_read | system_0_burst_12_downstream_write);
    end


  //system_0_burst_12_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_12_downstream_address != system_0_burst_12_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_12_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_12_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_12_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_12_downstream_burstcount_last_time <= system_0_burst_12_downstream_burstcount;
    end


  //system_0_burst_12_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_12_downstream_burstcount != system_0_burst_12_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_12_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_12_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_12_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_12_downstream_byteenable_last_time <= system_0_burst_12_downstream_byteenable;
    end


  //system_0_burst_12_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_12_downstream_byteenable != system_0_burst_12_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_12_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_12_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_12_downstream_read_last_time <= 0;
      else 
        system_0_burst_12_downstream_read_last_time <= system_0_burst_12_downstream_read;
    end


  //system_0_burst_12_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_12_downstream_read != system_0_burst_12_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_12_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_12_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_12_downstream_write_last_time <= 0;
      else 
        system_0_burst_12_downstream_write_last_time <= system_0_burst_12_downstream_write;
    end


  //system_0_burst_12_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_12_downstream_write != system_0_burst_12_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_12_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_12_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_12_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_12_downstream_writedata_last_time <= system_0_burst_12_downstream_writedata;
    end


  //system_0_burst_12_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_12_downstream_writedata != system_0_burst_12_downstream_writedata_last_time) & system_0_burst_12_downstream_write)
        begin
          $write("%0d ns: system_0_burst_12_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_13_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_13_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_13_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_13_upstream_readdata,
                                                system_0_burst_13_upstream_readdatavalid,
                                                system_0_burst_13_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_13_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_13_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_13_upstream,
                                                d1_system_0_burst_13_upstream_end_xfer,
                                                system_0_burst_13_upstream_address,
                                                system_0_burst_13_upstream_burstcount,
                                                system_0_burst_13_upstream_byteaddress,
                                                system_0_burst_13_upstream_byteenable,
                                                system_0_burst_13_upstream_debugaccess,
                                                system_0_burst_13_upstream_read,
                                                system_0_burst_13_upstream_readdata_from_sa,
                                                system_0_burst_13_upstream_waitrequest_from_sa,
                                                system_0_burst_13_upstream_write,
                                                system_0_burst_13_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_13_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_13_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_13_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_13_upstream;
  output           d1_system_0_burst_13_upstream_end_xfer;
  output  [  1: 0] system_0_burst_13_upstream_address;
  output  [  3: 0] system_0_burst_13_upstream_burstcount;
  output  [  3: 0] system_0_burst_13_upstream_byteaddress;
  output  [  3: 0] system_0_burst_13_upstream_byteenable;
  output           system_0_burst_13_upstream_debugaccess;
  output           system_0_burst_13_upstream_read;
  output  [ 31: 0] system_0_burst_13_upstream_readdata_from_sa;
  output           system_0_burst_13_upstream_waitrequest_from_sa;
  output           system_0_burst_13_upstream_write;
  output  [ 31: 0] system_0_burst_13_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [ 31: 0] system_0_burst_13_upstream_readdata;
  input            system_0_burst_13_upstream_readdatavalid;
  input            system_0_burst_13_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_13_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_13_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_13_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_13_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_13_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_13_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_13_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_13_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_13_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_13_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_13_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_13_upstream_address;
  wire             system_0_burst_13_upstream_allgrants;
  wire             system_0_burst_13_upstream_allow_new_arb_cycle;
  wire             system_0_burst_13_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_13_upstream_any_continuerequest;
  wire             system_0_burst_13_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_13_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_13_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_13_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_13_upstream_bbt_burstcounter;
  wire             system_0_burst_13_upstream_beginbursttransfer_internal;
  wire             system_0_burst_13_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_13_upstream_burstcount;
  wire             system_0_burst_13_upstream_burstcount_fifo_empty;
  wire    [  3: 0] system_0_burst_13_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_13_upstream_byteenable;
  reg     [  3: 0] system_0_burst_13_upstream_current_burst;
  wire    [  3: 0] system_0_burst_13_upstream_current_burst_minus_one;
  wire             system_0_burst_13_upstream_debugaccess;
  wire             system_0_burst_13_upstream_end_xfer;
  wire             system_0_burst_13_upstream_firsttransfer;
  wire             system_0_burst_13_upstream_grant_vector;
  wire             system_0_burst_13_upstream_in_a_read_cycle;
  wire             system_0_burst_13_upstream_in_a_write_cycle;
  reg              system_0_burst_13_upstream_load_fifo;
  wire             system_0_burst_13_upstream_master_qreq_vector;
  wire             system_0_burst_13_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_13_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_13_upstream_next_burst_count;
  wire             system_0_burst_13_upstream_non_bursting_master_requests;
  wire             system_0_burst_13_upstream_read;
  wire    [ 31: 0] system_0_burst_13_upstream_readdata_from_sa;
  wire             system_0_burst_13_upstream_readdatavalid_from_sa;
  reg              system_0_burst_13_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_13_upstream_selected_burstcount;
  reg              system_0_burst_13_upstream_slavearbiterlockenable;
  wire             system_0_burst_13_upstream_slavearbiterlockenable2;
  wire             system_0_burst_13_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_13_upstream_transaction_burst_count;
  wire             system_0_burst_13_upstream_unreg_firsttransfer;
  wire             system_0_burst_13_upstream_waitrequest_from_sa;
  wire             system_0_burst_13_upstream_waits_for_read;
  wire             system_0_burst_13_upstream_waits_for_write;
  wire             system_0_burst_13_upstream_write;
  wire    [ 31: 0] system_0_burst_13_upstream_writedata;
  wire             wait_for_system_0_burst_13_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_13_upstream_end_xfer;
    end


  assign system_0_burst_13_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_13_upstream));
  //assign system_0_burst_13_upstream_readdatavalid_from_sa = system_0_burst_13_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_13_upstream_readdatavalid_from_sa = system_0_burst_13_upstream_readdatavalid;

  //assign system_0_burst_13_upstream_readdata_from_sa = system_0_burst_13_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_13_upstream_readdata_from_sa = system_0_burst_13_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_13_upstream = ({cpu_0_data_master_address_to_slave[24 : 2] , 2'b0} == 25'h190a1d8) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_13_upstream_waitrequest_from_sa = system_0_burst_13_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_13_upstream_waitrequest_from_sa = system_0_burst_13_upstream_waitrequest;

  //system_0_burst_13_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_13_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_13_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_13_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_13_upstream_non_bursting_master_requests = 0;

  //system_0_burst_13_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_13_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_13_upstream;

  //system_0_burst_13_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_13_upstream_arb_share_counter_next_value = system_0_burst_13_upstream_firsttransfer ? (system_0_burst_13_upstream_arb_share_set_values - 1) : |system_0_burst_13_upstream_arb_share_counter ? (system_0_burst_13_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_13_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_13_upstream_allgrants = |system_0_burst_13_upstream_grant_vector;

  //system_0_burst_13_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_13_upstream_end_xfer = ~(system_0_burst_13_upstream_waits_for_read | system_0_burst_13_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_13_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_13_upstream = system_0_burst_13_upstream_end_xfer & (~system_0_burst_13_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_13_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_13_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_13_upstream & system_0_burst_13_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_13_upstream & ~system_0_burst_13_upstream_non_bursting_master_requests);

  //system_0_burst_13_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_13_upstream_arb_share_counter <= 0;
      else if (system_0_burst_13_upstream_arb_counter_enable)
          system_0_burst_13_upstream_arb_share_counter <= system_0_burst_13_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_13_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_13_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_13_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_13_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_13_upstream & ~system_0_burst_13_upstream_non_bursting_master_requests))
          system_0_burst_13_upstream_slavearbiterlockenable <= |system_0_burst_13_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_13/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_13_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_13_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_13_upstream_slavearbiterlockenable2 = |system_0_burst_13_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_13/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_13_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_13_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_13_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_13_upstream = cpu_0_data_master_requests_system_0_burst_13_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_13_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_13_upstream_move_on_to_next_transaction = system_0_burst_13_upstream_this_cycle_is_the_last_burst & system_0_burst_13_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_13_upstream, which is an e_mux
  assign system_0_burst_13_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_13_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_13_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_13_upstream_module burstcount_fifo_for_system_0_burst_13_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_13_upstream_selected_burstcount),
      .data_out             (system_0_burst_13_upstream_transaction_burst_count),
      .empty                (system_0_burst_13_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_13_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_13_upstream_waits_for_read & system_0_burst_13_upstream_load_fifo & ~(system_0_burst_13_upstream_this_cycle_is_the_last_burst & system_0_burst_13_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_13_upstream current burst minus one, which is an e_assign
  assign system_0_burst_13_upstream_current_burst_minus_one = system_0_burst_13_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_13_upstream, which is an e_mux
  assign system_0_burst_13_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_13_upstream_waits_for_read) & ~system_0_burst_13_upstream_load_fifo))? system_0_burst_13_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_13_upstream_waits_for_read & system_0_burst_13_upstream_this_cycle_is_the_last_burst & system_0_burst_13_upstream_burstcount_fifo_empty))? system_0_burst_13_upstream_selected_burstcount :
    (system_0_burst_13_upstream_this_cycle_is_the_last_burst)? system_0_burst_13_upstream_transaction_burst_count :
    system_0_burst_13_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_13_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_13_upstream_current_burst <= 0;
      else if (system_0_burst_13_upstream_readdatavalid_from_sa | (~system_0_burst_13_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_13_upstream_waits_for_read)))
          system_0_burst_13_upstream_current_burst <= system_0_burst_13_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_13_upstream_load_fifo = (~system_0_burst_13_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_13_upstream_waits_for_read) & system_0_burst_13_upstream_load_fifo))? 1 :
    ~system_0_burst_13_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_13_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_13_upstream_waits_for_read) & ~system_0_burst_13_upstream_load_fifo | system_0_burst_13_upstream_this_cycle_is_the_last_burst)
          system_0_burst_13_upstream_load_fifo <= p0_system_0_burst_13_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_13_upstream, which is an e_assign
  assign system_0_burst_13_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_13_upstream_current_burst_minus_one) & system_0_burst_13_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_13_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_13_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_13_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_13_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_13_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_13_upstream),
      .full                 (),
      .read                 (system_0_burst_13_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_13_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_13_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_13_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_13_upstream = system_0_burst_13_upstream_readdatavalid_from_sa;

  //system_0_burst_13_upstream_writedata mux, which is an e_mux
  assign system_0_burst_13_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_13/upstream, which is an e_mux
  assign system_0_burst_13_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_13_upstream = cpu_0_data_master_qualified_request_system_0_burst_13_upstream;

  //cpu_0/data_master saved-grant system_0_burst_13/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_13_upstream = cpu_0_data_master_requests_system_0_burst_13_upstream;

  //allow new arb cycle for system_0_burst_13/upstream, which is an e_assign
  assign system_0_burst_13_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_13_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_13_upstream_master_qreq_vector = 1;

  //system_0_burst_13_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_13_upstream_firsttransfer = system_0_burst_13_upstream_begins_xfer ? system_0_burst_13_upstream_unreg_firsttransfer : system_0_burst_13_upstream_reg_firsttransfer;

  //system_0_burst_13_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_13_upstream_unreg_firsttransfer = ~(system_0_burst_13_upstream_slavearbiterlockenable & system_0_burst_13_upstream_any_continuerequest);

  //system_0_burst_13_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_13_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_13_upstream_begins_xfer)
          system_0_burst_13_upstream_reg_firsttransfer <= system_0_burst_13_upstream_unreg_firsttransfer;
    end


  //system_0_burst_13_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_13_upstream_next_bbt_burstcount = ((((system_0_burst_13_upstream_write) && (system_0_burst_13_upstream_bbt_burstcounter == 0))))? (system_0_burst_13_upstream_burstcount - 1) :
    ((((system_0_burst_13_upstream_read) && (system_0_burst_13_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_13_upstream_bbt_burstcounter - 1);

  //system_0_burst_13_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_13_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_13_upstream_begins_xfer)
          system_0_burst_13_upstream_bbt_burstcounter <= system_0_burst_13_upstream_next_bbt_burstcount;
    end


  //system_0_burst_13_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_13_upstream_beginbursttransfer_internal = system_0_burst_13_upstream_begins_xfer & (system_0_burst_13_upstream_bbt_burstcounter == 0);

  //system_0_burst_13_upstream_read assignment, which is an e_mux
  assign system_0_burst_13_upstream_read = cpu_0_data_master_granted_system_0_burst_13_upstream & cpu_0_data_master_read;

  //system_0_burst_13_upstream_write assignment, which is an e_mux
  assign system_0_burst_13_upstream_write = cpu_0_data_master_granted_system_0_burst_13_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_13_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_13_upstream_address mux, which is an e_mux
  assign system_0_burst_13_upstream_address = shifted_address_to_system_0_burst_13_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_13_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_13_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_13_upstream_end_xfer <= system_0_burst_13_upstream_end_xfer;
    end


  //system_0_burst_13_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_13_upstream_waits_for_read = system_0_burst_13_upstream_in_a_read_cycle & system_0_burst_13_upstream_waitrequest_from_sa;

  //system_0_burst_13_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_13_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_13_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_13_upstream_in_a_read_cycle;

  //system_0_burst_13_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_13_upstream_waits_for_write = system_0_burst_13_upstream_in_a_write_cycle & system_0_burst_13_upstream_waitrequest_from_sa;

  //system_0_burst_13_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_13_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_13_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_13_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_13_upstream_counter = 0;
  //system_0_burst_13_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_13_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_13_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_13_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_13_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_13_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_13_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_13/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_13_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_13/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_13_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_SEG7_Display_avalon_slave_0_end_xfer,
                                                  reset_n,
                                                  system_0_burst_13_downstream_address,
                                                  system_0_burst_13_downstream_burstcount,
                                                  system_0_burst_13_downstream_byteenable,
                                                  system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0,
                                                  system_0_burst_13_downstream_qualified_request_SEG7_Display_avalon_slave_0,
                                                  system_0_burst_13_downstream_read,
                                                  system_0_burst_13_downstream_read_data_valid_SEG7_Display_avalon_slave_0,
                                                  system_0_burst_13_downstream_requests_SEG7_Display_avalon_slave_0,
                                                  system_0_burst_13_downstream_write,
                                                  system_0_burst_13_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_13_downstream_address_to_slave,
                                                  system_0_burst_13_downstream_latency_counter,
                                                  system_0_burst_13_downstream_readdata,
                                                  system_0_burst_13_downstream_readdatavalid,
                                                  system_0_burst_13_downstream_reset_n,
                                                  system_0_burst_13_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_13_downstream_address_to_slave;
  output           system_0_burst_13_downstream_latency_counter;
  output  [ 31: 0] system_0_burst_13_downstream_readdata;
  output           system_0_burst_13_downstream_readdatavalid;
  output           system_0_burst_13_downstream_reset_n;
  output           system_0_burst_13_downstream_waitrequest;
  input            clk;
  input            d1_SEG7_Display_avalon_slave_0_end_xfer;
  input            reset_n;
  input   [  1: 0] system_0_burst_13_downstream_address;
  input            system_0_burst_13_downstream_burstcount;
  input   [  3: 0] system_0_burst_13_downstream_byteenable;
  input            system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0;
  input            system_0_burst_13_downstream_qualified_request_SEG7_Display_avalon_slave_0;
  input            system_0_burst_13_downstream_read;
  input            system_0_burst_13_downstream_read_data_valid_SEG7_Display_avalon_slave_0;
  input            system_0_burst_13_downstream_requests_SEG7_Display_avalon_slave_0;
  input            system_0_burst_13_downstream_write;
  input   [ 31: 0] system_0_burst_13_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_13_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_13_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_13_downstream_address_to_slave;
  reg              system_0_burst_13_downstream_burstcount_last_time;
  reg     [  3: 0] system_0_burst_13_downstream_byteenable_last_time;
  wire             system_0_burst_13_downstream_latency_counter;
  reg              system_0_burst_13_downstream_read_last_time;
  wire    [ 31: 0] system_0_burst_13_downstream_readdata;
  wire             system_0_burst_13_downstream_readdatavalid;
  wire             system_0_burst_13_downstream_reset_n;
  wire             system_0_burst_13_downstream_run;
  wire             system_0_burst_13_downstream_waitrequest;
  reg              system_0_burst_13_downstream_write_last_time;
  reg     [ 31: 0] system_0_burst_13_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & ((~system_0_burst_13_downstream_qualified_request_SEG7_Display_avalon_slave_0 | ~(system_0_burst_13_downstream_read | system_0_burst_13_downstream_write) | (1 & ~d1_SEG7_Display_avalon_slave_0_end_xfer & (system_0_burst_13_downstream_read | system_0_burst_13_downstream_write)))) & ((~system_0_burst_13_downstream_qualified_request_SEG7_Display_avalon_slave_0 | ~(system_0_burst_13_downstream_read | system_0_burst_13_downstream_write) | (1 & ~d1_SEG7_Display_avalon_slave_0_end_xfer & (system_0_burst_13_downstream_read | system_0_burst_13_downstream_write))));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_13_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_13_downstream_address_to_slave = system_0_burst_13_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_13_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_13_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_13_downstream_readdatavalid |
    system_0_burst_13_downstream_read_data_valid_SEG7_Display_avalon_slave_0;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_13_downstream_waitrequest = ~system_0_burst_13_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_13_downstream_latency_counter = 0;

  //system_0_burst_13_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_13_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_13_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_13_downstream_address_last_time <= 0;
      else 
        system_0_burst_13_downstream_address_last_time <= system_0_burst_13_downstream_address;
    end


  //system_0_burst_13/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_13_downstream_waitrequest & (system_0_burst_13_downstream_read | system_0_burst_13_downstream_write);
    end


  //system_0_burst_13_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_13_downstream_address != system_0_burst_13_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_13_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_13_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_13_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_13_downstream_burstcount_last_time <= system_0_burst_13_downstream_burstcount;
    end


  //system_0_burst_13_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_13_downstream_burstcount != system_0_burst_13_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_13_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_13_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_13_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_13_downstream_byteenable_last_time <= system_0_burst_13_downstream_byteenable;
    end


  //system_0_burst_13_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_13_downstream_byteenable != system_0_burst_13_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_13_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_13_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_13_downstream_read_last_time <= 0;
      else 
        system_0_burst_13_downstream_read_last_time <= system_0_burst_13_downstream_read;
    end


  //system_0_burst_13_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_13_downstream_read != system_0_burst_13_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_13_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_13_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_13_downstream_write_last_time <= 0;
      else 
        system_0_burst_13_downstream_write_last_time <= system_0_burst_13_downstream_write;
    end


  //system_0_burst_13_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_13_downstream_write != system_0_burst_13_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_13_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_13_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_13_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_13_downstream_writedata_last_time <= system_0_burst_13_downstream_writedata;
    end


  //system_0_burst_13_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_13_downstream_writedata != system_0_burst_13_downstream_writedata_last_time) & system_0_burst_13_downstream_write)
        begin
          $write("%0d ns: system_0_burst_13_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_14_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  4: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  4: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  4: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  4: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  4: 0] p1_stage_1;
  reg     [  4: 0] stage_0;
  reg     [  4: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_14_upstream_module (
                                                                                    // inputs:
                                                                                     clear_fifo,
                                                                                     clk,
                                                                                     data_in,
                                                                                     read,
                                                                                     reset_n,
                                                                                     sync_reset,
                                                                                     write,

                                                                                    // outputs:
                                                                                     data_out,
                                                                                     empty,
                                                                                     fifo_contains_ones_n,
                                                                                     full
                                                                                  )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_14_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_instruction_master_address_to_slave,
                                                cpu_0_instruction_master_burstcount,
                                                cpu_0_instruction_master_dbs_address,
                                                cpu_0_instruction_master_latency_counter,
                                                cpu_0_instruction_master_read,
                                                cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register,
                                                cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register,
                                                cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register,
                                                cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register,
                                                cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register,
                                                reset_n,
                                                system_0_burst_14_upstream_readdata,
                                                system_0_burst_14_upstream_readdatavalid,
                                                system_0_burst_14_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_instruction_master_granted_system_0_burst_14_upstream,
                                                cpu_0_instruction_master_qualified_request_system_0_burst_14_upstream,
                                                cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream,
                                                cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register,
                                                cpu_0_instruction_master_requests_system_0_burst_14_upstream,
                                                d1_system_0_burst_14_upstream_end_xfer,
                                                system_0_burst_14_upstream_address,
                                                system_0_burst_14_upstream_byteaddress,
                                                system_0_burst_14_upstream_byteenable,
                                                system_0_burst_14_upstream_debugaccess,
                                                system_0_burst_14_upstream_read,
                                                system_0_burst_14_upstream_readdata_from_sa,
                                                system_0_burst_14_upstream_waitrequest_from_sa,
                                                system_0_burst_14_upstream_write
                                             )
;

  output           cpu_0_instruction_master_granted_system_0_burst_14_upstream;
  output           cpu_0_instruction_master_qualified_request_system_0_burst_14_upstream;
  output           cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream;
  output           cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register;
  output           cpu_0_instruction_master_requests_system_0_burst_14_upstream;
  output           d1_system_0_burst_14_upstream_end_xfer;
  output  [ 18: 0] system_0_burst_14_upstream_address;
  output  [ 19: 0] system_0_burst_14_upstream_byteaddress;
  output  [  1: 0] system_0_burst_14_upstream_byteenable;
  output           system_0_burst_14_upstream_debugaccess;
  output           system_0_burst_14_upstream_read;
  output  [ 15: 0] system_0_burst_14_upstream_readdata_from_sa;
  output           system_0_burst_14_upstream_waitrequest_from_sa;
  output           system_0_burst_14_upstream_write;
  input            clk;
  input   [ 24: 0] cpu_0_instruction_master_address_to_slave;
  input   [  3: 0] cpu_0_instruction_master_burstcount;
  input   [  1: 0] cpu_0_instruction_master_dbs_address;
  input            cpu_0_instruction_master_latency_counter;
  input            cpu_0_instruction_master_read;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register;
  input            reset_n;
  input   [ 15: 0] system_0_burst_14_upstream_readdata;
  input            system_0_burst_14_upstream_readdatavalid;
  input            system_0_burst_14_upstream_waitrequest;

  wire             cpu_0_instruction_master_arbiterlock;
  wire             cpu_0_instruction_master_arbiterlock2;
  wire             cpu_0_instruction_master_continuerequest;
  wire             cpu_0_instruction_master_granted_system_0_burst_14_upstream;
  wire             cpu_0_instruction_master_qualified_request_system_0_burst_14_upstream;
  wire             cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_14_upstream;
  wire             cpu_0_instruction_master_rdv_fifo_output_from_system_0_burst_14_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register;
  wire             cpu_0_instruction_master_requests_system_0_burst_14_upstream;
  wire             cpu_0_instruction_master_saved_grant_system_0_burst_14_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_14_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_14_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_14_upstream_load_fifo;
  wire    [ 18: 0] system_0_burst_14_upstream_address;
  wire             system_0_burst_14_upstream_allgrants;
  wire             system_0_burst_14_upstream_allow_new_arb_cycle;
  wire             system_0_burst_14_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_14_upstream_any_continuerequest;
  wire             system_0_burst_14_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_14_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_14_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_14_upstream_arb_share_set_values;
  wire             system_0_burst_14_upstream_beginbursttransfer_internal;
  wire             system_0_burst_14_upstream_begins_xfer;
  wire             system_0_burst_14_upstream_burstcount_fifo_empty;
  wire    [ 19: 0] system_0_burst_14_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_14_upstream_byteenable;
  reg     [  4: 0] system_0_burst_14_upstream_current_burst;
  wire    [  4: 0] system_0_burst_14_upstream_current_burst_minus_one;
  wire             system_0_burst_14_upstream_debugaccess;
  wire             system_0_burst_14_upstream_end_xfer;
  wire             system_0_burst_14_upstream_firsttransfer;
  wire             system_0_burst_14_upstream_grant_vector;
  wire             system_0_burst_14_upstream_in_a_read_cycle;
  wire             system_0_burst_14_upstream_in_a_write_cycle;
  reg              system_0_burst_14_upstream_load_fifo;
  wire             system_0_burst_14_upstream_master_qreq_vector;
  wire             system_0_burst_14_upstream_move_on_to_next_transaction;
  wire    [  4: 0] system_0_burst_14_upstream_next_burst_count;
  wire             system_0_burst_14_upstream_non_bursting_master_requests;
  wire             system_0_burst_14_upstream_read;
  wire    [ 15: 0] system_0_burst_14_upstream_readdata_from_sa;
  wire             system_0_burst_14_upstream_readdatavalid_from_sa;
  reg              system_0_burst_14_upstream_reg_firsttransfer;
  wire    [  4: 0] system_0_burst_14_upstream_selected_burstcount;
  reg              system_0_burst_14_upstream_slavearbiterlockenable;
  wire             system_0_burst_14_upstream_slavearbiterlockenable2;
  wire             system_0_burst_14_upstream_this_cycle_is_the_last_burst;
  wire    [  4: 0] system_0_burst_14_upstream_transaction_burst_count;
  wire             system_0_burst_14_upstream_unreg_firsttransfer;
  wire             system_0_burst_14_upstream_waitrequest_from_sa;
  wire             system_0_burst_14_upstream_waits_for_read;
  wire             system_0_burst_14_upstream_waits_for_write;
  wire             system_0_burst_14_upstream_write;
  wire             wait_for_system_0_burst_14_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_14_upstream_end_xfer;
    end


  assign system_0_burst_14_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_instruction_master_qualified_request_system_0_burst_14_upstream));
  //assign system_0_burst_14_upstream_readdatavalid_from_sa = system_0_burst_14_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_14_upstream_readdatavalid_from_sa = system_0_burst_14_upstream_readdatavalid;

  //assign system_0_burst_14_upstream_readdata_from_sa = system_0_burst_14_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_14_upstream_readdata_from_sa = system_0_burst_14_upstream_readdata;

  assign cpu_0_instruction_master_requests_system_0_burst_14_upstream = (({cpu_0_instruction_master_address_to_slave[24 : 19] , 19'b0} == 25'h1880000) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
  //assign system_0_burst_14_upstream_waitrequest_from_sa = system_0_burst_14_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_14_upstream_waitrequest_from_sa = system_0_burst_14_upstream_waitrequest;

  //system_0_burst_14_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_14_upstream_arb_share_set_values = 1;

  //system_0_burst_14_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_14_upstream_non_bursting_master_requests = 0;

  //system_0_burst_14_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_14_upstream_any_bursting_master_saved_grant = cpu_0_instruction_master_saved_grant_system_0_burst_14_upstream;

  //system_0_burst_14_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_14_upstream_arb_share_counter_next_value = system_0_burst_14_upstream_firsttransfer ? (system_0_burst_14_upstream_arb_share_set_values - 1) : |system_0_burst_14_upstream_arb_share_counter ? (system_0_burst_14_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_14_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_14_upstream_allgrants = |system_0_burst_14_upstream_grant_vector;

  //system_0_burst_14_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_14_upstream_end_xfer = ~(system_0_burst_14_upstream_waits_for_read | system_0_burst_14_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_14_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_14_upstream = system_0_burst_14_upstream_end_xfer & (~system_0_burst_14_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_14_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_14_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_14_upstream & system_0_burst_14_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_14_upstream & ~system_0_burst_14_upstream_non_bursting_master_requests);

  //system_0_burst_14_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_14_upstream_arb_share_counter <= 0;
      else if (system_0_burst_14_upstream_arb_counter_enable)
          system_0_burst_14_upstream_arb_share_counter <= system_0_burst_14_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_14_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_14_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_14_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_14_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_14_upstream & ~system_0_burst_14_upstream_non_bursting_master_requests))
          system_0_burst_14_upstream_slavearbiterlockenable <= |system_0_burst_14_upstream_arb_share_counter_next_value;
    end


  //cpu_0/instruction_master system_0_burst_14/upstream arbiterlock, which is an e_assign
  assign cpu_0_instruction_master_arbiterlock = system_0_burst_14_upstream_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;

  //system_0_burst_14_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_14_upstream_slavearbiterlockenable2 = |system_0_burst_14_upstream_arb_share_counter_next_value;

  //cpu_0/instruction_master system_0_burst_14/upstream arbiterlock2, which is an e_assign
  assign cpu_0_instruction_master_arbiterlock2 = system_0_burst_14_upstream_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;

  //system_0_burst_14_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_14_upstream_any_continuerequest = 1;

  //cpu_0_instruction_master_continuerequest continued request, which is an e_assign
  assign cpu_0_instruction_master_continuerequest = 1;

  assign cpu_0_instruction_master_qualified_request_system_0_burst_14_upstream = cpu_0_instruction_master_requests_system_0_burst_14_upstream & ~((cpu_0_instruction_master_read & ((cpu_0_instruction_master_latency_counter != 0) | (1 < cpu_0_instruction_master_latency_counter) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register))));
  //unique name for system_0_burst_14_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_14_upstream_move_on_to_next_transaction = system_0_burst_14_upstream_this_cycle_is_the_last_burst & system_0_burst_14_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_14_upstream, which is an e_mux
  assign system_0_burst_14_upstream_selected_burstcount = (cpu_0_instruction_master_granted_system_0_burst_14_upstream)? cpu_0_instruction_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_14_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_14_upstream_module burstcount_fifo_for_system_0_burst_14_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_14_upstream_selected_burstcount),
      .data_out             (system_0_burst_14_upstream_transaction_burst_count),
      .empty                (system_0_burst_14_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_14_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_14_upstream_waits_for_read & system_0_burst_14_upstream_load_fifo & ~(system_0_burst_14_upstream_this_cycle_is_the_last_burst & system_0_burst_14_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_14_upstream current burst minus one, which is an e_assign
  assign system_0_burst_14_upstream_current_burst_minus_one = system_0_burst_14_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_14_upstream, which is an e_mux
  assign system_0_burst_14_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_14_upstream_waits_for_read) & ~system_0_burst_14_upstream_load_fifo))? {system_0_burst_14_upstream_selected_burstcount, 1'b0} :
    ((in_a_read_cycle & ~system_0_burst_14_upstream_waits_for_read & system_0_burst_14_upstream_this_cycle_is_the_last_burst & system_0_burst_14_upstream_burstcount_fifo_empty))? {system_0_burst_14_upstream_selected_burstcount, 1'b0} :
    (system_0_burst_14_upstream_this_cycle_is_the_last_burst)? {system_0_burst_14_upstream_transaction_burst_count,  1'b0} :
    system_0_burst_14_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_14_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_14_upstream_current_burst <= 0;
      else if (system_0_burst_14_upstream_readdatavalid_from_sa | (~system_0_burst_14_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_14_upstream_waits_for_read)))
          system_0_burst_14_upstream_current_burst <= system_0_burst_14_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_14_upstream_load_fifo = (~system_0_burst_14_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_14_upstream_waits_for_read) & system_0_burst_14_upstream_load_fifo))? 1 :
    ~system_0_burst_14_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_14_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_14_upstream_waits_for_read) & ~system_0_burst_14_upstream_load_fifo | system_0_burst_14_upstream_this_cycle_is_the_last_burst)
          system_0_burst_14_upstream_load_fifo <= p0_system_0_burst_14_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_14_upstream, which is an e_assign
  assign system_0_burst_14_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_14_upstream_current_burst_minus_one) & system_0_burst_14_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_14_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_14_upstream_module rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_14_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_instruction_master_granted_system_0_burst_14_upstream),
      .data_out             (cpu_0_instruction_master_rdv_fifo_output_from_system_0_burst_14_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_14_upstream),
      .full                 (),
      .read                 (system_0_burst_14_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_14_upstream_waits_for_read)
    );

  assign cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register = ~cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_14_upstream;
  //local readdatavalid cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream, which is an e_mux
  assign cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream = system_0_burst_14_upstream_readdatavalid_from_sa;

  //byteaddress mux for system_0_burst_14/upstream, which is an e_mux
  assign system_0_burst_14_upstream_byteaddress = cpu_0_instruction_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_instruction_master_granted_system_0_burst_14_upstream = cpu_0_instruction_master_qualified_request_system_0_burst_14_upstream;

  //cpu_0/instruction_master saved-grant system_0_burst_14/upstream, which is an e_assign
  assign cpu_0_instruction_master_saved_grant_system_0_burst_14_upstream = cpu_0_instruction_master_requests_system_0_burst_14_upstream;

  //allow new arb cycle for system_0_burst_14/upstream, which is an e_assign
  assign system_0_burst_14_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_14_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_14_upstream_master_qreq_vector = 1;

  //system_0_burst_14_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_14_upstream_firsttransfer = system_0_burst_14_upstream_begins_xfer ? system_0_burst_14_upstream_unreg_firsttransfer : system_0_burst_14_upstream_reg_firsttransfer;

  //system_0_burst_14_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_14_upstream_unreg_firsttransfer = ~(system_0_burst_14_upstream_slavearbiterlockenable & system_0_burst_14_upstream_any_continuerequest);

  //system_0_burst_14_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_14_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_14_upstream_begins_xfer)
          system_0_burst_14_upstream_reg_firsttransfer <= system_0_burst_14_upstream_unreg_firsttransfer;
    end


  //system_0_burst_14_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_14_upstream_beginbursttransfer_internal = system_0_burst_14_upstream_begins_xfer;

  //system_0_burst_14_upstream_read assignment, which is an e_mux
  assign system_0_burst_14_upstream_read = cpu_0_instruction_master_granted_system_0_burst_14_upstream & cpu_0_instruction_master_read;

  //system_0_burst_14_upstream_write assignment, which is an e_mux
  assign system_0_burst_14_upstream_write = 0;

  //system_0_burst_14_upstream_address mux, which is an e_mux
  assign system_0_burst_14_upstream_address = {cpu_0_instruction_master_address_to_slave >> 2,
    cpu_0_instruction_master_dbs_address[1],
    {1 {1'b0}}};

  //d1_system_0_burst_14_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_14_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_14_upstream_end_xfer <= system_0_burst_14_upstream_end_xfer;
    end


  //system_0_burst_14_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_14_upstream_waits_for_read = system_0_burst_14_upstream_in_a_read_cycle & system_0_burst_14_upstream_waitrequest_from_sa;

  //system_0_burst_14_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_14_upstream_in_a_read_cycle = cpu_0_instruction_master_granted_system_0_burst_14_upstream & cpu_0_instruction_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_14_upstream_in_a_read_cycle;

  //system_0_burst_14_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_14_upstream_waits_for_write = system_0_burst_14_upstream_in_a_write_cycle & system_0_burst_14_upstream_waitrequest_from_sa;

  //system_0_burst_14_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_14_upstream_in_a_write_cycle = 0;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_14_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_14_upstream_counter = 0;
  //system_0_burst_14_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_14_upstream_byteenable = -1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_14_upstream_debugaccess = 0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_14/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/instruction_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_instruction_master_requests_system_0_burst_14_upstream && (cpu_0_instruction_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/instruction_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_14/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_14_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_sram_0_avalon_slave_0_end_xfer,
                                                  reset_n,
                                                  sram_0_avalon_slave_0_readdata_from_sa,
                                                  sram_0_avalon_slave_0_wait_counter_eq_0,
                                                  system_0_burst_14_downstream_address,
                                                  system_0_burst_14_downstream_burstcount,
                                                  system_0_burst_14_downstream_byteenable,
                                                  system_0_burst_14_downstream_granted_sram_0_avalon_slave_0,
                                                  system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0,
                                                  system_0_burst_14_downstream_read,
                                                  system_0_burst_14_downstream_read_data_valid_sram_0_avalon_slave_0,
                                                  system_0_burst_14_downstream_requests_sram_0_avalon_slave_0,
                                                  system_0_burst_14_downstream_write,
                                                  system_0_burst_14_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_14_downstream_address_to_slave,
                                                  system_0_burst_14_downstream_latency_counter,
                                                  system_0_burst_14_downstream_readdata,
                                                  system_0_burst_14_downstream_readdatavalid,
                                                  system_0_burst_14_downstream_reset_n,
                                                  system_0_burst_14_downstream_waitrequest
                                               )
;

  output  [ 18: 0] system_0_burst_14_downstream_address_to_slave;
  output           system_0_burst_14_downstream_latency_counter;
  output  [ 15: 0] system_0_burst_14_downstream_readdata;
  output           system_0_burst_14_downstream_readdatavalid;
  output           system_0_burst_14_downstream_reset_n;
  output           system_0_burst_14_downstream_waitrequest;
  input            clk;
  input            d1_sram_0_avalon_slave_0_end_xfer;
  input            reset_n;
  input   [ 15: 0] sram_0_avalon_slave_0_readdata_from_sa;
  input            sram_0_avalon_slave_0_wait_counter_eq_0;
  input   [ 18: 0] system_0_burst_14_downstream_address;
  input            system_0_burst_14_downstream_burstcount;
  input   [  1: 0] system_0_burst_14_downstream_byteenable;
  input            system_0_burst_14_downstream_granted_sram_0_avalon_slave_0;
  input            system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0;
  input            system_0_burst_14_downstream_read;
  input            system_0_burst_14_downstream_read_data_valid_sram_0_avalon_slave_0;
  input            system_0_burst_14_downstream_requests_sram_0_avalon_slave_0;
  input            system_0_burst_14_downstream_write;
  input   [ 15: 0] system_0_burst_14_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             latency_load_value;
  wire             p1_system_0_burst_14_downstream_latency_counter;
  wire             pre_flush_system_0_burst_14_downstream_readdatavalid;
  wire             r_0;
  reg     [ 18: 0] system_0_burst_14_downstream_address_last_time;
  wire    [ 18: 0] system_0_burst_14_downstream_address_to_slave;
  reg              system_0_burst_14_downstream_burstcount_last_time;
  reg     [  1: 0] system_0_burst_14_downstream_byteenable_last_time;
  wire             system_0_burst_14_downstream_is_granted_some_slave;
  reg              system_0_burst_14_downstream_latency_counter;
  reg              system_0_burst_14_downstream_read_but_no_slave_selected;
  reg              system_0_burst_14_downstream_read_last_time;
  wire    [ 15: 0] system_0_burst_14_downstream_readdata;
  wire             system_0_burst_14_downstream_readdatavalid;
  wire             system_0_burst_14_downstream_reset_n;
  wire             system_0_burst_14_downstream_run;
  wire             system_0_burst_14_downstream_waitrequest;
  reg              system_0_burst_14_downstream_write_last_time;
  reg     [ 15: 0] system_0_burst_14_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0 | ~system_0_burst_14_downstream_requests_sram_0_avalon_slave_0) & (system_0_burst_14_downstream_granted_sram_0_avalon_slave_0 | ~system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0) & ((~system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0 | ~system_0_burst_14_downstream_read | (1 & ((sram_0_avalon_slave_0_wait_counter_eq_0 & ~d1_sram_0_avalon_slave_0_end_xfer)) & system_0_burst_14_downstream_read))) & ((~system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0 | ~system_0_burst_14_downstream_write | (1 & ((sram_0_avalon_slave_0_wait_counter_eq_0 & ~d1_sram_0_avalon_slave_0_end_xfer)) & system_0_burst_14_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_14_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_14_downstream_address_to_slave = system_0_burst_14_downstream_address;

  //system_0_burst_14_downstream_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_14_downstream_read_but_no_slave_selected <= 0;
      else 
        system_0_burst_14_downstream_read_but_no_slave_selected <= system_0_burst_14_downstream_read & system_0_burst_14_downstream_run & ~system_0_burst_14_downstream_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign system_0_burst_14_downstream_is_granted_some_slave = system_0_burst_14_downstream_granted_sram_0_avalon_slave_0;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_14_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_14_downstream_readdatavalid = system_0_burst_14_downstream_read_but_no_slave_selected |
    pre_flush_system_0_burst_14_downstream_readdatavalid |
    system_0_burst_14_downstream_read_data_valid_sram_0_avalon_slave_0;

  //system_0_burst_14/downstream readdata mux, which is an e_mux
  assign system_0_burst_14_downstream_readdata = sram_0_avalon_slave_0_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_14_downstream_waitrequest = ~system_0_burst_14_downstream_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_14_downstream_latency_counter <= 0;
      else 
        system_0_burst_14_downstream_latency_counter <= p1_system_0_burst_14_downstream_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_system_0_burst_14_downstream_latency_counter = ((system_0_burst_14_downstream_run & system_0_burst_14_downstream_read))? latency_load_value :
    (system_0_burst_14_downstream_latency_counter)? system_0_burst_14_downstream_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = 0;

  //system_0_burst_14_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_14_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_14_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_14_downstream_address_last_time <= 0;
      else 
        system_0_burst_14_downstream_address_last_time <= system_0_burst_14_downstream_address;
    end


  //system_0_burst_14/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_14_downstream_waitrequest & (system_0_burst_14_downstream_read | system_0_burst_14_downstream_write);
    end


  //system_0_burst_14_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_14_downstream_address != system_0_burst_14_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_14_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_14_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_14_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_14_downstream_burstcount_last_time <= system_0_burst_14_downstream_burstcount;
    end


  //system_0_burst_14_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_14_downstream_burstcount != system_0_burst_14_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_14_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_14_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_14_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_14_downstream_byteenable_last_time <= system_0_burst_14_downstream_byteenable;
    end


  //system_0_burst_14_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_14_downstream_byteenable != system_0_burst_14_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_14_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_14_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_14_downstream_read_last_time <= 0;
      else 
        system_0_burst_14_downstream_read_last_time <= system_0_burst_14_downstream_read;
    end


  //system_0_burst_14_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_14_downstream_read != system_0_burst_14_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_14_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_14_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_14_downstream_write_last_time <= 0;
      else 
        system_0_burst_14_downstream_write_last_time <= system_0_burst_14_downstream_write;
    end


  //system_0_burst_14_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_14_downstream_write != system_0_burst_14_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_14_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_14_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_14_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_14_downstream_writedata_last_time <= system_0_burst_14_downstream_writedata;
    end


  //system_0_burst_14_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_14_downstream_writedata != system_0_burst_14_downstream_writedata_last_time) & system_0_burst_14_downstream_write)
        begin
          $write("%0d ns: system_0_burst_14_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_15_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  4: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  4: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  4: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  4: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  4: 0] p1_stage_1;
  reg     [  4: 0] stage_0;
  reg     [  4: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_15_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_15_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_dbs_address,
                                                cpu_0_data_master_dbs_write_16,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                reset_n,
                                                system_0_burst_15_upstream_readdata,
                                                system_0_burst_15_upstream_readdatavalid,
                                                system_0_burst_15_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_byteenable_system_0_burst_15_upstream,
                                                cpu_0_data_master_granted_system_0_burst_15_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_15_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_15_upstream,
                                                d1_system_0_burst_15_upstream_end_xfer,
                                                system_0_burst_15_upstream_address,
                                                system_0_burst_15_upstream_burstcount,
                                                system_0_burst_15_upstream_byteaddress,
                                                system_0_burst_15_upstream_byteenable,
                                                system_0_burst_15_upstream_debugaccess,
                                                system_0_burst_15_upstream_read,
                                                system_0_burst_15_upstream_readdata_from_sa,
                                                system_0_burst_15_upstream_waitrequest_from_sa,
                                                system_0_burst_15_upstream_write,
                                                system_0_burst_15_upstream_writedata
                                             )
;

  output  [  1: 0] cpu_0_data_master_byteenable_system_0_burst_15_upstream;
  output           cpu_0_data_master_granted_system_0_burst_15_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_15_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_15_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_15_upstream;
  output           d1_system_0_burst_15_upstream_end_xfer;
  output  [ 18: 0] system_0_burst_15_upstream_address;
  output  [  3: 0] system_0_burst_15_upstream_burstcount;
  output  [ 19: 0] system_0_burst_15_upstream_byteaddress;
  output  [  1: 0] system_0_burst_15_upstream_byteenable;
  output           system_0_burst_15_upstream_debugaccess;
  output           system_0_burst_15_upstream_read;
  output  [ 15: 0] system_0_burst_15_upstream_readdata_from_sa;
  output           system_0_burst_15_upstream_waitrequest_from_sa;
  output           system_0_burst_15_upstream_write;
  output  [ 15: 0] system_0_burst_15_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input   [  1: 0] cpu_0_data_master_dbs_address;
  input   [ 15: 0] cpu_0_data_master_dbs_write_16;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input            reset_n;
  input   [ 15: 0] system_0_burst_15_upstream_readdata;
  input            system_0_burst_15_upstream_readdatavalid;
  input            system_0_burst_15_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire    [  1: 0] cpu_0_data_master_byteenable_system_0_burst_15_upstream;
  wire    [  1: 0] cpu_0_data_master_byteenable_system_0_burst_15_upstream_segment_0;
  wire    [  1: 0] cpu_0_data_master_byteenable_system_0_burst_15_upstream_segment_1;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_15_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_15_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_15_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_15_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_15_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_15_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_15_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_15_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_15_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_15_upstream_load_fifo;
  wire    [ 18: 0] system_0_burst_15_upstream_address;
  wire             system_0_burst_15_upstream_allgrants;
  wire             system_0_burst_15_upstream_allow_new_arb_cycle;
  wire             system_0_burst_15_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_15_upstream_any_continuerequest;
  wire             system_0_burst_15_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_15_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_15_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_15_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_15_upstream_bbt_burstcounter;
  wire             system_0_burst_15_upstream_beginbursttransfer_internal;
  wire             system_0_burst_15_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_15_upstream_burstcount;
  wire             system_0_burst_15_upstream_burstcount_fifo_empty;
  wire    [ 19: 0] system_0_burst_15_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_15_upstream_byteenable;
  reg     [  4: 0] system_0_burst_15_upstream_current_burst;
  wire    [  4: 0] system_0_burst_15_upstream_current_burst_minus_one;
  wire             system_0_burst_15_upstream_debugaccess;
  wire             system_0_burst_15_upstream_end_xfer;
  wire             system_0_burst_15_upstream_firsttransfer;
  wire             system_0_burst_15_upstream_grant_vector;
  wire             system_0_burst_15_upstream_in_a_read_cycle;
  wire             system_0_burst_15_upstream_in_a_write_cycle;
  reg              system_0_burst_15_upstream_load_fifo;
  wire             system_0_burst_15_upstream_master_qreq_vector;
  wire             system_0_burst_15_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_15_upstream_next_bbt_burstcount;
  wire    [  4: 0] system_0_burst_15_upstream_next_burst_count;
  wire             system_0_burst_15_upstream_non_bursting_master_requests;
  wire             system_0_burst_15_upstream_read;
  wire    [ 15: 0] system_0_burst_15_upstream_readdata_from_sa;
  wire             system_0_burst_15_upstream_readdatavalid_from_sa;
  reg              system_0_burst_15_upstream_reg_firsttransfer;
  wire    [  4: 0] system_0_burst_15_upstream_selected_burstcount;
  reg              system_0_burst_15_upstream_slavearbiterlockenable;
  wire             system_0_burst_15_upstream_slavearbiterlockenable2;
  wire             system_0_burst_15_upstream_this_cycle_is_the_last_burst;
  wire    [  4: 0] system_0_burst_15_upstream_transaction_burst_count;
  wire             system_0_burst_15_upstream_unreg_firsttransfer;
  wire             system_0_burst_15_upstream_waitrequest_from_sa;
  wire             system_0_burst_15_upstream_waits_for_read;
  wire             system_0_burst_15_upstream_waits_for_write;
  wire             system_0_burst_15_upstream_write;
  wire    [ 15: 0] system_0_burst_15_upstream_writedata;
  wire             wait_for_system_0_burst_15_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_15_upstream_end_xfer;
    end


  assign system_0_burst_15_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_15_upstream));
  //assign system_0_burst_15_upstream_readdatavalid_from_sa = system_0_burst_15_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_15_upstream_readdatavalid_from_sa = system_0_burst_15_upstream_readdatavalid;

  //assign system_0_burst_15_upstream_readdata_from_sa = system_0_burst_15_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_15_upstream_readdata_from_sa = system_0_burst_15_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_15_upstream = ({cpu_0_data_master_address_to_slave[24 : 19] , 19'b0} == 25'h1880000) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_15_upstream_waitrequest_from_sa = system_0_burst_15_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_15_upstream_waitrequest_from_sa = system_0_burst_15_upstream_waitrequest;

  //system_0_burst_15_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_15_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_15_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount<< 1 : 1)) :
    1;

  //system_0_burst_15_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_15_upstream_non_bursting_master_requests = 0;

  //system_0_burst_15_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_15_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_15_upstream;

  //system_0_burst_15_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_15_upstream_arb_share_counter_next_value = system_0_burst_15_upstream_firsttransfer ? (system_0_burst_15_upstream_arb_share_set_values - 1) : |system_0_burst_15_upstream_arb_share_counter ? (system_0_burst_15_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_15_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_15_upstream_allgrants = |system_0_burst_15_upstream_grant_vector;

  //system_0_burst_15_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_15_upstream_end_xfer = ~(system_0_burst_15_upstream_waits_for_read | system_0_burst_15_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_15_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_15_upstream = system_0_burst_15_upstream_end_xfer & (~system_0_burst_15_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_15_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_15_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_15_upstream & system_0_burst_15_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_15_upstream & ~system_0_burst_15_upstream_non_bursting_master_requests);

  //system_0_burst_15_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_15_upstream_arb_share_counter <= 0;
      else if (system_0_burst_15_upstream_arb_counter_enable)
          system_0_burst_15_upstream_arb_share_counter <= system_0_burst_15_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_15_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_15_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_15_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_15_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_15_upstream & ~system_0_burst_15_upstream_non_bursting_master_requests))
          system_0_burst_15_upstream_slavearbiterlockenable <= |system_0_burst_15_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_15/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_15_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_15_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_15_upstream_slavearbiterlockenable2 = |system_0_burst_15_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_15/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_15_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_15_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_15_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_15_upstream = cpu_0_data_master_requests_system_0_burst_15_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_15_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_15_upstream_move_on_to_next_transaction = system_0_burst_15_upstream_this_cycle_is_the_last_burst & system_0_burst_15_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_15_upstream, which is an e_mux
  assign system_0_burst_15_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_15_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_15_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_15_upstream_module burstcount_fifo_for_system_0_burst_15_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_15_upstream_selected_burstcount),
      .data_out             (system_0_burst_15_upstream_transaction_burst_count),
      .empty                (system_0_burst_15_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_15_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_15_upstream_waits_for_read & system_0_burst_15_upstream_load_fifo & ~(system_0_burst_15_upstream_this_cycle_is_the_last_burst & system_0_burst_15_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_15_upstream current burst minus one, which is an e_assign
  assign system_0_burst_15_upstream_current_burst_minus_one = system_0_burst_15_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_15_upstream, which is an e_mux
  assign system_0_burst_15_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_15_upstream_waits_for_read) & ~system_0_burst_15_upstream_load_fifo))? {system_0_burst_15_upstream_selected_burstcount, 1'b0} :
    ((in_a_read_cycle & ~system_0_burst_15_upstream_waits_for_read & system_0_burst_15_upstream_this_cycle_is_the_last_burst & system_0_burst_15_upstream_burstcount_fifo_empty))? {system_0_burst_15_upstream_selected_burstcount, 1'b0} :
    (system_0_burst_15_upstream_this_cycle_is_the_last_burst)? {system_0_burst_15_upstream_transaction_burst_count,  1'b0} :
    system_0_burst_15_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_15_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_15_upstream_current_burst <= 0;
      else if (system_0_burst_15_upstream_readdatavalid_from_sa | (~system_0_burst_15_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_15_upstream_waits_for_read)))
          system_0_burst_15_upstream_current_burst <= system_0_burst_15_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_15_upstream_load_fifo = (~system_0_burst_15_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_15_upstream_waits_for_read) & system_0_burst_15_upstream_load_fifo))? 1 :
    ~system_0_burst_15_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_15_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_15_upstream_waits_for_read) & ~system_0_burst_15_upstream_load_fifo | system_0_burst_15_upstream_this_cycle_is_the_last_burst)
          system_0_burst_15_upstream_load_fifo <= p0_system_0_burst_15_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_15_upstream, which is an e_assign
  assign system_0_burst_15_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_15_upstream_current_burst_minus_one) & system_0_burst_15_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_15_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_15_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_15_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_15_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_15_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_15_upstream),
      .full                 (),
      .read                 (system_0_burst_15_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_15_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_15_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_15_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_15_upstream = system_0_burst_15_upstream_readdatavalid_from_sa;

  //system_0_burst_15_upstream_writedata mux, which is an e_mux
  assign system_0_burst_15_upstream_writedata = cpu_0_data_master_dbs_write_16;

  //byteaddress mux for system_0_burst_15/upstream, which is an e_mux
  assign system_0_burst_15_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_15_upstream = cpu_0_data_master_qualified_request_system_0_burst_15_upstream;

  //cpu_0/data_master saved-grant system_0_burst_15/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_15_upstream = cpu_0_data_master_requests_system_0_burst_15_upstream;

  //allow new arb cycle for system_0_burst_15/upstream, which is an e_assign
  assign system_0_burst_15_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_15_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_15_upstream_master_qreq_vector = 1;

  //system_0_burst_15_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_15_upstream_firsttransfer = system_0_burst_15_upstream_begins_xfer ? system_0_burst_15_upstream_unreg_firsttransfer : system_0_burst_15_upstream_reg_firsttransfer;

  //system_0_burst_15_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_15_upstream_unreg_firsttransfer = ~(system_0_burst_15_upstream_slavearbiterlockenable & system_0_burst_15_upstream_any_continuerequest);

  //system_0_burst_15_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_15_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_15_upstream_begins_xfer)
          system_0_burst_15_upstream_reg_firsttransfer <= system_0_burst_15_upstream_unreg_firsttransfer;
    end


  //system_0_burst_15_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_15_upstream_next_bbt_burstcount = ((((system_0_burst_15_upstream_write) && (system_0_burst_15_upstream_bbt_burstcounter == 0))))? (system_0_burst_15_upstream_burstcount - 1) :
    ((((system_0_burst_15_upstream_read) && (system_0_burst_15_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_15_upstream_bbt_burstcounter - 1);

  //system_0_burst_15_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_15_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_15_upstream_begins_xfer)
          system_0_burst_15_upstream_bbt_burstcounter <= system_0_burst_15_upstream_next_bbt_burstcount;
    end


  //system_0_burst_15_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_15_upstream_beginbursttransfer_internal = system_0_burst_15_upstream_begins_xfer & (system_0_burst_15_upstream_bbt_burstcounter == 0);

  //system_0_burst_15_upstream_read assignment, which is an e_mux
  assign system_0_burst_15_upstream_read = cpu_0_data_master_granted_system_0_burst_15_upstream & cpu_0_data_master_read;

  //system_0_burst_15_upstream_write assignment, which is an e_mux
  assign system_0_burst_15_upstream_write = cpu_0_data_master_granted_system_0_burst_15_upstream & cpu_0_data_master_write;

  //system_0_burst_15_upstream_address mux, which is an e_mux
  assign system_0_burst_15_upstream_address = {cpu_0_data_master_address_to_slave >> 2,
    cpu_0_data_master_dbs_address[1],
    {1 {1'b0}}};

  //d1_system_0_burst_15_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_15_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_15_upstream_end_xfer <= system_0_burst_15_upstream_end_xfer;
    end


  //system_0_burst_15_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_15_upstream_waits_for_read = system_0_burst_15_upstream_in_a_read_cycle & system_0_burst_15_upstream_waitrequest_from_sa;

  //system_0_burst_15_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_15_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_15_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_15_upstream_in_a_read_cycle;

  //system_0_burst_15_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_15_upstream_waits_for_write = system_0_burst_15_upstream_in_a_write_cycle & system_0_burst_15_upstream_waitrequest_from_sa;

  //system_0_burst_15_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_15_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_15_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_15_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_15_upstream_counter = 0;
  //system_0_burst_15_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_15_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_15_upstream)? cpu_0_data_master_byteenable_system_0_burst_15_upstream :
    -1;

  assign {cpu_0_data_master_byteenable_system_0_burst_15_upstream_segment_1,
cpu_0_data_master_byteenable_system_0_burst_15_upstream_segment_0} = cpu_0_data_master_byteenable;
  assign cpu_0_data_master_byteenable_system_0_burst_15_upstream = ((cpu_0_data_master_dbs_address[1] == 0))? cpu_0_data_master_byteenable_system_0_burst_15_upstream_segment_0 :
    cpu_0_data_master_byteenable_system_0_burst_15_upstream_segment_1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_15_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_15_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_15_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_15_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_15/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_15_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_15/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_15_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_sram_0_avalon_slave_0_end_xfer,
                                                  reset_n,
                                                  sram_0_avalon_slave_0_readdata_from_sa,
                                                  sram_0_avalon_slave_0_wait_counter_eq_0,
                                                  system_0_burst_15_downstream_address,
                                                  system_0_burst_15_downstream_burstcount,
                                                  system_0_burst_15_downstream_byteenable,
                                                  system_0_burst_15_downstream_granted_sram_0_avalon_slave_0,
                                                  system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0,
                                                  system_0_burst_15_downstream_read,
                                                  system_0_burst_15_downstream_read_data_valid_sram_0_avalon_slave_0,
                                                  system_0_burst_15_downstream_requests_sram_0_avalon_slave_0,
                                                  system_0_burst_15_downstream_write,
                                                  system_0_burst_15_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_15_downstream_address_to_slave,
                                                  system_0_burst_15_downstream_latency_counter,
                                                  system_0_burst_15_downstream_readdata,
                                                  system_0_burst_15_downstream_readdatavalid,
                                                  system_0_burst_15_downstream_reset_n,
                                                  system_0_burst_15_downstream_waitrequest
                                               )
;

  output  [ 18: 0] system_0_burst_15_downstream_address_to_slave;
  output           system_0_burst_15_downstream_latency_counter;
  output  [ 15: 0] system_0_burst_15_downstream_readdata;
  output           system_0_burst_15_downstream_readdatavalid;
  output           system_0_burst_15_downstream_reset_n;
  output           system_0_burst_15_downstream_waitrequest;
  input            clk;
  input            d1_sram_0_avalon_slave_0_end_xfer;
  input            reset_n;
  input   [ 15: 0] sram_0_avalon_slave_0_readdata_from_sa;
  input            sram_0_avalon_slave_0_wait_counter_eq_0;
  input   [ 18: 0] system_0_burst_15_downstream_address;
  input            system_0_burst_15_downstream_burstcount;
  input   [  1: 0] system_0_burst_15_downstream_byteenable;
  input            system_0_burst_15_downstream_granted_sram_0_avalon_slave_0;
  input            system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0;
  input            system_0_burst_15_downstream_read;
  input            system_0_burst_15_downstream_read_data_valid_sram_0_avalon_slave_0;
  input            system_0_burst_15_downstream_requests_sram_0_avalon_slave_0;
  input            system_0_burst_15_downstream_write;
  input   [ 15: 0] system_0_burst_15_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             latency_load_value;
  wire             p1_system_0_burst_15_downstream_latency_counter;
  wire             pre_flush_system_0_burst_15_downstream_readdatavalid;
  wire             r_0;
  reg     [ 18: 0] system_0_burst_15_downstream_address_last_time;
  wire    [ 18: 0] system_0_burst_15_downstream_address_to_slave;
  reg              system_0_burst_15_downstream_burstcount_last_time;
  reg     [  1: 0] system_0_burst_15_downstream_byteenable_last_time;
  wire             system_0_burst_15_downstream_is_granted_some_slave;
  reg              system_0_burst_15_downstream_latency_counter;
  reg              system_0_burst_15_downstream_read_but_no_slave_selected;
  reg              system_0_burst_15_downstream_read_last_time;
  wire    [ 15: 0] system_0_burst_15_downstream_readdata;
  wire             system_0_burst_15_downstream_readdatavalid;
  wire             system_0_burst_15_downstream_reset_n;
  wire             system_0_burst_15_downstream_run;
  wire             system_0_burst_15_downstream_waitrequest;
  reg              system_0_burst_15_downstream_write_last_time;
  reg     [ 15: 0] system_0_burst_15_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0 | ~system_0_burst_15_downstream_requests_sram_0_avalon_slave_0) & (system_0_burst_15_downstream_granted_sram_0_avalon_slave_0 | ~system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0) & ((~system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0 | ~system_0_burst_15_downstream_read | (1 & ((sram_0_avalon_slave_0_wait_counter_eq_0 & ~d1_sram_0_avalon_slave_0_end_xfer)) & system_0_burst_15_downstream_read))) & ((~system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0 | ~system_0_burst_15_downstream_write | (1 & ((sram_0_avalon_slave_0_wait_counter_eq_0 & ~d1_sram_0_avalon_slave_0_end_xfer)) & system_0_burst_15_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_15_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_15_downstream_address_to_slave = system_0_burst_15_downstream_address;

  //system_0_burst_15_downstream_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_15_downstream_read_but_no_slave_selected <= 0;
      else 
        system_0_burst_15_downstream_read_but_no_slave_selected <= system_0_burst_15_downstream_read & system_0_burst_15_downstream_run & ~system_0_burst_15_downstream_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign system_0_burst_15_downstream_is_granted_some_slave = system_0_burst_15_downstream_granted_sram_0_avalon_slave_0;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_15_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_15_downstream_readdatavalid = system_0_burst_15_downstream_read_but_no_slave_selected |
    pre_flush_system_0_burst_15_downstream_readdatavalid |
    system_0_burst_15_downstream_read_data_valid_sram_0_avalon_slave_0;

  //system_0_burst_15/downstream readdata mux, which is an e_mux
  assign system_0_burst_15_downstream_readdata = sram_0_avalon_slave_0_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_15_downstream_waitrequest = ~system_0_burst_15_downstream_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_15_downstream_latency_counter <= 0;
      else 
        system_0_burst_15_downstream_latency_counter <= p1_system_0_burst_15_downstream_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_system_0_burst_15_downstream_latency_counter = ((system_0_burst_15_downstream_run & system_0_burst_15_downstream_read))? latency_load_value :
    (system_0_burst_15_downstream_latency_counter)? system_0_burst_15_downstream_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = 0;

  //system_0_burst_15_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_15_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_15_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_15_downstream_address_last_time <= 0;
      else 
        system_0_burst_15_downstream_address_last_time <= system_0_burst_15_downstream_address;
    end


  //system_0_burst_15/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_15_downstream_waitrequest & (system_0_burst_15_downstream_read | system_0_burst_15_downstream_write);
    end


  //system_0_burst_15_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_15_downstream_address != system_0_burst_15_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_15_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_15_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_15_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_15_downstream_burstcount_last_time <= system_0_burst_15_downstream_burstcount;
    end


  //system_0_burst_15_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_15_downstream_burstcount != system_0_burst_15_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_15_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_15_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_15_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_15_downstream_byteenable_last_time <= system_0_burst_15_downstream_byteenable;
    end


  //system_0_burst_15_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_15_downstream_byteenable != system_0_burst_15_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_15_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_15_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_15_downstream_read_last_time <= 0;
      else 
        system_0_burst_15_downstream_read_last_time <= system_0_burst_15_downstream_read;
    end


  //system_0_burst_15_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_15_downstream_read != system_0_burst_15_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_15_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_15_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_15_downstream_write_last_time <= 0;
      else 
        system_0_burst_15_downstream_write_last_time <= system_0_burst_15_downstream_write;
    end


  //system_0_burst_15_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_15_downstream_write != system_0_burst_15_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_15_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_15_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_15_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_15_downstream_writedata_last_time <= system_0_burst_15_downstream_writedata;
    end


  //system_0_burst_15_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_15_downstream_writedata != system_0_burst_15_downstream_writedata_last_time) & system_0_burst_15_downstream_write)
        begin
          $write("%0d ns: system_0_burst_15_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_16_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_16_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_16_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_16_upstream_readdata,
                                                system_0_burst_16_upstream_readdatavalid,
                                                system_0_burst_16_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_16_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_16_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_16_upstream,
                                                d1_system_0_burst_16_upstream_end_xfer,
                                                system_0_burst_16_upstream_address,
                                                system_0_burst_16_upstream_burstcount,
                                                system_0_burst_16_upstream_byteaddress,
                                                system_0_burst_16_upstream_byteenable,
                                                system_0_burst_16_upstream_debugaccess,
                                                system_0_burst_16_upstream_read,
                                                system_0_burst_16_upstream_readdata_from_sa,
                                                system_0_burst_16_upstream_waitrequest_from_sa,
                                                system_0_burst_16_upstream_write,
                                                system_0_burst_16_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_16_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_16_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_16_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_16_upstream;
  output           d1_system_0_burst_16_upstream_end_xfer;
  output           system_0_burst_16_upstream_address;
  output  [  3: 0] system_0_burst_16_upstream_burstcount;
  output  [  1: 0] system_0_burst_16_upstream_byteaddress;
  output  [  1: 0] system_0_burst_16_upstream_byteenable;
  output           system_0_burst_16_upstream_debugaccess;
  output           system_0_burst_16_upstream_read;
  output  [ 15: 0] system_0_burst_16_upstream_readdata_from_sa;
  output           system_0_burst_16_upstream_waitrequest_from_sa;
  output           system_0_burst_16_upstream_write;
  output  [ 15: 0] system_0_burst_16_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [ 15: 0] system_0_burst_16_upstream_readdata;
  input            system_0_burst_16_upstream_readdatavalid;
  input            system_0_burst_16_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_16_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_16_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_16_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_16_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_16_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_16_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_16_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_16_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_16_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_16_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_16_upstream_from_cpu_0_data_master;
  wire             system_0_burst_16_upstream_address;
  wire             system_0_burst_16_upstream_allgrants;
  wire             system_0_burst_16_upstream_allow_new_arb_cycle;
  wire             system_0_burst_16_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_16_upstream_any_continuerequest;
  wire             system_0_burst_16_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_16_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_16_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_16_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_16_upstream_bbt_burstcounter;
  wire             system_0_burst_16_upstream_beginbursttransfer_internal;
  wire             system_0_burst_16_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_16_upstream_burstcount;
  wire             system_0_burst_16_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_16_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_16_upstream_byteenable;
  reg     [  3: 0] system_0_burst_16_upstream_current_burst;
  wire    [  3: 0] system_0_burst_16_upstream_current_burst_minus_one;
  wire             system_0_burst_16_upstream_debugaccess;
  wire             system_0_burst_16_upstream_end_xfer;
  wire             system_0_burst_16_upstream_firsttransfer;
  wire             system_0_burst_16_upstream_grant_vector;
  wire             system_0_burst_16_upstream_in_a_read_cycle;
  wire             system_0_burst_16_upstream_in_a_write_cycle;
  reg              system_0_burst_16_upstream_load_fifo;
  wire             system_0_burst_16_upstream_master_qreq_vector;
  wire             system_0_burst_16_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_16_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_16_upstream_next_burst_count;
  wire             system_0_burst_16_upstream_non_bursting_master_requests;
  wire             system_0_burst_16_upstream_read;
  wire    [ 15: 0] system_0_burst_16_upstream_readdata_from_sa;
  wire             system_0_burst_16_upstream_readdatavalid_from_sa;
  reg              system_0_burst_16_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_16_upstream_selected_burstcount;
  reg              system_0_burst_16_upstream_slavearbiterlockenable;
  wire             system_0_burst_16_upstream_slavearbiterlockenable2;
  wire             system_0_burst_16_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_16_upstream_transaction_burst_count;
  wire             system_0_burst_16_upstream_unreg_firsttransfer;
  wire             system_0_burst_16_upstream_waitrequest_from_sa;
  wire             system_0_burst_16_upstream_waits_for_read;
  wire             system_0_burst_16_upstream_waits_for_write;
  wire             system_0_burst_16_upstream_write;
  wire    [ 15: 0] system_0_burst_16_upstream_writedata;
  wire             wait_for_system_0_burst_16_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_16_upstream_end_xfer;
    end


  assign system_0_burst_16_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_16_upstream));
  //assign system_0_burst_16_upstream_readdatavalid_from_sa = system_0_burst_16_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_16_upstream_readdatavalid_from_sa = system_0_burst_16_upstream_readdatavalid;

  //assign system_0_burst_16_upstream_readdata_from_sa = system_0_burst_16_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_16_upstream_readdata_from_sa = system_0_burst_16_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_16_upstream = ({cpu_0_data_master_address_to_slave[24 : 2] , 2'b0} == 25'h190a1dc) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_16_upstream_waitrequest_from_sa = system_0_burst_16_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_16_upstream_waitrequest_from_sa = system_0_burst_16_upstream_waitrequest;

  //system_0_burst_16_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_16_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_16_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_16_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_16_upstream_non_bursting_master_requests = 0;

  //system_0_burst_16_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_16_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_16_upstream;

  //system_0_burst_16_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_16_upstream_arb_share_counter_next_value = system_0_burst_16_upstream_firsttransfer ? (system_0_burst_16_upstream_arb_share_set_values - 1) : |system_0_burst_16_upstream_arb_share_counter ? (system_0_burst_16_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_16_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_16_upstream_allgrants = |system_0_burst_16_upstream_grant_vector;

  //system_0_burst_16_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_16_upstream_end_xfer = ~(system_0_burst_16_upstream_waits_for_read | system_0_burst_16_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_16_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_16_upstream = system_0_burst_16_upstream_end_xfer & (~system_0_burst_16_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_16_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_16_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_16_upstream & system_0_burst_16_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_16_upstream & ~system_0_burst_16_upstream_non_bursting_master_requests);

  //system_0_burst_16_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_16_upstream_arb_share_counter <= 0;
      else if (system_0_burst_16_upstream_arb_counter_enable)
          system_0_burst_16_upstream_arb_share_counter <= system_0_burst_16_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_16_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_16_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_16_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_16_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_16_upstream & ~system_0_burst_16_upstream_non_bursting_master_requests))
          system_0_burst_16_upstream_slavearbiterlockenable <= |system_0_burst_16_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_16/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_16_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_16_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_16_upstream_slavearbiterlockenable2 = |system_0_burst_16_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_16/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_16_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_16_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_16_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_16_upstream = cpu_0_data_master_requests_system_0_burst_16_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_16_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_16_upstream_move_on_to_next_transaction = system_0_burst_16_upstream_this_cycle_is_the_last_burst & system_0_burst_16_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_16_upstream, which is an e_mux
  assign system_0_burst_16_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_16_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_16_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_16_upstream_module burstcount_fifo_for_system_0_burst_16_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_16_upstream_selected_burstcount),
      .data_out             (system_0_burst_16_upstream_transaction_burst_count),
      .empty                (system_0_burst_16_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_16_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_16_upstream_waits_for_read & system_0_burst_16_upstream_load_fifo & ~(system_0_burst_16_upstream_this_cycle_is_the_last_burst & system_0_burst_16_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_16_upstream current burst minus one, which is an e_assign
  assign system_0_burst_16_upstream_current_burst_minus_one = system_0_burst_16_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_16_upstream, which is an e_mux
  assign system_0_burst_16_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_16_upstream_waits_for_read) & ~system_0_burst_16_upstream_load_fifo))? system_0_burst_16_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_16_upstream_waits_for_read & system_0_burst_16_upstream_this_cycle_is_the_last_burst & system_0_burst_16_upstream_burstcount_fifo_empty))? system_0_burst_16_upstream_selected_burstcount :
    (system_0_burst_16_upstream_this_cycle_is_the_last_burst)? system_0_burst_16_upstream_transaction_burst_count :
    system_0_burst_16_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_16_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_16_upstream_current_burst <= 0;
      else if (system_0_burst_16_upstream_readdatavalid_from_sa | (~system_0_burst_16_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_16_upstream_waits_for_read)))
          system_0_burst_16_upstream_current_burst <= system_0_burst_16_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_16_upstream_load_fifo = (~system_0_burst_16_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_16_upstream_waits_for_read) & system_0_burst_16_upstream_load_fifo))? 1 :
    ~system_0_burst_16_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_16_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_16_upstream_waits_for_read) & ~system_0_burst_16_upstream_load_fifo | system_0_burst_16_upstream_this_cycle_is_the_last_burst)
          system_0_burst_16_upstream_load_fifo <= p0_system_0_burst_16_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_16_upstream, which is an e_assign
  assign system_0_burst_16_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_16_upstream_current_burst_minus_one) & system_0_burst_16_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_16_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_16_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_16_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_16_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_16_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_16_upstream),
      .full                 (),
      .read                 (system_0_burst_16_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_16_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_16_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_16_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_16_upstream = system_0_burst_16_upstream_readdatavalid_from_sa;

  //system_0_burst_16_upstream_writedata mux, which is an e_mux
  assign system_0_burst_16_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_16/upstream, which is an e_mux
  assign system_0_burst_16_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_16_upstream = cpu_0_data_master_qualified_request_system_0_burst_16_upstream;

  //cpu_0/data_master saved-grant system_0_burst_16/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_16_upstream = cpu_0_data_master_requests_system_0_burst_16_upstream;

  //allow new arb cycle for system_0_burst_16/upstream, which is an e_assign
  assign system_0_burst_16_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_16_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_16_upstream_master_qreq_vector = 1;

  //system_0_burst_16_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_16_upstream_firsttransfer = system_0_burst_16_upstream_begins_xfer ? system_0_burst_16_upstream_unreg_firsttransfer : system_0_burst_16_upstream_reg_firsttransfer;

  //system_0_burst_16_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_16_upstream_unreg_firsttransfer = ~(system_0_burst_16_upstream_slavearbiterlockenable & system_0_burst_16_upstream_any_continuerequest);

  //system_0_burst_16_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_16_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_16_upstream_begins_xfer)
          system_0_burst_16_upstream_reg_firsttransfer <= system_0_burst_16_upstream_unreg_firsttransfer;
    end


  //system_0_burst_16_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_16_upstream_next_bbt_burstcount = ((((system_0_burst_16_upstream_write) && (system_0_burst_16_upstream_bbt_burstcounter == 0))))? (system_0_burst_16_upstream_burstcount - 1) :
    ((((system_0_burst_16_upstream_read) && (system_0_burst_16_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_16_upstream_bbt_burstcounter - 1);

  //system_0_burst_16_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_16_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_16_upstream_begins_xfer)
          system_0_burst_16_upstream_bbt_burstcounter <= system_0_burst_16_upstream_next_bbt_burstcount;
    end


  //system_0_burst_16_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_16_upstream_beginbursttransfer_internal = system_0_burst_16_upstream_begins_xfer & (system_0_burst_16_upstream_bbt_burstcounter == 0);

  //system_0_burst_16_upstream_read assignment, which is an e_mux
  assign system_0_burst_16_upstream_read = cpu_0_data_master_granted_system_0_burst_16_upstream & cpu_0_data_master_read;

  //system_0_burst_16_upstream_write assignment, which is an e_mux
  assign system_0_burst_16_upstream_write = cpu_0_data_master_granted_system_0_burst_16_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_16_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_16_upstream_address mux, which is an e_mux
  assign system_0_burst_16_upstream_address = shifted_address_to_system_0_burst_16_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_16_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_16_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_16_upstream_end_xfer <= system_0_burst_16_upstream_end_xfer;
    end


  //system_0_burst_16_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_16_upstream_waits_for_read = system_0_burst_16_upstream_in_a_read_cycle & system_0_burst_16_upstream_waitrequest_from_sa;

  //system_0_burst_16_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_16_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_16_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_16_upstream_in_a_read_cycle;

  //system_0_burst_16_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_16_upstream_waits_for_write = system_0_burst_16_upstream_in_a_write_cycle & system_0_burst_16_upstream_waitrequest_from_sa;

  //system_0_burst_16_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_16_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_16_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_16_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_16_upstream_counter = 0;
  //system_0_burst_16_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_16_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_16_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_16_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_16_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_16_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_16_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_16/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_16_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_16/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_16_downstream_arbitrator (
                                                 // inputs:
                                                  Audio_0_avalon_slave_0_readdata_from_sa,
                                                  clk,
                                                  d1_Audio_0_avalon_slave_0_end_xfer,
                                                  reset_n,
                                                  system_0_burst_16_downstream_address,
                                                  system_0_burst_16_downstream_burstcount,
                                                  system_0_burst_16_downstream_byteenable,
                                                  system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0,
                                                  system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0,
                                                  system_0_burst_16_downstream_read,
                                                  system_0_burst_16_downstream_read_data_valid_Audio_0_avalon_slave_0,
                                                  system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0,
                                                  system_0_burst_16_downstream_write,
                                                  system_0_burst_16_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_16_downstream_address_to_slave,
                                                  system_0_burst_16_downstream_latency_counter,
                                                  system_0_burst_16_downstream_readdata,
                                                  system_0_burst_16_downstream_readdatavalid,
                                                  system_0_burst_16_downstream_reset_n,
                                                  system_0_burst_16_downstream_waitrequest
                                               )
;

  output           system_0_burst_16_downstream_address_to_slave;
  output           system_0_burst_16_downstream_latency_counter;
  output  [ 15: 0] system_0_burst_16_downstream_readdata;
  output           system_0_burst_16_downstream_readdatavalid;
  output           system_0_burst_16_downstream_reset_n;
  output           system_0_burst_16_downstream_waitrequest;
  input   [ 15: 0] Audio_0_avalon_slave_0_readdata_from_sa;
  input            clk;
  input            d1_Audio_0_avalon_slave_0_end_xfer;
  input            reset_n;
  input            system_0_burst_16_downstream_address;
  input            system_0_burst_16_downstream_burstcount;
  input   [  1: 0] system_0_burst_16_downstream_byteenable;
  input            system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0;
  input            system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0;
  input            system_0_burst_16_downstream_read;
  input            system_0_burst_16_downstream_read_data_valid_Audio_0_avalon_slave_0;
  input            system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0;
  input            system_0_burst_16_downstream_write;
  input   [ 15: 0] system_0_burst_16_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_16_downstream_readdatavalid;
  wire             r_0;
  reg              system_0_burst_16_downstream_address_last_time;
  wire             system_0_burst_16_downstream_address_to_slave;
  reg              system_0_burst_16_downstream_burstcount_last_time;
  reg     [  1: 0] system_0_burst_16_downstream_byteenable_last_time;
  wire             system_0_burst_16_downstream_latency_counter;
  reg              system_0_burst_16_downstream_read_last_time;
  wire    [ 15: 0] system_0_burst_16_downstream_readdata;
  wire             system_0_burst_16_downstream_readdatavalid;
  wire             system_0_burst_16_downstream_reset_n;
  wire             system_0_burst_16_downstream_run;
  wire             system_0_burst_16_downstream_waitrequest;
  reg              system_0_burst_16_downstream_write_last_time;
  reg     [ 15: 0] system_0_burst_16_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0 | ~system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0) & ((~system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0 | ~(system_0_burst_16_downstream_read | system_0_burst_16_downstream_write) | (1 & (system_0_burst_16_downstream_read | system_0_burst_16_downstream_write)))) & ((~system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0 | ~(system_0_burst_16_downstream_read | system_0_burst_16_downstream_write) | (1 & (system_0_burst_16_downstream_read | system_0_burst_16_downstream_write))));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_16_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_16_downstream_address_to_slave = system_0_burst_16_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_16_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_16_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_16_downstream_readdatavalid |
    system_0_burst_16_downstream_read_data_valid_Audio_0_avalon_slave_0;

  //system_0_burst_16/downstream readdata mux, which is an e_mux
  assign system_0_burst_16_downstream_readdata = Audio_0_avalon_slave_0_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_16_downstream_waitrequest = ~system_0_burst_16_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_16_downstream_latency_counter = 0;

  //system_0_burst_16_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_16_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_16_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_16_downstream_address_last_time <= 0;
      else 
        system_0_burst_16_downstream_address_last_time <= system_0_burst_16_downstream_address;
    end


  //system_0_burst_16/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_16_downstream_waitrequest & (system_0_burst_16_downstream_read | system_0_burst_16_downstream_write);
    end


  //system_0_burst_16_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_16_downstream_address != system_0_burst_16_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_16_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_16_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_16_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_16_downstream_burstcount_last_time <= system_0_burst_16_downstream_burstcount;
    end


  //system_0_burst_16_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_16_downstream_burstcount != system_0_burst_16_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_16_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_16_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_16_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_16_downstream_byteenable_last_time <= system_0_burst_16_downstream_byteenable;
    end


  //system_0_burst_16_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_16_downstream_byteenable != system_0_burst_16_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_16_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_16_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_16_downstream_read_last_time <= 0;
      else 
        system_0_burst_16_downstream_read_last_time <= system_0_burst_16_downstream_read;
    end


  //system_0_burst_16_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_16_downstream_read != system_0_burst_16_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_16_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_16_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_16_downstream_write_last_time <= 0;
      else 
        system_0_burst_16_downstream_write_last_time <= system_0_burst_16_downstream_write;
    end


  //system_0_burst_16_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_16_downstream_write != system_0_burst_16_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_16_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_16_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_16_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_16_downstream_writedata_last_time <= system_0_burst_16_downstream_writedata;
    end


  //system_0_burst_16_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_16_downstream_writedata != system_0_burst_16_downstream_writedata_last_time) & system_0_burst_16_downstream_write)
        begin
          $write("%0d ns: system_0_burst_16_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_17_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_17_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_17_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_17_upstream_readdata,
                                                system_0_burst_17_upstream_readdatavalid,
                                                system_0_burst_17_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_17_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_17_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_17_upstream,
                                                d1_system_0_burst_17_upstream_end_xfer,
                                                system_0_burst_17_upstream_address,
                                                system_0_burst_17_upstream_burstcount,
                                                system_0_burst_17_upstream_byteaddress,
                                                system_0_burst_17_upstream_byteenable,
                                                system_0_burst_17_upstream_debugaccess,
                                                system_0_burst_17_upstream_read,
                                                system_0_burst_17_upstream_readdata_from_sa,
                                                system_0_burst_17_upstream_waitrequest_from_sa,
                                                system_0_burst_17_upstream_write,
                                                system_0_burst_17_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_17_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_17_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_17_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_17_upstream;
  output           d1_system_0_burst_17_upstream_end_xfer;
  output  [  1: 0] system_0_burst_17_upstream_address;
  output  [  3: 0] system_0_burst_17_upstream_burstcount;
  output  [  1: 0] system_0_burst_17_upstream_byteaddress;
  output           system_0_burst_17_upstream_byteenable;
  output           system_0_burst_17_upstream_debugaccess;
  output           system_0_burst_17_upstream_read;
  output  [  7: 0] system_0_burst_17_upstream_readdata_from_sa;
  output           system_0_burst_17_upstream_waitrequest_from_sa;
  output           system_0_burst_17_upstream_write;
  output  [  7: 0] system_0_burst_17_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_17_upstream_readdata;
  input            system_0_burst_17_upstream_readdatavalid;
  input            system_0_burst_17_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_17_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_17_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_17_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_17_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_17_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_17_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_17_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_17_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_17_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_17_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_17_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_17_upstream_address;
  wire             system_0_burst_17_upstream_allgrants;
  wire             system_0_burst_17_upstream_allow_new_arb_cycle;
  wire             system_0_burst_17_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_17_upstream_any_continuerequest;
  wire             system_0_burst_17_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_17_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_17_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_17_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_17_upstream_bbt_burstcounter;
  wire             system_0_burst_17_upstream_beginbursttransfer_internal;
  wire             system_0_burst_17_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_17_upstream_burstcount;
  wire             system_0_burst_17_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_17_upstream_byteaddress;
  wire             system_0_burst_17_upstream_byteenable;
  reg     [  3: 0] system_0_burst_17_upstream_current_burst;
  wire    [  3: 0] system_0_burst_17_upstream_current_burst_minus_one;
  wire             system_0_burst_17_upstream_debugaccess;
  wire             system_0_burst_17_upstream_end_xfer;
  wire             system_0_burst_17_upstream_firsttransfer;
  wire             system_0_burst_17_upstream_grant_vector;
  wire             system_0_burst_17_upstream_in_a_read_cycle;
  wire             system_0_burst_17_upstream_in_a_write_cycle;
  reg              system_0_burst_17_upstream_load_fifo;
  wire             system_0_burst_17_upstream_master_qreq_vector;
  wire             system_0_burst_17_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_17_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_17_upstream_next_burst_count;
  wire             system_0_burst_17_upstream_non_bursting_master_requests;
  wire             system_0_burst_17_upstream_read;
  wire    [  7: 0] system_0_burst_17_upstream_readdata_from_sa;
  wire             system_0_burst_17_upstream_readdatavalid_from_sa;
  reg              system_0_burst_17_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_17_upstream_selected_burstcount;
  reg              system_0_burst_17_upstream_slavearbiterlockenable;
  wire             system_0_burst_17_upstream_slavearbiterlockenable2;
  wire             system_0_burst_17_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_17_upstream_transaction_burst_count;
  wire             system_0_burst_17_upstream_unreg_firsttransfer;
  wire             system_0_burst_17_upstream_waitrequest_from_sa;
  wire             system_0_burst_17_upstream_waits_for_read;
  wire             system_0_burst_17_upstream_waits_for_write;
  wire             system_0_burst_17_upstream_write;
  wire    [  7: 0] system_0_burst_17_upstream_writedata;
  wire             wait_for_system_0_burst_17_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_17_upstream_end_xfer;
    end


  assign system_0_burst_17_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_17_upstream));
  //assign system_0_burst_17_upstream_readdatavalid_from_sa = system_0_burst_17_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_17_upstream_readdatavalid_from_sa = system_0_burst_17_upstream_readdatavalid;

  //assign system_0_burst_17_upstream_readdata_from_sa = system_0_burst_17_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_17_upstream_readdata_from_sa = system_0_burst_17_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_17_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a0d0) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_17_upstream_waitrequest_from_sa = system_0_burst_17_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_17_upstream_waitrequest_from_sa = system_0_burst_17_upstream_waitrequest;

  //system_0_burst_17_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_17_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_17_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_17_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_17_upstream_non_bursting_master_requests = 0;

  //system_0_burst_17_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_17_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_17_upstream;

  //system_0_burst_17_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_17_upstream_arb_share_counter_next_value = system_0_burst_17_upstream_firsttransfer ? (system_0_burst_17_upstream_arb_share_set_values - 1) : |system_0_burst_17_upstream_arb_share_counter ? (system_0_burst_17_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_17_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_17_upstream_allgrants = |system_0_burst_17_upstream_grant_vector;

  //system_0_burst_17_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_17_upstream_end_xfer = ~(system_0_burst_17_upstream_waits_for_read | system_0_burst_17_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_17_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_17_upstream = system_0_burst_17_upstream_end_xfer & (~system_0_burst_17_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_17_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_17_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_17_upstream & system_0_burst_17_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_17_upstream & ~system_0_burst_17_upstream_non_bursting_master_requests);

  //system_0_burst_17_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_17_upstream_arb_share_counter <= 0;
      else if (system_0_burst_17_upstream_arb_counter_enable)
          system_0_burst_17_upstream_arb_share_counter <= system_0_burst_17_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_17_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_17_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_17_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_17_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_17_upstream & ~system_0_burst_17_upstream_non_bursting_master_requests))
          system_0_burst_17_upstream_slavearbiterlockenable <= |system_0_burst_17_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_17/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_17_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_17_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_17_upstream_slavearbiterlockenable2 = |system_0_burst_17_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_17/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_17_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_17_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_17_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_17_upstream = cpu_0_data_master_requests_system_0_burst_17_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_17_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_17_upstream_move_on_to_next_transaction = system_0_burst_17_upstream_this_cycle_is_the_last_burst & system_0_burst_17_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_17_upstream, which is an e_mux
  assign system_0_burst_17_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_17_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_17_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_17_upstream_module burstcount_fifo_for_system_0_burst_17_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_17_upstream_selected_burstcount),
      .data_out             (system_0_burst_17_upstream_transaction_burst_count),
      .empty                (system_0_burst_17_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_17_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_17_upstream_waits_for_read & system_0_burst_17_upstream_load_fifo & ~(system_0_burst_17_upstream_this_cycle_is_the_last_burst & system_0_burst_17_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_17_upstream current burst minus one, which is an e_assign
  assign system_0_burst_17_upstream_current_burst_minus_one = system_0_burst_17_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_17_upstream, which is an e_mux
  assign system_0_burst_17_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_17_upstream_waits_for_read) & ~system_0_burst_17_upstream_load_fifo))? system_0_burst_17_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_17_upstream_waits_for_read & system_0_burst_17_upstream_this_cycle_is_the_last_burst & system_0_burst_17_upstream_burstcount_fifo_empty))? system_0_burst_17_upstream_selected_burstcount :
    (system_0_burst_17_upstream_this_cycle_is_the_last_burst)? system_0_burst_17_upstream_transaction_burst_count :
    system_0_burst_17_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_17_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_17_upstream_current_burst <= 0;
      else if (system_0_burst_17_upstream_readdatavalid_from_sa | (~system_0_burst_17_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_17_upstream_waits_for_read)))
          system_0_burst_17_upstream_current_burst <= system_0_burst_17_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_17_upstream_load_fifo = (~system_0_burst_17_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_17_upstream_waits_for_read) & system_0_burst_17_upstream_load_fifo))? 1 :
    ~system_0_burst_17_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_17_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_17_upstream_waits_for_read) & ~system_0_burst_17_upstream_load_fifo | system_0_burst_17_upstream_this_cycle_is_the_last_burst)
          system_0_burst_17_upstream_load_fifo <= p0_system_0_burst_17_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_17_upstream, which is an e_assign
  assign system_0_burst_17_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_17_upstream_current_burst_minus_one) & system_0_burst_17_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_17_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_17_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_17_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_17_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_17_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_17_upstream),
      .full                 (),
      .read                 (system_0_burst_17_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_17_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_17_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_17_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_17_upstream = system_0_burst_17_upstream_readdatavalid_from_sa;

  //system_0_burst_17_upstream_writedata mux, which is an e_mux
  assign system_0_burst_17_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_17/upstream, which is an e_mux
  assign system_0_burst_17_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_17_upstream = cpu_0_data_master_qualified_request_system_0_burst_17_upstream;

  //cpu_0/data_master saved-grant system_0_burst_17/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_17_upstream = cpu_0_data_master_requests_system_0_burst_17_upstream;

  //allow new arb cycle for system_0_burst_17/upstream, which is an e_assign
  assign system_0_burst_17_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_17_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_17_upstream_master_qreq_vector = 1;

  //system_0_burst_17_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_17_upstream_firsttransfer = system_0_burst_17_upstream_begins_xfer ? system_0_burst_17_upstream_unreg_firsttransfer : system_0_burst_17_upstream_reg_firsttransfer;

  //system_0_burst_17_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_17_upstream_unreg_firsttransfer = ~(system_0_burst_17_upstream_slavearbiterlockenable & system_0_burst_17_upstream_any_continuerequest);

  //system_0_burst_17_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_17_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_17_upstream_begins_xfer)
          system_0_burst_17_upstream_reg_firsttransfer <= system_0_burst_17_upstream_unreg_firsttransfer;
    end


  //system_0_burst_17_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_17_upstream_next_bbt_burstcount = ((((system_0_burst_17_upstream_write) && (system_0_burst_17_upstream_bbt_burstcounter == 0))))? (system_0_burst_17_upstream_burstcount - 1) :
    ((((system_0_burst_17_upstream_read) && (system_0_burst_17_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_17_upstream_bbt_burstcounter - 1);

  //system_0_burst_17_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_17_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_17_upstream_begins_xfer)
          system_0_burst_17_upstream_bbt_burstcounter <= system_0_burst_17_upstream_next_bbt_burstcount;
    end


  //system_0_burst_17_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_17_upstream_beginbursttransfer_internal = system_0_burst_17_upstream_begins_xfer & (system_0_burst_17_upstream_bbt_burstcounter == 0);

  //system_0_burst_17_upstream_read assignment, which is an e_mux
  assign system_0_burst_17_upstream_read = cpu_0_data_master_granted_system_0_burst_17_upstream & cpu_0_data_master_read;

  //system_0_burst_17_upstream_write assignment, which is an e_mux
  assign system_0_burst_17_upstream_write = cpu_0_data_master_granted_system_0_burst_17_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_17_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_17_upstream_address mux, which is an e_mux
  assign system_0_burst_17_upstream_address = shifted_address_to_system_0_burst_17_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_17_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_17_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_17_upstream_end_xfer <= system_0_burst_17_upstream_end_xfer;
    end


  //system_0_burst_17_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_17_upstream_waits_for_read = system_0_burst_17_upstream_in_a_read_cycle & system_0_burst_17_upstream_waitrequest_from_sa;

  //system_0_burst_17_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_17_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_17_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_17_upstream_in_a_read_cycle;

  //system_0_burst_17_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_17_upstream_waits_for_write = system_0_burst_17_upstream_in_a_write_cycle & system_0_burst_17_upstream_waitrequest_from_sa;

  //system_0_burst_17_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_17_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_17_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_17_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_17_upstream_counter = 0;
  //system_0_burst_17_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_17_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_17_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_17_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_17_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_17_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_17_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_17/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_17_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_17/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_17_downstream_arbitrator (
                                                 // inputs:
                                                  SD_DAT_s1_readdata_from_sa,
                                                  clk,
                                                  d1_SD_DAT_s1_end_xfer,
                                                  reset_n,
                                                  system_0_burst_17_downstream_address,
                                                  system_0_burst_17_downstream_burstcount,
                                                  system_0_burst_17_downstream_byteenable,
                                                  system_0_burst_17_downstream_granted_SD_DAT_s1,
                                                  system_0_burst_17_downstream_qualified_request_SD_DAT_s1,
                                                  system_0_burst_17_downstream_read,
                                                  system_0_burst_17_downstream_read_data_valid_SD_DAT_s1,
                                                  system_0_burst_17_downstream_requests_SD_DAT_s1,
                                                  system_0_burst_17_downstream_write,
                                                  system_0_burst_17_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_17_downstream_address_to_slave,
                                                  system_0_burst_17_downstream_latency_counter,
                                                  system_0_burst_17_downstream_readdata,
                                                  system_0_burst_17_downstream_readdatavalid,
                                                  system_0_burst_17_downstream_reset_n,
                                                  system_0_burst_17_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_17_downstream_address_to_slave;
  output           system_0_burst_17_downstream_latency_counter;
  output  [  7: 0] system_0_burst_17_downstream_readdata;
  output           system_0_burst_17_downstream_readdatavalid;
  output           system_0_burst_17_downstream_reset_n;
  output           system_0_burst_17_downstream_waitrequest;
  input            SD_DAT_s1_readdata_from_sa;
  input            clk;
  input            d1_SD_DAT_s1_end_xfer;
  input            reset_n;
  input   [  1: 0] system_0_burst_17_downstream_address;
  input            system_0_burst_17_downstream_burstcount;
  input            system_0_burst_17_downstream_byteenable;
  input            system_0_burst_17_downstream_granted_SD_DAT_s1;
  input            system_0_burst_17_downstream_qualified_request_SD_DAT_s1;
  input            system_0_burst_17_downstream_read;
  input            system_0_burst_17_downstream_read_data_valid_SD_DAT_s1;
  input            system_0_burst_17_downstream_requests_SD_DAT_s1;
  input            system_0_burst_17_downstream_write;
  input   [  7: 0] system_0_burst_17_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_17_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_17_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_17_downstream_address_to_slave;
  reg              system_0_burst_17_downstream_burstcount_last_time;
  reg              system_0_burst_17_downstream_byteenable_last_time;
  wire             system_0_burst_17_downstream_latency_counter;
  reg              system_0_burst_17_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_17_downstream_readdata;
  wire             system_0_burst_17_downstream_readdatavalid;
  wire             system_0_burst_17_downstream_reset_n;
  wire             system_0_burst_17_downstream_run;
  wire             system_0_burst_17_downstream_waitrequest;
  reg              system_0_burst_17_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_17_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_17_downstream_qualified_request_SD_DAT_s1 | ~system_0_burst_17_downstream_requests_SD_DAT_s1) & ((~system_0_burst_17_downstream_qualified_request_SD_DAT_s1 | ~system_0_burst_17_downstream_read | (1 & ~d1_SD_DAT_s1_end_xfer & system_0_burst_17_downstream_read))) & ((~system_0_burst_17_downstream_qualified_request_SD_DAT_s1 | ~system_0_burst_17_downstream_write | (1 & system_0_burst_17_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_17_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_17_downstream_address_to_slave = system_0_burst_17_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_17_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_17_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_17_downstream_readdatavalid |
    system_0_burst_17_downstream_read_data_valid_SD_DAT_s1;

  //system_0_burst_17/downstream readdata mux, which is an e_mux
  assign system_0_burst_17_downstream_readdata = SD_DAT_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_17_downstream_waitrequest = ~system_0_burst_17_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_17_downstream_latency_counter = 0;

  //system_0_burst_17_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_17_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_17_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_17_downstream_address_last_time <= 0;
      else 
        system_0_burst_17_downstream_address_last_time <= system_0_burst_17_downstream_address;
    end


  //system_0_burst_17/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_17_downstream_waitrequest & (system_0_burst_17_downstream_read | system_0_burst_17_downstream_write);
    end


  //system_0_burst_17_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_17_downstream_address != system_0_burst_17_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_17_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_17_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_17_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_17_downstream_burstcount_last_time <= system_0_burst_17_downstream_burstcount;
    end


  //system_0_burst_17_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_17_downstream_burstcount != system_0_burst_17_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_17_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_17_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_17_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_17_downstream_byteenable_last_time <= system_0_burst_17_downstream_byteenable;
    end


  //system_0_burst_17_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_17_downstream_byteenable != system_0_burst_17_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_17_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_17_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_17_downstream_read_last_time <= 0;
      else 
        system_0_burst_17_downstream_read_last_time <= system_0_burst_17_downstream_read;
    end


  //system_0_burst_17_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_17_downstream_read != system_0_burst_17_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_17_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_17_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_17_downstream_write_last_time <= 0;
      else 
        system_0_burst_17_downstream_write_last_time <= system_0_burst_17_downstream_write;
    end


  //system_0_burst_17_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_17_downstream_write != system_0_burst_17_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_17_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_17_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_17_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_17_downstream_writedata_last_time <= system_0_burst_17_downstream_writedata;
    end


  //system_0_burst_17_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_17_downstream_writedata != system_0_burst_17_downstream_writedata_last_time) & system_0_burst_17_downstream_write)
        begin
          $write("%0d ns: system_0_burst_17_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_18_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_18_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_18_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_18_upstream_readdata,
                                                system_0_burst_18_upstream_readdatavalid,
                                                system_0_burst_18_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_18_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_18_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_18_upstream,
                                                d1_system_0_burst_18_upstream_end_xfer,
                                                system_0_burst_18_upstream_address,
                                                system_0_burst_18_upstream_burstcount,
                                                system_0_burst_18_upstream_byteaddress,
                                                system_0_burst_18_upstream_byteenable,
                                                system_0_burst_18_upstream_debugaccess,
                                                system_0_burst_18_upstream_read,
                                                system_0_burst_18_upstream_readdata_from_sa,
                                                system_0_burst_18_upstream_waitrequest_from_sa,
                                                system_0_burst_18_upstream_write,
                                                system_0_burst_18_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_18_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_18_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_18_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_18_upstream;
  output           d1_system_0_burst_18_upstream_end_xfer;
  output  [  1: 0] system_0_burst_18_upstream_address;
  output  [  3: 0] system_0_burst_18_upstream_burstcount;
  output  [  1: 0] system_0_burst_18_upstream_byteaddress;
  output           system_0_burst_18_upstream_byteenable;
  output           system_0_burst_18_upstream_debugaccess;
  output           system_0_burst_18_upstream_read;
  output  [  7: 0] system_0_burst_18_upstream_readdata_from_sa;
  output           system_0_burst_18_upstream_waitrequest_from_sa;
  output           system_0_burst_18_upstream_write;
  output  [  7: 0] system_0_burst_18_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_18_upstream_readdata;
  input            system_0_burst_18_upstream_readdatavalid;
  input            system_0_burst_18_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_18_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_18_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_18_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_18_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_18_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_18_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_18_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_18_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_18_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_18_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_18_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_18_upstream_address;
  wire             system_0_burst_18_upstream_allgrants;
  wire             system_0_burst_18_upstream_allow_new_arb_cycle;
  wire             system_0_burst_18_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_18_upstream_any_continuerequest;
  wire             system_0_burst_18_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_18_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_18_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_18_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_18_upstream_bbt_burstcounter;
  wire             system_0_burst_18_upstream_beginbursttransfer_internal;
  wire             system_0_burst_18_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_18_upstream_burstcount;
  wire             system_0_burst_18_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_18_upstream_byteaddress;
  wire             system_0_burst_18_upstream_byteenable;
  reg     [  3: 0] system_0_burst_18_upstream_current_burst;
  wire    [  3: 0] system_0_burst_18_upstream_current_burst_minus_one;
  wire             system_0_burst_18_upstream_debugaccess;
  wire             system_0_burst_18_upstream_end_xfer;
  wire             system_0_burst_18_upstream_firsttransfer;
  wire             system_0_burst_18_upstream_grant_vector;
  wire             system_0_burst_18_upstream_in_a_read_cycle;
  wire             system_0_burst_18_upstream_in_a_write_cycle;
  reg              system_0_burst_18_upstream_load_fifo;
  wire             system_0_burst_18_upstream_master_qreq_vector;
  wire             system_0_burst_18_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_18_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_18_upstream_next_burst_count;
  wire             system_0_burst_18_upstream_non_bursting_master_requests;
  wire             system_0_burst_18_upstream_read;
  wire    [  7: 0] system_0_burst_18_upstream_readdata_from_sa;
  wire             system_0_burst_18_upstream_readdatavalid_from_sa;
  reg              system_0_burst_18_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_18_upstream_selected_burstcount;
  reg              system_0_burst_18_upstream_slavearbiterlockenable;
  wire             system_0_burst_18_upstream_slavearbiterlockenable2;
  wire             system_0_burst_18_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_18_upstream_transaction_burst_count;
  wire             system_0_burst_18_upstream_unreg_firsttransfer;
  wire             system_0_burst_18_upstream_waitrequest_from_sa;
  wire             system_0_burst_18_upstream_waits_for_read;
  wire             system_0_burst_18_upstream_waits_for_write;
  wire             system_0_burst_18_upstream_write;
  wire    [  7: 0] system_0_burst_18_upstream_writedata;
  wire             wait_for_system_0_burst_18_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_18_upstream_end_xfer;
    end


  assign system_0_burst_18_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_18_upstream));
  //assign system_0_burst_18_upstream_readdatavalid_from_sa = system_0_burst_18_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_18_upstream_readdatavalid_from_sa = system_0_burst_18_upstream_readdatavalid;

  //assign system_0_burst_18_upstream_readdata_from_sa = system_0_burst_18_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_18_upstream_readdata_from_sa = system_0_burst_18_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_18_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a0e0) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_18_upstream_waitrequest_from_sa = system_0_burst_18_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_18_upstream_waitrequest_from_sa = system_0_burst_18_upstream_waitrequest;

  //system_0_burst_18_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_18_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_18_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_18_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_18_upstream_non_bursting_master_requests = 0;

  //system_0_burst_18_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_18_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_18_upstream;

  //system_0_burst_18_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_18_upstream_arb_share_counter_next_value = system_0_burst_18_upstream_firsttransfer ? (system_0_burst_18_upstream_arb_share_set_values - 1) : |system_0_burst_18_upstream_arb_share_counter ? (system_0_burst_18_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_18_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_18_upstream_allgrants = |system_0_burst_18_upstream_grant_vector;

  //system_0_burst_18_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_18_upstream_end_xfer = ~(system_0_burst_18_upstream_waits_for_read | system_0_burst_18_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_18_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_18_upstream = system_0_burst_18_upstream_end_xfer & (~system_0_burst_18_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_18_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_18_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_18_upstream & system_0_burst_18_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_18_upstream & ~system_0_burst_18_upstream_non_bursting_master_requests);

  //system_0_burst_18_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_18_upstream_arb_share_counter <= 0;
      else if (system_0_burst_18_upstream_arb_counter_enable)
          system_0_burst_18_upstream_arb_share_counter <= system_0_burst_18_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_18_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_18_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_18_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_18_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_18_upstream & ~system_0_burst_18_upstream_non_bursting_master_requests))
          system_0_burst_18_upstream_slavearbiterlockenable <= |system_0_burst_18_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_18/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_18_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_18_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_18_upstream_slavearbiterlockenable2 = |system_0_burst_18_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_18/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_18_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_18_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_18_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_18_upstream = cpu_0_data_master_requests_system_0_burst_18_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_18_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_18_upstream_move_on_to_next_transaction = system_0_burst_18_upstream_this_cycle_is_the_last_burst & system_0_burst_18_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_18_upstream, which is an e_mux
  assign system_0_burst_18_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_18_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_18_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_18_upstream_module burstcount_fifo_for_system_0_burst_18_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_18_upstream_selected_burstcount),
      .data_out             (system_0_burst_18_upstream_transaction_burst_count),
      .empty                (system_0_burst_18_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_18_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_18_upstream_waits_for_read & system_0_burst_18_upstream_load_fifo & ~(system_0_burst_18_upstream_this_cycle_is_the_last_burst & system_0_burst_18_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_18_upstream current burst minus one, which is an e_assign
  assign system_0_burst_18_upstream_current_burst_minus_one = system_0_burst_18_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_18_upstream, which is an e_mux
  assign system_0_burst_18_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_18_upstream_waits_for_read) & ~system_0_burst_18_upstream_load_fifo))? system_0_burst_18_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_18_upstream_waits_for_read & system_0_burst_18_upstream_this_cycle_is_the_last_burst & system_0_burst_18_upstream_burstcount_fifo_empty))? system_0_burst_18_upstream_selected_burstcount :
    (system_0_burst_18_upstream_this_cycle_is_the_last_burst)? system_0_burst_18_upstream_transaction_burst_count :
    system_0_burst_18_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_18_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_18_upstream_current_burst <= 0;
      else if (system_0_burst_18_upstream_readdatavalid_from_sa | (~system_0_burst_18_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_18_upstream_waits_for_read)))
          system_0_burst_18_upstream_current_burst <= system_0_burst_18_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_18_upstream_load_fifo = (~system_0_burst_18_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_18_upstream_waits_for_read) & system_0_burst_18_upstream_load_fifo))? 1 :
    ~system_0_burst_18_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_18_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_18_upstream_waits_for_read) & ~system_0_burst_18_upstream_load_fifo | system_0_burst_18_upstream_this_cycle_is_the_last_burst)
          system_0_burst_18_upstream_load_fifo <= p0_system_0_burst_18_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_18_upstream, which is an e_assign
  assign system_0_burst_18_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_18_upstream_current_burst_minus_one) & system_0_burst_18_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_18_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_18_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_18_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_18_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_18_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_18_upstream),
      .full                 (),
      .read                 (system_0_burst_18_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_18_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_18_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_18_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_18_upstream = system_0_burst_18_upstream_readdatavalid_from_sa;

  //system_0_burst_18_upstream_writedata mux, which is an e_mux
  assign system_0_burst_18_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_18/upstream, which is an e_mux
  assign system_0_burst_18_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_18_upstream = cpu_0_data_master_qualified_request_system_0_burst_18_upstream;

  //cpu_0/data_master saved-grant system_0_burst_18/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_18_upstream = cpu_0_data_master_requests_system_0_burst_18_upstream;

  //allow new arb cycle for system_0_burst_18/upstream, which is an e_assign
  assign system_0_burst_18_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_18_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_18_upstream_master_qreq_vector = 1;

  //system_0_burst_18_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_18_upstream_firsttransfer = system_0_burst_18_upstream_begins_xfer ? system_0_burst_18_upstream_unreg_firsttransfer : system_0_burst_18_upstream_reg_firsttransfer;

  //system_0_burst_18_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_18_upstream_unreg_firsttransfer = ~(system_0_burst_18_upstream_slavearbiterlockenable & system_0_burst_18_upstream_any_continuerequest);

  //system_0_burst_18_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_18_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_18_upstream_begins_xfer)
          system_0_burst_18_upstream_reg_firsttransfer <= system_0_burst_18_upstream_unreg_firsttransfer;
    end


  //system_0_burst_18_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_18_upstream_next_bbt_burstcount = ((((system_0_burst_18_upstream_write) && (system_0_burst_18_upstream_bbt_burstcounter == 0))))? (system_0_burst_18_upstream_burstcount - 1) :
    ((((system_0_burst_18_upstream_read) && (system_0_burst_18_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_18_upstream_bbt_burstcounter - 1);

  //system_0_burst_18_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_18_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_18_upstream_begins_xfer)
          system_0_burst_18_upstream_bbt_burstcounter <= system_0_burst_18_upstream_next_bbt_burstcount;
    end


  //system_0_burst_18_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_18_upstream_beginbursttransfer_internal = system_0_burst_18_upstream_begins_xfer & (system_0_burst_18_upstream_bbt_burstcounter == 0);

  //system_0_burst_18_upstream_read assignment, which is an e_mux
  assign system_0_burst_18_upstream_read = cpu_0_data_master_granted_system_0_burst_18_upstream & cpu_0_data_master_read;

  //system_0_burst_18_upstream_write assignment, which is an e_mux
  assign system_0_burst_18_upstream_write = cpu_0_data_master_granted_system_0_burst_18_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_18_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_18_upstream_address mux, which is an e_mux
  assign system_0_burst_18_upstream_address = shifted_address_to_system_0_burst_18_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_18_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_18_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_18_upstream_end_xfer <= system_0_burst_18_upstream_end_xfer;
    end


  //system_0_burst_18_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_18_upstream_waits_for_read = system_0_burst_18_upstream_in_a_read_cycle & system_0_burst_18_upstream_waitrequest_from_sa;

  //system_0_burst_18_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_18_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_18_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_18_upstream_in_a_read_cycle;

  //system_0_burst_18_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_18_upstream_waits_for_write = system_0_burst_18_upstream_in_a_write_cycle & system_0_burst_18_upstream_waitrequest_from_sa;

  //system_0_burst_18_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_18_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_18_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_18_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_18_upstream_counter = 0;
  //system_0_burst_18_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_18_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_18_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_18_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_18_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_18_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_18_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_18/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_18_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_18/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_18_downstream_arbitrator (
                                                 // inputs:
                                                  SD_CMD_s1_readdata_from_sa,
                                                  clk,
                                                  d1_SD_CMD_s1_end_xfer,
                                                  reset_n,
                                                  system_0_burst_18_downstream_address,
                                                  system_0_burst_18_downstream_burstcount,
                                                  system_0_burst_18_downstream_byteenable,
                                                  system_0_burst_18_downstream_granted_SD_CMD_s1,
                                                  system_0_burst_18_downstream_qualified_request_SD_CMD_s1,
                                                  system_0_burst_18_downstream_read,
                                                  system_0_burst_18_downstream_read_data_valid_SD_CMD_s1,
                                                  system_0_burst_18_downstream_requests_SD_CMD_s1,
                                                  system_0_burst_18_downstream_write,
                                                  system_0_burst_18_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_18_downstream_address_to_slave,
                                                  system_0_burst_18_downstream_latency_counter,
                                                  system_0_burst_18_downstream_readdata,
                                                  system_0_burst_18_downstream_readdatavalid,
                                                  system_0_burst_18_downstream_reset_n,
                                                  system_0_burst_18_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_18_downstream_address_to_slave;
  output           system_0_burst_18_downstream_latency_counter;
  output  [  7: 0] system_0_burst_18_downstream_readdata;
  output           system_0_burst_18_downstream_readdatavalid;
  output           system_0_burst_18_downstream_reset_n;
  output           system_0_burst_18_downstream_waitrequest;
  input            SD_CMD_s1_readdata_from_sa;
  input            clk;
  input            d1_SD_CMD_s1_end_xfer;
  input            reset_n;
  input   [  1: 0] system_0_burst_18_downstream_address;
  input            system_0_burst_18_downstream_burstcount;
  input            system_0_burst_18_downstream_byteenable;
  input            system_0_burst_18_downstream_granted_SD_CMD_s1;
  input            system_0_burst_18_downstream_qualified_request_SD_CMD_s1;
  input            system_0_burst_18_downstream_read;
  input            system_0_burst_18_downstream_read_data_valid_SD_CMD_s1;
  input            system_0_burst_18_downstream_requests_SD_CMD_s1;
  input            system_0_burst_18_downstream_write;
  input   [  7: 0] system_0_burst_18_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_18_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_18_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_18_downstream_address_to_slave;
  reg              system_0_burst_18_downstream_burstcount_last_time;
  reg              system_0_burst_18_downstream_byteenable_last_time;
  wire             system_0_burst_18_downstream_latency_counter;
  reg              system_0_burst_18_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_18_downstream_readdata;
  wire             system_0_burst_18_downstream_readdatavalid;
  wire             system_0_burst_18_downstream_reset_n;
  wire             system_0_burst_18_downstream_run;
  wire             system_0_burst_18_downstream_waitrequest;
  reg              system_0_burst_18_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_18_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_18_downstream_qualified_request_SD_CMD_s1 | ~system_0_burst_18_downstream_requests_SD_CMD_s1) & ((~system_0_burst_18_downstream_qualified_request_SD_CMD_s1 | ~system_0_burst_18_downstream_read | (1 & ~d1_SD_CMD_s1_end_xfer & system_0_burst_18_downstream_read))) & ((~system_0_burst_18_downstream_qualified_request_SD_CMD_s1 | ~system_0_burst_18_downstream_write | (1 & system_0_burst_18_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_18_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_18_downstream_address_to_slave = system_0_burst_18_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_18_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_18_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_18_downstream_readdatavalid |
    system_0_burst_18_downstream_read_data_valid_SD_CMD_s1;

  //system_0_burst_18/downstream readdata mux, which is an e_mux
  assign system_0_burst_18_downstream_readdata = SD_CMD_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_18_downstream_waitrequest = ~system_0_burst_18_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_18_downstream_latency_counter = 0;

  //system_0_burst_18_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_18_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_18_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_18_downstream_address_last_time <= 0;
      else 
        system_0_burst_18_downstream_address_last_time <= system_0_burst_18_downstream_address;
    end


  //system_0_burst_18/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_18_downstream_waitrequest & (system_0_burst_18_downstream_read | system_0_burst_18_downstream_write);
    end


  //system_0_burst_18_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_18_downstream_address != system_0_burst_18_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_18_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_18_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_18_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_18_downstream_burstcount_last_time <= system_0_burst_18_downstream_burstcount;
    end


  //system_0_burst_18_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_18_downstream_burstcount != system_0_burst_18_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_18_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_18_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_18_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_18_downstream_byteenable_last_time <= system_0_burst_18_downstream_byteenable;
    end


  //system_0_burst_18_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_18_downstream_byteenable != system_0_burst_18_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_18_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_18_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_18_downstream_read_last_time <= 0;
      else 
        system_0_burst_18_downstream_read_last_time <= system_0_burst_18_downstream_read;
    end


  //system_0_burst_18_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_18_downstream_read != system_0_burst_18_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_18_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_18_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_18_downstream_write_last_time <= 0;
      else 
        system_0_burst_18_downstream_write_last_time <= system_0_burst_18_downstream_write;
    end


  //system_0_burst_18_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_18_downstream_write != system_0_burst_18_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_18_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_18_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_18_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_18_downstream_writedata_last_time <= system_0_burst_18_downstream_writedata;
    end


  //system_0_burst_18_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_18_downstream_writedata != system_0_burst_18_downstream_writedata_last_time) & system_0_burst_18_downstream_write)
        begin
          $write("%0d ns: system_0_burst_18_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_19_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_19_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_19_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_19_upstream_readdata,
                                                system_0_burst_19_upstream_readdatavalid,
                                                system_0_burst_19_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_19_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_19_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_19_upstream,
                                                d1_system_0_burst_19_upstream_end_xfer,
                                                system_0_burst_19_upstream_address,
                                                system_0_burst_19_upstream_burstcount,
                                                system_0_burst_19_upstream_byteaddress,
                                                system_0_burst_19_upstream_byteenable,
                                                system_0_burst_19_upstream_debugaccess,
                                                system_0_burst_19_upstream_read,
                                                system_0_burst_19_upstream_readdata_from_sa,
                                                system_0_burst_19_upstream_waitrequest_from_sa,
                                                system_0_burst_19_upstream_write,
                                                system_0_burst_19_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_19_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_19_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_19_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_19_upstream;
  output           d1_system_0_burst_19_upstream_end_xfer;
  output  [  1: 0] system_0_burst_19_upstream_address;
  output  [  3: 0] system_0_burst_19_upstream_burstcount;
  output  [  1: 0] system_0_burst_19_upstream_byteaddress;
  output           system_0_burst_19_upstream_byteenable;
  output           system_0_burst_19_upstream_debugaccess;
  output           system_0_burst_19_upstream_read;
  output  [  7: 0] system_0_burst_19_upstream_readdata_from_sa;
  output           system_0_burst_19_upstream_waitrequest_from_sa;
  output           system_0_burst_19_upstream_write;
  output  [  7: 0] system_0_burst_19_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_19_upstream_readdata;
  input            system_0_burst_19_upstream_readdatavalid;
  input            system_0_burst_19_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_19_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_19_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_19_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_19_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_19_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_19_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_19_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_19_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_19_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_19_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_19_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_19_upstream_address;
  wire             system_0_burst_19_upstream_allgrants;
  wire             system_0_burst_19_upstream_allow_new_arb_cycle;
  wire             system_0_burst_19_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_19_upstream_any_continuerequest;
  wire             system_0_burst_19_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_19_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_19_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_19_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_19_upstream_bbt_burstcounter;
  wire             system_0_burst_19_upstream_beginbursttransfer_internal;
  wire             system_0_burst_19_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_19_upstream_burstcount;
  wire             system_0_burst_19_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_19_upstream_byteaddress;
  wire             system_0_burst_19_upstream_byteenable;
  reg     [  3: 0] system_0_burst_19_upstream_current_burst;
  wire    [  3: 0] system_0_burst_19_upstream_current_burst_minus_one;
  wire             system_0_burst_19_upstream_debugaccess;
  wire             system_0_burst_19_upstream_end_xfer;
  wire             system_0_burst_19_upstream_firsttransfer;
  wire             system_0_burst_19_upstream_grant_vector;
  wire             system_0_burst_19_upstream_in_a_read_cycle;
  wire             system_0_burst_19_upstream_in_a_write_cycle;
  reg              system_0_burst_19_upstream_load_fifo;
  wire             system_0_burst_19_upstream_master_qreq_vector;
  wire             system_0_burst_19_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_19_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_19_upstream_next_burst_count;
  wire             system_0_burst_19_upstream_non_bursting_master_requests;
  wire             system_0_burst_19_upstream_read;
  wire    [  7: 0] system_0_burst_19_upstream_readdata_from_sa;
  wire             system_0_burst_19_upstream_readdatavalid_from_sa;
  reg              system_0_burst_19_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_19_upstream_selected_burstcount;
  reg              system_0_burst_19_upstream_slavearbiterlockenable;
  wire             system_0_burst_19_upstream_slavearbiterlockenable2;
  wire             system_0_burst_19_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_19_upstream_transaction_burst_count;
  wire             system_0_burst_19_upstream_unreg_firsttransfer;
  wire             system_0_burst_19_upstream_waitrequest_from_sa;
  wire             system_0_burst_19_upstream_waits_for_read;
  wire             system_0_burst_19_upstream_waits_for_write;
  wire             system_0_burst_19_upstream_write;
  wire    [  7: 0] system_0_burst_19_upstream_writedata;
  wire             wait_for_system_0_burst_19_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_19_upstream_end_xfer;
    end


  assign system_0_burst_19_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_19_upstream));
  //assign system_0_burst_19_upstream_readdatavalid_from_sa = system_0_burst_19_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_19_upstream_readdatavalid_from_sa = system_0_burst_19_upstream_readdatavalid;

  //assign system_0_burst_19_upstream_readdata_from_sa = system_0_burst_19_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_19_upstream_readdata_from_sa = system_0_burst_19_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_19_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a0f0) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_19_upstream_waitrequest_from_sa = system_0_burst_19_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_19_upstream_waitrequest_from_sa = system_0_burst_19_upstream_waitrequest;

  //system_0_burst_19_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_19_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_19_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_19_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_19_upstream_non_bursting_master_requests = 0;

  //system_0_burst_19_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_19_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_19_upstream;

  //system_0_burst_19_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_19_upstream_arb_share_counter_next_value = system_0_burst_19_upstream_firsttransfer ? (system_0_burst_19_upstream_arb_share_set_values - 1) : |system_0_burst_19_upstream_arb_share_counter ? (system_0_burst_19_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_19_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_19_upstream_allgrants = |system_0_burst_19_upstream_grant_vector;

  //system_0_burst_19_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_19_upstream_end_xfer = ~(system_0_burst_19_upstream_waits_for_read | system_0_burst_19_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_19_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_19_upstream = system_0_burst_19_upstream_end_xfer & (~system_0_burst_19_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_19_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_19_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_19_upstream & system_0_burst_19_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_19_upstream & ~system_0_burst_19_upstream_non_bursting_master_requests);

  //system_0_burst_19_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_19_upstream_arb_share_counter <= 0;
      else if (system_0_burst_19_upstream_arb_counter_enable)
          system_0_burst_19_upstream_arb_share_counter <= system_0_burst_19_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_19_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_19_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_19_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_19_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_19_upstream & ~system_0_burst_19_upstream_non_bursting_master_requests))
          system_0_burst_19_upstream_slavearbiterlockenable <= |system_0_burst_19_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_19/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_19_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_19_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_19_upstream_slavearbiterlockenable2 = |system_0_burst_19_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_19/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_19_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_19_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_19_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_19_upstream = cpu_0_data_master_requests_system_0_burst_19_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_19_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_19_upstream_move_on_to_next_transaction = system_0_burst_19_upstream_this_cycle_is_the_last_burst & system_0_burst_19_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_19_upstream, which is an e_mux
  assign system_0_burst_19_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_19_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_19_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_19_upstream_module burstcount_fifo_for_system_0_burst_19_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_19_upstream_selected_burstcount),
      .data_out             (system_0_burst_19_upstream_transaction_burst_count),
      .empty                (system_0_burst_19_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_19_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_19_upstream_waits_for_read & system_0_burst_19_upstream_load_fifo & ~(system_0_burst_19_upstream_this_cycle_is_the_last_burst & system_0_burst_19_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_19_upstream current burst minus one, which is an e_assign
  assign system_0_burst_19_upstream_current_burst_minus_one = system_0_burst_19_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_19_upstream, which is an e_mux
  assign system_0_burst_19_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_19_upstream_waits_for_read) & ~system_0_burst_19_upstream_load_fifo))? system_0_burst_19_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_19_upstream_waits_for_read & system_0_burst_19_upstream_this_cycle_is_the_last_burst & system_0_burst_19_upstream_burstcount_fifo_empty))? system_0_burst_19_upstream_selected_burstcount :
    (system_0_burst_19_upstream_this_cycle_is_the_last_burst)? system_0_burst_19_upstream_transaction_burst_count :
    system_0_burst_19_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_19_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_19_upstream_current_burst <= 0;
      else if (system_0_burst_19_upstream_readdatavalid_from_sa | (~system_0_burst_19_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_19_upstream_waits_for_read)))
          system_0_burst_19_upstream_current_burst <= system_0_burst_19_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_19_upstream_load_fifo = (~system_0_burst_19_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_19_upstream_waits_for_read) & system_0_burst_19_upstream_load_fifo))? 1 :
    ~system_0_burst_19_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_19_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_19_upstream_waits_for_read) & ~system_0_burst_19_upstream_load_fifo | system_0_burst_19_upstream_this_cycle_is_the_last_burst)
          system_0_burst_19_upstream_load_fifo <= p0_system_0_burst_19_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_19_upstream, which is an e_assign
  assign system_0_burst_19_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_19_upstream_current_burst_minus_one) & system_0_burst_19_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_19_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_19_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_19_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_19_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_19_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_19_upstream),
      .full                 (),
      .read                 (system_0_burst_19_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_19_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_19_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_19_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_19_upstream = system_0_burst_19_upstream_readdatavalid_from_sa;

  //system_0_burst_19_upstream_writedata mux, which is an e_mux
  assign system_0_burst_19_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_19/upstream, which is an e_mux
  assign system_0_burst_19_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_19_upstream = cpu_0_data_master_qualified_request_system_0_burst_19_upstream;

  //cpu_0/data_master saved-grant system_0_burst_19/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_19_upstream = cpu_0_data_master_requests_system_0_burst_19_upstream;

  //allow new arb cycle for system_0_burst_19/upstream, which is an e_assign
  assign system_0_burst_19_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_19_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_19_upstream_master_qreq_vector = 1;

  //system_0_burst_19_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_19_upstream_firsttransfer = system_0_burst_19_upstream_begins_xfer ? system_0_burst_19_upstream_unreg_firsttransfer : system_0_burst_19_upstream_reg_firsttransfer;

  //system_0_burst_19_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_19_upstream_unreg_firsttransfer = ~(system_0_burst_19_upstream_slavearbiterlockenable & system_0_burst_19_upstream_any_continuerequest);

  //system_0_burst_19_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_19_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_19_upstream_begins_xfer)
          system_0_burst_19_upstream_reg_firsttransfer <= system_0_burst_19_upstream_unreg_firsttransfer;
    end


  //system_0_burst_19_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_19_upstream_next_bbt_burstcount = ((((system_0_burst_19_upstream_write) && (system_0_burst_19_upstream_bbt_burstcounter == 0))))? (system_0_burst_19_upstream_burstcount - 1) :
    ((((system_0_burst_19_upstream_read) && (system_0_burst_19_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_19_upstream_bbt_burstcounter - 1);

  //system_0_burst_19_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_19_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_19_upstream_begins_xfer)
          system_0_burst_19_upstream_bbt_burstcounter <= system_0_burst_19_upstream_next_bbt_burstcount;
    end


  //system_0_burst_19_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_19_upstream_beginbursttransfer_internal = system_0_burst_19_upstream_begins_xfer & (system_0_burst_19_upstream_bbt_burstcounter == 0);

  //system_0_burst_19_upstream_read assignment, which is an e_mux
  assign system_0_burst_19_upstream_read = cpu_0_data_master_granted_system_0_burst_19_upstream & cpu_0_data_master_read;

  //system_0_burst_19_upstream_write assignment, which is an e_mux
  assign system_0_burst_19_upstream_write = cpu_0_data_master_granted_system_0_burst_19_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_19_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_19_upstream_address mux, which is an e_mux
  assign system_0_burst_19_upstream_address = shifted_address_to_system_0_burst_19_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_19_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_19_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_19_upstream_end_xfer <= system_0_burst_19_upstream_end_xfer;
    end


  //system_0_burst_19_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_19_upstream_waits_for_read = system_0_burst_19_upstream_in_a_read_cycle & system_0_burst_19_upstream_waitrequest_from_sa;

  //system_0_burst_19_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_19_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_19_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_19_upstream_in_a_read_cycle;

  //system_0_burst_19_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_19_upstream_waits_for_write = system_0_burst_19_upstream_in_a_write_cycle & system_0_burst_19_upstream_waitrequest_from_sa;

  //system_0_burst_19_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_19_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_19_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_19_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_19_upstream_counter = 0;
  //system_0_burst_19_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_19_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_19_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_19_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_19_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_19_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_19_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_19/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_19_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_19/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_19_downstream_arbitrator (
                                                 // inputs:
                                                  SD_CLK_s1_readdata_from_sa,
                                                  clk,
                                                  d1_SD_CLK_s1_end_xfer,
                                                  reset_n,
                                                  system_0_burst_19_downstream_address,
                                                  system_0_burst_19_downstream_burstcount,
                                                  system_0_burst_19_downstream_byteenable,
                                                  system_0_burst_19_downstream_granted_SD_CLK_s1,
                                                  system_0_burst_19_downstream_qualified_request_SD_CLK_s1,
                                                  system_0_burst_19_downstream_read,
                                                  system_0_burst_19_downstream_read_data_valid_SD_CLK_s1,
                                                  system_0_burst_19_downstream_requests_SD_CLK_s1,
                                                  system_0_burst_19_downstream_write,
                                                  system_0_burst_19_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_19_downstream_address_to_slave,
                                                  system_0_burst_19_downstream_latency_counter,
                                                  system_0_burst_19_downstream_readdata,
                                                  system_0_burst_19_downstream_readdatavalid,
                                                  system_0_burst_19_downstream_reset_n,
                                                  system_0_burst_19_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_19_downstream_address_to_slave;
  output           system_0_burst_19_downstream_latency_counter;
  output  [  7: 0] system_0_burst_19_downstream_readdata;
  output           system_0_burst_19_downstream_readdatavalid;
  output           system_0_burst_19_downstream_reset_n;
  output           system_0_burst_19_downstream_waitrequest;
  input            SD_CLK_s1_readdata_from_sa;
  input            clk;
  input            d1_SD_CLK_s1_end_xfer;
  input            reset_n;
  input   [  1: 0] system_0_burst_19_downstream_address;
  input            system_0_burst_19_downstream_burstcount;
  input            system_0_burst_19_downstream_byteenable;
  input            system_0_burst_19_downstream_granted_SD_CLK_s1;
  input            system_0_burst_19_downstream_qualified_request_SD_CLK_s1;
  input            system_0_burst_19_downstream_read;
  input            system_0_burst_19_downstream_read_data_valid_SD_CLK_s1;
  input            system_0_burst_19_downstream_requests_SD_CLK_s1;
  input            system_0_burst_19_downstream_write;
  input   [  7: 0] system_0_burst_19_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_19_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_19_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_19_downstream_address_to_slave;
  reg              system_0_burst_19_downstream_burstcount_last_time;
  reg              system_0_burst_19_downstream_byteenable_last_time;
  wire             system_0_burst_19_downstream_latency_counter;
  reg              system_0_burst_19_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_19_downstream_readdata;
  wire             system_0_burst_19_downstream_readdatavalid;
  wire             system_0_burst_19_downstream_reset_n;
  wire             system_0_burst_19_downstream_run;
  wire             system_0_burst_19_downstream_waitrequest;
  reg              system_0_burst_19_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_19_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_19_downstream_qualified_request_SD_CLK_s1 | ~system_0_burst_19_downstream_requests_SD_CLK_s1) & ((~system_0_burst_19_downstream_qualified_request_SD_CLK_s1 | ~system_0_burst_19_downstream_read | (1 & ~d1_SD_CLK_s1_end_xfer & system_0_burst_19_downstream_read))) & ((~system_0_burst_19_downstream_qualified_request_SD_CLK_s1 | ~system_0_burst_19_downstream_write | (1 & system_0_burst_19_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_19_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_19_downstream_address_to_slave = system_0_burst_19_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_19_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_19_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_19_downstream_readdatavalid |
    system_0_burst_19_downstream_read_data_valid_SD_CLK_s1;

  //system_0_burst_19/downstream readdata mux, which is an e_mux
  assign system_0_burst_19_downstream_readdata = SD_CLK_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_19_downstream_waitrequest = ~system_0_burst_19_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_19_downstream_latency_counter = 0;

  //system_0_burst_19_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_19_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_19_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_19_downstream_address_last_time <= 0;
      else 
        system_0_burst_19_downstream_address_last_time <= system_0_burst_19_downstream_address;
    end


  //system_0_burst_19/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_19_downstream_waitrequest & (system_0_burst_19_downstream_read | system_0_burst_19_downstream_write);
    end


  //system_0_burst_19_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_19_downstream_address != system_0_burst_19_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_19_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_19_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_19_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_19_downstream_burstcount_last_time <= system_0_burst_19_downstream_burstcount;
    end


  //system_0_burst_19_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_19_downstream_burstcount != system_0_burst_19_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_19_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_19_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_19_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_19_downstream_byteenable_last_time <= system_0_burst_19_downstream_byteenable;
    end


  //system_0_burst_19_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_19_downstream_byteenable != system_0_burst_19_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_19_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_19_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_19_downstream_read_last_time <= 0;
      else 
        system_0_burst_19_downstream_read_last_time <= system_0_burst_19_downstream_read;
    end


  //system_0_burst_19_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_19_downstream_read != system_0_burst_19_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_19_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_19_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_19_downstream_write_last_time <= 0;
      else 
        system_0_burst_19_downstream_write_last_time <= system_0_burst_19_downstream_write;
    end


  //system_0_burst_19_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_19_downstream_write != system_0_burst_19_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_19_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_19_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_19_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_19_downstream_writedata_last_time <= system_0_burst_19_downstream_writedata;
    end


  //system_0_burst_19_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_19_downstream_writedata != system_0_burst_19_downstream_writedata_last_time) & system_0_burst_19_downstream_write)
        begin
          $write("%0d ns: system_0_burst_19_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_2_upstream_module (
                                                              // inputs:
                                                               clear_fifo,
                                                               clk,
                                                               data_in,
                                                               read,
                                                               reset_n,
                                                               sync_reset,
                                                               write,

                                                              // outputs:
                                                               data_out,
                                                               empty,
                                                               fifo_contains_ones_n,
                                                               full
                                                            )
;

  output  [  5: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  5: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  5: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  reg              full_2;
  reg              full_3;
  wire             full_4;
  reg     [  3: 0] how_many_ones;
  wire    [  3: 0] one_count_minus_one;
  wire    [  3: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  5: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  5: 0] p1_stage_1;
  wire             p2_full_2;
  wire    [  5: 0] p2_stage_2;
  wire             p3_full_3;
  wire    [  5: 0] p3_stage_3;
  reg     [  5: 0] stage_0;
  reg     [  5: 0] stage_1;
  reg     [  5: 0] stage_2;
  reg     [  5: 0] stage_3;
  wire    [  3: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_3;
  assign empty = !full_0;
  assign full_4 = 0;
  //data_3, which is an e_mux
  assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_3 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_3))
          if (sync_reset & full_3 & !((full_4 == 0) & read & write))
              stage_3 <= 0;
          else 
            stage_3 <= p3_stage_3;
    end


  //control_3, which is an e_mux
  assign p3_full_3 = ((read & !write) == 0)? full_2 :
    0;

  //control_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_2_upstream_module (
                                                                                   // inputs:
                                                                                    clear_fifo,
                                                                                    clk,
                                                                                    data_in,
                                                                                    read,
                                                                                    reset_n,
                                                                                    sync_reset,
                                                                                    write,

                                                                                   // outputs:
                                                                                    data_out,
                                                                                    empty,
                                                                                    fifo_contains_ones_n,
                                                                                    full
                                                                                 )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  reg              full_2;
  reg              full_3;
  wire             full_4;
  reg     [  3: 0] how_many_ones;
  wire    [  3: 0] one_count_minus_one;
  wire    [  3: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  wire             p2_full_2;
  wire             p2_stage_2;
  wire             p3_full_3;
  wire             p3_stage_3;
  reg              stage_0;
  reg              stage_1;
  reg              stage_2;
  reg              stage_3;
  wire    [  3: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_3;
  assign empty = !full_0;
  assign full_4 = 0;
  //data_3, which is an e_mux
  assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_3 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_3))
          if (sync_reset & full_3 & !((full_4 == 0) & read & write))
              stage_3 <= 0;
          else 
            stage_3 <= p3_stage_3;
    end


  //control_3, which is an e_mux
  assign p3_full_3 = ((read & !write) == 0)? full_2 :
    0;

  //control_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_2_upstream_arbitrator (
                                              // inputs:
                                               clk,
                                               cpu_0_instruction_master_address_to_slave,
                                               cpu_0_instruction_master_burstcount,
                                               cpu_0_instruction_master_dbs_address,
                                               cpu_0_instruction_master_latency_counter,
                                               cpu_0_instruction_master_read,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register,
                                               reset_n,
                                               system_0_burst_2_upstream_readdata,
                                               system_0_burst_2_upstream_readdatavalid,
                                               system_0_burst_2_upstream_waitrequest,

                                              // outputs:
                                               cpu_0_instruction_master_granted_system_0_burst_2_upstream,
                                               cpu_0_instruction_master_qualified_request_system_0_burst_2_upstream,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register,
                                               cpu_0_instruction_master_requests_system_0_burst_2_upstream,
                                               d1_system_0_burst_2_upstream_end_xfer,
                                               system_0_burst_2_upstream_address,
                                               system_0_burst_2_upstream_byteaddress,
                                               system_0_burst_2_upstream_byteenable,
                                               system_0_burst_2_upstream_debugaccess,
                                               system_0_burst_2_upstream_read,
                                               system_0_burst_2_upstream_readdata_from_sa,
                                               system_0_burst_2_upstream_waitrequest_from_sa,
                                               system_0_burst_2_upstream_write
                                            )
;

  output           cpu_0_instruction_master_granted_system_0_burst_2_upstream;
  output           cpu_0_instruction_master_qualified_request_system_0_burst_2_upstream;
  output           cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream;
  output           cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register;
  output           cpu_0_instruction_master_requests_system_0_burst_2_upstream;
  output           d1_system_0_burst_2_upstream_end_xfer;
  output  [ 21: 0] system_0_burst_2_upstream_address;
  output  [ 21: 0] system_0_burst_2_upstream_byteaddress;
  output           system_0_burst_2_upstream_byteenable;
  output           system_0_burst_2_upstream_debugaccess;
  output           system_0_burst_2_upstream_read;
  output  [  7: 0] system_0_burst_2_upstream_readdata_from_sa;
  output           system_0_burst_2_upstream_waitrequest_from_sa;
  output           system_0_burst_2_upstream_write;
  input            clk;
  input   [ 24: 0] cpu_0_instruction_master_address_to_slave;
  input   [  3: 0] cpu_0_instruction_master_burstcount;
  input   [  1: 0] cpu_0_instruction_master_dbs_address;
  input            cpu_0_instruction_master_latency_counter;
  input            cpu_0_instruction_master_read;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register;
  input            reset_n;
  input   [  7: 0] system_0_burst_2_upstream_readdata;
  input            system_0_burst_2_upstream_readdatavalid;
  input            system_0_burst_2_upstream_waitrequest;

  wire             cpu_0_instruction_master_arbiterlock;
  wire             cpu_0_instruction_master_arbiterlock2;
  wire             cpu_0_instruction_master_continuerequest;
  wire             cpu_0_instruction_master_granted_system_0_burst_2_upstream;
  wire             cpu_0_instruction_master_qualified_request_system_0_burst_2_upstream;
  wire             cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_2_upstream;
  wire             cpu_0_instruction_master_rdv_fifo_output_from_system_0_burst_2_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register;
  wire             cpu_0_instruction_master_requests_system_0_burst_2_upstream;
  wire             cpu_0_instruction_master_saved_grant_system_0_burst_2_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_2_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_2_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_2_upstream_load_fifo;
  wire    [ 21: 0] system_0_burst_2_upstream_address;
  wire             system_0_burst_2_upstream_allgrants;
  wire             system_0_burst_2_upstream_allow_new_arb_cycle;
  wire             system_0_burst_2_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_2_upstream_any_continuerequest;
  wire             system_0_burst_2_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_2_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_2_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_2_upstream_arb_share_set_values;
  wire             system_0_burst_2_upstream_beginbursttransfer_internal;
  wire             system_0_burst_2_upstream_begins_xfer;
  wire             system_0_burst_2_upstream_burstcount_fifo_empty;
  wire    [ 21: 0] system_0_burst_2_upstream_byteaddress;
  wire             system_0_burst_2_upstream_byteenable;
  reg     [  5: 0] system_0_burst_2_upstream_current_burst;
  wire    [  5: 0] system_0_burst_2_upstream_current_burst_minus_one;
  wire             system_0_burst_2_upstream_debugaccess;
  wire             system_0_burst_2_upstream_end_xfer;
  wire             system_0_burst_2_upstream_firsttransfer;
  wire             system_0_burst_2_upstream_grant_vector;
  wire             system_0_burst_2_upstream_in_a_read_cycle;
  wire             system_0_burst_2_upstream_in_a_write_cycle;
  reg              system_0_burst_2_upstream_load_fifo;
  wire             system_0_burst_2_upstream_master_qreq_vector;
  wire             system_0_burst_2_upstream_move_on_to_next_transaction;
  wire    [  5: 0] system_0_burst_2_upstream_next_burst_count;
  wire             system_0_burst_2_upstream_non_bursting_master_requests;
  wire             system_0_burst_2_upstream_read;
  wire    [  7: 0] system_0_burst_2_upstream_readdata_from_sa;
  wire             system_0_burst_2_upstream_readdatavalid_from_sa;
  reg              system_0_burst_2_upstream_reg_firsttransfer;
  wire    [  5: 0] system_0_burst_2_upstream_selected_burstcount;
  reg              system_0_burst_2_upstream_slavearbiterlockenable;
  wire             system_0_burst_2_upstream_slavearbiterlockenable2;
  wire             system_0_burst_2_upstream_this_cycle_is_the_last_burst;
  wire    [  5: 0] system_0_burst_2_upstream_transaction_burst_count;
  wire             system_0_burst_2_upstream_unreg_firsttransfer;
  wire             system_0_burst_2_upstream_waitrequest_from_sa;
  wire             system_0_burst_2_upstream_waits_for_read;
  wire             system_0_burst_2_upstream_waits_for_write;
  wire             system_0_burst_2_upstream_write;
  wire             wait_for_system_0_burst_2_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_2_upstream_end_xfer;
    end


  assign system_0_burst_2_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_instruction_master_qualified_request_system_0_burst_2_upstream));
  //assign system_0_burst_2_upstream_readdatavalid_from_sa = system_0_burst_2_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_2_upstream_readdatavalid_from_sa = system_0_burst_2_upstream_readdatavalid;

  //assign system_0_burst_2_upstream_readdata_from_sa = system_0_burst_2_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_2_upstream_readdata_from_sa = system_0_burst_2_upstream_readdata;

  assign cpu_0_instruction_master_requests_system_0_burst_2_upstream = (({cpu_0_instruction_master_address_to_slave[24 : 22] , 22'b0} == 25'h1400000) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
  //assign system_0_burst_2_upstream_waitrequest_from_sa = system_0_burst_2_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_2_upstream_waitrequest_from_sa = system_0_burst_2_upstream_waitrequest;

  //system_0_burst_2_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_2_upstream_arb_share_set_values = 1;

  //system_0_burst_2_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_2_upstream_non_bursting_master_requests = 0;

  //system_0_burst_2_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_2_upstream_any_bursting_master_saved_grant = cpu_0_instruction_master_saved_grant_system_0_burst_2_upstream;

  //system_0_burst_2_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_2_upstream_arb_share_counter_next_value = system_0_burst_2_upstream_firsttransfer ? (system_0_burst_2_upstream_arb_share_set_values - 1) : |system_0_burst_2_upstream_arb_share_counter ? (system_0_burst_2_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_2_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_2_upstream_allgrants = |system_0_burst_2_upstream_grant_vector;

  //system_0_burst_2_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_2_upstream_end_xfer = ~(system_0_burst_2_upstream_waits_for_read | system_0_burst_2_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_2_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_2_upstream = system_0_burst_2_upstream_end_xfer & (~system_0_burst_2_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_2_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_2_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_2_upstream & system_0_burst_2_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_2_upstream & ~system_0_burst_2_upstream_non_bursting_master_requests);

  //system_0_burst_2_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_2_upstream_arb_share_counter <= 0;
      else if (system_0_burst_2_upstream_arb_counter_enable)
          system_0_burst_2_upstream_arb_share_counter <= system_0_burst_2_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_2_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_2_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_2_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_2_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_2_upstream & ~system_0_burst_2_upstream_non_bursting_master_requests))
          system_0_burst_2_upstream_slavearbiterlockenable <= |system_0_burst_2_upstream_arb_share_counter_next_value;
    end


  //cpu_0/instruction_master system_0_burst_2/upstream arbiterlock, which is an e_assign
  assign cpu_0_instruction_master_arbiterlock = system_0_burst_2_upstream_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;

  //system_0_burst_2_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_2_upstream_slavearbiterlockenable2 = |system_0_burst_2_upstream_arb_share_counter_next_value;

  //cpu_0/instruction_master system_0_burst_2/upstream arbiterlock2, which is an e_assign
  assign cpu_0_instruction_master_arbiterlock2 = system_0_burst_2_upstream_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;

  //system_0_burst_2_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_2_upstream_any_continuerequest = 1;

  //cpu_0_instruction_master_continuerequest continued request, which is an e_assign
  assign cpu_0_instruction_master_continuerequest = 1;

  assign cpu_0_instruction_master_qualified_request_system_0_burst_2_upstream = cpu_0_instruction_master_requests_system_0_burst_2_upstream & ~((cpu_0_instruction_master_read & ((cpu_0_instruction_master_latency_counter != 0) | (1 < cpu_0_instruction_master_latency_counter) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register))));
  //unique name for system_0_burst_2_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_2_upstream_move_on_to_next_transaction = system_0_burst_2_upstream_this_cycle_is_the_last_burst & system_0_burst_2_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_2_upstream, which is an e_mux
  assign system_0_burst_2_upstream_selected_burstcount = (cpu_0_instruction_master_granted_system_0_burst_2_upstream)? cpu_0_instruction_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_2_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_2_upstream_module burstcount_fifo_for_system_0_burst_2_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_2_upstream_selected_burstcount),
      .data_out             (system_0_burst_2_upstream_transaction_burst_count),
      .empty                (system_0_burst_2_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_2_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_2_upstream_waits_for_read & system_0_burst_2_upstream_load_fifo & ~(system_0_burst_2_upstream_this_cycle_is_the_last_burst & system_0_burst_2_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_2_upstream current burst minus one, which is an e_assign
  assign system_0_burst_2_upstream_current_burst_minus_one = system_0_burst_2_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_2_upstream, which is an e_mux
  assign system_0_burst_2_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_2_upstream_waits_for_read) & ~system_0_burst_2_upstream_load_fifo))? {system_0_burst_2_upstream_selected_burstcount, 2'b0} :
    ((in_a_read_cycle & ~system_0_burst_2_upstream_waits_for_read & system_0_burst_2_upstream_this_cycle_is_the_last_burst & system_0_burst_2_upstream_burstcount_fifo_empty))? {system_0_burst_2_upstream_selected_burstcount, 2'b0} :
    (system_0_burst_2_upstream_this_cycle_is_the_last_burst)? {system_0_burst_2_upstream_transaction_burst_count,  2'b0} :
    system_0_burst_2_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_2_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_2_upstream_current_burst <= 0;
      else if (system_0_burst_2_upstream_readdatavalid_from_sa | (~system_0_burst_2_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_2_upstream_waits_for_read)))
          system_0_burst_2_upstream_current_burst <= system_0_burst_2_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_2_upstream_load_fifo = (~system_0_burst_2_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_2_upstream_waits_for_read) & system_0_burst_2_upstream_load_fifo))? 1 :
    ~system_0_burst_2_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_2_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_2_upstream_waits_for_read) & ~system_0_burst_2_upstream_load_fifo | system_0_burst_2_upstream_this_cycle_is_the_last_burst)
          system_0_burst_2_upstream_load_fifo <= p0_system_0_burst_2_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_2_upstream, which is an e_assign
  assign system_0_burst_2_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_2_upstream_current_burst_minus_one) & system_0_burst_2_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_2_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_2_upstream_module rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_2_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_instruction_master_granted_system_0_burst_2_upstream),
      .data_out             (cpu_0_instruction_master_rdv_fifo_output_from_system_0_burst_2_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_2_upstream),
      .full                 (),
      .read                 (system_0_burst_2_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_2_upstream_waits_for_read)
    );

  assign cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register = ~cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_2_upstream;
  //local readdatavalid cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream, which is an e_mux
  assign cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream = system_0_burst_2_upstream_readdatavalid_from_sa;

  //byteaddress mux for system_0_burst_2/upstream, which is an e_mux
  assign system_0_burst_2_upstream_byteaddress = cpu_0_instruction_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_instruction_master_granted_system_0_burst_2_upstream = cpu_0_instruction_master_qualified_request_system_0_burst_2_upstream;

  //cpu_0/instruction_master saved-grant system_0_burst_2/upstream, which is an e_assign
  assign cpu_0_instruction_master_saved_grant_system_0_burst_2_upstream = cpu_0_instruction_master_requests_system_0_burst_2_upstream;

  //allow new arb cycle for system_0_burst_2/upstream, which is an e_assign
  assign system_0_burst_2_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_2_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_2_upstream_master_qreq_vector = 1;

  //system_0_burst_2_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_2_upstream_firsttransfer = system_0_burst_2_upstream_begins_xfer ? system_0_burst_2_upstream_unreg_firsttransfer : system_0_burst_2_upstream_reg_firsttransfer;

  //system_0_burst_2_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_2_upstream_unreg_firsttransfer = ~(system_0_burst_2_upstream_slavearbiterlockenable & system_0_burst_2_upstream_any_continuerequest);

  //system_0_burst_2_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_2_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_2_upstream_begins_xfer)
          system_0_burst_2_upstream_reg_firsttransfer <= system_0_burst_2_upstream_unreg_firsttransfer;
    end


  //system_0_burst_2_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_2_upstream_beginbursttransfer_internal = system_0_burst_2_upstream_begins_xfer;

  //system_0_burst_2_upstream_read assignment, which is an e_mux
  assign system_0_burst_2_upstream_read = cpu_0_instruction_master_granted_system_0_burst_2_upstream & cpu_0_instruction_master_read;

  //system_0_burst_2_upstream_write assignment, which is an e_mux
  assign system_0_burst_2_upstream_write = 0;

  //system_0_burst_2_upstream_address mux, which is an e_mux
  assign system_0_burst_2_upstream_address = {cpu_0_instruction_master_address_to_slave >> 2,
    cpu_0_instruction_master_dbs_address[1 : 0]};

  //d1_system_0_burst_2_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_2_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_2_upstream_end_xfer <= system_0_burst_2_upstream_end_xfer;
    end


  //system_0_burst_2_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_2_upstream_waits_for_read = system_0_burst_2_upstream_in_a_read_cycle & system_0_burst_2_upstream_waitrequest_from_sa;

  //system_0_burst_2_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_2_upstream_in_a_read_cycle = cpu_0_instruction_master_granted_system_0_burst_2_upstream & cpu_0_instruction_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_2_upstream_in_a_read_cycle;

  //system_0_burst_2_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_2_upstream_waits_for_write = system_0_burst_2_upstream_in_a_write_cycle & system_0_burst_2_upstream_waitrequest_from_sa;

  //system_0_burst_2_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_2_upstream_in_a_write_cycle = 0;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_2_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_2_upstream_counter = 0;
  //system_0_burst_2_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_2_upstream_byteenable = -1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_2_upstream_debugaccess = 0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_2/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/instruction_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_instruction_master_requests_system_0_burst_2_upstream && (cpu_0_instruction_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/instruction_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_2/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_2_downstream_arbitrator (
                                                // inputs:
                                                 cfi_flash_0_s1_wait_counter_eq_0,
                                                 clk,
                                                 d1_tri_state_bridge_0_avalon_slave_end_xfer,
                                                 incoming_tri_state_bridge_0_data_with_Xs_converted_to_0,
                                                 reset_n,
                                                 system_0_burst_2_downstream_address,
                                                 system_0_burst_2_downstream_burstcount,
                                                 system_0_burst_2_downstream_byteenable,
                                                 system_0_burst_2_downstream_granted_cfi_flash_0_s1,
                                                 system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1,
                                                 system_0_burst_2_downstream_read,
                                                 system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1,
                                                 system_0_burst_2_downstream_requests_cfi_flash_0_s1,
                                                 system_0_burst_2_downstream_write,
                                                 system_0_burst_2_downstream_writedata,

                                                // outputs:
                                                 system_0_burst_2_downstream_address_to_slave,
                                                 system_0_burst_2_downstream_latency_counter,
                                                 system_0_burst_2_downstream_readdata,
                                                 system_0_burst_2_downstream_readdatavalid,
                                                 system_0_burst_2_downstream_reset_n,
                                                 system_0_burst_2_downstream_waitrequest
                                              )
;

  output  [ 21: 0] system_0_burst_2_downstream_address_to_slave;
  output  [  1: 0] system_0_burst_2_downstream_latency_counter;
  output  [  7: 0] system_0_burst_2_downstream_readdata;
  output           system_0_burst_2_downstream_readdatavalid;
  output           system_0_burst_2_downstream_reset_n;
  output           system_0_burst_2_downstream_waitrequest;
  input            cfi_flash_0_s1_wait_counter_eq_0;
  input            clk;
  input            d1_tri_state_bridge_0_avalon_slave_end_xfer;
  input   [  7: 0] incoming_tri_state_bridge_0_data_with_Xs_converted_to_0;
  input            reset_n;
  input   [ 21: 0] system_0_burst_2_downstream_address;
  input            system_0_burst_2_downstream_burstcount;
  input            system_0_burst_2_downstream_byteenable;
  input            system_0_burst_2_downstream_granted_cfi_flash_0_s1;
  input            system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1;
  input            system_0_burst_2_downstream_read;
  input            system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1;
  input            system_0_burst_2_downstream_requests_cfi_flash_0_s1;
  input            system_0_burst_2_downstream_write;
  input   [  7: 0] system_0_burst_2_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire    [  1: 0] latency_load_value;
  wire    [  1: 0] p1_system_0_burst_2_downstream_latency_counter;
  wire             pre_flush_system_0_burst_2_downstream_readdatavalid;
  wire             r_6;
  reg     [ 21: 0] system_0_burst_2_downstream_address_last_time;
  wire    [ 21: 0] system_0_burst_2_downstream_address_to_slave;
  reg              system_0_burst_2_downstream_burstcount_last_time;
  reg              system_0_burst_2_downstream_byteenable_last_time;
  wire             system_0_burst_2_downstream_is_granted_some_slave;
  reg     [  1: 0] system_0_burst_2_downstream_latency_counter;
  reg              system_0_burst_2_downstream_read_but_no_slave_selected;
  reg              system_0_burst_2_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_2_downstream_readdata;
  wire             system_0_burst_2_downstream_readdatavalid;
  wire             system_0_burst_2_downstream_reset_n;
  wire             system_0_burst_2_downstream_run;
  wire             system_0_burst_2_downstream_waitrequest;
  reg              system_0_burst_2_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_2_downstream_writedata_last_time;
  //r_6 master_run cascaded wait assignment, which is an e_assign
  assign r_6 = 1 & (system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1 | ~system_0_burst_2_downstream_requests_cfi_flash_0_s1) & (system_0_burst_2_downstream_granted_cfi_flash_0_s1 | ~system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1) & ((~system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1 | ~system_0_burst_2_downstream_read | (1 & ((cfi_flash_0_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_0_avalon_slave_end_xfer)) & system_0_burst_2_downstream_read))) & ((~system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1 | ~system_0_burst_2_downstream_write | (1 & ((cfi_flash_0_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_0_avalon_slave_end_xfer)) & system_0_burst_2_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_2_downstream_run = r_6;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_2_downstream_address_to_slave = system_0_burst_2_downstream_address;

  //system_0_burst_2_downstream_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_2_downstream_read_but_no_slave_selected <= 0;
      else 
        system_0_burst_2_downstream_read_but_no_slave_selected <= system_0_burst_2_downstream_read & system_0_burst_2_downstream_run & ~system_0_burst_2_downstream_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign system_0_burst_2_downstream_is_granted_some_slave = system_0_burst_2_downstream_granted_cfi_flash_0_s1;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_2_downstream_readdatavalid = system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_2_downstream_readdatavalid = system_0_burst_2_downstream_read_but_no_slave_selected |
    pre_flush_system_0_burst_2_downstream_readdatavalid;

  //system_0_burst_2/downstream readdata mux, which is an e_mux
  assign system_0_burst_2_downstream_readdata = incoming_tri_state_bridge_0_data_with_Xs_converted_to_0;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_2_downstream_waitrequest = ~system_0_burst_2_downstream_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_2_downstream_latency_counter <= 0;
      else 
        system_0_burst_2_downstream_latency_counter <= p1_system_0_burst_2_downstream_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_system_0_burst_2_downstream_latency_counter = ((system_0_burst_2_downstream_run & system_0_burst_2_downstream_read))? latency_load_value :
    (system_0_burst_2_downstream_latency_counter)? system_0_burst_2_downstream_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = {2 {system_0_burst_2_downstream_requests_cfi_flash_0_s1}} & 2;

  //system_0_burst_2_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_2_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_2_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_2_downstream_address_last_time <= 0;
      else 
        system_0_burst_2_downstream_address_last_time <= system_0_burst_2_downstream_address;
    end


  //system_0_burst_2/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_2_downstream_waitrequest & (system_0_burst_2_downstream_read | system_0_burst_2_downstream_write);
    end


  //system_0_burst_2_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_2_downstream_address != system_0_burst_2_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_2_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_2_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_2_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_2_downstream_burstcount_last_time <= system_0_burst_2_downstream_burstcount;
    end


  //system_0_burst_2_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_2_downstream_burstcount != system_0_burst_2_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_2_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_2_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_2_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_2_downstream_byteenable_last_time <= system_0_burst_2_downstream_byteenable;
    end


  //system_0_burst_2_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_2_downstream_byteenable != system_0_burst_2_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_2_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_2_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_2_downstream_read_last_time <= 0;
      else 
        system_0_burst_2_downstream_read_last_time <= system_0_burst_2_downstream_read;
    end


  //system_0_burst_2_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_2_downstream_read != system_0_burst_2_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_2_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_2_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_2_downstream_write_last_time <= 0;
      else 
        system_0_burst_2_downstream_write_last_time <= system_0_burst_2_downstream_write;
    end


  //system_0_burst_2_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_2_downstream_write != system_0_burst_2_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_2_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_2_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_2_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_2_downstream_writedata_last_time <= system_0_burst_2_downstream_writedata;
    end


  //system_0_burst_2_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_2_downstream_writedata != system_0_burst_2_downstream_writedata_last_time) & system_0_burst_2_downstream_write)
        begin
          $write("%0d ns: system_0_burst_2_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_20_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_20_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_20_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_20_upstream_readdata,
                                                system_0_burst_20_upstream_readdatavalid,
                                                system_0_burst_20_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_20_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_20_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_20_upstream,
                                                d1_system_0_burst_20_upstream_end_xfer,
                                                system_0_burst_20_upstream_address,
                                                system_0_burst_20_upstream_burstcount,
                                                system_0_burst_20_upstream_byteaddress,
                                                system_0_burst_20_upstream_byteenable,
                                                system_0_burst_20_upstream_debugaccess,
                                                system_0_burst_20_upstream_read,
                                                system_0_burst_20_upstream_readdata_from_sa,
                                                system_0_burst_20_upstream_waitrequest_from_sa,
                                                system_0_burst_20_upstream_write,
                                                system_0_burst_20_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_20_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_20_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_20_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_20_upstream;
  output           d1_system_0_burst_20_upstream_end_xfer;
  output  [  1: 0] system_0_burst_20_upstream_address;
  output  [  3: 0] system_0_burst_20_upstream_burstcount;
  output  [  1: 0] system_0_burst_20_upstream_byteaddress;
  output           system_0_burst_20_upstream_byteenable;
  output           system_0_burst_20_upstream_debugaccess;
  output           system_0_burst_20_upstream_read;
  output  [  7: 0] system_0_burst_20_upstream_readdata_from_sa;
  output           system_0_burst_20_upstream_waitrequest_from_sa;
  output           system_0_burst_20_upstream_write;
  output  [  7: 0] system_0_burst_20_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_20_upstream_readdata;
  input            system_0_burst_20_upstream_readdatavalid;
  input            system_0_burst_20_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_20_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_20_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_20_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_20_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_20_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_20_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_20_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_20_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_20_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_20_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_20_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_20_upstream_address;
  wire             system_0_burst_20_upstream_allgrants;
  wire             system_0_burst_20_upstream_allow_new_arb_cycle;
  wire             system_0_burst_20_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_20_upstream_any_continuerequest;
  wire             system_0_burst_20_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_20_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_20_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_20_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_20_upstream_bbt_burstcounter;
  wire             system_0_burst_20_upstream_beginbursttransfer_internal;
  wire             system_0_burst_20_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_20_upstream_burstcount;
  wire             system_0_burst_20_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_20_upstream_byteaddress;
  wire             system_0_burst_20_upstream_byteenable;
  reg     [  3: 0] system_0_burst_20_upstream_current_burst;
  wire    [  3: 0] system_0_burst_20_upstream_current_burst_minus_one;
  wire             system_0_burst_20_upstream_debugaccess;
  wire             system_0_burst_20_upstream_end_xfer;
  wire             system_0_burst_20_upstream_firsttransfer;
  wire             system_0_burst_20_upstream_grant_vector;
  wire             system_0_burst_20_upstream_in_a_read_cycle;
  wire             system_0_burst_20_upstream_in_a_write_cycle;
  reg              system_0_burst_20_upstream_load_fifo;
  wire             system_0_burst_20_upstream_master_qreq_vector;
  wire             system_0_burst_20_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_20_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_20_upstream_next_burst_count;
  wire             system_0_burst_20_upstream_non_bursting_master_requests;
  wire             system_0_burst_20_upstream_read;
  wire    [  7: 0] system_0_burst_20_upstream_readdata_from_sa;
  wire             system_0_burst_20_upstream_readdatavalid_from_sa;
  reg              system_0_burst_20_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_20_upstream_selected_burstcount;
  reg              system_0_burst_20_upstream_slavearbiterlockenable;
  wire             system_0_burst_20_upstream_slavearbiterlockenable2;
  wire             system_0_burst_20_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_20_upstream_transaction_burst_count;
  wire             system_0_burst_20_upstream_unreg_firsttransfer;
  wire             system_0_burst_20_upstream_waitrequest_from_sa;
  wire             system_0_burst_20_upstream_waits_for_read;
  wire             system_0_burst_20_upstream_waits_for_write;
  wire             system_0_burst_20_upstream_write;
  wire    [  7: 0] system_0_burst_20_upstream_writedata;
  wire             wait_for_system_0_burst_20_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_20_upstream_end_xfer;
    end


  assign system_0_burst_20_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_20_upstream));
  //assign system_0_burst_20_upstream_readdatavalid_from_sa = system_0_burst_20_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_20_upstream_readdatavalid_from_sa = system_0_burst_20_upstream_readdatavalid;

  //assign system_0_burst_20_upstream_readdata_from_sa = system_0_burst_20_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_20_upstream_readdata_from_sa = system_0_burst_20_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_20_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a100) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_20_upstream_waitrequest_from_sa = system_0_burst_20_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_20_upstream_waitrequest_from_sa = system_0_burst_20_upstream_waitrequest;

  //system_0_burst_20_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_20_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_20_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_20_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_20_upstream_non_bursting_master_requests = 0;

  //system_0_burst_20_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_20_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_20_upstream;

  //system_0_burst_20_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_20_upstream_arb_share_counter_next_value = system_0_burst_20_upstream_firsttransfer ? (system_0_burst_20_upstream_arb_share_set_values - 1) : |system_0_burst_20_upstream_arb_share_counter ? (system_0_burst_20_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_20_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_20_upstream_allgrants = |system_0_burst_20_upstream_grant_vector;

  //system_0_burst_20_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_20_upstream_end_xfer = ~(system_0_burst_20_upstream_waits_for_read | system_0_burst_20_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_20_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_20_upstream = system_0_burst_20_upstream_end_xfer & (~system_0_burst_20_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_20_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_20_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_20_upstream & system_0_burst_20_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_20_upstream & ~system_0_burst_20_upstream_non_bursting_master_requests);

  //system_0_burst_20_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_20_upstream_arb_share_counter <= 0;
      else if (system_0_burst_20_upstream_arb_counter_enable)
          system_0_burst_20_upstream_arb_share_counter <= system_0_burst_20_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_20_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_20_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_20_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_20_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_20_upstream & ~system_0_burst_20_upstream_non_bursting_master_requests))
          system_0_burst_20_upstream_slavearbiterlockenable <= |system_0_burst_20_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_20/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_20_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_20_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_20_upstream_slavearbiterlockenable2 = |system_0_burst_20_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_20/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_20_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_20_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_20_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_20_upstream = cpu_0_data_master_requests_system_0_burst_20_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_20_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_20_upstream_move_on_to_next_transaction = system_0_burst_20_upstream_this_cycle_is_the_last_burst & system_0_burst_20_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_20_upstream, which is an e_mux
  assign system_0_burst_20_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_20_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_20_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_20_upstream_module burstcount_fifo_for_system_0_burst_20_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_20_upstream_selected_burstcount),
      .data_out             (system_0_burst_20_upstream_transaction_burst_count),
      .empty                (system_0_burst_20_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_20_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_20_upstream_waits_for_read & system_0_burst_20_upstream_load_fifo & ~(system_0_burst_20_upstream_this_cycle_is_the_last_burst & system_0_burst_20_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_20_upstream current burst minus one, which is an e_assign
  assign system_0_burst_20_upstream_current_burst_minus_one = system_0_burst_20_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_20_upstream, which is an e_mux
  assign system_0_burst_20_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_20_upstream_waits_for_read) & ~system_0_burst_20_upstream_load_fifo))? system_0_burst_20_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_20_upstream_waits_for_read & system_0_burst_20_upstream_this_cycle_is_the_last_burst & system_0_burst_20_upstream_burstcount_fifo_empty))? system_0_burst_20_upstream_selected_burstcount :
    (system_0_burst_20_upstream_this_cycle_is_the_last_burst)? system_0_burst_20_upstream_transaction_burst_count :
    system_0_burst_20_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_20_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_20_upstream_current_burst <= 0;
      else if (system_0_burst_20_upstream_readdatavalid_from_sa | (~system_0_burst_20_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_20_upstream_waits_for_read)))
          system_0_burst_20_upstream_current_burst <= system_0_burst_20_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_20_upstream_load_fifo = (~system_0_burst_20_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_20_upstream_waits_for_read) & system_0_burst_20_upstream_load_fifo))? 1 :
    ~system_0_burst_20_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_20_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_20_upstream_waits_for_read) & ~system_0_burst_20_upstream_load_fifo | system_0_burst_20_upstream_this_cycle_is_the_last_burst)
          system_0_burst_20_upstream_load_fifo <= p0_system_0_burst_20_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_20_upstream, which is an e_assign
  assign system_0_burst_20_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_20_upstream_current_burst_minus_one) & system_0_burst_20_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_20_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_20_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_20_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_20_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_20_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_20_upstream),
      .full                 (),
      .read                 (system_0_burst_20_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_20_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_20_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_20_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_20_upstream = system_0_burst_20_upstream_readdatavalid_from_sa;

  //system_0_burst_20_upstream_writedata mux, which is an e_mux
  assign system_0_burst_20_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_20/upstream, which is an e_mux
  assign system_0_burst_20_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_20_upstream = cpu_0_data_master_qualified_request_system_0_burst_20_upstream;

  //cpu_0/data_master saved-grant system_0_burst_20/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_20_upstream = cpu_0_data_master_requests_system_0_burst_20_upstream;

  //allow new arb cycle for system_0_burst_20/upstream, which is an e_assign
  assign system_0_burst_20_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_20_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_20_upstream_master_qreq_vector = 1;

  //system_0_burst_20_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_20_upstream_firsttransfer = system_0_burst_20_upstream_begins_xfer ? system_0_burst_20_upstream_unreg_firsttransfer : system_0_burst_20_upstream_reg_firsttransfer;

  //system_0_burst_20_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_20_upstream_unreg_firsttransfer = ~(system_0_burst_20_upstream_slavearbiterlockenable & system_0_burst_20_upstream_any_continuerequest);

  //system_0_burst_20_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_20_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_20_upstream_begins_xfer)
          system_0_burst_20_upstream_reg_firsttransfer <= system_0_burst_20_upstream_unreg_firsttransfer;
    end


  //system_0_burst_20_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_20_upstream_next_bbt_burstcount = ((((system_0_burst_20_upstream_write) && (system_0_burst_20_upstream_bbt_burstcounter == 0))))? (system_0_burst_20_upstream_burstcount - 1) :
    ((((system_0_burst_20_upstream_read) && (system_0_burst_20_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_20_upstream_bbt_burstcounter - 1);

  //system_0_burst_20_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_20_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_20_upstream_begins_xfer)
          system_0_burst_20_upstream_bbt_burstcounter <= system_0_burst_20_upstream_next_bbt_burstcount;
    end


  //system_0_burst_20_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_20_upstream_beginbursttransfer_internal = system_0_burst_20_upstream_begins_xfer & (system_0_burst_20_upstream_bbt_burstcounter == 0);

  //system_0_burst_20_upstream_read assignment, which is an e_mux
  assign system_0_burst_20_upstream_read = cpu_0_data_master_granted_system_0_burst_20_upstream & cpu_0_data_master_read;

  //system_0_burst_20_upstream_write assignment, which is an e_mux
  assign system_0_burst_20_upstream_write = cpu_0_data_master_granted_system_0_burst_20_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_20_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_20_upstream_address mux, which is an e_mux
  assign system_0_burst_20_upstream_address = shifted_address_to_system_0_burst_20_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_20_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_20_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_20_upstream_end_xfer <= system_0_burst_20_upstream_end_xfer;
    end


  //system_0_burst_20_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_20_upstream_waits_for_read = system_0_burst_20_upstream_in_a_read_cycle & system_0_burst_20_upstream_waitrequest_from_sa;

  //system_0_burst_20_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_20_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_20_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_20_upstream_in_a_read_cycle;

  //system_0_burst_20_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_20_upstream_waits_for_write = system_0_burst_20_upstream_in_a_write_cycle & system_0_burst_20_upstream_waitrequest_from_sa;

  //system_0_burst_20_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_20_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_20_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_20_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_20_upstream_counter = 0;
  //system_0_burst_20_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_20_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_20_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_20_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_20_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_20_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_20_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_20/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_20_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_20/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_20_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_noteA_s1_end_xfer,
                                                  noteA_s1_readdata_from_sa,
                                                  reset_n,
                                                  system_0_burst_20_downstream_address,
                                                  system_0_burst_20_downstream_burstcount,
                                                  system_0_burst_20_downstream_byteenable,
                                                  system_0_burst_20_downstream_granted_noteA_s1,
                                                  system_0_burst_20_downstream_qualified_request_noteA_s1,
                                                  system_0_burst_20_downstream_read,
                                                  system_0_burst_20_downstream_read_data_valid_noteA_s1,
                                                  system_0_burst_20_downstream_requests_noteA_s1,
                                                  system_0_burst_20_downstream_write,
                                                  system_0_burst_20_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_20_downstream_address_to_slave,
                                                  system_0_burst_20_downstream_latency_counter,
                                                  system_0_burst_20_downstream_readdata,
                                                  system_0_burst_20_downstream_readdatavalid,
                                                  system_0_burst_20_downstream_reset_n,
                                                  system_0_burst_20_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_20_downstream_address_to_slave;
  output           system_0_burst_20_downstream_latency_counter;
  output  [  7: 0] system_0_burst_20_downstream_readdata;
  output           system_0_burst_20_downstream_readdatavalid;
  output           system_0_burst_20_downstream_reset_n;
  output           system_0_burst_20_downstream_waitrequest;
  input            clk;
  input            d1_noteA_s1_end_xfer;
  input            noteA_s1_readdata_from_sa;
  input            reset_n;
  input   [  1: 0] system_0_burst_20_downstream_address;
  input            system_0_burst_20_downstream_burstcount;
  input            system_0_burst_20_downstream_byteenable;
  input            system_0_burst_20_downstream_granted_noteA_s1;
  input            system_0_burst_20_downstream_qualified_request_noteA_s1;
  input            system_0_burst_20_downstream_read;
  input            system_0_burst_20_downstream_read_data_valid_noteA_s1;
  input            system_0_burst_20_downstream_requests_noteA_s1;
  input            system_0_burst_20_downstream_write;
  input   [  7: 0] system_0_burst_20_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_20_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_20_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_20_downstream_address_to_slave;
  reg              system_0_burst_20_downstream_burstcount_last_time;
  reg              system_0_burst_20_downstream_byteenable_last_time;
  wire             system_0_burst_20_downstream_latency_counter;
  reg              system_0_burst_20_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_20_downstream_readdata;
  wire             system_0_burst_20_downstream_readdatavalid;
  wire             system_0_burst_20_downstream_reset_n;
  wire             system_0_burst_20_downstream_run;
  wire             system_0_burst_20_downstream_waitrequest;
  reg              system_0_burst_20_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_20_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_20_downstream_qualified_request_noteA_s1 | ~system_0_burst_20_downstream_requests_noteA_s1) & ((~system_0_burst_20_downstream_qualified_request_noteA_s1 | ~system_0_burst_20_downstream_read | (1 & ~d1_noteA_s1_end_xfer & system_0_burst_20_downstream_read))) & ((~system_0_burst_20_downstream_qualified_request_noteA_s1 | ~system_0_burst_20_downstream_write | (1 & system_0_burst_20_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_20_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_20_downstream_address_to_slave = system_0_burst_20_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_20_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_20_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_20_downstream_readdatavalid |
    system_0_burst_20_downstream_read_data_valid_noteA_s1;

  //system_0_burst_20/downstream readdata mux, which is an e_mux
  assign system_0_burst_20_downstream_readdata = noteA_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_20_downstream_waitrequest = ~system_0_burst_20_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_20_downstream_latency_counter = 0;

  //system_0_burst_20_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_20_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_20_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_20_downstream_address_last_time <= 0;
      else 
        system_0_burst_20_downstream_address_last_time <= system_0_burst_20_downstream_address;
    end


  //system_0_burst_20/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_20_downstream_waitrequest & (system_0_burst_20_downstream_read | system_0_burst_20_downstream_write);
    end


  //system_0_burst_20_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_20_downstream_address != system_0_burst_20_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_20_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_20_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_20_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_20_downstream_burstcount_last_time <= system_0_burst_20_downstream_burstcount;
    end


  //system_0_burst_20_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_20_downstream_burstcount != system_0_burst_20_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_20_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_20_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_20_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_20_downstream_byteenable_last_time <= system_0_burst_20_downstream_byteenable;
    end


  //system_0_burst_20_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_20_downstream_byteenable != system_0_burst_20_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_20_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_20_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_20_downstream_read_last_time <= 0;
      else 
        system_0_burst_20_downstream_read_last_time <= system_0_burst_20_downstream_read;
    end


  //system_0_burst_20_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_20_downstream_read != system_0_burst_20_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_20_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_20_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_20_downstream_write_last_time <= 0;
      else 
        system_0_burst_20_downstream_write_last_time <= system_0_burst_20_downstream_write;
    end


  //system_0_burst_20_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_20_downstream_write != system_0_burst_20_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_20_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_20_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_20_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_20_downstream_writedata_last_time <= system_0_burst_20_downstream_writedata;
    end


  //system_0_burst_20_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_20_downstream_writedata != system_0_burst_20_downstream_writedata_last_time) & system_0_burst_20_downstream_write)
        begin
          $write("%0d ns: system_0_burst_20_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_21_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_21_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_21_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_21_upstream_readdata,
                                                system_0_burst_21_upstream_readdatavalid,
                                                system_0_burst_21_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_21_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_21_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_21_upstream,
                                                d1_system_0_burst_21_upstream_end_xfer,
                                                system_0_burst_21_upstream_address,
                                                system_0_burst_21_upstream_burstcount,
                                                system_0_burst_21_upstream_byteaddress,
                                                system_0_burst_21_upstream_byteenable,
                                                system_0_burst_21_upstream_debugaccess,
                                                system_0_burst_21_upstream_read,
                                                system_0_burst_21_upstream_readdata_from_sa,
                                                system_0_burst_21_upstream_waitrequest_from_sa,
                                                system_0_burst_21_upstream_write,
                                                system_0_burst_21_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_21_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_21_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_21_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_21_upstream;
  output           d1_system_0_burst_21_upstream_end_xfer;
  output  [  1: 0] system_0_burst_21_upstream_address;
  output  [  3: 0] system_0_burst_21_upstream_burstcount;
  output  [  1: 0] system_0_burst_21_upstream_byteaddress;
  output           system_0_burst_21_upstream_byteenable;
  output           system_0_burst_21_upstream_debugaccess;
  output           system_0_burst_21_upstream_read;
  output  [  7: 0] system_0_burst_21_upstream_readdata_from_sa;
  output           system_0_burst_21_upstream_waitrequest_from_sa;
  output           system_0_burst_21_upstream_write;
  output  [  7: 0] system_0_burst_21_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_21_upstream_readdata;
  input            system_0_burst_21_upstream_readdatavalid;
  input            system_0_burst_21_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_21_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_21_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_21_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_21_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_21_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_21_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_21_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_21_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_21_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_21_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_21_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_21_upstream_address;
  wire             system_0_burst_21_upstream_allgrants;
  wire             system_0_burst_21_upstream_allow_new_arb_cycle;
  wire             system_0_burst_21_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_21_upstream_any_continuerequest;
  wire             system_0_burst_21_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_21_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_21_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_21_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_21_upstream_bbt_burstcounter;
  wire             system_0_burst_21_upstream_beginbursttransfer_internal;
  wire             system_0_burst_21_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_21_upstream_burstcount;
  wire             system_0_burst_21_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_21_upstream_byteaddress;
  wire             system_0_burst_21_upstream_byteenable;
  reg     [  3: 0] system_0_burst_21_upstream_current_burst;
  wire    [  3: 0] system_0_burst_21_upstream_current_burst_minus_one;
  wire             system_0_burst_21_upstream_debugaccess;
  wire             system_0_burst_21_upstream_end_xfer;
  wire             system_0_burst_21_upstream_firsttransfer;
  wire             system_0_burst_21_upstream_grant_vector;
  wire             system_0_burst_21_upstream_in_a_read_cycle;
  wire             system_0_burst_21_upstream_in_a_write_cycle;
  reg              system_0_burst_21_upstream_load_fifo;
  wire             system_0_burst_21_upstream_master_qreq_vector;
  wire             system_0_burst_21_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_21_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_21_upstream_next_burst_count;
  wire             system_0_burst_21_upstream_non_bursting_master_requests;
  wire             system_0_burst_21_upstream_read;
  wire    [  7: 0] system_0_burst_21_upstream_readdata_from_sa;
  wire             system_0_burst_21_upstream_readdatavalid_from_sa;
  reg              system_0_burst_21_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_21_upstream_selected_burstcount;
  reg              system_0_burst_21_upstream_slavearbiterlockenable;
  wire             system_0_burst_21_upstream_slavearbiterlockenable2;
  wire             system_0_burst_21_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_21_upstream_transaction_burst_count;
  wire             system_0_burst_21_upstream_unreg_firsttransfer;
  wire             system_0_burst_21_upstream_waitrequest_from_sa;
  wire             system_0_burst_21_upstream_waits_for_read;
  wire             system_0_burst_21_upstream_waits_for_write;
  wire             system_0_burst_21_upstream_write;
  wire    [  7: 0] system_0_burst_21_upstream_writedata;
  wire             wait_for_system_0_burst_21_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_21_upstream_end_xfer;
    end


  assign system_0_burst_21_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_21_upstream));
  //assign system_0_burst_21_upstream_readdatavalid_from_sa = system_0_burst_21_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_21_upstream_readdatavalid_from_sa = system_0_burst_21_upstream_readdatavalid;

  //assign system_0_burst_21_upstream_readdata_from_sa = system_0_burst_21_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_21_upstream_readdata_from_sa = system_0_burst_21_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_21_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a110) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_21_upstream_waitrequest_from_sa = system_0_burst_21_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_21_upstream_waitrequest_from_sa = system_0_burst_21_upstream_waitrequest;

  //system_0_burst_21_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_21_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_21_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_21_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_21_upstream_non_bursting_master_requests = 0;

  //system_0_burst_21_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_21_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_21_upstream;

  //system_0_burst_21_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_21_upstream_arb_share_counter_next_value = system_0_burst_21_upstream_firsttransfer ? (system_0_burst_21_upstream_arb_share_set_values - 1) : |system_0_burst_21_upstream_arb_share_counter ? (system_0_burst_21_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_21_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_21_upstream_allgrants = |system_0_burst_21_upstream_grant_vector;

  //system_0_burst_21_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_21_upstream_end_xfer = ~(system_0_burst_21_upstream_waits_for_read | system_0_burst_21_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_21_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_21_upstream = system_0_burst_21_upstream_end_xfer & (~system_0_burst_21_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_21_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_21_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_21_upstream & system_0_burst_21_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_21_upstream & ~system_0_burst_21_upstream_non_bursting_master_requests);

  //system_0_burst_21_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_21_upstream_arb_share_counter <= 0;
      else if (system_0_burst_21_upstream_arb_counter_enable)
          system_0_burst_21_upstream_arb_share_counter <= system_0_burst_21_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_21_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_21_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_21_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_21_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_21_upstream & ~system_0_burst_21_upstream_non_bursting_master_requests))
          system_0_burst_21_upstream_slavearbiterlockenable <= |system_0_burst_21_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_21/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_21_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_21_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_21_upstream_slavearbiterlockenable2 = |system_0_burst_21_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_21/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_21_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_21_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_21_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_21_upstream = cpu_0_data_master_requests_system_0_burst_21_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_21_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_21_upstream_move_on_to_next_transaction = system_0_burst_21_upstream_this_cycle_is_the_last_burst & system_0_burst_21_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_21_upstream, which is an e_mux
  assign system_0_burst_21_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_21_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_21_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_21_upstream_module burstcount_fifo_for_system_0_burst_21_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_21_upstream_selected_burstcount),
      .data_out             (system_0_burst_21_upstream_transaction_burst_count),
      .empty                (system_0_burst_21_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_21_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_21_upstream_waits_for_read & system_0_burst_21_upstream_load_fifo & ~(system_0_burst_21_upstream_this_cycle_is_the_last_burst & system_0_burst_21_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_21_upstream current burst minus one, which is an e_assign
  assign system_0_burst_21_upstream_current_burst_minus_one = system_0_burst_21_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_21_upstream, which is an e_mux
  assign system_0_burst_21_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_21_upstream_waits_for_read) & ~system_0_burst_21_upstream_load_fifo))? system_0_burst_21_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_21_upstream_waits_for_read & system_0_burst_21_upstream_this_cycle_is_the_last_burst & system_0_burst_21_upstream_burstcount_fifo_empty))? system_0_burst_21_upstream_selected_burstcount :
    (system_0_burst_21_upstream_this_cycle_is_the_last_burst)? system_0_burst_21_upstream_transaction_burst_count :
    system_0_burst_21_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_21_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_21_upstream_current_burst <= 0;
      else if (system_0_burst_21_upstream_readdatavalid_from_sa | (~system_0_burst_21_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_21_upstream_waits_for_read)))
          system_0_burst_21_upstream_current_burst <= system_0_burst_21_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_21_upstream_load_fifo = (~system_0_burst_21_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_21_upstream_waits_for_read) & system_0_burst_21_upstream_load_fifo))? 1 :
    ~system_0_burst_21_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_21_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_21_upstream_waits_for_read) & ~system_0_burst_21_upstream_load_fifo | system_0_burst_21_upstream_this_cycle_is_the_last_burst)
          system_0_burst_21_upstream_load_fifo <= p0_system_0_burst_21_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_21_upstream, which is an e_assign
  assign system_0_burst_21_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_21_upstream_current_burst_minus_one) & system_0_burst_21_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_21_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_21_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_21_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_21_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_21_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_21_upstream),
      .full                 (),
      .read                 (system_0_burst_21_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_21_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_21_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_21_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_21_upstream = system_0_burst_21_upstream_readdatavalid_from_sa;

  //system_0_burst_21_upstream_writedata mux, which is an e_mux
  assign system_0_burst_21_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_21/upstream, which is an e_mux
  assign system_0_burst_21_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_21_upstream = cpu_0_data_master_qualified_request_system_0_burst_21_upstream;

  //cpu_0/data_master saved-grant system_0_burst_21/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_21_upstream = cpu_0_data_master_requests_system_0_burst_21_upstream;

  //allow new arb cycle for system_0_burst_21/upstream, which is an e_assign
  assign system_0_burst_21_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_21_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_21_upstream_master_qreq_vector = 1;

  //system_0_burst_21_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_21_upstream_firsttransfer = system_0_burst_21_upstream_begins_xfer ? system_0_burst_21_upstream_unreg_firsttransfer : system_0_burst_21_upstream_reg_firsttransfer;

  //system_0_burst_21_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_21_upstream_unreg_firsttransfer = ~(system_0_burst_21_upstream_slavearbiterlockenable & system_0_burst_21_upstream_any_continuerequest);

  //system_0_burst_21_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_21_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_21_upstream_begins_xfer)
          system_0_burst_21_upstream_reg_firsttransfer <= system_0_burst_21_upstream_unreg_firsttransfer;
    end


  //system_0_burst_21_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_21_upstream_next_bbt_burstcount = ((((system_0_burst_21_upstream_write) && (system_0_burst_21_upstream_bbt_burstcounter == 0))))? (system_0_burst_21_upstream_burstcount - 1) :
    ((((system_0_burst_21_upstream_read) && (system_0_burst_21_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_21_upstream_bbt_burstcounter - 1);

  //system_0_burst_21_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_21_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_21_upstream_begins_xfer)
          system_0_burst_21_upstream_bbt_burstcounter <= system_0_burst_21_upstream_next_bbt_burstcount;
    end


  //system_0_burst_21_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_21_upstream_beginbursttransfer_internal = system_0_burst_21_upstream_begins_xfer & (system_0_burst_21_upstream_bbt_burstcounter == 0);

  //system_0_burst_21_upstream_read assignment, which is an e_mux
  assign system_0_burst_21_upstream_read = cpu_0_data_master_granted_system_0_burst_21_upstream & cpu_0_data_master_read;

  //system_0_burst_21_upstream_write assignment, which is an e_mux
  assign system_0_burst_21_upstream_write = cpu_0_data_master_granted_system_0_burst_21_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_21_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_21_upstream_address mux, which is an e_mux
  assign system_0_burst_21_upstream_address = shifted_address_to_system_0_burst_21_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_21_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_21_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_21_upstream_end_xfer <= system_0_burst_21_upstream_end_xfer;
    end


  //system_0_burst_21_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_21_upstream_waits_for_read = system_0_burst_21_upstream_in_a_read_cycle & system_0_burst_21_upstream_waitrequest_from_sa;

  //system_0_burst_21_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_21_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_21_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_21_upstream_in_a_read_cycle;

  //system_0_burst_21_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_21_upstream_waits_for_write = system_0_burst_21_upstream_in_a_write_cycle & system_0_burst_21_upstream_waitrequest_from_sa;

  //system_0_burst_21_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_21_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_21_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_21_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_21_upstream_counter = 0;
  //system_0_burst_21_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_21_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_21_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_21_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_21_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_21_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_21_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_21/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_21_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_21/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_21_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_noteB_s1_end_xfer,
                                                  noteB_s1_readdata_from_sa,
                                                  reset_n,
                                                  system_0_burst_21_downstream_address,
                                                  system_0_burst_21_downstream_burstcount,
                                                  system_0_burst_21_downstream_byteenable,
                                                  system_0_burst_21_downstream_granted_noteB_s1,
                                                  system_0_burst_21_downstream_qualified_request_noteB_s1,
                                                  system_0_burst_21_downstream_read,
                                                  system_0_burst_21_downstream_read_data_valid_noteB_s1,
                                                  system_0_burst_21_downstream_requests_noteB_s1,
                                                  system_0_burst_21_downstream_write,
                                                  system_0_burst_21_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_21_downstream_address_to_slave,
                                                  system_0_burst_21_downstream_latency_counter,
                                                  system_0_burst_21_downstream_readdata,
                                                  system_0_burst_21_downstream_readdatavalid,
                                                  system_0_burst_21_downstream_reset_n,
                                                  system_0_burst_21_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_21_downstream_address_to_slave;
  output           system_0_burst_21_downstream_latency_counter;
  output  [  7: 0] system_0_burst_21_downstream_readdata;
  output           system_0_burst_21_downstream_readdatavalid;
  output           system_0_burst_21_downstream_reset_n;
  output           system_0_burst_21_downstream_waitrequest;
  input            clk;
  input            d1_noteB_s1_end_xfer;
  input            noteB_s1_readdata_from_sa;
  input            reset_n;
  input   [  1: 0] system_0_burst_21_downstream_address;
  input            system_0_burst_21_downstream_burstcount;
  input            system_0_burst_21_downstream_byteenable;
  input            system_0_burst_21_downstream_granted_noteB_s1;
  input            system_0_burst_21_downstream_qualified_request_noteB_s1;
  input            system_0_burst_21_downstream_read;
  input            system_0_burst_21_downstream_read_data_valid_noteB_s1;
  input            system_0_burst_21_downstream_requests_noteB_s1;
  input            system_0_burst_21_downstream_write;
  input   [  7: 0] system_0_burst_21_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_21_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_21_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_21_downstream_address_to_slave;
  reg              system_0_burst_21_downstream_burstcount_last_time;
  reg              system_0_burst_21_downstream_byteenable_last_time;
  wire             system_0_burst_21_downstream_latency_counter;
  reg              system_0_burst_21_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_21_downstream_readdata;
  wire             system_0_burst_21_downstream_readdatavalid;
  wire             system_0_burst_21_downstream_reset_n;
  wire             system_0_burst_21_downstream_run;
  wire             system_0_burst_21_downstream_waitrequest;
  reg              system_0_burst_21_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_21_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_21_downstream_qualified_request_noteB_s1 | ~system_0_burst_21_downstream_requests_noteB_s1) & ((~system_0_burst_21_downstream_qualified_request_noteB_s1 | ~system_0_burst_21_downstream_read | (1 & ~d1_noteB_s1_end_xfer & system_0_burst_21_downstream_read))) & ((~system_0_burst_21_downstream_qualified_request_noteB_s1 | ~system_0_burst_21_downstream_write | (1 & system_0_burst_21_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_21_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_21_downstream_address_to_slave = system_0_burst_21_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_21_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_21_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_21_downstream_readdatavalid |
    system_0_burst_21_downstream_read_data_valid_noteB_s1;

  //system_0_burst_21/downstream readdata mux, which is an e_mux
  assign system_0_burst_21_downstream_readdata = noteB_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_21_downstream_waitrequest = ~system_0_burst_21_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_21_downstream_latency_counter = 0;

  //system_0_burst_21_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_21_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_21_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_21_downstream_address_last_time <= 0;
      else 
        system_0_burst_21_downstream_address_last_time <= system_0_burst_21_downstream_address;
    end


  //system_0_burst_21/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_21_downstream_waitrequest & (system_0_burst_21_downstream_read | system_0_burst_21_downstream_write);
    end


  //system_0_burst_21_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_21_downstream_address != system_0_burst_21_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_21_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_21_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_21_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_21_downstream_burstcount_last_time <= system_0_burst_21_downstream_burstcount;
    end


  //system_0_burst_21_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_21_downstream_burstcount != system_0_burst_21_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_21_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_21_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_21_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_21_downstream_byteenable_last_time <= system_0_burst_21_downstream_byteenable;
    end


  //system_0_burst_21_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_21_downstream_byteenable != system_0_burst_21_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_21_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_21_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_21_downstream_read_last_time <= 0;
      else 
        system_0_burst_21_downstream_read_last_time <= system_0_burst_21_downstream_read;
    end


  //system_0_burst_21_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_21_downstream_read != system_0_burst_21_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_21_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_21_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_21_downstream_write_last_time <= 0;
      else 
        system_0_burst_21_downstream_write_last_time <= system_0_burst_21_downstream_write;
    end


  //system_0_burst_21_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_21_downstream_write != system_0_burst_21_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_21_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_21_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_21_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_21_downstream_writedata_last_time <= system_0_burst_21_downstream_writedata;
    end


  //system_0_burst_21_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_21_downstream_writedata != system_0_burst_21_downstream_writedata_last_time) & system_0_burst_21_downstream_write)
        begin
          $write("%0d ns: system_0_burst_21_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_22_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_22_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_22_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_22_upstream_readdata,
                                                system_0_burst_22_upstream_readdatavalid,
                                                system_0_burst_22_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_22_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_22_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_22_upstream,
                                                d1_system_0_burst_22_upstream_end_xfer,
                                                system_0_burst_22_upstream_address,
                                                system_0_burst_22_upstream_burstcount,
                                                system_0_burst_22_upstream_byteaddress,
                                                system_0_burst_22_upstream_byteenable,
                                                system_0_burst_22_upstream_debugaccess,
                                                system_0_burst_22_upstream_read,
                                                system_0_burst_22_upstream_readdata_from_sa,
                                                system_0_burst_22_upstream_waitrequest_from_sa,
                                                system_0_burst_22_upstream_write,
                                                system_0_burst_22_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_22_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_22_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_22_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_22_upstream;
  output           d1_system_0_burst_22_upstream_end_xfer;
  output  [  1: 0] system_0_burst_22_upstream_address;
  output  [  3: 0] system_0_burst_22_upstream_burstcount;
  output  [  1: 0] system_0_burst_22_upstream_byteaddress;
  output           system_0_burst_22_upstream_byteenable;
  output           system_0_burst_22_upstream_debugaccess;
  output           system_0_burst_22_upstream_read;
  output  [  7: 0] system_0_burst_22_upstream_readdata_from_sa;
  output           system_0_burst_22_upstream_waitrequest_from_sa;
  output           system_0_burst_22_upstream_write;
  output  [  7: 0] system_0_burst_22_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_22_upstream_readdata;
  input            system_0_burst_22_upstream_readdatavalid;
  input            system_0_burst_22_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_22_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_22_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_22_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_22_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_22_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_22_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_22_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_22_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_22_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_22_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_22_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_22_upstream_address;
  wire             system_0_burst_22_upstream_allgrants;
  wire             system_0_burst_22_upstream_allow_new_arb_cycle;
  wire             system_0_burst_22_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_22_upstream_any_continuerequest;
  wire             system_0_burst_22_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_22_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_22_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_22_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_22_upstream_bbt_burstcounter;
  wire             system_0_burst_22_upstream_beginbursttransfer_internal;
  wire             system_0_burst_22_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_22_upstream_burstcount;
  wire             system_0_burst_22_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_22_upstream_byteaddress;
  wire             system_0_burst_22_upstream_byteenable;
  reg     [  3: 0] system_0_burst_22_upstream_current_burst;
  wire    [  3: 0] system_0_burst_22_upstream_current_burst_minus_one;
  wire             system_0_burst_22_upstream_debugaccess;
  wire             system_0_burst_22_upstream_end_xfer;
  wire             system_0_burst_22_upstream_firsttransfer;
  wire             system_0_burst_22_upstream_grant_vector;
  wire             system_0_burst_22_upstream_in_a_read_cycle;
  wire             system_0_burst_22_upstream_in_a_write_cycle;
  reg              system_0_burst_22_upstream_load_fifo;
  wire             system_0_burst_22_upstream_master_qreq_vector;
  wire             system_0_burst_22_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_22_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_22_upstream_next_burst_count;
  wire             system_0_burst_22_upstream_non_bursting_master_requests;
  wire             system_0_burst_22_upstream_read;
  wire    [  7: 0] system_0_burst_22_upstream_readdata_from_sa;
  wire             system_0_burst_22_upstream_readdatavalid_from_sa;
  reg              system_0_burst_22_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_22_upstream_selected_burstcount;
  reg              system_0_burst_22_upstream_slavearbiterlockenable;
  wire             system_0_burst_22_upstream_slavearbiterlockenable2;
  wire             system_0_burst_22_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_22_upstream_transaction_burst_count;
  wire             system_0_burst_22_upstream_unreg_firsttransfer;
  wire             system_0_burst_22_upstream_waitrequest_from_sa;
  wire             system_0_burst_22_upstream_waits_for_read;
  wire             system_0_burst_22_upstream_waits_for_write;
  wire             system_0_burst_22_upstream_write;
  wire    [  7: 0] system_0_burst_22_upstream_writedata;
  wire             wait_for_system_0_burst_22_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_22_upstream_end_xfer;
    end


  assign system_0_burst_22_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_22_upstream));
  //assign system_0_burst_22_upstream_readdatavalid_from_sa = system_0_burst_22_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_22_upstream_readdatavalid_from_sa = system_0_burst_22_upstream_readdatavalid;

  //assign system_0_burst_22_upstream_readdata_from_sa = system_0_burst_22_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_22_upstream_readdata_from_sa = system_0_burst_22_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_22_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a120) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_22_upstream_waitrequest_from_sa = system_0_burst_22_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_22_upstream_waitrequest_from_sa = system_0_burst_22_upstream_waitrequest;

  //system_0_burst_22_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_22_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_22_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_22_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_22_upstream_non_bursting_master_requests = 0;

  //system_0_burst_22_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_22_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_22_upstream;

  //system_0_burst_22_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_22_upstream_arb_share_counter_next_value = system_0_burst_22_upstream_firsttransfer ? (system_0_burst_22_upstream_arb_share_set_values - 1) : |system_0_burst_22_upstream_arb_share_counter ? (system_0_burst_22_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_22_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_22_upstream_allgrants = |system_0_burst_22_upstream_grant_vector;

  //system_0_burst_22_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_22_upstream_end_xfer = ~(system_0_burst_22_upstream_waits_for_read | system_0_burst_22_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_22_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_22_upstream = system_0_burst_22_upstream_end_xfer & (~system_0_burst_22_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_22_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_22_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_22_upstream & system_0_burst_22_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_22_upstream & ~system_0_burst_22_upstream_non_bursting_master_requests);

  //system_0_burst_22_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_22_upstream_arb_share_counter <= 0;
      else if (system_0_burst_22_upstream_arb_counter_enable)
          system_0_burst_22_upstream_arb_share_counter <= system_0_burst_22_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_22_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_22_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_22_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_22_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_22_upstream & ~system_0_burst_22_upstream_non_bursting_master_requests))
          system_0_burst_22_upstream_slavearbiterlockenable <= |system_0_burst_22_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_22/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_22_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_22_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_22_upstream_slavearbiterlockenable2 = |system_0_burst_22_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_22/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_22_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_22_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_22_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_22_upstream = cpu_0_data_master_requests_system_0_burst_22_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_22_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_22_upstream_move_on_to_next_transaction = system_0_burst_22_upstream_this_cycle_is_the_last_burst & system_0_burst_22_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_22_upstream, which is an e_mux
  assign system_0_burst_22_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_22_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_22_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_22_upstream_module burstcount_fifo_for_system_0_burst_22_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_22_upstream_selected_burstcount),
      .data_out             (system_0_burst_22_upstream_transaction_burst_count),
      .empty                (system_0_burst_22_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_22_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_22_upstream_waits_for_read & system_0_burst_22_upstream_load_fifo & ~(system_0_burst_22_upstream_this_cycle_is_the_last_burst & system_0_burst_22_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_22_upstream current burst minus one, which is an e_assign
  assign system_0_burst_22_upstream_current_burst_minus_one = system_0_burst_22_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_22_upstream, which is an e_mux
  assign system_0_burst_22_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_22_upstream_waits_for_read) & ~system_0_burst_22_upstream_load_fifo))? system_0_burst_22_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_22_upstream_waits_for_read & system_0_burst_22_upstream_this_cycle_is_the_last_burst & system_0_burst_22_upstream_burstcount_fifo_empty))? system_0_burst_22_upstream_selected_burstcount :
    (system_0_burst_22_upstream_this_cycle_is_the_last_burst)? system_0_burst_22_upstream_transaction_burst_count :
    system_0_burst_22_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_22_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_22_upstream_current_burst <= 0;
      else if (system_0_burst_22_upstream_readdatavalid_from_sa | (~system_0_burst_22_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_22_upstream_waits_for_read)))
          system_0_burst_22_upstream_current_burst <= system_0_burst_22_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_22_upstream_load_fifo = (~system_0_burst_22_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_22_upstream_waits_for_read) & system_0_burst_22_upstream_load_fifo))? 1 :
    ~system_0_burst_22_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_22_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_22_upstream_waits_for_read) & ~system_0_burst_22_upstream_load_fifo | system_0_burst_22_upstream_this_cycle_is_the_last_burst)
          system_0_burst_22_upstream_load_fifo <= p0_system_0_burst_22_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_22_upstream, which is an e_assign
  assign system_0_burst_22_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_22_upstream_current_burst_minus_one) & system_0_burst_22_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_22_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_22_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_22_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_22_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_22_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_22_upstream),
      .full                 (),
      .read                 (system_0_burst_22_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_22_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_22_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_22_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_22_upstream = system_0_burst_22_upstream_readdatavalid_from_sa;

  //system_0_burst_22_upstream_writedata mux, which is an e_mux
  assign system_0_burst_22_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_22/upstream, which is an e_mux
  assign system_0_burst_22_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_22_upstream = cpu_0_data_master_qualified_request_system_0_burst_22_upstream;

  //cpu_0/data_master saved-grant system_0_burst_22/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_22_upstream = cpu_0_data_master_requests_system_0_burst_22_upstream;

  //allow new arb cycle for system_0_burst_22/upstream, which is an e_assign
  assign system_0_burst_22_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_22_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_22_upstream_master_qreq_vector = 1;

  //system_0_burst_22_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_22_upstream_firsttransfer = system_0_burst_22_upstream_begins_xfer ? system_0_burst_22_upstream_unreg_firsttransfer : system_0_burst_22_upstream_reg_firsttransfer;

  //system_0_burst_22_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_22_upstream_unreg_firsttransfer = ~(system_0_burst_22_upstream_slavearbiterlockenable & system_0_burst_22_upstream_any_continuerequest);

  //system_0_burst_22_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_22_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_22_upstream_begins_xfer)
          system_0_burst_22_upstream_reg_firsttransfer <= system_0_burst_22_upstream_unreg_firsttransfer;
    end


  //system_0_burst_22_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_22_upstream_next_bbt_burstcount = ((((system_0_burst_22_upstream_write) && (system_0_burst_22_upstream_bbt_burstcounter == 0))))? (system_0_burst_22_upstream_burstcount - 1) :
    ((((system_0_burst_22_upstream_read) && (system_0_burst_22_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_22_upstream_bbt_burstcounter - 1);

  //system_0_burst_22_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_22_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_22_upstream_begins_xfer)
          system_0_burst_22_upstream_bbt_burstcounter <= system_0_burst_22_upstream_next_bbt_burstcount;
    end


  //system_0_burst_22_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_22_upstream_beginbursttransfer_internal = system_0_burst_22_upstream_begins_xfer & (system_0_burst_22_upstream_bbt_burstcounter == 0);

  //system_0_burst_22_upstream_read assignment, which is an e_mux
  assign system_0_burst_22_upstream_read = cpu_0_data_master_granted_system_0_burst_22_upstream & cpu_0_data_master_read;

  //system_0_burst_22_upstream_write assignment, which is an e_mux
  assign system_0_burst_22_upstream_write = cpu_0_data_master_granted_system_0_burst_22_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_22_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_22_upstream_address mux, which is an e_mux
  assign system_0_burst_22_upstream_address = shifted_address_to_system_0_burst_22_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_22_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_22_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_22_upstream_end_xfer <= system_0_burst_22_upstream_end_xfer;
    end


  //system_0_burst_22_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_22_upstream_waits_for_read = system_0_burst_22_upstream_in_a_read_cycle & system_0_burst_22_upstream_waitrequest_from_sa;

  //system_0_burst_22_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_22_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_22_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_22_upstream_in_a_read_cycle;

  //system_0_burst_22_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_22_upstream_waits_for_write = system_0_burst_22_upstream_in_a_write_cycle & system_0_burst_22_upstream_waitrequest_from_sa;

  //system_0_burst_22_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_22_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_22_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_22_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_22_upstream_counter = 0;
  //system_0_burst_22_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_22_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_22_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_22_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_22_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_22_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_22_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_22/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_22_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_22/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_22_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_noteC_s1_end_xfer,
                                                  noteC_s1_readdata_from_sa,
                                                  reset_n,
                                                  system_0_burst_22_downstream_address,
                                                  system_0_burst_22_downstream_burstcount,
                                                  system_0_burst_22_downstream_byteenable,
                                                  system_0_burst_22_downstream_granted_noteC_s1,
                                                  system_0_burst_22_downstream_qualified_request_noteC_s1,
                                                  system_0_burst_22_downstream_read,
                                                  system_0_burst_22_downstream_read_data_valid_noteC_s1,
                                                  system_0_burst_22_downstream_requests_noteC_s1,
                                                  system_0_burst_22_downstream_write,
                                                  system_0_burst_22_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_22_downstream_address_to_slave,
                                                  system_0_burst_22_downstream_latency_counter,
                                                  system_0_burst_22_downstream_readdata,
                                                  system_0_burst_22_downstream_readdatavalid,
                                                  system_0_burst_22_downstream_reset_n,
                                                  system_0_burst_22_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_22_downstream_address_to_slave;
  output           system_0_burst_22_downstream_latency_counter;
  output  [  7: 0] system_0_burst_22_downstream_readdata;
  output           system_0_burst_22_downstream_readdatavalid;
  output           system_0_burst_22_downstream_reset_n;
  output           system_0_burst_22_downstream_waitrequest;
  input            clk;
  input            d1_noteC_s1_end_xfer;
  input            noteC_s1_readdata_from_sa;
  input            reset_n;
  input   [  1: 0] system_0_burst_22_downstream_address;
  input            system_0_burst_22_downstream_burstcount;
  input            system_0_burst_22_downstream_byteenable;
  input            system_0_burst_22_downstream_granted_noteC_s1;
  input            system_0_burst_22_downstream_qualified_request_noteC_s1;
  input            system_0_burst_22_downstream_read;
  input            system_0_burst_22_downstream_read_data_valid_noteC_s1;
  input            system_0_burst_22_downstream_requests_noteC_s1;
  input            system_0_burst_22_downstream_write;
  input   [  7: 0] system_0_burst_22_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_22_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_22_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_22_downstream_address_to_slave;
  reg              system_0_burst_22_downstream_burstcount_last_time;
  reg              system_0_burst_22_downstream_byteenable_last_time;
  wire             system_0_burst_22_downstream_latency_counter;
  reg              system_0_burst_22_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_22_downstream_readdata;
  wire             system_0_burst_22_downstream_readdatavalid;
  wire             system_0_burst_22_downstream_reset_n;
  wire             system_0_burst_22_downstream_run;
  wire             system_0_burst_22_downstream_waitrequest;
  reg              system_0_burst_22_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_22_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_22_downstream_qualified_request_noteC_s1 | ~system_0_burst_22_downstream_requests_noteC_s1) & ((~system_0_burst_22_downstream_qualified_request_noteC_s1 | ~system_0_burst_22_downstream_read | (1 & ~d1_noteC_s1_end_xfer & system_0_burst_22_downstream_read))) & ((~system_0_burst_22_downstream_qualified_request_noteC_s1 | ~system_0_burst_22_downstream_write | (1 & system_0_burst_22_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_22_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_22_downstream_address_to_slave = system_0_burst_22_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_22_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_22_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_22_downstream_readdatavalid |
    system_0_burst_22_downstream_read_data_valid_noteC_s1;

  //system_0_burst_22/downstream readdata mux, which is an e_mux
  assign system_0_burst_22_downstream_readdata = noteC_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_22_downstream_waitrequest = ~system_0_burst_22_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_22_downstream_latency_counter = 0;

  //system_0_burst_22_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_22_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_22_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_22_downstream_address_last_time <= 0;
      else 
        system_0_burst_22_downstream_address_last_time <= system_0_burst_22_downstream_address;
    end


  //system_0_burst_22/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_22_downstream_waitrequest & (system_0_burst_22_downstream_read | system_0_burst_22_downstream_write);
    end


  //system_0_burst_22_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_22_downstream_address != system_0_burst_22_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_22_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_22_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_22_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_22_downstream_burstcount_last_time <= system_0_burst_22_downstream_burstcount;
    end


  //system_0_burst_22_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_22_downstream_burstcount != system_0_burst_22_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_22_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_22_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_22_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_22_downstream_byteenable_last_time <= system_0_burst_22_downstream_byteenable;
    end


  //system_0_burst_22_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_22_downstream_byteenable != system_0_burst_22_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_22_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_22_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_22_downstream_read_last_time <= 0;
      else 
        system_0_burst_22_downstream_read_last_time <= system_0_burst_22_downstream_read;
    end


  //system_0_burst_22_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_22_downstream_read != system_0_burst_22_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_22_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_22_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_22_downstream_write_last_time <= 0;
      else 
        system_0_burst_22_downstream_write_last_time <= system_0_burst_22_downstream_write;
    end


  //system_0_burst_22_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_22_downstream_write != system_0_burst_22_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_22_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_22_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_22_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_22_downstream_writedata_last_time <= system_0_burst_22_downstream_writedata;
    end


  //system_0_burst_22_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_22_downstream_writedata != system_0_burst_22_downstream_writedata_last_time) & system_0_burst_22_downstream_write)
        begin
          $write("%0d ns: system_0_burst_22_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_23_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_23_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_23_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_23_upstream_readdata,
                                                system_0_burst_23_upstream_readdatavalid,
                                                system_0_burst_23_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_23_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_23_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_23_upstream,
                                                d1_system_0_burst_23_upstream_end_xfer,
                                                system_0_burst_23_upstream_address,
                                                system_0_burst_23_upstream_burstcount,
                                                system_0_burst_23_upstream_byteaddress,
                                                system_0_burst_23_upstream_byteenable,
                                                system_0_burst_23_upstream_debugaccess,
                                                system_0_burst_23_upstream_read,
                                                system_0_burst_23_upstream_readdata_from_sa,
                                                system_0_burst_23_upstream_waitrequest_from_sa,
                                                system_0_burst_23_upstream_write,
                                                system_0_burst_23_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_23_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_23_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_23_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_23_upstream;
  output           d1_system_0_burst_23_upstream_end_xfer;
  output  [  1: 0] system_0_burst_23_upstream_address;
  output  [  3: 0] system_0_burst_23_upstream_burstcount;
  output  [  1: 0] system_0_burst_23_upstream_byteaddress;
  output           system_0_burst_23_upstream_byteenable;
  output           system_0_burst_23_upstream_debugaccess;
  output           system_0_burst_23_upstream_read;
  output  [  7: 0] system_0_burst_23_upstream_readdata_from_sa;
  output           system_0_burst_23_upstream_waitrequest_from_sa;
  output           system_0_burst_23_upstream_write;
  output  [  7: 0] system_0_burst_23_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_23_upstream_readdata;
  input            system_0_burst_23_upstream_readdatavalid;
  input            system_0_burst_23_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_23_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_23_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_23_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_23_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_23_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_23_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_23_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_23_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_23_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_23_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_23_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_23_upstream_address;
  wire             system_0_burst_23_upstream_allgrants;
  wire             system_0_burst_23_upstream_allow_new_arb_cycle;
  wire             system_0_burst_23_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_23_upstream_any_continuerequest;
  wire             system_0_burst_23_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_23_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_23_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_23_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_23_upstream_bbt_burstcounter;
  wire             system_0_burst_23_upstream_beginbursttransfer_internal;
  wire             system_0_burst_23_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_23_upstream_burstcount;
  wire             system_0_burst_23_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_23_upstream_byteaddress;
  wire             system_0_burst_23_upstream_byteenable;
  reg     [  3: 0] system_0_burst_23_upstream_current_burst;
  wire    [  3: 0] system_0_burst_23_upstream_current_burst_minus_one;
  wire             system_0_burst_23_upstream_debugaccess;
  wire             system_0_burst_23_upstream_end_xfer;
  wire             system_0_burst_23_upstream_firsttransfer;
  wire             system_0_burst_23_upstream_grant_vector;
  wire             system_0_burst_23_upstream_in_a_read_cycle;
  wire             system_0_burst_23_upstream_in_a_write_cycle;
  reg              system_0_burst_23_upstream_load_fifo;
  wire             system_0_burst_23_upstream_master_qreq_vector;
  wire             system_0_burst_23_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_23_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_23_upstream_next_burst_count;
  wire             system_0_burst_23_upstream_non_bursting_master_requests;
  wire             system_0_burst_23_upstream_read;
  wire    [  7: 0] system_0_burst_23_upstream_readdata_from_sa;
  wire             system_0_burst_23_upstream_readdatavalid_from_sa;
  reg              system_0_burst_23_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_23_upstream_selected_burstcount;
  reg              system_0_burst_23_upstream_slavearbiterlockenable;
  wire             system_0_burst_23_upstream_slavearbiterlockenable2;
  wire             system_0_burst_23_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_23_upstream_transaction_burst_count;
  wire             system_0_burst_23_upstream_unreg_firsttransfer;
  wire             system_0_burst_23_upstream_waitrequest_from_sa;
  wire             system_0_burst_23_upstream_waits_for_read;
  wire             system_0_burst_23_upstream_waits_for_write;
  wire             system_0_burst_23_upstream_write;
  wire    [  7: 0] system_0_burst_23_upstream_writedata;
  wire             wait_for_system_0_burst_23_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_23_upstream_end_xfer;
    end


  assign system_0_burst_23_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_23_upstream));
  //assign system_0_burst_23_upstream_readdatavalid_from_sa = system_0_burst_23_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_23_upstream_readdatavalid_from_sa = system_0_burst_23_upstream_readdatavalid;

  //assign system_0_burst_23_upstream_readdata_from_sa = system_0_burst_23_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_23_upstream_readdata_from_sa = system_0_burst_23_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_23_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a130) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_23_upstream_waitrequest_from_sa = system_0_burst_23_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_23_upstream_waitrequest_from_sa = system_0_burst_23_upstream_waitrequest;

  //system_0_burst_23_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_23_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_23_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_23_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_23_upstream_non_bursting_master_requests = 0;

  //system_0_burst_23_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_23_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_23_upstream;

  //system_0_burst_23_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_23_upstream_arb_share_counter_next_value = system_0_burst_23_upstream_firsttransfer ? (system_0_burst_23_upstream_arb_share_set_values - 1) : |system_0_burst_23_upstream_arb_share_counter ? (system_0_burst_23_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_23_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_23_upstream_allgrants = |system_0_burst_23_upstream_grant_vector;

  //system_0_burst_23_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_23_upstream_end_xfer = ~(system_0_burst_23_upstream_waits_for_read | system_0_burst_23_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_23_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_23_upstream = system_0_burst_23_upstream_end_xfer & (~system_0_burst_23_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_23_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_23_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_23_upstream & system_0_burst_23_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_23_upstream & ~system_0_burst_23_upstream_non_bursting_master_requests);

  //system_0_burst_23_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_23_upstream_arb_share_counter <= 0;
      else if (system_0_burst_23_upstream_arb_counter_enable)
          system_0_burst_23_upstream_arb_share_counter <= system_0_burst_23_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_23_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_23_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_23_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_23_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_23_upstream & ~system_0_burst_23_upstream_non_bursting_master_requests))
          system_0_burst_23_upstream_slavearbiterlockenable <= |system_0_burst_23_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_23/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_23_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_23_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_23_upstream_slavearbiterlockenable2 = |system_0_burst_23_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_23/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_23_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_23_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_23_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_23_upstream = cpu_0_data_master_requests_system_0_burst_23_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_23_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_23_upstream_move_on_to_next_transaction = system_0_burst_23_upstream_this_cycle_is_the_last_burst & system_0_burst_23_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_23_upstream, which is an e_mux
  assign system_0_burst_23_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_23_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_23_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_23_upstream_module burstcount_fifo_for_system_0_burst_23_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_23_upstream_selected_burstcount),
      .data_out             (system_0_burst_23_upstream_transaction_burst_count),
      .empty                (system_0_burst_23_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_23_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_23_upstream_waits_for_read & system_0_burst_23_upstream_load_fifo & ~(system_0_burst_23_upstream_this_cycle_is_the_last_burst & system_0_burst_23_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_23_upstream current burst minus one, which is an e_assign
  assign system_0_burst_23_upstream_current_burst_minus_one = system_0_burst_23_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_23_upstream, which is an e_mux
  assign system_0_burst_23_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_23_upstream_waits_for_read) & ~system_0_burst_23_upstream_load_fifo))? system_0_burst_23_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_23_upstream_waits_for_read & system_0_burst_23_upstream_this_cycle_is_the_last_burst & system_0_burst_23_upstream_burstcount_fifo_empty))? system_0_burst_23_upstream_selected_burstcount :
    (system_0_burst_23_upstream_this_cycle_is_the_last_burst)? system_0_burst_23_upstream_transaction_burst_count :
    system_0_burst_23_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_23_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_23_upstream_current_burst <= 0;
      else if (system_0_burst_23_upstream_readdatavalid_from_sa | (~system_0_burst_23_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_23_upstream_waits_for_read)))
          system_0_burst_23_upstream_current_burst <= system_0_burst_23_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_23_upstream_load_fifo = (~system_0_burst_23_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_23_upstream_waits_for_read) & system_0_burst_23_upstream_load_fifo))? 1 :
    ~system_0_burst_23_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_23_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_23_upstream_waits_for_read) & ~system_0_burst_23_upstream_load_fifo | system_0_burst_23_upstream_this_cycle_is_the_last_burst)
          system_0_burst_23_upstream_load_fifo <= p0_system_0_burst_23_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_23_upstream, which is an e_assign
  assign system_0_burst_23_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_23_upstream_current_burst_minus_one) & system_0_burst_23_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_23_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_23_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_23_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_23_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_23_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_23_upstream),
      .full                 (),
      .read                 (system_0_burst_23_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_23_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_23_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_23_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_23_upstream = system_0_burst_23_upstream_readdatavalid_from_sa;

  //system_0_burst_23_upstream_writedata mux, which is an e_mux
  assign system_0_burst_23_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_23/upstream, which is an e_mux
  assign system_0_burst_23_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_23_upstream = cpu_0_data_master_qualified_request_system_0_burst_23_upstream;

  //cpu_0/data_master saved-grant system_0_burst_23/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_23_upstream = cpu_0_data_master_requests_system_0_burst_23_upstream;

  //allow new arb cycle for system_0_burst_23/upstream, which is an e_assign
  assign system_0_burst_23_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_23_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_23_upstream_master_qreq_vector = 1;

  //system_0_burst_23_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_23_upstream_firsttransfer = system_0_burst_23_upstream_begins_xfer ? system_0_burst_23_upstream_unreg_firsttransfer : system_0_burst_23_upstream_reg_firsttransfer;

  //system_0_burst_23_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_23_upstream_unreg_firsttransfer = ~(system_0_burst_23_upstream_slavearbiterlockenable & system_0_burst_23_upstream_any_continuerequest);

  //system_0_burst_23_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_23_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_23_upstream_begins_xfer)
          system_0_burst_23_upstream_reg_firsttransfer <= system_0_burst_23_upstream_unreg_firsttransfer;
    end


  //system_0_burst_23_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_23_upstream_next_bbt_burstcount = ((((system_0_burst_23_upstream_write) && (system_0_burst_23_upstream_bbt_burstcounter == 0))))? (system_0_burst_23_upstream_burstcount - 1) :
    ((((system_0_burst_23_upstream_read) && (system_0_burst_23_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_23_upstream_bbt_burstcounter - 1);

  //system_0_burst_23_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_23_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_23_upstream_begins_xfer)
          system_0_burst_23_upstream_bbt_burstcounter <= system_0_burst_23_upstream_next_bbt_burstcount;
    end


  //system_0_burst_23_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_23_upstream_beginbursttransfer_internal = system_0_burst_23_upstream_begins_xfer & (system_0_burst_23_upstream_bbt_burstcounter == 0);

  //system_0_burst_23_upstream_read assignment, which is an e_mux
  assign system_0_burst_23_upstream_read = cpu_0_data_master_granted_system_0_burst_23_upstream & cpu_0_data_master_read;

  //system_0_burst_23_upstream_write assignment, which is an e_mux
  assign system_0_burst_23_upstream_write = cpu_0_data_master_granted_system_0_burst_23_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_23_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_23_upstream_address mux, which is an e_mux
  assign system_0_burst_23_upstream_address = shifted_address_to_system_0_burst_23_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_23_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_23_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_23_upstream_end_xfer <= system_0_burst_23_upstream_end_xfer;
    end


  //system_0_burst_23_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_23_upstream_waits_for_read = system_0_burst_23_upstream_in_a_read_cycle & system_0_burst_23_upstream_waitrequest_from_sa;

  //system_0_burst_23_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_23_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_23_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_23_upstream_in_a_read_cycle;

  //system_0_burst_23_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_23_upstream_waits_for_write = system_0_burst_23_upstream_in_a_write_cycle & system_0_burst_23_upstream_waitrequest_from_sa;

  //system_0_burst_23_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_23_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_23_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_23_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_23_upstream_counter = 0;
  //system_0_burst_23_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_23_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_23_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_23_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_23_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_23_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_23_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_23/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_23_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_23/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_23_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_noteD_s1_end_xfer,
                                                  noteD_s1_readdata_from_sa,
                                                  reset_n,
                                                  system_0_burst_23_downstream_address,
                                                  system_0_burst_23_downstream_burstcount,
                                                  system_0_burst_23_downstream_byteenable,
                                                  system_0_burst_23_downstream_granted_noteD_s1,
                                                  system_0_burst_23_downstream_qualified_request_noteD_s1,
                                                  system_0_burst_23_downstream_read,
                                                  system_0_burst_23_downstream_read_data_valid_noteD_s1,
                                                  system_0_burst_23_downstream_requests_noteD_s1,
                                                  system_0_burst_23_downstream_write,
                                                  system_0_burst_23_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_23_downstream_address_to_slave,
                                                  system_0_burst_23_downstream_latency_counter,
                                                  system_0_burst_23_downstream_readdata,
                                                  system_0_burst_23_downstream_readdatavalid,
                                                  system_0_burst_23_downstream_reset_n,
                                                  system_0_burst_23_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_23_downstream_address_to_slave;
  output           system_0_burst_23_downstream_latency_counter;
  output  [  7: 0] system_0_burst_23_downstream_readdata;
  output           system_0_burst_23_downstream_readdatavalid;
  output           system_0_burst_23_downstream_reset_n;
  output           system_0_burst_23_downstream_waitrequest;
  input            clk;
  input            d1_noteD_s1_end_xfer;
  input            noteD_s1_readdata_from_sa;
  input            reset_n;
  input   [  1: 0] system_0_burst_23_downstream_address;
  input            system_0_burst_23_downstream_burstcount;
  input            system_0_burst_23_downstream_byteenable;
  input            system_0_burst_23_downstream_granted_noteD_s1;
  input            system_0_burst_23_downstream_qualified_request_noteD_s1;
  input            system_0_burst_23_downstream_read;
  input            system_0_burst_23_downstream_read_data_valid_noteD_s1;
  input            system_0_burst_23_downstream_requests_noteD_s1;
  input            system_0_burst_23_downstream_write;
  input   [  7: 0] system_0_burst_23_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_23_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_23_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_23_downstream_address_to_slave;
  reg              system_0_burst_23_downstream_burstcount_last_time;
  reg              system_0_burst_23_downstream_byteenable_last_time;
  wire             system_0_burst_23_downstream_latency_counter;
  reg              system_0_burst_23_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_23_downstream_readdata;
  wire             system_0_burst_23_downstream_readdatavalid;
  wire             system_0_burst_23_downstream_reset_n;
  wire             system_0_burst_23_downstream_run;
  wire             system_0_burst_23_downstream_waitrequest;
  reg              system_0_burst_23_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_23_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_23_downstream_qualified_request_noteD_s1 | ~system_0_burst_23_downstream_requests_noteD_s1) & ((~system_0_burst_23_downstream_qualified_request_noteD_s1 | ~system_0_burst_23_downstream_read | (1 & ~d1_noteD_s1_end_xfer & system_0_burst_23_downstream_read))) & ((~system_0_burst_23_downstream_qualified_request_noteD_s1 | ~system_0_burst_23_downstream_write | (1 & system_0_burst_23_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_23_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_23_downstream_address_to_slave = system_0_burst_23_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_23_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_23_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_23_downstream_readdatavalid |
    system_0_burst_23_downstream_read_data_valid_noteD_s1;

  //system_0_burst_23/downstream readdata mux, which is an e_mux
  assign system_0_burst_23_downstream_readdata = noteD_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_23_downstream_waitrequest = ~system_0_burst_23_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_23_downstream_latency_counter = 0;

  //system_0_burst_23_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_23_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_23_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_23_downstream_address_last_time <= 0;
      else 
        system_0_burst_23_downstream_address_last_time <= system_0_burst_23_downstream_address;
    end


  //system_0_burst_23/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_23_downstream_waitrequest & (system_0_burst_23_downstream_read | system_0_burst_23_downstream_write);
    end


  //system_0_burst_23_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_23_downstream_address != system_0_burst_23_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_23_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_23_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_23_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_23_downstream_burstcount_last_time <= system_0_burst_23_downstream_burstcount;
    end


  //system_0_burst_23_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_23_downstream_burstcount != system_0_burst_23_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_23_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_23_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_23_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_23_downstream_byteenable_last_time <= system_0_burst_23_downstream_byteenable;
    end


  //system_0_burst_23_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_23_downstream_byteenable != system_0_burst_23_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_23_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_23_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_23_downstream_read_last_time <= 0;
      else 
        system_0_burst_23_downstream_read_last_time <= system_0_burst_23_downstream_read;
    end


  //system_0_burst_23_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_23_downstream_read != system_0_burst_23_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_23_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_23_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_23_downstream_write_last_time <= 0;
      else 
        system_0_burst_23_downstream_write_last_time <= system_0_burst_23_downstream_write;
    end


  //system_0_burst_23_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_23_downstream_write != system_0_burst_23_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_23_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_23_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_23_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_23_downstream_writedata_last_time <= system_0_burst_23_downstream_writedata;
    end


  //system_0_burst_23_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_23_downstream_writedata != system_0_burst_23_downstream_writedata_last_time) & system_0_burst_23_downstream_write)
        begin
          $write("%0d ns: system_0_burst_23_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_24_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_24_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_24_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_24_upstream_readdata,
                                                system_0_burst_24_upstream_readdatavalid,
                                                system_0_burst_24_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_24_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_24_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_24_upstream,
                                                d1_system_0_burst_24_upstream_end_xfer,
                                                system_0_burst_24_upstream_address,
                                                system_0_burst_24_upstream_burstcount,
                                                system_0_burst_24_upstream_byteaddress,
                                                system_0_burst_24_upstream_byteenable,
                                                system_0_burst_24_upstream_debugaccess,
                                                system_0_burst_24_upstream_read,
                                                system_0_burst_24_upstream_readdata_from_sa,
                                                system_0_burst_24_upstream_waitrequest_from_sa,
                                                system_0_burst_24_upstream_write,
                                                system_0_burst_24_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_24_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_24_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_24_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_24_upstream;
  output           d1_system_0_burst_24_upstream_end_xfer;
  output  [  1: 0] system_0_burst_24_upstream_address;
  output  [  3: 0] system_0_burst_24_upstream_burstcount;
  output  [  1: 0] system_0_burst_24_upstream_byteaddress;
  output           system_0_burst_24_upstream_byteenable;
  output           system_0_burst_24_upstream_debugaccess;
  output           system_0_burst_24_upstream_read;
  output  [  7: 0] system_0_burst_24_upstream_readdata_from_sa;
  output           system_0_burst_24_upstream_waitrequest_from_sa;
  output           system_0_burst_24_upstream_write;
  output  [  7: 0] system_0_burst_24_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_24_upstream_readdata;
  input            system_0_burst_24_upstream_readdatavalid;
  input            system_0_burst_24_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_24_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_24_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_24_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_24_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_24_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_24_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_24_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_24_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_24_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_24_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_24_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_24_upstream_address;
  wire             system_0_burst_24_upstream_allgrants;
  wire             system_0_burst_24_upstream_allow_new_arb_cycle;
  wire             system_0_burst_24_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_24_upstream_any_continuerequest;
  wire             system_0_burst_24_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_24_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_24_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_24_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_24_upstream_bbt_burstcounter;
  wire             system_0_burst_24_upstream_beginbursttransfer_internal;
  wire             system_0_burst_24_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_24_upstream_burstcount;
  wire             system_0_burst_24_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_24_upstream_byteaddress;
  wire             system_0_burst_24_upstream_byteenable;
  reg     [  3: 0] system_0_burst_24_upstream_current_burst;
  wire    [  3: 0] system_0_burst_24_upstream_current_burst_minus_one;
  wire             system_0_burst_24_upstream_debugaccess;
  wire             system_0_burst_24_upstream_end_xfer;
  wire             system_0_burst_24_upstream_firsttransfer;
  wire             system_0_burst_24_upstream_grant_vector;
  wire             system_0_burst_24_upstream_in_a_read_cycle;
  wire             system_0_burst_24_upstream_in_a_write_cycle;
  reg              system_0_burst_24_upstream_load_fifo;
  wire             system_0_burst_24_upstream_master_qreq_vector;
  wire             system_0_burst_24_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_24_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_24_upstream_next_burst_count;
  wire             system_0_burst_24_upstream_non_bursting_master_requests;
  wire             system_0_burst_24_upstream_read;
  wire    [  7: 0] system_0_burst_24_upstream_readdata_from_sa;
  wire             system_0_burst_24_upstream_readdatavalid_from_sa;
  reg              system_0_burst_24_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_24_upstream_selected_burstcount;
  reg              system_0_burst_24_upstream_slavearbiterlockenable;
  wire             system_0_burst_24_upstream_slavearbiterlockenable2;
  wire             system_0_burst_24_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_24_upstream_transaction_burst_count;
  wire             system_0_burst_24_upstream_unreg_firsttransfer;
  wire             system_0_burst_24_upstream_waitrequest_from_sa;
  wire             system_0_burst_24_upstream_waits_for_read;
  wire             system_0_burst_24_upstream_waits_for_write;
  wire             system_0_burst_24_upstream_write;
  wire    [  7: 0] system_0_burst_24_upstream_writedata;
  wire             wait_for_system_0_burst_24_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_24_upstream_end_xfer;
    end


  assign system_0_burst_24_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_24_upstream));
  //assign system_0_burst_24_upstream_readdatavalid_from_sa = system_0_burst_24_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_24_upstream_readdatavalid_from_sa = system_0_burst_24_upstream_readdatavalid;

  //assign system_0_burst_24_upstream_readdata_from_sa = system_0_burst_24_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_24_upstream_readdata_from_sa = system_0_burst_24_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_24_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a140) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_24_upstream_waitrequest_from_sa = system_0_burst_24_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_24_upstream_waitrequest_from_sa = system_0_burst_24_upstream_waitrequest;

  //system_0_burst_24_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_24_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_24_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_24_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_24_upstream_non_bursting_master_requests = 0;

  //system_0_burst_24_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_24_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_24_upstream;

  //system_0_burst_24_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_24_upstream_arb_share_counter_next_value = system_0_burst_24_upstream_firsttransfer ? (system_0_burst_24_upstream_arb_share_set_values - 1) : |system_0_burst_24_upstream_arb_share_counter ? (system_0_burst_24_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_24_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_24_upstream_allgrants = |system_0_burst_24_upstream_grant_vector;

  //system_0_burst_24_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_24_upstream_end_xfer = ~(system_0_burst_24_upstream_waits_for_read | system_0_burst_24_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_24_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_24_upstream = system_0_burst_24_upstream_end_xfer & (~system_0_burst_24_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_24_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_24_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_24_upstream & system_0_burst_24_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_24_upstream & ~system_0_burst_24_upstream_non_bursting_master_requests);

  //system_0_burst_24_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_24_upstream_arb_share_counter <= 0;
      else if (system_0_burst_24_upstream_arb_counter_enable)
          system_0_burst_24_upstream_arb_share_counter <= system_0_burst_24_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_24_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_24_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_24_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_24_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_24_upstream & ~system_0_burst_24_upstream_non_bursting_master_requests))
          system_0_burst_24_upstream_slavearbiterlockenable <= |system_0_burst_24_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_24/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_24_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_24_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_24_upstream_slavearbiterlockenable2 = |system_0_burst_24_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_24/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_24_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_24_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_24_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_24_upstream = cpu_0_data_master_requests_system_0_burst_24_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_24_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_24_upstream_move_on_to_next_transaction = system_0_burst_24_upstream_this_cycle_is_the_last_burst & system_0_burst_24_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_24_upstream, which is an e_mux
  assign system_0_burst_24_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_24_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_24_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_24_upstream_module burstcount_fifo_for_system_0_burst_24_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_24_upstream_selected_burstcount),
      .data_out             (system_0_burst_24_upstream_transaction_burst_count),
      .empty                (system_0_burst_24_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_24_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_24_upstream_waits_for_read & system_0_burst_24_upstream_load_fifo & ~(system_0_burst_24_upstream_this_cycle_is_the_last_burst & system_0_burst_24_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_24_upstream current burst minus one, which is an e_assign
  assign system_0_burst_24_upstream_current_burst_minus_one = system_0_burst_24_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_24_upstream, which is an e_mux
  assign system_0_burst_24_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_24_upstream_waits_for_read) & ~system_0_burst_24_upstream_load_fifo))? system_0_burst_24_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_24_upstream_waits_for_read & system_0_burst_24_upstream_this_cycle_is_the_last_burst & system_0_burst_24_upstream_burstcount_fifo_empty))? system_0_burst_24_upstream_selected_burstcount :
    (system_0_burst_24_upstream_this_cycle_is_the_last_burst)? system_0_burst_24_upstream_transaction_burst_count :
    system_0_burst_24_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_24_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_24_upstream_current_burst <= 0;
      else if (system_0_burst_24_upstream_readdatavalid_from_sa | (~system_0_burst_24_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_24_upstream_waits_for_read)))
          system_0_burst_24_upstream_current_burst <= system_0_burst_24_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_24_upstream_load_fifo = (~system_0_burst_24_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_24_upstream_waits_for_read) & system_0_burst_24_upstream_load_fifo))? 1 :
    ~system_0_burst_24_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_24_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_24_upstream_waits_for_read) & ~system_0_burst_24_upstream_load_fifo | system_0_burst_24_upstream_this_cycle_is_the_last_burst)
          system_0_burst_24_upstream_load_fifo <= p0_system_0_burst_24_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_24_upstream, which is an e_assign
  assign system_0_burst_24_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_24_upstream_current_burst_minus_one) & system_0_burst_24_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_24_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_24_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_24_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_24_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_24_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_24_upstream),
      .full                 (),
      .read                 (system_0_burst_24_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_24_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_24_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_24_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_24_upstream = system_0_burst_24_upstream_readdatavalid_from_sa;

  //system_0_burst_24_upstream_writedata mux, which is an e_mux
  assign system_0_burst_24_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_24/upstream, which is an e_mux
  assign system_0_burst_24_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_24_upstream = cpu_0_data_master_qualified_request_system_0_burst_24_upstream;

  //cpu_0/data_master saved-grant system_0_burst_24/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_24_upstream = cpu_0_data_master_requests_system_0_burst_24_upstream;

  //allow new arb cycle for system_0_burst_24/upstream, which is an e_assign
  assign system_0_burst_24_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_24_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_24_upstream_master_qreq_vector = 1;

  //system_0_burst_24_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_24_upstream_firsttransfer = system_0_burst_24_upstream_begins_xfer ? system_0_burst_24_upstream_unreg_firsttransfer : system_0_burst_24_upstream_reg_firsttransfer;

  //system_0_burst_24_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_24_upstream_unreg_firsttransfer = ~(system_0_burst_24_upstream_slavearbiterlockenable & system_0_burst_24_upstream_any_continuerequest);

  //system_0_burst_24_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_24_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_24_upstream_begins_xfer)
          system_0_burst_24_upstream_reg_firsttransfer <= system_0_burst_24_upstream_unreg_firsttransfer;
    end


  //system_0_burst_24_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_24_upstream_next_bbt_burstcount = ((((system_0_burst_24_upstream_write) && (system_0_burst_24_upstream_bbt_burstcounter == 0))))? (system_0_burst_24_upstream_burstcount - 1) :
    ((((system_0_burst_24_upstream_read) && (system_0_burst_24_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_24_upstream_bbt_burstcounter - 1);

  //system_0_burst_24_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_24_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_24_upstream_begins_xfer)
          system_0_burst_24_upstream_bbt_burstcounter <= system_0_burst_24_upstream_next_bbt_burstcount;
    end


  //system_0_burst_24_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_24_upstream_beginbursttransfer_internal = system_0_burst_24_upstream_begins_xfer & (system_0_burst_24_upstream_bbt_burstcounter == 0);

  //system_0_burst_24_upstream_read assignment, which is an e_mux
  assign system_0_burst_24_upstream_read = cpu_0_data_master_granted_system_0_burst_24_upstream & cpu_0_data_master_read;

  //system_0_burst_24_upstream_write assignment, which is an e_mux
  assign system_0_burst_24_upstream_write = cpu_0_data_master_granted_system_0_burst_24_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_24_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_24_upstream_address mux, which is an e_mux
  assign system_0_burst_24_upstream_address = shifted_address_to_system_0_burst_24_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_24_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_24_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_24_upstream_end_xfer <= system_0_burst_24_upstream_end_xfer;
    end


  //system_0_burst_24_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_24_upstream_waits_for_read = system_0_burst_24_upstream_in_a_read_cycle & system_0_burst_24_upstream_waitrequest_from_sa;

  //system_0_burst_24_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_24_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_24_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_24_upstream_in_a_read_cycle;

  //system_0_burst_24_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_24_upstream_waits_for_write = system_0_burst_24_upstream_in_a_write_cycle & system_0_burst_24_upstream_waitrequest_from_sa;

  //system_0_burst_24_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_24_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_24_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_24_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_24_upstream_counter = 0;
  //system_0_burst_24_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_24_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_24_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_24_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_24_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_24_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_24_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_24/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_24_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_24/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_24_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_noteE_s1_end_xfer,
                                                  noteE_s1_readdata_from_sa,
                                                  reset_n,
                                                  system_0_burst_24_downstream_address,
                                                  system_0_burst_24_downstream_burstcount,
                                                  system_0_burst_24_downstream_byteenable,
                                                  system_0_burst_24_downstream_granted_noteE_s1,
                                                  system_0_burst_24_downstream_qualified_request_noteE_s1,
                                                  system_0_burst_24_downstream_read,
                                                  system_0_burst_24_downstream_read_data_valid_noteE_s1,
                                                  system_0_burst_24_downstream_requests_noteE_s1,
                                                  system_0_burst_24_downstream_write,
                                                  system_0_burst_24_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_24_downstream_address_to_slave,
                                                  system_0_burst_24_downstream_latency_counter,
                                                  system_0_burst_24_downstream_readdata,
                                                  system_0_burst_24_downstream_readdatavalid,
                                                  system_0_burst_24_downstream_reset_n,
                                                  system_0_burst_24_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_24_downstream_address_to_slave;
  output           system_0_burst_24_downstream_latency_counter;
  output  [  7: 0] system_0_burst_24_downstream_readdata;
  output           system_0_burst_24_downstream_readdatavalid;
  output           system_0_burst_24_downstream_reset_n;
  output           system_0_burst_24_downstream_waitrequest;
  input            clk;
  input            d1_noteE_s1_end_xfer;
  input            noteE_s1_readdata_from_sa;
  input            reset_n;
  input   [  1: 0] system_0_burst_24_downstream_address;
  input            system_0_burst_24_downstream_burstcount;
  input            system_0_burst_24_downstream_byteenable;
  input            system_0_burst_24_downstream_granted_noteE_s1;
  input            system_0_burst_24_downstream_qualified_request_noteE_s1;
  input            system_0_burst_24_downstream_read;
  input            system_0_burst_24_downstream_read_data_valid_noteE_s1;
  input            system_0_burst_24_downstream_requests_noteE_s1;
  input            system_0_burst_24_downstream_write;
  input   [  7: 0] system_0_burst_24_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_24_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_24_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_24_downstream_address_to_slave;
  reg              system_0_burst_24_downstream_burstcount_last_time;
  reg              system_0_burst_24_downstream_byteenable_last_time;
  wire             system_0_burst_24_downstream_latency_counter;
  reg              system_0_burst_24_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_24_downstream_readdata;
  wire             system_0_burst_24_downstream_readdatavalid;
  wire             system_0_burst_24_downstream_reset_n;
  wire             system_0_burst_24_downstream_run;
  wire             system_0_burst_24_downstream_waitrequest;
  reg              system_0_burst_24_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_24_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_24_downstream_qualified_request_noteE_s1 | ~system_0_burst_24_downstream_requests_noteE_s1) & ((~system_0_burst_24_downstream_qualified_request_noteE_s1 | ~system_0_burst_24_downstream_read | (1 & ~d1_noteE_s1_end_xfer & system_0_burst_24_downstream_read))) & ((~system_0_burst_24_downstream_qualified_request_noteE_s1 | ~system_0_burst_24_downstream_write | (1 & system_0_burst_24_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_24_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_24_downstream_address_to_slave = system_0_burst_24_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_24_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_24_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_24_downstream_readdatavalid |
    system_0_burst_24_downstream_read_data_valid_noteE_s1;

  //system_0_burst_24/downstream readdata mux, which is an e_mux
  assign system_0_burst_24_downstream_readdata = noteE_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_24_downstream_waitrequest = ~system_0_burst_24_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_24_downstream_latency_counter = 0;

  //system_0_burst_24_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_24_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_24_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_24_downstream_address_last_time <= 0;
      else 
        system_0_burst_24_downstream_address_last_time <= system_0_burst_24_downstream_address;
    end


  //system_0_burst_24/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_24_downstream_waitrequest & (system_0_burst_24_downstream_read | system_0_burst_24_downstream_write);
    end


  //system_0_burst_24_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_24_downstream_address != system_0_burst_24_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_24_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_24_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_24_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_24_downstream_burstcount_last_time <= system_0_burst_24_downstream_burstcount;
    end


  //system_0_burst_24_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_24_downstream_burstcount != system_0_burst_24_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_24_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_24_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_24_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_24_downstream_byteenable_last_time <= system_0_burst_24_downstream_byteenable;
    end


  //system_0_burst_24_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_24_downstream_byteenable != system_0_burst_24_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_24_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_24_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_24_downstream_read_last_time <= 0;
      else 
        system_0_burst_24_downstream_read_last_time <= system_0_burst_24_downstream_read;
    end


  //system_0_burst_24_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_24_downstream_read != system_0_burst_24_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_24_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_24_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_24_downstream_write_last_time <= 0;
      else 
        system_0_burst_24_downstream_write_last_time <= system_0_burst_24_downstream_write;
    end


  //system_0_burst_24_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_24_downstream_write != system_0_burst_24_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_24_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_24_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_24_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_24_downstream_writedata_last_time <= system_0_burst_24_downstream_writedata;
    end


  //system_0_burst_24_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_24_downstream_writedata != system_0_burst_24_downstream_writedata_last_time) & system_0_burst_24_downstream_write)
        begin
          $write("%0d ns: system_0_burst_24_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_25_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_25_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_25_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_25_upstream_readdata,
                                                system_0_burst_25_upstream_readdatavalid,
                                                system_0_burst_25_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_25_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_25_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_25_upstream,
                                                d1_system_0_burst_25_upstream_end_xfer,
                                                system_0_burst_25_upstream_address,
                                                system_0_burst_25_upstream_burstcount,
                                                system_0_burst_25_upstream_byteaddress,
                                                system_0_burst_25_upstream_byteenable,
                                                system_0_burst_25_upstream_debugaccess,
                                                system_0_burst_25_upstream_read,
                                                system_0_burst_25_upstream_readdata_from_sa,
                                                system_0_burst_25_upstream_waitrequest_from_sa,
                                                system_0_burst_25_upstream_write,
                                                system_0_burst_25_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_25_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_25_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_25_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_25_upstream;
  output           d1_system_0_burst_25_upstream_end_xfer;
  output  [  1: 0] system_0_burst_25_upstream_address;
  output  [  3: 0] system_0_burst_25_upstream_burstcount;
  output  [  1: 0] system_0_burst_25_upstream_byteaddress;
  output           system_0_burst_25_upstream_byteenable;
  output           system_0_burst_25_upstream_debugaccess;
  output           system_0_burst_25_upstream_read;
  output  [  7: 0] system_0_burst_25_upstream_readdata_from_sa;
  output           system_0_burst_25_upstream_waitrequest_from_sa;
  output           system_0_burst_25_upstream_write;
  output  [  7: 0] system_0_burst_25_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_25_upstream_readdata;
  input            system_0_burst_25_upstream_readdatavalid;
  input            system_0_burst_25_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_25_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_25_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_25_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_25_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_25_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_25_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_25_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_25_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_25_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_25_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_25_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_25_upstream_address;
  wire             system_0_burst_25_upstream_allgrants;
  wire             system_0_burst_25_upstream_allow_new_arb_cycle;
  wire             system_0_burst_25_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_25_upstream_any_continuerequest;
  wire             system_0_burst_25_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_25_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_25_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_25_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_25_upstream_bbt_burstcounter;
  wire             system_0_burst_25_upstream_beginbursttransfer_internal;
  wire             system_0_burst_25_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_25_upstream_burstcount;
  wire             system_0_burst_25_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_25_upstream_byteaddress;
  wire             system_0_burst_25_upstream_byteenable;
  reg     [  3: 0] system_0_burst_25_upstream_current_burst;
  wire    [  3: 0] system_0_burst_25_upstream_current_burst_minus_one;
  wire             system_0_burst_25_upstream_debugaccess;
  wire             system_0_burst_25_upstream_end_xfer;
  wire             system_0_burst_25_upstream_firsttransfer;
  wire             system_0_burst_25_upstream_grant_vector;
  wire             system_0_burst_25_upstream_in_a_read_cycle;
  wire             system_0_burst_25_upstream_in_a_write_cycle;
  reg              system_0_burst_25_upstream_load_fifo;
  wire             system_0_burst_25_upstream_master_qreq_vector;
  wire             system_0_burst_25_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_25_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_25_upstream_next_burst_count;
  wire             system_0_burst_25_upstream_non_bursting_master_requests;
  wire             system_0_burst_25_upstream_read;
  wire    [  7: 0] system_0_burst_25_upstream_readdata_from_sa;
  wire             system_0_burst_25_upstream_readdatavalid_from_sa;
  reg              system_0_burst_25_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_25_upstream_selected_burstcount;
  reg              system_0_burst_25_upstream_slavearbiterlockenable;
  wire             system_0_burst_25_upstream_slavearbiterlockenable2;
  wire             system_0_burst_25_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_25_upstream_transaction_burst_count;
  wire             system_0_burst_25_upstream_unreg_firsttransfer;
  wire             system_0_burst_25_upstream_waitrequest_from_sa;
  wire             system_0_burst_25_upstream_waits_for_read;
  wire             system_0_burst_25_upstream_waits_for_write;
  wire             system_0_burst_25_upstream_write;
  wire    [  7: 0] system_0_burst_25_upstream_writedata;
  wire             wait_for_system_0_burst_25_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_25_upstream_end_xfer;
    end


  assign system_0_burst_25_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_25_upstream));
  //assign system_0_burst_25_upstream_readdatavalid_from_sa = system_0_burst_25_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_25_upstream_readdatavalid_from_sa = system_0_burst_25_upstream_readdatavalid;

  //assign system_0_burst_25_upstream_readdata_from_sa = system_0_burst_25_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_25_upstream_readdata_from_sa = system_0_burst_25_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_25_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a150) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_25_upstream_waitrequest_from_sa = system_0_burst_25_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_25_upstream_waitrequest_from_sa = system_0_burst_25_upstream_waitrequest;

  //system_0_burst_25_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_25_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_25_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_25_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_25_upstream_non_bursting_master_requests = 0;

  //system_0_burst_25_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_25_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_25_upstream;

  //system_0_burst_25_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_25_upstream_arb_share_counter_next_value = system_0_burst_25_upstream_firsttransfer ? (system_0_burst_25_upstream_arb_share_set_values - 1) : |system_0_burst_25_upstream_arb_share_counter ? (system_0_burst_25_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_25_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_25_upstream_allgrants = |system_0_burst_25_upstream_grant_vector;

  //system_0_burst_25_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_25_upstream_end_xfer = ~(system_0_burst_25_upstream_waits_for_read | system_0_burst_25_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_25_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_25_upstream = system_0_burst_25_upstream_end_xfer & (~system_0_burst_25_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_25_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_25_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_25_upstream & system_0_burst_25_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_25_upstream & ~system_0_burst_25_upstream_non_bursting_master_requests);

  //system_0_burst_25_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_25_upstream_arb_share_counter <= 0;
      else if (system_0_burst_25_upstream_arb_counter_enable)
          system_0_burst_25_upstream_arb_share_counter <= system_0_burst_25_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_25_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_25_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_25_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_25_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_25_upstream & ~system_0_burst_25_upstream_non_bursting_master_requests))
          system_0_burst_25_upstream_slavearbiterlockenable <= |system_0_burst_25_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_25/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_25_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_25_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_25_upstream_slavearbiterlockenable2 = |system_0_burst_25_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_25/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_25_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_25_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_25_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_25_upstream = cpu_0_data_master_requests_system_0_burst_25_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_25_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_25_upstream_move_on_to_next_transaction = system_0_burst_25_upstream_this_cycle_is_the_last_burst & system_0_burst_25_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_25_upstream, which is an e_mux
  assign system_0_burst_25_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_25_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_25_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_25_upstream_module burstcount_fifo_for_system_0_burst_25_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_25_upstream_selected_burstcount),
      .data_out             (system_0_burst_25_upstream_transaction_burst_count),
      .empty                (system_0_burst_25_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_25_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_25_upstream_waits_for_read & system_0_burst_25_upstream_load_fifo & ~(system_0_burst_25_upstream_this_cycle_is_the_last_burst & system_0_burst_25_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_25_upstream current burst minus one, which is an e_assign
  assign system_0_burst_25_upstream_current_burst_minus_one = system_0_burst_25_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_25_upstream, which is an e_mux
  assign system_0_burst_25_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_25_upstream_waits_for_read) & ~system_0_burst_25_upstream_load_fifo))? system_0_burst_25_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_25_upstream_waits_for_read & system_0_burst_25_upstream_this_cycle_is_the_last_burst & system_0_burst_25_upstream_burstcount_fifo_empty))? system_0_burst_25_upstream_selected_burstcount :
    (system_0_burst_25_upstream_this_cycle_is_the_last_burst)? system_0_burst_25_upstream_transaction_burst_count :
    system_0_burst_25_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_25_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_25_upstream_current_burst <= 0;
      else if (system_0_burst_25_upstream_readdatavalid_from_sa | (~system_0_burst_25_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_25_upstream_waits_for_read)))
          system_0_burst_25_upstream_current_burst <= system_0_burst_25_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_25_upstream_load_fifo = (~system_0_burst_25_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_25_upstream_waits_for_read) & system_0_burst_25_upstream_load_fifo))? 1 :
    ~system_0_burst_25_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_25_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_25_upstream_waits_for_read) & ~system_0_burst_25_upstream_load_fifo | system_0_burst_25_upstream_this_cycle_is_the_last_burst)
          system_0_burst_25_upstream_load_fifo <= p0_system_0_burst_25_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_25_upstream, which is an e_assign
  assign system_0_burst_25_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_25_upstream_current_burst_minus_one) & system_0_burst_25_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_25_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_25_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_25_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_25_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_25_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_25_upstream),
      .full                 (),
      .read                 (system_0_burst_25_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_25_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_25_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_25_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_25_upstream = system_0_burst_25_upstream_readdatavalid_from_sa;

  //system_0_burst_25_upstream_writedata mux, which is an e_mux
  assign system_0_burst_25_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_25/upstream, which is an e_mux
  assign system_0_burst_25_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_25_upstream = cpu_0_data_master_qualified_request_system_0_burst_25_upstream;

  //cpu_0/data_master saved-grant system_0_burst_25/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_25_upstream = cpu_0_data_master_requests_system_0_burst_25_upstream;

  //allow new arb cycle for system_0_burst_25/upstream, which is an e_assign
  assign system_0_burst_25_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_25_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_25_upstream_master_qreq_vector = 1;

  //system_0_burst_25_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_25_upstream_firsttransfer = system_0_burst_25_upstream_begins_xfer ? system_0_burst_25_upstream_unreg_firsttransfer : system_0_burst_25_upstream_reg_firsttransfer;

  //system_0_burst_25_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_25_upstream_unreg_firsttransfer = ~(system_0_burst_25_upstream_slavearbiterlockenable & system_0_burst_25_upstream_any_continuerequest);

  //system_0_burst_25_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_25_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_25_upstream_begins_xfer)
          system_0_burst_25_upstream_reg_firsttransfer <= system_0_burst_25_upstream_unreg_firsttransfer;
    end


  //system_0_burst_25_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_25_upstream_next_bbt_burstcount = ((((system_0_burst_25_upstream_write) && (system_0_burst_25_upstream_bbt_burstcounter == 0))))? (system_0_burst_25_upstream_burstcount - 1) :
    ((((system_0_burst_25_upstream_read) && (system_0_burst_25_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_25_upstream_bbt_burstcounter - 1);

  //system_0_burst_25_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_25_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_25_upstream_begins_xfer)
          system_0_burst_25_upstream_bbt_burstcounter <= system_0_burst_25_upstream_next_bbt_burstcount;
    end


  //system_0_burst_25_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_25_upstream_beginbursttransfer_internal = system_0_burst_25_upstream_begins_xfer & (system_0_burst_25_upstream_bbt_burstcounter == 0);

  //system_0_burst_25_upstream_read assignment, which is an e_mux
  assign system_0_burst_25_upstream_read = cpu_0_data_master_granted_system_0_burst_25_upstream & cpu_0_data_master_read;

  //system_0_burst_25_upstream_write assignment, which is an e_mux
  assign system_0_burst_25_upstream_write = cpu_0_data_master_granted_system_0_burst_25_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_25_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_25_upstream_address mux, which is an e_mux
  assign system_0_burst_25_upstream_address = shifted_address_to_system_0_burst_25_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_25_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_25_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_25_upstream_end_xfer <= system_0_burst_25_upstream_end_xfer;
    end


  //system_0_burst_25_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_25_upstream_waits_for_read = system_0_burst_25_upstream_in_a_read_cycle & system_0_burst_25_upstream_waitrequest_from_sa;

  //system_0_burst_25_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_25_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_25_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_25_upstream_in_a_read_cycle;

  //system_0_burst_25_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_25_upstream_waits_for_write = system_0_burst_25_upstream_in_a_write_cycle & system_0_burst_25_upstream_waitrequest_from_sa;

  //system_0_burst_25_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_25_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_25_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_25_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_25_upstream_counter = 0;
  //system_0_burst_25_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_25_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_25_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_25_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_25_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_25_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_25_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_25/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_25_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_25/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_25_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_noteF_s1_end_xfer,
                                                  noteF_s1_readdata_from_sa,
                                                  reset_n,
                                                  system_0_burst_25_downstream_address,
                                                  system_0_burst_25_downstream_burstcount,
                                                  system_0_burst_25_downstream_byteenable,
                                                  system_0_burst_25_downstream_granted_noteF_s1,
                                                  system_0_burst_25_downstream_qualified_request_noteF_s1,
                                                  system_0_burst_25_downstream_read,
                                                  system_0_burst_25_downstream_read_data_valid_noteF_s1,
                                                  system_0_burst_25_downstream_requests_noteF_s1,
                                                  system_0_burst_25_downstream_write,
                                                  system_0_burst_25_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_25_downstream_address_to_slave,
                                                  system_0_burst_25_downstream_latency_counter,
                                                  system_0_burst_25_downstream_readdata,
                                                  system_0_burst_25_downstream_readdatavalid,
                                                  system_0_burst_25_downstream_reset_n,
                                                  system_0_burst_25_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_25_downstream_address_to_slave;
  output           system_0_burst_25_downstream_latency_counter;
  output  [  7: 0] system_0_burst_25_downstream_readdata;
  output           system_0_burst_25_downstream_readdatavalid;
  output           system_0_burst_25_downstream_reset_n;
  output           system_0_burst_25_downstream_waitrequest;
  input            clk;
  input            d1_noteF_s1_end_xfer;
  input            noteF_s1_readdata_from_sa;
  input            reset_n;
  input   [  1: 0] system_0_burst_25_downstream_address;
  input            system_0_burst_25_downstream_burstcount;
  input            system_0_burst_25_downstream_byteenable;
  input            system_0_burst_25_downstream_granted_noteF_s1;
  input            system_0_burst_25_downstream_qualified_request_noteF_s1;
  input            system_0_burst_25_downstream_read;
  input            system_0_burst_25_downstream_read_data_valid_noteF_s1;
  input            system_0_burst_25_downstream_requests_noteF_s1;
  input            system_0_burst_25_downstream_write;
  input   [  7: 0] system_0_burst_25_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_25_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_25_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_25_downstream_address_to_slave;
  reg              system_0_burst_25_downstream_burstcount_last_time;
  reg              system_0_burst_25_downstream_byteenable_last_time;
  wire             system_0_burst_25_downstream_latency_counter;
  reg              system_0_burst_25_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_25_downstream_readdata;
  wire             system_0_burst_25_downstream_readdatavalid;
  wire             system_0_burst_25_downstream_reset_n;
  wire             system_0_burst_25_downstream_run;
  wire             system_0_burst_25_downstream_waitrequest;
  reg              system_0_burst_25_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_25_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_25_downstream_qualified_request_noteF_s1 | ~system_0_burst_25_downstream_requests_noteF_s1) & ((~system_0_burst_25_downstream_qualified_request_noteF_s1 | ~system_0_burst_25_downstream_read | (1 & ~d1_noteF_s1_end_xfer & system_0_burst_25_downstream_read))) & ((~system_0_burst_25_downstream_qualified_request_noteF_s1 | ~system_0_burst_25_downstream_write | (1 & system_0_burst_25_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_25_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_25_downstream_address_to_slave = system_0_burst_25_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_25_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_25_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_25_downstream_readdatavalid |
    system_0_burst_25_downstream_read_data_valid_noteF_s1;

  //system_0_burst_25/downstream readdata mux, which is an e_mux
  assign system_0_burst_25_downstream_readdata = noteF_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_25_downstream_waitrequest = ~system_0_burst_25_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_25_downstream_latency_counter = 0;

  //system_0_burst_25_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_25_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_25_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_25_downstream_address_last_time <= 0;
      else 
        system_0_burst_25_downstream_address_last_time <= system_0_burst_25_downstream_address;
    end


  //system_0_burst_25/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_25_downstream_waitrequest & (system_0_burst_25_downstream_read | system_0_burst_25_downstream_write);
    end


  //system_0_burst_25_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_25_downstream_address != system_0_burst_25_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_25_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_25_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_25_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_25_downstream_burstcount_last_time <= system_0_burst_25_downstream_burstcount;
    end


  //system_0_burst_25_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_25_downstream_burstcount != system_0_burst_25_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_25_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_25_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_25_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_25_downstream_byteenable_last_time <= system_0_burst_25_downstream_byteenable;
    end


  //system_0_burst_25_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_25_downstream_byteenable != system_0_burst_25_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_25_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_25_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_25_downstream_read_last_time <= 0;
      else 
        system_0_burst_25_downstream_read_last_time <= system_0_burst_25_downstream_read;
    end


  //system_0_burst_25_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_25_downstream_read != system_0_burst_25_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_25_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_25_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_25_downstream_write_last_time <= 0;
      else 
        system_0_burst_25_downstream_write_last_time <= system_0_burst_25_downstream_write;
    end


  //system_0_burst_25_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_25_downstream_write != system_0_burst_25_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_25_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_25_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_25_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_25_downstream_writedata_last_time <= system_0_burst_25_downstream_writedata;
    end


  //system_0_burst_25_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_25_downstream_writedata != system_0_burst_25_downstream_writedata_last_time) & system_0_burst_25_downstream_write)
        begin
          $write("%0d ns: system_0_burst_25_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_26_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_26_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_26_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_26_upstream_readdata,
                                                system_0_burst_26_upstream_readdatavalid,
                                                system_0_burst_26_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_26_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_26_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_26_upstream,
                                                d1_system_0_burst_26_upstream_end_xfer,
                                                system_0_burst_26_upstream_address,
                                                system_0_burst_26_upstream_burstcount,
                                                system_0_burst_26_upstream_byteaddress,
                                                system_0_burst_26_upstream_byteenable,
                                                system_0_burst_26_upstream_debugaccess,
                                                system_0_burst_26_upstream_read,
                                                system_0_burst_26_upstream_readdata_from_sa,
                                                system_0_burst_26_upstream_waitrequest_from_sa,
                                                system_0_burst_26_upstream_write,
                                                system_0_burst_26_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_26_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_26_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_26_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_26_upstream;
  output           d1_system_0_burst_26_upstream_end_xfer;
  output  [  1: 0] system_0_burst_26_upstream_address;
  output  [  3: 0] system_0_burst_26_upstream_burstcount;
  output  [  1: 0] system_0_burst_26_upstream_byteaddress;
  output           system_0_burst_26_upstream_byteenable;
  output           system_0_burst_26_upstream_debugaccess;
  output           system_0_burst_26_upstream_read;
  output  [  7: 0] system_0_burst_26_upstream_readdata_from_sa;
  output           system_0_burst_26_upstream_waitrequest_from_sa;
  output           system_0_burst_26_upstream_write;
  output  [  7: 0] system_0_burst_26_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_26_upstream_readdata;
  input            system_0_burst_26_upstream_readdatavalid;
  input            system_0_burst_26_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_26_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_26_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_26_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_26_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_26_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_26_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_26_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_26_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_26_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_26_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_26_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_26_upstream_address;
  wire             system_0_burst_26_upstream_allgrants;
  wire             system_0_burst_26_upstream_allow_new_arb_cycle;
  wire             system_0_burst_26_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_26_upstream_any_continuerequest;
  wire             system_0_burst_26_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_26_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_26_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_26_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_26_upstream_bbt_burstcounter;
  wire             system_0_burst_26_upstream_beginbursttransfer_internal;
  wire             system_0_burst_26_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_26_upstream_burstcount;
  wire             system_0_burst_26_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_26_upstream_byteaddress;
  wire             system_0_burst_26_upstream_byteenable;
  reg     [  3: 0] system_0_burst_26_upstream_current_burst;
  wire    [  3: 0] system_0_burst_26_upstream_current_burst_minus_one;
  wire             system_0_burst_26_upstream_debugaccess;
  wire             system_0_burst_26_upstream_end_xfer;
  wire             system_0_burst_26_upstream_firsttransfer;
  wire             system_0_burst_26_upstream_grant_vector;
  wire             system_0_burst_26_upstream_in_a_read_cycle;
  wire             system_0_burst_26_upstream_in_a_write_cycle;
  reg              system_0_burst_26_upstream_load_fifo;
  wire             system_0_burst_26_upstream_master_qreq_vector;
  wire             system_0_burst_26_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_26_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_26_upstream_next_burst_count;
  wire             system_0_burst_26_upstream_non_bursting_master_requests;
  wire             system_0_burst_26_upstream_read;
  wire    [  7: 0] system_0_burst_26_upstream_readdata_from_sa;
  wire             system_0_burst_26_upstream_readdatavalid_from_sa;
  reg              system_0_burst_26_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_26_upstream_selected_burstcount;
  reg              system_0_burst_26_upstream_slavearbiterlockenable;
  wire             system_0_burst_26_upstream_slavearbiterlockenable2;
  wire             system_0_burst_26_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_26_upstream_transaction_burst_count;
  wire             system_0_burst_26_upstream_unreg_firsttransfer;
  wire             system_0_burst_26_upstream_waitrequest_from_sa;
  wire             system_0_burst_26_upstream_waits_for_read;
  wire             system_0_burst_26_upstream_waits_for_write;
  wire             system_0_burst_26_upstream_write;
  wire    [  7: 0] system_0_burst_26_upstream_writedata;
  wire             wait_for_system_0_burst_26_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_26_upstream_end_xfer;
    end


  assign system_0_burst_26_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_26_upstream));
  //assign system_0_burst_26_upstream_readdatavalid_from_sa = system_0_burst_26_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_26_upstream_readdatavalid_from_sa = system_0_burst_26_upstream_readdatavalid;

  //assign system_0_burst_26_upstream_readdata_from_sa = system_0_burst_26_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_26_upstream_readdata_from_sa = system_0_burst_26_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_26_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a160) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_26_upstream_waitrequest_from_sa = system_0_burst_26_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_26_upstream_waitrequest_from_sa = system_0_burst_26_upstream_waitrequest;

  //system_0_burst_26_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_26_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_26_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_26_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_26_upstream_non_bursting_master_requests = 0;

  //system_0_burst_26_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_26_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_26_upstream;

  //system_0_burst_26_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_26_upstream_arb_share_counter_next_value = system_0_burst_26_upstream_firsttransfer ? (system_0_burst_26_upstream_arb_share_set_values - 1) : |system_0_burst_26_upstream_arb_share_counter ? (system_0_burst_26_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_26_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_26_upstream_allgrants = |system_0_burst_26_upstream_grant_vector;

  //system_0_burst_26_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_26_upstream_end_xfer = ~(system_0_burst_26_upstream_waits_for_read | system_0_burst_26_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_26_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_26_upstream = system_0_burst_26_upstream_end_xfer & (~system_0_burst_26_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_26_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_26_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_26_upstream & system_0_burst_26_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_26_upstream & ~system_0_burst_26_upstream_non_bursting_master_requests);

  //system_0_burst_26_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_26_upstream_arb_share_counter <= 0;
      else if (system_0_burst_26_upstream_arb_counter_enable)
          system_0_burst_26_upstream_arb_share_counter <= system_0_burst_26_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_26_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_26_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_26_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_26_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_26_upstream & ~system_0_burst_26_upstream_non_bursting_master_requests))
          system_0_burst_26_upstream_slavearbiterlockenable <= |system_0_burst_26_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_26/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_26_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_26_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_26_upstream_slavearbiterlockenable2 = |system_0_burst_26_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_26/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_26_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_26_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_26_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_26_upstream = cpu_0_data_master_requests_system_0_burst_26_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_26_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_26_upstream_move_on_to_next_transaction = system_0_burst_26_upstream_this_cycle_is_the_last_burst & system_0_burst_26_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_26_upstream, which is an e_mux
  assign system_0_burst_26_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_26_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_26_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_26_upstream_module burstcount_fifo_for_system_0_burst_26_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_26_upstream_selected_burstcount),
      .data_out             (system_0_burst_26_upstream_transaction_burst_count),
      .empty                (system_0_burst_26_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_26_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_26_upstream_waits_for_read & system_0_burst_26_upstream_load_fifo & ~(system_0_burst_26_upstream_this_cycle_is_the_last_burst & system_0_burst_26_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_26_upstream current burst minus one, which is an e_assign
  assign system_0_burst_26_upstream_current_burst_minus_one = system_0_burst_26_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_26_upstream, which is an e_mux
  assign system_0_burst_26_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_26_upstream_waits_for_read) & ~system_0_burst_26_upstream_load_fifo))? system_0_burst_26_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_26_upstream_waits_for_read & system_0_burst_26_upstream_this_cycle_is_the_last_burst & system_0_burst_26_upstream_burstcount_fifo_empty))? system_0_burst_26_upstream_selected_burstcount :
    (system_0_burst_26_upstream_this_cycle_is_the_last_burst)? system_0_burst_26_upstream_transaction_burst_count :
    system_0_burst_26_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_26_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_26_upstream_current_burst <= 0;
      else if (system_0_burst_26_upstream_readdatavalid_from_sa | (~system_0_burst_26_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_26_upstream_waits_for_read)))
          system_0_burst_26_upstream_current_burst <= system_0_burst_26_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_26_upstream_load_fifo = (~system_0_burst_26_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_26_upstream_waits_for_read) & system_0_burst_26_upstream_load_fifo))? 1 :
    ~system_0_burst_26_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_26_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_26_upstream_waits_for_read) & ~system_0_burst_26_upstream_load_fifo | system_0_burst_26_upstream_this_cycle_is_the_last_burst)
          system_0_burst_26_upstream_load_fifo <= p0_system_0_burst_26_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_26_upstream, which is an e_assign
  assign system_0_burst_26_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_26_upstream_current_burst_minus_one) & system_0_burst_26_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_26_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_26_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_26_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_26_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_26_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_26_upstream),
      .full                 (),
      .read                 (system_0_burst_26_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_26_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_26_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_26_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_26_upstream = system_0_burst_26_upstream_readdatavalid_from_sa;

  //system_0_burst_26_upstream_writedata mux, which is an e_mux
  assign system_0_burst_26_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_26/upstream, which is an e_mux
  assign system_0_burst_26_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_26_upstream = cpu_0_data_master_qualified_request_system_0_burst_26_upstream;

  //cpu_0/data_master saved-grant system_0_burst_26/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_26_upstream = cpu_0_data_master_requests_system_0_burst_26_upstream;

  //allow new arb cycle for system_0_burst_26/upstream, which is an e_assign
  assign system_0_burst_26_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_26_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_26_upstream_master_qreq_vector = 1;

  //system_0_burst_26_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_26_upstream_firsttransfer = system_0_burst_26_upstream_begins_xfer ? system_0_burst_26_upstream_unreg_firsttransfer : system_0_burst_26_upstream_reg_firsttransfer;

  //system_0_burst_26_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_26_upstream_unreg_firsttransfer = ~(system_0_burst_26_upstream_slavearbiterlockenable & system_0_burst_26_upstream_any_continuerequest);

  //system_0_burst_26_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_26_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_26_upstream_begins_xfer)
          system_0_burst_26_upstream_reg_firsttransfer <= system_0_burst_26_upstream_unreg_firsttransfer;
    end


  //system_0_burst_26_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_26_upstream_next_bbt_burstcount = ((((system_0_burst_26_upstream_write) && (system_0_burst_26_upstream_bbt_burstcounter == 0))))? (system_0_burst_26_upstream_burstcount - 1) :
    ((((system_0_burst_26_upstream_read) && (system_0_burst_26_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_26_upstream_bbt_burstcounter - 1);

  //system_0_burst_26_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_26_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_26_upstream_begins_xfer)
          system_0_burst_26_upstream_bbt_burstcounter <= system_0_burst_26_upstream_next_bbt_burstcount;
    end


  //system_0_burst_26_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_26_upstream_beginbursttransfer_internal = system_0_burst_26_upstream_begins_xfer & (system_0_burst_26_upstream_bbt_burstcounter == 0);

  //system_0_burst_26_upstream_read assignment, which is an e_mux
  assign system_0_burst_26_upstream_read = cpu_0_data_master_granted_system_0_burst_26_upstream & cpu_0_data_master_read;

  //system_0_burst_26_upstream_write assignment, which is an e_mux
  assign system_0_burst_26_upstream_write = cpu_0_data_master_granted_system_0_burst_26_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_26_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_26_upstream_address mux, which is an e_mux
  assign system_0_burst_26_upstream_address = shifted_address_to_system_0_burst_26_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_26_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_26_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_26_upstream_end_xfer <= system_0_burst_26_upstream_end_xfer;
    end


  //system_0_burst_26_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_26_upstream_waits_for_read = system_0_burst_26_upstream_in_a_read_cycle & system_0_burst_26_upstream_waitrequest_from_sa;

  //system_0_burst_26_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_26_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_26_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_26_upstream_in_a_read_cycle;

  //system_0_burst_26_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_26_upstream_waits_for_write = system_0_burst_26_upstream_in_a_write_cycle & system_0_burst_26_upstream_waitrequest_from_sa;

  //system_0_burst_26_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_26_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_26_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_26_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_26_upstream_counter = 0;
  //system_0_burst_26_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_26_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_26_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_26_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_26_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_26_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_26_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_26/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_26_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_26/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_26_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_noteG_s1_end_xfer,
                                                  noteG_s1_readdata_from_sa,
                                                  reset_n,
                                                  system_0_burst_26_downstream_address,
                                                  system_0_burst_26_downstream_burstcount,
                                                  system_0_burst_26_downstream_byteenable,
                                                  system_0_burst_26_downstream_granted_noteG_s1,
                                                  system_0_burst_26_downstream_qualified_request_noteG_s1,
                                                  system_0_burst_26_downstream_read,
                                                  system_0_burst_26_downstream_read_data_valid_noteG_s1,
                                                  system_0_burst_26_downstream_requests_noteG_s1,
                                                  system_0_burst_26_downstream_write,
                                                  system_0_burst_26_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_26_downstream_address_to_slave,
                                                  system_0_burst_26_downstream_latency_counter,
                                                  system_0_burst_26_downstream_readdata,
                                                  system_0_burst_26_downstream_readdatavalid,
                                                  system_0_burst_26_downstream_reset_n,
                                                  system_0_burst_26_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_26_downstream_address_to_slave;
  output           system_0_burst_26_downstream_latency_counter;
  output  [  7: 0] system_0_burst_26_downstream_readdata;
  output           system_0_burst_26_downstream_readdatavalid;
  output           system_0_burst_26_downstream_reset_n;
  output           system_0_burst_26_downstream_waitrequest;
  input            clk;
  input            d1_noteG_s1_end_xfer;
  input            noteG_s1_readdata_from_sa;
  input            reset_n;
  input   [  1: 0] system_0_burst_26_downstream_address;
  input            system_0_burst_26_downstream_burstcount;
  input            system_0_burst_26_downstream_byteenable;
  input            system_0_burst_26_downstream_granted_noteG_s1;
  input            system_0_burst_26_downstream_qualified_request_noteG_s1;
  input            system_0_burst_26_downstream_read;
  input            system_0_burst_26_downstream_read_data_valid_noteG_s1;
  input            system_0_burst_26_downstream_requests_noteG_s1;
  input            system_0_burst_26_downstream_write;
  input   [  7: 0] system_0_burst_26_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_26_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_26_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_26_downstream_address_to_slave;
  reg              system_0_burst_26_downstream_burstcount_last_time;
  reg              system_0_burst_26_downstream_byteenable_last_time;
  wire             system_0_burst_26_downstream_latency_counter;
  reg              system_0_burst_26_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_26_downstream_readdata;
  wire             system_0_burst_26_downstream_readdatavalid;
  wire             system_0_burst_26_downstream_reset_n;
  wire             system_0_burst_26_downstream_run;
  wire             system_0_burst_26_downstream_waitrequest;
  reg              system_0_burst_26_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_26_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_26_downstream_qualified_request_noteG_s1 | ~system_0_burst_26_downstream_requests_noteG_s1) & ((~system_0_burst_26_downstream_qualified_request_noteG_s1 | ~system_0_burst_26_downstream_read | (1 & ~d1_noteG_s1_end_xfer & system_0_burst_26_downstream_read))) & ((~system_0_burst_26_downstream_qualified_request_noteG_s1 | ~system_0_burst_26_downstream_write | (1 & system_0_burst_26_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_26_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_26_downstream_address_to_slave = system_0_burst_26_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_26_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_26_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_26_downstream_readdatavalid |
    system_0_burst_26_downstream_read_data_valid_noteG_s1;

  //system_0_burst_26/downstream readdata mux, which is an e_mux
  assign system_0_burst_26_downstream_readdata = noteG_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_26_downstream_waitrequest = ~system_0_burst_26_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_26_downstream_latency_counter = 0;

  //system_0_burst_26_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_26_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_26_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_26_downstream_address_last_time <= 0;
      else 
        system_0_burst_26_downstream_address_last_time <= system_0_burst_26_downstream_address;
    end


  //system_0_burst_26/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_26_downstream_waitrequest & (system_0_burst_26_downstream_read | system_0_burst_26_downstream_write);
    end


  //system_0_burst_26_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_26_downstream_address != system_0_burst_26_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_26_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_26_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_26_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_26_downstream_burstcount_last_time <= system_0_burst_26_downstream_burstcount;
    end


  //system_0_burst_26_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_26_downstream_burstcount != system_0_burst_26_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_26_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_26_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_26_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_26_downstream_byteenable_last_time <= system_0_burst_26_downstream_byteenable;
    end


  //system_0_burst_26_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_26_downstream_byteenable != system_0_burst_26_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_26_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_26_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_26_downstream_read_last_time <= 0;
      else 
        system_0_burst_26_downstream_read_last_time <= system_0_burst_26_downstream_read;
    end


  //system_0_burst_26_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_26_downstream_read != system_0_burst_26_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_26_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_26_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_26_downstream_write_last_time <= 0;
      else 
        system_0_burst_26_downstream_write_last_time <= system_0_burst_26_downstream_write;
    end


  //system_0_burst_26_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_26_downstream_write != system_0_burst_26_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_26_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_26_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_26_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_26_downstream_writedata_last_time <= system_0_burst_26_downstream_writedata;
    end


  //system_0_burst_26_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_26_downstream_writedata != system_0_burst_26_downstream_writedata_last_time) & system_0_burst_26_downstream_write)
        begin
          $write("%0d ns: system_0_burst_26_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_27_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_27_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_27_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_27_upstream_readdata,
                                                system_0_burst_27_upstream_readdatavalid,
                                                system_0_burst_27_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_27_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_27_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_27_upstream,
                                                d1_system_0_burst_27_upstream_end_xfer,
                                                system_0_burst_27_upstream_address,
                                                system_0_burst_27_upstream_burstcount,
                                                system_0_burst_27_upstream_byteaddress,
                                                system_0_burst_27_upstream_byteenable,
                                                system_0_burst_27_upstream_debugaccess,
                                                system_0_burst_27_upstream_read,
                                                system_0_burst_27_upstream_readdata_from_sa,
                                                system_0_burst_27_upstream_waitrequest_from_sa,
                                                system_0_burst_27_upstream_write,
                                                system_0_burst_27_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_27_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_27_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_27_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_27_upstream;
  output           d1_system_0_burst_27_upstream_end_xfer;
  output  [  1: 0] system_0_burst_27_upstream_address;
  output  [  3: 0] system_0_burst_27_upstream_burstcount;
  output  [  1: 0] system_0_burst_27_upstream_byteaddress;
  output           system_0_burst_27_upstream_byteenable;
  output           system_0_burst_27_upstream_debugaccess;
  output           system_0_burst_27_upstream_read;
  output  [  7: 0] system_0_burst_27_upstream_readdata_from_sa;
  output           system_0_burst_27_upstream_waitrequest_from_sa;
  output           system_0_burst_27_upstream_write;
  output  [  7: 0] system_0_burst_27_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_27_upstream_readdata;
  input            system_0_burst_27_upstream_readdatavalid;
  input            system_0_burst_27_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_27_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_27_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_27_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_27_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_27_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_27_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_27_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_27_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_27_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_27_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_27_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_27_upstream_address;
  wire             system_0_burst_27_upstream_allgrants;
  wire             system_0_burst_27_upstream_allow_new_arb_cycle;
  wire             system_0_burst_27_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_27_upstream_any_continuerequest;
  wire             system_0_burst_27_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_27_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_27_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_27_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_27_upstream_bbt_burstcounter;
  wire             system_0_burst_27_upstream_beginbursttransfer_internal;
  wire             system_0_burst_27_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_27_upstream_burstcount;
  wire             system_0_burst_27_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_27_upstream_byteaddress;
  wire             system_0_burst_27_upstream_byteenable;
  reg     [  3: 0] system_0_burst_27_upstream_current_burst;
  wire    [  3: 0] system_0_burst_27_upstream_current_burst_minus_one;
  wire             system_0_burst_27_upstream_debugaccess;
  wire             system_0_burst_27_upstream_end_xfer;
  wire             system_0_burst_27_upstream_firsttransfer;
  wire             system_0_burst_27_upstream_grant_vector;
  wire             system_0_burst_27_upstream_in_a_read_cycle;
  wire             system_0_burst_27_upstream_in_a_write_cycle;
  reg              system_0_burst_27_upstream_load_fifo;
  wire             system_0_burst_27_upstream_master_qreq_vector;
  wire             system_0_burst_27_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_27_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_27_upstream_next_burst_count;
  wire             system_0_burst_27_upstream_non_bursting_master_requests;
  wire             system_0_burst_27_upstream_read;
  wire    [  7: 0] system_0_burst_27_upstream_readdata_from_sa;
  wire             system_0_burst_27_upstream_readdatavalid_from_sa;
  reg              system_0_burst_27_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_27_upstream_selected_burstcount;
  reg              system_0_burst_27_upstream_slavearbiterlockenable;
  wire             system_0_burst_27_upstream_slavearbiterlockenable2;
  wire             system_0_burst_27_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_27_upstream_transaction_burst_count;
  wire             system_0_burst_27_upstream_unreg_firsttransfer;
  wire             system_0_burst_27_upstream_waitrequest_from_sa;
  wire             system_0_burst_27_upstream_waits_for_read;
  wire             system_0_burst_27_upstream_waits_for_write;
  wire             system_0_burst_27_upstream_write;
  wire    [  7: 0] system_0_burst_27_upstream_writedata;
  wire             wait_for_system_0_burst_27_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_27_upstream_end_xfer;
    end


  assign system_0_burst_27_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_27_upstream));
  //assign system_0_burst_27_upstream_readdatavalid_from_sa = system_0_burst_27_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_27_upstream_readdatavalid_from_sa = system_0_burst_27_upstream_readdatavalid;

  //assign system_0_burst_27_upstream_readdata_from_sa = system_0_burst_27_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_27_upstream_readdata_from_sa = system_0_burst_27_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_27_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a170) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_27_upstream_waitrequest_from_sa = system_0_burst_27_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_27_upstream_waitrequest_from_sa = system_0_burst_27_upstream_waitrequest;

  //system_0_burst_27_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_27_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_27_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_27_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_27_upstream_non_bursting_master_requests = 0;

  //system_0_burst_27_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_27_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_27_upstream;

  //system_0_burst_27_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_27_upstream_arb_share_counter_next_value = system_0_burst_27_upstream_firsttransfer ? (system_0_burst_27_upstream_arb_share_set_values - 1) : |system_0_burst_27_upstream_arb_share_counter ? (system_0_burst_27_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_27_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_27_upstream_allgrants = |system_0_burst_27_upstream_grant_vector;

  //system_0_burst_27_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_27_upstream_end_xfer = ~(system_0_burst_27_upstream_waits_for_read | system_0_burst_27_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_27_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_27_upstream = system_0_burst_27_upstream_end_xfer & (~system_0_burst_27_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_27_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_27_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_27_upstream & system_0_burst_27_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_27_upstream & ~system_0_burst_27_upstream_non_bursting_master_requests);

  //system_0_burst_27_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_27_upstream_arb_share_counter <= 0;
      else if (system_0_burst_27_upstream_arb_counter_enable)
          system_0_burst_27_upstream_arb_share_counter <= system_0_burst_27_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_27_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_27_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_27_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_27_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_27_upstream & ~system_0_burst_27_upstream_non_bursting_master_requests))
          system_0_burst_27_upstream_slavearbiterlockenable <= |system_0_burst_27_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_27/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_27_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_27_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_27_upstream_slavearbiterlockenable2 = |system_0_burst_27_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_27/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_27_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_27_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_27_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_27_upstream = cpu_0_data_master_requests_system_0_burst_27_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_27_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_27_upstream_move_on_to_next_transaction = system_0_burst_27_upstream_this_cycle_is_the_last_burst & system_0_burst_27_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_27_upstream, which is an e_mux
  assign system_0_burst_27_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_27_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_27_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_27_upstream_module burstcount_fifo_for_system_0_burst_27_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_27_upstream_selected_burstcount),
      .data_out             (system_0_burst_27_upstream_transaction_burst_count),
      .empty                (system_0_burst_27_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_27_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_27_upstream_waits_for_read & system_0_burst_27_upstream_load_fifo & ~(system_0_burst_27_upstream_this_cycle_is_the_last_burst & system_0_burst_27_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_27_upstream current burst minus one, which is an e_assign
  assign system_0_burst_27_upstream_current_burst_minus_one = system_0_burst_27_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_27_upstream, which is an e_mux
  assign system_0_burst_27_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_27_upstream_waits_for_read) & ~system_0_burst_27_upstream_load_fifo))? system_0_burst_27_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_27_upstream_waits_for_read & system_0_burst_27_upstream_this_cycle_is_the_last_burst & system_0_burst_27_upstream_burstcount_fifo_empty))? system_0_burst_27_upstream_selected_burstcount :
    (system_0_burst_27_upstream_this_cycle_is_the_last_burst)? system_0_burst_27_upstream_transaction_burst_count :
    system_0_burst_27_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_27_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_27_upstream_current_burst <= 0;
      else if (system_0_burst_27_upstream_readdatavalid_from_sa | (~system_0_burst_27_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_27_upstream_waits_for_read)))
          system_0_burst_27_upstream_current_burst <= system_0_burst_27_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_27_upstream_load_fifo = (~system_0_burst_27_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_27_upstream_waits_for_read) & system_0_burst_27_upstream_load_fifo))? 1 :
    ~system_0_burst_27_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_27_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_27_upstream_waits_for_read) & ~system_0_burst_27_upstream_load_fifo | system_0_burst_27_upstream_this_cycle_is_the_last_burst)
          system_0_burst_27_upstream_load_fifo <= p0_system_0_burst_27_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_27_upstream, which is an e_assign
  assign system_0_burst_27_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_27_upstream_current_burst_minus_one) & system_0_burst_27_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_27_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_27_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_27_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_27_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_27_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_27_upstream),
      .full                 (),
      .read                 (system_0_burst_27_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_27_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_27_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_27_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_27_upstream = system_0_burst_27_upstream_readdatavalid_from_sa;

  //system_0_burst_27_upstream_writedata mux, which is an e_mux
  assign system_0_burst_27_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_27/upstream, which is an e_mux
  assign system_0_burst_27_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_27_upstream = cpu_0_data_master_qualified_request_system_0_burst_27_upstream;

  //cpu_0/data_master saved-grant system_0_burst_27/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_27_upstream = cpu_0_data_master_requests_system_0_burst_27_upstream;

  //allow new arb cycle for system_0_burst_27/upstream, which is an e_assign
  assign system_0_burst_27_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_27_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_27_upstream_master_qreq_vector = 1;

  //system_0_burst_27_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_27_upstream_firsttransfer = system_0_burst_27_upstream_begins_xfer ? system_0_burst_27_upstream_unreg_firsttransfer : system_0_burst_27_upstream_reg_firsttransfer;

  //system_0_burst_27_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_27_upstream_unreg_firsttransfer = ~(system_0_burst_27_upstream_slavearbiterlockenable & system_0_burst_27_upstream_any_continuerequest);

  //system_0_burst_27_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_27_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_27_upstream_begins_xfer)
          system_0_burst_27_upstream_reg_firsttransfer <= system_0_burst_27_upstream_unreg_firsttransfer;
    end


  //system_0_burst_27_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_27_upstream_next_bbt_burstcount = ((((system_0_burst_27_upstream_write) && (system_0_burst_27_upstream_bbt_burstcounter == 0))))? (system_0_burst_27_upstream_burstcount - 1) :
    ((((system_0_burst_27_upstream_read) && (system_0_burst_27_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_27_upstream_bbt_burstcounter - 1);

  //system_0_burst_27_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_27_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_27_upstream_begins_xfer)
          system_0_burst_27_upstream_bbt_burstcounter <= system_0_burst_27_upstream_next_bbt_burstcount;
    end


  //system_0_burst_27_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_27_upstream_beginbursttransfer_internal = system_0_burst_27_upstream_begins_xfer & (system_0_burst_27_upstream_bbt_burstcounter == 0);

  //system_0_burst_27_upstream_read assignment, which is an e_mux
  assign system_0_burst_27_upstream_read = cpu_0_data_master_granted_system_0_burst_27_upstream & cpu_0_data_master_read;

  //system_0_burst_27_upstream_write assignment, which is an e_mux
  assign system_0_burst_27_upstream_write = cpu_0_data_master_granted_system_0_burst_27_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_27_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_27_upstream_address mux, which is an e_mux
  assign system_0_burst_27_upstream_address = shifted_address_to_system_0_burst_27_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_27_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_27_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_27_upstream_end_xfer <= system_0_burst_27_upstream_end_xfer;
    end


  //system_0_burst_27_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_27_upstream_waits_for_read = system_0_burst_27_upstream_in_a_read_cycle & system_0_burst_27_upstream_waitrequest_from_sa;

  //system_0_burst_27_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_27_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_27_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_27_upstream_in_a_read_cycle;

  //system_0_burst_27_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_27_upstream_waits_for_write = system_0_burst_27_upstream_in_a_write_cycle & system_0_burst_27_upstream_waitrequest_from_sa;

  //system_0_burst_27_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_27_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_27_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_27_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_27_upstream_counter = 0;
  //system_0_burst_27_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_27_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_27_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_27_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_27_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_27_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_27_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_27/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_27_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_27/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_27_downstream_arbitrator (
                                                 // inputs:
                                                  MS_s1_readdata_from_sa,
                                                  clk,
                                                  d1_MS_s1_end_xfer,
                                                  reset_n,
                                                  system_0_burst_27_downstream_address,
                                                  system_0_burst_27_downstream_burstcount,
                                                  system_0_burst_27_downstream_byteenable,
                                                  system_0_burst_27_downstream_granted_MS_s1,
                                                  system_0_burst_27_downstream_qualified_request_MS_s1,
                                                  system_0_burst_27_downstream_read,
                                                  system_0_burst_27_downstream_read_data_valid_MS_s1,
                                                  system_0_burst_27_downstream_requests_MS_s1,
                                                  system_0_burst_27_downstream_write,
                                                  system_0_burst_27_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_27_downstream_address_to_slave,
                                                  system_0_burst_27_downstream_latency_counter,
                                                  system_0_burst_27_downstream_readdata,
                                                  system_0_burst_27_downstream_readdatavalid,
                                                  system_0_burst_27_downstream_reset_n,
                                                  system_0_burst_27_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_27_downstream_address_to_slave;
  output           system_0_burst_27_downstream_latency_counter;
  output  [  7: 0] system_0_burst_27_downstream_readdata;
  output           system_0_burst_27_downstream_readdatavalid;
  output           system_0_burst_27_downstream_reset_n;
  output           system_0_burst_27_downstream_waitrequest;
  input            MS_s1_readdata_from_sa;
  input            clk;
  input            d1_MS_s1_end_xfer;
  input            reset_n;
  input   [  1: 0] system_0_burst_27_downstream_address;
  input            system_0_burst_27_downstream_burstcount;
  input            system_0_burst_27_downstream_byteenable;
  input            system_0_burst_27_downstream_granted_MS_s1;
  input            system_0_burst_27_downstream_qualified_request_MS_s1;
  input            system_0_burst_27_downstream_read;
  input            system_0_burst_27_downstream_read_data_valid_MS_s1;
  input            system_0_burst_27_downstream_requests_MS_s1;
  input            system_0_burst_27_downstream_write;
  input   [  7: 0] system_0_burst_27_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_27_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_27_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_27_downstream_address_to_slave;
  reg              system_0_burst_27_downstream_burstcount_last_time;
  reg              system_0_burst_27_downstream_byteenable_last_time;
  wire             system_0_burst_27_downstream_latency_counter;
  reg              system_0_burst_27_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_27_downstream_readdata;
  wire             system_0_burst_27_downstream_readdatavalid;
  wire             system_0_burst_27_downstream_reset_n;
  wire             system_0_burst_27_downstream_run;
  wire             system_0_burst_27_downstream_waitrequest;
  reg              system_0_burst_27_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_27_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_27_downstream_qualified_request_MS_s1 | ~system_0_burst_27_downstream_requests_MS_s1) & ((~system_0_burst_27_downstream_qualified_request_MS_s1 | ~system_0_burst_27_downstream_read | (1 & ~d1_MS_s1_end_xfer & system_0_burst_27_downstream_read))) & ((~system_0_burst_27_downstream_qualified_request_MS_s1 | ~system_0_burst_27_downstream_write | (1 & system_0_burst_27_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_27_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_27_downstream_address_to_slave = system_0_burst_27_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_27_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_27_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_27_downstream_readdatavalid |
    system_0_burst_27_downstream_read_data_valid_MS_s1;

  //system_0_burst_27/downstream readdata mux, which is an e_mux
  assign system_0_burst_27_downstream_readdata = MS_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_27_downstream_waitrequest = ~system_0_burst_27_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_27_downstream_latency_counter = 0;

  //system_0_burst_27_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_27_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_27_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_27_downstream_address_last_time <= 0;
      else 
        system_0_burst_27_downstream_address_last_time <= system_0_burst_27_downstream_address;
    end


  //system_0_burst_27/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_27_downstream_waitrequest & (system_0_burst_27_downstream_read | system_0_burst_27_downstream_write);
    end


  //system_0_burst_27_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_27_downstream_address != system_0_burst_27_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_27_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_27_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_27_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_27_downstream_burstcount_last_time <= system_0_burst_27_downstream_burstcount;
    end


  //system_0_burst_27_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_27_downstream_burstcount != system_0_burst_27_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_27_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_27_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_27_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_27_downstream_byteenable_last_time <= system_0_burst_27_downstream_byteenable;
    end


  //system_0_burst_27_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_27_downstream_byteenable != system_0_burst_27_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_27_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_27_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_27_downstream_read_last_time <= 0;
      else 
        system_0_burst_27_downstream_read_last_time <= system_0_burst_27_downstream_read;
    end


  //system_0_burst_27_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_27_downstream_read != system_0_burst_27_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_27_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_27_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_27_downstream_write_last_time <= 0;
      else 
        system_0_burst_27_downstream_write_last_time <= system_0_burst_27_downstream_write;
    end


  //system_0_burst_27_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_27_downstream_write != system_0_burst_27_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_27_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_27_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_27_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_27_downstream_writedata_last_time <= system_0_burst_27_downstream_writedata;
    end


  //system_0_burst_27_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_27_downstream_writedata != system_0_burst_27_downstream_writedata_last_time) & system_0_burst_27_downstream_write)
        begin
          $write("%0d ns: system_0_burst_27_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_28_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_28_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_28_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_28_upstream_readdata,
                                                system_0_burst_28_upstream_readdatavalid,
                                                system_0_burst_28_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_28_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_28_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_28_upstream,
                                                d1_system_0_burst_28_upstream_end_xfer,
                                                system_0_burst_28_upstream_address,
                                                system_0_burst_28_upstream_burstcount,
                                                system_0_burst_28_upstream_byteaddress,
                                                system_0_burst_28_upstream_byteenable,
                                                system_0_burst_28_upstream_debugaccess,
                                                system_0_burst_28_upstream_read,
                                                system_0_burst_28_upstream_readdata_from_sa,
                                                system_0_burst_28_upstream_waitrequest_from_sa,
                                                system_0_burst_28_upstream_write,
                                                system_0_burst_28_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_28_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_28_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_28_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_28_upstream;
  output           d1_system_0_burst_28_upstream_end_xfer;
  output  [  1: 0] system_0_burst_28_upstream_address;
  output  [  3: 0] system_0_burst_28_upstream_burstcount;
  output  [  1: 0] system_0_burst_28_upstream_byteaddress;
  output           system_0_burst_28_upstream_byteenable;
  output           system_0_burst_28_upstream_debugaccess;
  output           system_0_burst_28_upstream_read;
  output  [  7: 0] system_0_burst_28_upstream_readdata_from_sa;
  output           system_0_burst_28_upstream_waitrequest_from_sa;
  output           system_0_burst_28_upstream_write;
  output  [  7: 0] system_0_burst_28_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_28_upstream_readdata;
  input            system_0_burst_28_upstream_readdatavalid;
  input            system_0_burst_28_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_28_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_28_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_28_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_28_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_28_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_28_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_28_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_28_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_28_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_28_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_28_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_28_upstream_address;
  wire             system_0_burst_28_upstream_allgrants;
  wire             system_0_burst_28_upstream_allow_new_arb_cycle;
  wire             system_0_burst_28_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_28_upstream_any_continuerequest;
  wire             system_0_burst_28_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_28_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_28_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_28_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_28_upstream_bbt_burstcounter;
  wire             system_0_burst_28_upstream_beginbursttransfer_internal;
  wire             system_0_burst_28_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_28_upstream_burstcount;
  wire             system_0_burst_28_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_28_upstream_byteaddress;
  wire             system_0_burst_28_upstream_byteenable;
  reg     [  3: 0] system_0_burst_28_upstream_current_burst;
  wire    [  3: 0] system_0_burst_28_upstream_current_burst_minus_one;
  wire             system_0_burst_28_upstream_debugaccess;
  wire             system_0_burst_28_upstream_end_xfer;
  wire             system_0_burst_28_upstream_firsttransfer;
  wire             system_0_burst_28_upstream_grant_vector;
  wire             system_0_burst_28_upstream_in_a_read_cycle;
  wire             system_0_burst_28_upstream_in_a_write_cycle;
  reg              system_0_burst_28_upstream_load_fifo;
  wire             system_0_burst_28_upstream_master_qreq_vector;
  wire             system_0_burst_28_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_28_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_28_upstream_next_burst_count;
  wire             system_0_burst_28_upstream_non_bursting_master_requests;
  wire             system_0_burst_28_upstream_read;
  wire    [  7: 0] system_0_burst_28_upstream_readdata_from_sa;
  wire             system_0_burst_28_upstream_readdatavalid_from_sa;
  reg              system_0_burst_28_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_28_upstream_selected_burstcount;
  reg              system_0_burst_28_upstream_slavearbiterlockenable;
  wire             system_0_burst_28_upstream_slavearbiterlockenable2;
  wire             system_0_burst_28_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_28_upstream_transaction_burst_count;
  wire             system_0_burst_28_upstream_unreg_firsttransfer;
  wire             system_0_burst_28_upstream_waitrequest_from_sa;
  wire             system_0_burst_28_upstream_waits_for_read;
  wire             system_0_burst_28_upstream_waits_for_write;
  wire             system_0_burst_28_upstream_write;
  wire    [  7: 0] system_0_burst_28_upstream_writedata;
  wire             wait_for_system_0_burst_28_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_28_upstream_end_xfer;
    end


  assign system_0_burst_28_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_28_upstream));
  //assign system_0_burst_28_upstream_readdatavalid_from_sa = system_0_burst_28_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_28_upstream_readdatavalid_from_sa = system_0_burst_28_upstream_readdatavalid;

  //assign system_0_burst_28_upstream_readdata_from_sa = system_0_burst_28_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_28_upstream_readdata_from_sa = system_0_burst_28_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_28_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a180) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_28_upstream_waitrequest_from_sa = system_0_burst_28_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_28_upstream_waitrequest_from_sa = system_0_burst_28_upstream_waitrequest;

  //system_0_burst_28_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_28_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_28_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_28_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_28_upstream_non_bursting_master_requests = 0;

  //system_0_burst_28_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_28_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_28_upstream;

  //system_0_burst_28_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_28_upstream_arb_share_counter_next_value = system_0_burst_28_upstream_firsttransfer ? (system_0_burst_28_upstream_arb_share_set_values - 1) : |system_0_burst_28_upstream_arb_share_counter ? (system_0_burst_28_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_28_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_28_upstream_allgrants = |system_0_burst_28_upstream_grant_vector;

  //system_0_burst_28_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_28_upstream_end_xfer = ~(system_0_burst_28_upstream_waits_for_read | system_0_burst_28_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_28_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_28_upstream = system_0_burst_28_upstream_end_xfer & (~system_0_burst_28_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_28_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_28_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_28_upstream & system_0_burst_28_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_28_upstream & ~system_0_burst_28_upstream_non_bursting_master_requests);

  //system_0_burst_28_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_28_upstream_arb_share_counter <= 0;
      else if (system_0_burst_28_upstream_arb_counter_enable)
          system_0_burst_28_upstream_arb_share_counter <= system_0_burst_28_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_28_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_28_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_28_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_28_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_28_upstream & ~system_0_burst_28_upstream_non_bursting_master_requests))
          system_0_burst_28_upstream_slavearbiterlockenable <= |system_0_burst_28_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_28/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_28_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_28_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_28_upstream_slavearbiterlockenable2 = |system_0_burst_28_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_28/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_28_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_28_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_28_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_28_upstream = cpu_0_data_master_requests_system_0_burst_28_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_28_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_28_upstream_move_on_to_next_transaction = system_0_burst_28_upstream_this_cycle_is_the_last_burst & system_0_burst_28_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_28_upstream, which is an e_mux
  assign system_0_burst_28_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_28_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_28_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_28_upstream_module burstcount_fifo_for_system_0_burst_28_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_28_upstream_selected_burstcount),
      .data_out             (system_0_burst_28_upstream_transaction_burst_count),
      .empty                (system_0_burst_28_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_28_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_28_upstream_waits_for_read & system_0_burst_28_upstream_load_fifo & ~(system_0_burst_28_upstream_this_cycle_is_the_last_burst & system_0_burst_28_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_28_upstream current burst minus one, which is an e_assign
  assign system_0_burst_28_upstream_current_burst_minus_one = system_0_burst_28_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_28_upstream, which is an e_mux
  assign system_0_burst_28_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_28_upstream_waits_for_read) & ~system_0_burst_28_upstream_load_fifo))? system_0_burst_28_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_28_upstream_waits_for_read & system_0_burst_28_upstream_this_cycle_is_the_last_burst & system_0_burst_28_upstream_burstcount_fifo_empty))? system_0_burst_28_upstream_selected_burstcount :
    (system_0_burst_28_upstream_this_cycle_is_the_last_burst)? system_0_burst_28_upstream_transaction_burst_count :
    system_0_burst_28_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_28_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_28_upstream_current_burst <= 0;
      else if (system_0_burst_28_upstream_readdatavalid_from_sa | (~system_0_burst_28_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_28_upstream_waits_for_read)))
          system_0_burst_28_upstream_current_burst <= system_0_burst_28_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_28_upstream_load_fifo = (~system_0_burst_28_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_28_upstream_waits_for_read) & system_0_burst_28_upstream_load_fifo))? 1 :
    ~system_0_burst_28_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_28_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_28_upstream_waits_for_read) & ~system_0_burst_28_upstream_load_fifo | system_0_burst_28_upstream_this_cycle_is_the_last_burst)
          system_0_burst_28_upstream_load_fifo <= p0_system_0_burst_28_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_28_upstream, which is an e_assign
  assign system_0_burst_28_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_28_upstream_current_burst_minus_one) & system_0_burst_28_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_28_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_28_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_28_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_28_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_28_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_28_upstream),
      .full                 (),
      .read                 (system_0_burst_28_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_28_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_28_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_28_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_28_upstream = system_0_burst_28_upstream_readdatavalid_from_sa;

  //system_0_burst_28_upstream_writedata mux, which is an e_mux
  assign system_0_burst_28_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_28/upstream, which is an e_mux
  assign system_0_burst_28_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_28_upstream = cpu_0_data_master_qualified_request_system_0_burst_28_upstream;

  //cpu_0/data_master saved-grant system_0_burst_28/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_28_upstream = cpu_0_data_master_requests_system_0_burst_28_upstream;

  //allow new arb cycle for system_0_burst_28/upstream, which is an e_assign
  assign system_0_burst_28_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_28_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_28_upstream_master_qreq_vector = 1;

  //system_0_burst_28_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_28_upstream_firsttransfer = system_0_burst_28_upstream_begins_xfer ? system_0_burst_28_upstream_unreg_firsttransfer : system_0_burst_28_upstream_reg_firsttransfer;

  //system_0_burst_28_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_28_upstream_unreg_firsttransfer = ~(system_0_burst_28_upstream_slavearbiterlockenable & system_0_burst_28_upstream_any_continuerequest);

  //system_0_burst_28_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_28_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_28_upstream_begins_xfer)
          system_0_burst_28_upstream_reg_firsttransfer <= system_0_burst_28_upstream_unreg_firsttransfer;
    end


  //system_0_burst_28_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_28_upstream_next_bbt_burstcount = ((((system_0_burst_28_upstream_write) && (system_0_burst_28_upstream_bbt_burstcounter == 0))))? (system_0_burst_28_upstream_burstcount - 1) :
    ((((system_0_burst_28_upstream_read) && (system_0_burst_28_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_28_upstream_bbt_burstcounter - 1);

  //system_0_burst_28_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_28_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_28_upstream_begins_xfer)
          system_0_burst_28_upstream_bbt_burstcounter <= system_0_burst_28_upstream_next_bbt_burstcount;
    end


  //system_0_burst_28_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_28_upstream_beginbursttransfer_internal = system_0_burst_28_upstream_begins_xfer & (system_0_burst_28_upstream_bbt_burstcounter == 0);

  //system_0_burst_28_upstream_read assignment, which is an e_mux
  assign system_0_burst_28_upstream_read = cpu_0_data_master_granted_system_0_burst_28_upstream & cpu_0_data_master_read;

  //system_0_burst_28_upstream_write assignment, which is an e_mux
  assign system_0_burst_28_upstream_write = cpu_0_data_master_granted_system_0_burst_28_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_28_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_28_upstream_address mux, which is an e_mux
  assign system_0_burst_28_upstream_address = shifted_address_to_system_0_burst_28_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_28_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_28_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_28_upstream_end_xfer <= system_0_burst_28_upstream_end_xfer;
    end


  //system_0_burst_28_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_28_upstream_waits_for_read = system_0_burst_28_upstream_in_a_read_cycle & system_0_burst_28_upstream_waitrequest_from_sa;

  //system_0_burst_28_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_28_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_28_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_28_upstream_in_a_read_cycle;

  //system_0_burst_28_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_28_upstream_waits_for_write = system_0_burst_28_upstream_in_a_write_cycle & system_0_burst_28_upstream_waitrequest_from_sa;

  //system_0_burst_28_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_28_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_28_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_28_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_28_upstream_counter = 0;
  //system_0_burst_28_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_28_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_28_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_28_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_28_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_28_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_28_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_28/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_28_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_28/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_28_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_dist_sensor_s1_end_xfer,
                                                  dist_sensor_s1_readdata_from_sa,
                                                  reset_n,
                                                  system_0_burst_28_downstream_address,
                                                  system_0_burst_28_downstream_burstcount,
                                                  system_0_burst_28_downstream_byteenable,
                                                  system_0_burst_28_downstream_granted_dist_sensor_s1,
                                                  system_0_burst_28_downstream_qualified_request_dist_sensor_s1,
                                                  system_0_burst_28_downstream_read,
                                                  system_0_burst_28_downstream_read_data_valid_dist_sensor_s1,
                                                  system_0_burst_28_downstream_requests_dist_sensor_s1,
                                                  system_0_burst_28_downstream_write,
                                                  system_0_burst_28_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_28_downstream_address_to_slave,
                                                  system_0_burst_28_downstream_latency_counter,
                                                  system_0_burst_28_downstream_readdata,
                                                  system_0_burst_28_downstream_readdatavalid,
                                                  system_0_burst_28_downstream_reset_n,
                                                  system_0_burst_28_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_28_downstream_address_to_slave;
  output           system_0_burst_28_downstream_latency_counter;
  output  [  7: 0] system_0_burst_28_downstream_readdata;
  output           system_0_burst_28_downstream_readdatavalid;
  output           system_0_burst_28_downstream_reset_n;
  output           system_0_burst_28_downstream_waitrequest;
  input            clk;
  input            d1_dist_sensor_s1_end_xfer;
  input            dist_sensor_s1_readdata_from_sa;
  input            reset_n;
  input   [  1: 0] system_0_burst_28_downstream_address;
  input            system_0_burst_28_downstream_burstcount;
  input            system_0_burst_28_downstream_byteenable;
  input            system_0_burst_28_downstream_granted_dist_sensor_s1;
  input            system_0_burst_28_downstream_qualified_request_dist_sensor_s1;
  input            system_0_burst_28_downstream_read;
  input            system_0_burst_28_downstream_read_data_valid_dist_sensor_s1;
  input            system_0_burst_28_downstream_requests_dist_sensor_s1;
  input            system_0_burst_28_downstream_write;
  input   [  7: 0] system_0_burst_28_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_28_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_28_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_28_downstream_address_to_slave;
  reg              system_0_burst_28_downstream_burstcount_last_time;
  reg              system_0_burst_28_downstream_byteenable_last_time;
  wire             system_0_burst_28_downstream_latency_counter;
  reg              system_0_burst_28_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_28_downstream_readdata;
  wire             system_0_burst_28_downstream_readdatavalid;
  wire             system_0_burst_28_downstream_reset_n;
  wire             system_0_burst_28_downstream_run;
  wire             system_0_burst_28_downstream_waitrequest;
  reg              system_0_burst_28_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_28_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_28_downstream_qualified_request_dist_sensor_s1 | ~system_0_burst_28_downstream_requests_dist_sensor_s1) & ((~system_0_burst_28_downstream_qualified_request_dist_sensor_s1 | ~system_0_burst_28_downstream_read | (1 & ~d1_dist_sensor_s1_end_xfer & system_0_burst_28_downstream_read))) & ((~system_0_burst_28_downstream_qualified_request_dist_sensor_s1 | ~system_0_burst_28_downstream_write | (1 & system_0_burst_28_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_28_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_28_downstream_address_to_slave = system_0_burst_28_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_28_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_28_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_28_downstream_readdatavalid |
    system_0_burst_28_downstream_read_data_valid_dist_sensor_s1;

  //system_0_burst_28/downstream readdata mux, which is an e_mux
  assign system_0_burst_28_downstream_readdata = dist_sensor_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_28_downstream_waitrequest = ~system_0_burst_28_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_28_downstream_latency_counter = 0;

  //system_0_burst_28_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_28_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_28_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_28_downstream_address_last_time <= 0;
      else 
        system_0_burst_28_downstream_address_last_time <= system_0_burst_28_downstream_address;
    end


  //system_0_burst_28/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_28_downstream_waitrequest & (system_0_burst_28_downstream_read | system_0_burst_28_downstream_write);
    end


  //system_0_burst_28_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_28_downstream_address != system_0_burst_28_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_28_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_28_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_28_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_28_downstream_burstcount_last_time <= system_0_burst_28_downstream_burstcount;
    end


  //system_0_burst_28_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_28_downstream_burstcount != system_0_burst_28_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_28_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_28_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_28_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_28_downstream_byteenable_last_time <= system_0_burst_28_downstream_byteenable;
    end


  //system_0_burst_28_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_28_downstream_byteenable != system_0_burst_28_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_28_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_28_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_28_downstream_read_last_time <= 0;
      else 
        system_0_burst_28_downstream_read_last_time <= system_0_burst_28_downstream_read;
    end


  //system_0_burst_28_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_28_downstream_read != system_0_burst_28_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_28_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_28_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_28_downstream_write_last_time <= 0;
      else 
        system_0_burst_28_downstream_write_last_time <= system_0_burst_28_downstream_write;
    end


  //system_0_burst_28_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_28_downstream_write != system_0_burst_28_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_28_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_28_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_28_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_28_downstream_writedata_last_time <= system_0_burst_28_downstream_writedata;
    end


  //system_0_burst_28_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_28_downstream_writedata != system_0_burst_28_downstream_writedata_last_time) & system_0_burst_28_downstream_write)
        begin
          $write("%0d ns: system_0_burst_28_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_29_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_29_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_29_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_29_upstream_readdata,
                                                system_0_burst_29_upstream_readdatavalid,
                                                system_0_burst_29_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_29_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_29_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_29_upstream,
                                                d1_system_0_burst_29_upstream_end_xfer,
                                                system_0_burst_29_upstream_address,
                                                system_0_burst_29_upstream_burstcount,
                                                system_0_burst_29_upstream_byteaddress,
                                                system_0_burst_29_upstream_byteenable,
                                                system_0_burst_29_upstream_debugaccess,
                                                system_0_burst_29_upstream_read,
                                                system_0_burst_29_upstream_readdata_from_sa,
                                                system_0_burst_29_upstream_waitrequest_from_sa,
                                                system_0_burst_29_upstream_write,
                                                system_0_burst_29_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_29_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_29_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_29_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_29_upstream;
  output           d1_system_0_burst_29_upstream_end_xfer;
  output  [  1: 0] system_0_burst_29_upstream_address;
  output  [  3: 0] system_0_burst_29_upstream_burstcount;
  output  [  1: 0] system_0_burst_29_upstream_byteaddress;
  output           system_0_burst_29_upstream_byteenable;
  output           system_0_burst_29_upstream_debugaccess;
  output           system_0_burst_29_upstream_read;
  output  [  7: 0] system_0_burst_29_upstream_readdata_from_sa;
  output           system_0_burst_29_upstream_waitrequest_from_sa;
  output           system_0_burst_29_upstream_write;
  output  [  7: 0] system_0_burst_29_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_29_upstream_readdata;
  input            system_0_burst_29_upstream_readdatavalid;
  input            system_0_burst_29_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_29_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_29_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_29_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_29_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_29_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_29_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_29_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_29_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_29_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_29_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_29_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_29_upstream_address;
  wire             system_0_burst_29_upstream_allgrants;
  wire             system_0_burst_29_upstream_allow_new_arb_cycle;
  wire             system_0_burst_29_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_29_upstream_any_continuerequest;
  wire             system_0_burst_29_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_29_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_29_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_29_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_29_upstream_bbt_burstcounter;
  wire             system_0_burst_29_upstream_beginbursttransfer_internal;
  wire             system_0_burst_29_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_29_upstream_burstcount;
  wire             system_0_burst_29_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_29_upstream_byteaddress;
  wire             system_0_burst_29_upstream_byteenable;
  reg     [  3: 0] system_0_burst_29_upstream_current_burst;
  wire    [  3: 0] system_0_burst_29_upstream_current_burst_minus_one;
  wire             system_0_burst_29_upstream_debugaccess;
  wire             system_0_burst_29_upstream_end_xfer;
  wire             system_0_burst_29_upstream_firsttransfer;
  wire             system_0_burst_29_upstream_grant_vector;
  wire             system_0_burst_29_upstream_in_a_read_cycle;
  wire             system_0_burst_29_upstream_in_a_write_cycle;
  reg              system_0_burst_29_upstream_load_fifo;
  wire             system_0_burst_29_upstream_master_qreq_vector;
  wire             system_0_burst_29_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_29_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_29_upstream_next_burst_count;
  wire             system_0_burst_29_upstream_non_bursting_master_requests;
  wire             system_0_burst_29_upstream_read;
  wire    [  7: 0] system_0_burst_29_upstream_readdata_from_sa;
  wire             system_0_burst_29_upstream_readdatavalid_from_sa;
  reg              system_0_burst_29_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_29_upstream_selected_burstcount;
  reg              system_0_burst_29_upstream_slavearbiterlockenable;
  wire             system_0_burst_29_upstream_slavearbiterlockenable2;
  wire             system_0_burst_29_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_29_upstream_transaction_burst_count;
  wire             system_0_burst_29_upstream_unreg_firsttransfer;
  wire             system_0_burst_29_upstream_waitrequest_from_sa;
  wire             system_0_burst_29_upstream_waits_for_read;
  wire             system_0_burst_29_upstream_waits_for_write;
  wire             system_0_burst_29_upstream_write;
  wire    [  7: 0] system_0_burst_29_upstream_writedata;
  wire             wait_for_system_0_burst_29_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_29_upstream_end_xfer;
    end


  assign system_0_burst_29_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_29_upstream));
  //assign system_0_burst_29_upstream_readdatavalid_from_sa = system_0_burst_29_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_29_upstream_readdatavalid_from_sa = system_0_burst_29_upstream_readdatavalid;

  //assign system_0_burst_29_upstream_readdata_from_sa = system_0_burst_29_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_29_upstream_readdata_from_sa = system_0_burst_29_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_29_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a190) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_29_upstream_waitrequest_from_sa = system_0_burst_29_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_29_upstream_waitrequest_from_sa = system_0_burst_29_upstream_waitrequest;

  //system_0_burst_29_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_29_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_29_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_29_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_29_upstream_non_bursting_master_requests = 0;

  //system_0_burst_29_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_29_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_29_upstream;

  //system_0_burst_29_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_29_upstream_arb_share_counter_next_value = system_0_burst_29_upstream_firsttransfer ? (system_0_burst_29_upstream_arb_share_set_values - 1) : |system_0_burst_29_upstream_arb_share_counter ? (system_0_burst_29_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_29_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_29_upstream_allgrants = |system_0_burst_29_upstream_grant_vector;

  //system_0_burst_29_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_29_upstream_end_xfer = ~(system_0_burst_29_upstream_waits_for_read | system_0_burst_29_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_29_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_29_upstream = system_0_burst_29_upstream_end_xfer & (~system_0_burst_29_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_29_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_29_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_29_upstream & system_0_burst_29_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_29_upstream & ~system_0_burst_29_upstream_non_bursting_master_requests);

  //system_0_burst_29_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_29_upstream_arb_share_counter <= 0;
      else if (system_0_burst_29_upstream_arb_counter_enable)
          system_0_burst_29_upstream_arb_share_counter <= system_0_burst_29_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_29_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_29_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_29_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_29_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_29_upstream & ~system_0_burst_29_upstream_non_bursting_master_requests))
          system_0_burst_29_upstream_slavearbiterlockenable <= |system_0_burst_29_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_29/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_29_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_29_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_29_upstream_slavearbiterlockenable2 = |system_0_burst_29_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_29/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_29_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_29_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_29_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_29_upstream = cpu_0_data_master_requests_system_0_burst_29_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_29_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_29_upstream_move_on_to_next_transaction = system_0_burst_29_upstream_this_cycle_is_the_last_burst & system_0_burst_29_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_29_upstream, which is an e_mux
  assign system_0_burst_29_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_29_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_29_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_29_upstream_module burstcount_fifo_for_system_0_burst_29_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_29_upstream_selected_burstcount),
      .data_out             (system_0_burst_29_upstream_transaction_burst_count),
      .empty                (system_0_burst_29_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_29_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_29_upstream_waits_for_read & system_0_burst_29_upstream_load_fifo & ~(system_0_burst_29_upstream_this_cycle_is_the_last_burst & system_0_burst_29_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_29_upstream current burst minus one, which is an e_assign
  assign system_0_burst_29_upstream_current_burst_minus_one = system_0_burst_29_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_29_upstream, which is an e_mux
  assign system_0_burst_29_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_29_upstream_waits_for_read) & ~system_0_burst_29_upstream_load_fifo))? system_0_burst_29_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_29_upstream_waits_for_read & system_0_burst_29_upstream_this_cycle_is_the_last_burst & system_0_burst_29_upstream_burstcount_fifo_empty))? system_0_burst_29_upstream_selected_burstcount :
    (system_0_burst_29_upstream_this_cycle_is_the_last_burst)? system_0_burst_29_upstream_transaction_burst_count :
    system_0_burst_29_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_29_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_29_upstream_current_burst <= 0;
      else if (system_0_burst_29_upstream_readdatavalid_from_sa | (~system_0_burst_29_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_29_upstream_waits_for_read)))
          system_0_burst_29_upstream_current_burst <= system_0_burst_29_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_29_upstream_load_fifo = (~system_0_burst_29_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_29_upstream_waits_for_read) & system_0_burst_29_upstream_load_fifo))? 1 :
    ~system_0_burst_29_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_29_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_29_upstream_waits_for_read) & ~system_0_burst_29_upstream_load_fifo | system_0_burst_29_upstream_this_cycle_is_the_last_burst)
          system_0_burst_29_upstream_load_fifo <= p0_system_0_burst_29_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_29_upstream, which is an e_assign
  assign system_0_burst_29_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_29_upstream_current_burst_minus_one) & system_0_burst_29_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_29_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_29_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_29_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_29_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_29_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_29_upstream),
      .full                 (),
      .read                 (system_0_burst_29_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_29_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_29_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_29_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_29_upstream = system_0_burst_29_upstream_readdatavalid_from_sa;

  //system_0_burst_29_upstream_writedata mux, which is an e_mux
  assign system_0_burst_29_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_29/upstream, which is an e_mux
  assign system_0_burst_29_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_29_upstream = cpu_0_data_master_qualified_request_system_0_burst_29_upstream;

  //cpu_0/data_master saved-grant system_0_burst_29/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_29_upstream = cpu_0_data_master_requests_system_0_burst_29_upstream;

  //allow new arb cycle for system_0_burst_29/upstream, which is an e_assign
  assign system_0_burst_29_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_29_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_29_upstream_master_qreq_vector = 1;

  //system_0_burst_29_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_29_upstream_firsttransfer = system_0_burst_29_upstream_begins_xfer ? system_0_burst_29_upstream_unreg_firsttransfer : system_0_burst_29_upstream_reg_firsttransfer;

  //system_0_burst_29_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_29_upstream_unreg_firsttransfer = ~(system_0_burst_29_upstream_slavearbiterlockenable & system_0_burst_29_upstream_any_continuerequest);

  //system_0_burst_29_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_29_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_29_upstream_begins_xfer)
          system_0_burst_29_upstream_reg_firsttransfer <= system_0_burst_29_upstream_unreg_firsttransfer;
    end


  //system_0_burst_29_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_29_upstream_next_bbt_burstcount = ((((system_0_burst_29_upstream_write) && (system_0_burst_29_upstream_bbt_burstcounter == 0))))? (system_0_burst_29_upstream_burstcount - 1) :
    ((((system_0_burst_29_upstream_read) && (system_0_burst_29_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_29_upstream_bbt_burstcounter - 1);

  //system_0_burst_29_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_29_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_29_upstream_begins_xfer)
          system_0_burst_29_upstream_bbt_burstcounter <= system_0_burst_29_upstream_next_bbt_burstcount;
    end


  //system_0_burst_29_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_29_upstream_beginbursttransfer_internal = system_0_burst_29_upstream_begins_xfer & (system_0_burst_29_upstream_bbt_burstcounter == 0);

  //system_0_burst_29_upstream_read assignment, which is an e_mux
  assign system_0_burst_29_upstream_read = cpu_0_data_master_granted_system_0_burst_29_upstream & cpu_0_data_master_read;

  //system_0_burst_29_upstream_write assignment, which is an e_mux
  assign system_0_burst_29_upstream_write = cpu_0_data_master_granted_system_0_burst_29_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_29_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_29_upstream_address mux, which is an e_mux
  assign system_0_burst_29_upstream_address = shifted_address_to_system_0_burst_29_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_29_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_29_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_29_upstream_end_xfer <= system_0_burst_29_upstream_end_xfer;
    end


  //system_0_burst_29_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_29_upstream_waits_for_read = system_0_burst_29_upstream_in_a_read_cycle & system_0_burst_29_upstream_waitrequest_from_sa;

  //system_0_burst_29_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_29_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_29_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_29_upstream_in_a_read_cycle;

  //system_0_burst_29_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_29_upstream_waits_for_write = system_0_burst_29_upstream_in_a_write_cycle & system_0_burst_29_upstream_waitrequest_from_sa;

  //system_0_burst_29_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_29_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_29_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_29_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_29_upstream_counter = 0;
  //system_0_burst_29_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_29_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_29_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_29_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_29_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_29_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_29_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_29/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_29_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_29/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_29_downstream_arbitrator (
                                                 // inputs:
                                                  RST_s1_readdata_from_sa,
                                                  clk,
                                                  d1_RST_s1_end_xfer,
                                                  reset_n,
                                                  system_0_burst_29_downstream_address,
                                                  system_0_burst_29_downstream_burstcount,
                                                  system_0_burst_29_downstream_byteenable,
                                                  system_0_burst_29_downstream_granted_RST_s1,
                                                  system_0_burst_29_downstream_qualified_request_RST_s1,
                                                  system_0_burst_29_downstream_read,
                                                  system_0_burst_29_downstream_read_data_valid_RST_s1,
                                                  system_0_burst_29_downstream_requests_RST_s1,
                                                  system_0_burst_29_downstream_write,
                                                  system_0_burst_29_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_29_downstream_address_to_slave,
                                                  system_0_burst_29_downstream_latency_counter,
                                                  system_0_burst_29_downstream_readdata,
                                                  system_0_burst_29_downstream_readdatavalid,
                                                  system_0_burst_29_downstream_reset_n,
                                                  system_0_burst_29_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_29_downstream_address_to_slave;
  output           system_0_burst_29_downstream_latency_counter;
  output  [  7: 0] system_0_burst_29_downstream_readdata;
  output           system_0_burst_29_downstream_readdatavalid;
  output           system_0_burst_29_downstream_reset_n;
  output           system_0_burst_29_downstream_waitrequest;
  input            RST_s1_readdata_from_sa;
  input            clk;
  input            d1_RST_s1_end_xfer;
  input            reset_n;
  input   [  1: 0] system_0_burst_29_downstream_address;
  input            system_0_burst_29_downstream_burstcount;
  input            system_0_burst_29_downstream_byteenable;
  input            system_0_burst_29_downstream_granted_RST_s1;
  input            system_0_burst_29_downstream_qualified_request_RST_s1;
  input            system_0_burst_29_downstream_read;
  input            system_0_burst_29_downstream_read_data_valid_RST_s1;
  input            system_0_burst_29_downstream_requests_RST_s1;
  input            system_0_burst_29_downstream_write;
  input   [  7: 0] system_0_burst_29_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_29_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_29_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_29_downstream_address_to_slave;
  reg              system_0_burst_29_downstream_burstcount_last_time;
  reg              system_0_burst_29_downstream_byteenable_last_time;
  wire             system_0_burst_29_downstream_latency_counter;
  reg              system_0_burst_29_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_29_downstream_readdata;
  wire             system_0_burst_29_downstream_readdatavalid;
  wire             system_0_burst_29_downstream_reset_n;
  wire             system_0_burst_29_downstream_run;
  wire             system_0_burst_29_downstream_waitrequest;
  reg              system_0_burst_29_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_29_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_29_downstream_qualified_request_RST_s1 | ~system_0_burst_29_downstream_requests_RST_s1) & ((~system_0_burst_29_downstream_qualified_request_RST_s1 | ~system_0_burst_29_downstream_read | (1 & ~d1_RST_s1_end_xfer & system_0_burst_29_downstream_read))) & ((~system_0_burst_29_downstream_qualified_request_RST_s1 | ~system_0_burst_29_downstream_write | (1 & system_0_burst_29_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_29_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_29_downstream_address_to_slave = system_0_burst_29_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_29_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_29_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_29_downstream_readdatavalid |
    system_0_burst_29_downstream_read_data_valid_RST_s1;

  //system_0_burst_29/downstream readdata mux, which is an e_mux
  assign system_0_burst_29_downstream_readdata = RST_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_29_downstream_waitrequest = ~system_0_burst_29_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_29_downstream_latency_counter = 0;

  //system_0_burst_29_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_29_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_29_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_29_downstream_address_last_time <= 0;
      else 
        system_0_burst_29_downstream_address_last_time <= system_0_burst_29_downstream_address;
    end


  //system_0_burst_29/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_29_downstream_waitrequest & (system_0_burst_29_downstream_read | system_0_burst_29_downstream_write);
    end


  //system_0_burst_29_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_29_downstream_address != system_0_burst_29_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_29_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_29_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_29_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_29_downstream_burstcount_last_time <= system_0_burst_29_downstream_burstcount;
    end


  //system_0_burst_29_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_29_downstream_burstcount != system_0_burst_29_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_29_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_29_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_29_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_29_downstream_byteenable_last_time <= system_0_burst_29_downstream_byteenable;
    end


  //system_0_burst_29_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_29_downstream_byteenable != system_0_burst_29_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_29_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_29_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_29_downstream_read_last_time <= 0;
      else 
        system_0_burst_29_downstream_read_last_time <= system_0_burst_29_downstream_read;
    end


  //system_0_burst_29_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_29_downstream_read != system_0_burst_29_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_29_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_29_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_29_downstream_write_last_time <= 0;
      else 
        system_0_burst_29_downstream_write_last_time <= system_0_burst_29_downstream_write;
    end


  //system_0_burst_29_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_29_downstream_write != system_0_burst_29_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_29_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_29_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_29_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_29_downstream_writedata_last_time <= system_0_burst_29_downstream_writedata;
    end


  //system_0_burst_29_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_29_downstream_writedata != system_0_burst_29_downstream_writedata_last_time) & system_0_burst_29_downstream_write)
        begin
          $write("%0d ns: system_0_burst_29_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_3_upstream_module (
                                                              // inputs:
                                                               clear_fifo,
                                                               clk,
                                                               data_in,
                                                               read,
                                                               reset_n,
                                                               sync_reset,
                                                               write,

                                                              // outputs:
                                                               data_out,
                                                               empty,
                                                               fifo_contains_ones_n,
                                                               full
                                                            )
;

  output  [  5: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  5: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  5: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  reg              full_2;
  reg              full_3;
  wire             full_4;
  reg     [  3: 0] how_many_ones;
  wire    [  3: 0] one_count_minus_one;
  wire    [  3: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  5: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  5: 0] p1_stage_1;
  wire             p2_full_2;
  wire    [  5: 0] p2_stage_2;
  wire             p3_full_3;
  wire    [  5: 0] p3_stage_3;
  reg     [  5: 0] stage_0;
  reg     [  5: 0] stage_1;
  reg     [  5: 0] stage_2;
  reg     [  5: 0] stage_3;
  wire    [  3: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_3;
  assign empty = !full_0;
  assign full_4 = 0;
  //data_3, which is an e_mux
  assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_3 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_3))
          if (sync_reset & full_3 & !((full_4 == 0) & read & write))
              stage_3 <= 0;
          else 
            stage_3 <= p3_stage_3;
    end


  //control_3, which is an e_mux
  assign p3_full_3 = ((read & !write) == 0)? full_2 :
    0;

  //control_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_3_upstream_module (
                                                                            // inputs:
                                                                             clear_fifo,
                                                                             clk,
                                                                             data_in,
                                                                             read,
                                                                             reset_n,
                                                                             sync_reset,
                                                                             write,

                                                                            // outputs:
                                                                             data_out,
                                                                             empty,
                                                                             fifo_contains_ones_n,
                                                                             full
                                                                          )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  reg              full_2;
  reg              full_3;
  wire             full_4;
  reg     [  3: 0] how_many_ones;
  wire    [  3: 0] one_count_minus_one;
  wire    [  3: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  wire             p2_full_2;
  wire             p2_stage_2;
  wire             p3_full_3;
  wire             p3_stage_3;
  reg              stage_0;
  reg              stage_1;
  reg              stage_2;
  reg              stage_3;
  wire    [  3: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_3;
  assign empty = !full_0;
  assign full_4 = 0;
  //data_3, which is an e_mux
  assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_3 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_3))
          if (sync_reset & full_3 & !((full_4 == 0) & read & write))
              stage_3 <= 0;
          else 
            stage_3 <= p3_stage_3;
    end


  //control_3, which is an e_mux
  assign p3_full_3 = ((read & !write) == 0)? full_2 :
    0;

  //control_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_3_upstream_arbitrator (
                                              // inputs:
                                               clk,
                                               cpu_0_data_master_address_to_slave,
                                               cpu_0_data_master_burstcount,
                                               cpu_0_data_master_byteenable,
                                               cpu_0_data_master_dbs_address,
                                               cpu_0_data_master_dbs_write_8,
                                               cpu_0_data_master_debugaccess,
                                               cpu_0_data_master_latency_counter,
                                               cpu_0_data_master_read,
                                               cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                               cpu_0_data_master_write,
                                               reset_n,
                                               system_0_burst_3_upstream_readdata,
                                               system_0_burst_3_upstream_readdatavalid,
                                               system_0_burst_3_upstream_waitrequest,

                                              // outputs:
                                               cpu_0_data_master_byteenable_system_0_burst_3_upstream,
                                               cpu_0_data_master_granted_system_0_burst_3_upstream,
                                               cpu_0_data_master_qualified_request_system_0_burst_3_upstream,
                                               cpu_0_data_master_read_data_valid_system_0_burst_3_upstream,
                                               cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                               cpu_0_data_master_requests_system_0_burst_3_upstream,
                                               d1_system_0_burst_3_upstream_end_xfer,
                                               system_0_burst_3_upstream_address,
                                               system_0_burst_3_upstream_burstcount,
                                               system_0_burst_3_upstream_byteaddress,
                                               system_0_burst_3_upstream_byteenable,
                                               system_0_burst_3_upstream_debugaccess,
                                               system_0_burst_3_upstream_read,
                                               system_0_burst_3_upstream_readdata_from_sa,
                                               system_0_burst_3_upstream_waitrequest_from_sa,
                                               system_0_burst_3_upstream_write,
                                               system_0_burst_3_upstream_writedata
                                            )
;

  output           cpu_0_data_master_byteenable_system_0_burst_3_upstream;
  output           cpu_0_data_master_granted_system_0_burst_3_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_3_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_3_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_3_upstream;
  output           d1_system_0_burst_3_upstream_end_xfer;
  output  [ 21: 0] system_0_burst_3_upstream_address;
  output  [  3: 0] system_0_burst_3_upstream_burstcount;
  output  [ 21: 0] system_0_burst_3_upstream_byteaddress;
  output           system_0_burst_3_upstream_byteenable;
  output           system_0_burst_3_upstream_debugaccess;
  output           system_0_burst_3_upstream_read;
  output  [  7: 0] system_0_burst_3_upstream_readdata_from_sa;
  output           system_0_burst_3_upstream_waitrequest_from_sa;
  output           system_0_burst_3_upstream_write;
  output  [  7: 0] system_0_burst_3_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input   [  1: 0] cpu_0_data_master_dbs_address;
  input   [  7: 0] cpu_0_data_master_dbs_write_8;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input            reset_n;
  input   [  7: 0] system_0_burst_3_upstream_readdata;
  input            system_0_burst_3_upstream_readdatavalid;
  input            system_0_burst_3_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_byteenable_system_0_burst_3_upstream;
  wire             cpu_0_data_master_byteenable_system_0_burst_3_upstream_segment_0;
  wire             cpu_0_data_master_byteenable_system_0_burst_3_upstream_segment_1;
  wire             cpu_0_data_master_byteenable_system_0_burst_3_upstream_segment_2;
  wire             cpu_0_data_master_byteenable_system_0_burst_3_upstream_segment_3;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_3_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_3_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_3_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_3_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_3_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_3_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_3_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_3_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_3_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_3_upstream_load_fifo;
  wire    [ 21: 0] system_0_burst_3_upstream_address;
  wire             system_0_burst_3_upstream_allgrants;
  wire             system_0_burst_3_upstream_allow_new_arb_cycle;
  wire             system_0_burst_3_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_3_upstream_any_continuerequest;
  wire             system_0_burst_3_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_3_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_3_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_3_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_3_upstream_bbt_burstcounter;
  wire             system_0_burst_3_upstream_beginbursttransfer_internal;
  wire             system_0_burst_3_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_3_upstream_burstcount;
  wire             system_0_burst_3_upstream_burstcount_fifo_empty;
  wire    [ 21: 0] system_0_burst_3_upstream_byteaddress;
  wire             system_0_burst_3_upstream_byteenable;
  reg     [  5: 0] system_0_burst_3_upstream_current_burst;
  wire    [  5: 0] system_0_burst_3_upstream_current_burst_minus_one;
  wire             system_0_burst_3_upstream_debugaccess;
  wire             system_0_burst_3_upstream_end_xfer;
  wire             system_0_burst_3_upstream_firsttransfer;
  wire             system_0_burst_3_upstream_grant_vector;
  wire             system_0_burst_3_upstream_in_a_read_cycle;
  wire             system_0_burst_3_upstream_in_a_write_cycle;
  reg              system_0_burst_3_upstream_load_fifo;
  wire             system_0_burst_3_upstream_master_qreq_vector;
  wire             system_0_burst_3_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_3_upstream_next_bbt_burstcount;
  wire    [  5: 0] system_0_burst_3_upstream_next_burst_count;
  wire             system_0_burst_3_upstream_non_bursting_master_requests;
  wire             system_0_burst_3_upstream_read;
  wire    [  7: 0] system_0_burst_3_upstream_readdata_from_sa;
  wire             system_0_burst_3_upstream_readdatavalid_from_sa;
  reg              system_0_burst_3_upstream_reg_firsttransfer;
  wire    [  5: 0] system_0_burst_3_upstream_selected_burstcount;
  reg              system_0_burst_3_upstream_slavearbiterlockenable;
  wire             system_0_burst_3_upstream_slavearbiterlockenable2;
  wire             system_0_burst_3_upstream_this_cycle_is_the_last_burst;
  wire    [  5: 0] system_0_burst_3_upstream_transaction_burst_count;
  wire             system_0_burst_3_upstream_unreg_firsttransfer;
  wire             system_0_burst_3_upstream_waitrequest_from_sa;
  wire             system_0_burst_3_upstream_waits_for_read;
  wire             system_0_burst_3_upstream_waits_for_write;
  wire             system_0_burst_3_upstream_write;
  wire    [  7: 0] system_0_burst_3_upstream_writedata;
  wire             wait_for_system_0_burst_3_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_3_upstream_end_xfer;
    end


  assign system_0_burst_3_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_3_upstream));
  //assign system_0_burst_3_upstream_readdatavalid_from_sa = system_0_burst_3_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_3_upstream_readdatavalid_from_sa = system_0_burst_3_upstream_readdatavalid;

  //assign system_0_burst_3_upstream_readdata_from_sa = system_0_burst_3_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_3_upstream_readdata_from_sa = system_0_burst_3_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_3_upstream = ({cpu_0_data_master_address_to_slave[24 : 22] , 22'b0} == 25'h1400000) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_3_upstream_waitrequest_from_sa = system_0_burst_3_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_3_upstream_waitrequest_from_sa = system_0_burst_3_upstream_waitrequest;

  //system_0_burst_3_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_3_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_3_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount<< 2 : 1)) :
    1;

  //system_0_burst_3_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_3_upstream_non_bursting_master_requests = 0;

  //system_0_burst_3_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_3_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_3_upstream;

  //system_0_burst_3_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_3_upstream_arb_share_counter_next_value = system_0_burst_3_upstream_firsttransfer ? (system_0_burst_3_upstream_arb_share_set_values - 1) : |system_0_burst_3_upstream_arb_share_counter ? (system_0_burst_3_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_3_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_3_upstream_allgrants = |system_0_burst_3_upstream_grant_vector;

  //system_0_burst_3_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_3_upstream_end_xfer = ~(system_0_burst_3_upstream_waits_for_read | system_0_burst_3_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_3_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_3_upstream = system_0_burst_3_upstream_end_xfer & (~system_0_burst_3_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_3_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_3_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_3_upstream & system_0_burst_3_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_3_upstream & ~system_0_burst_3_upstream_non_bursting_master_requests);

  //system_0_burst_3_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_3_upstream_arb_share_counter <= 0;
      else if (system_0_burst_3_upstream_arb_counter_enable)
          system_0_burst_3_upstream_arb_share_counter <= system_0_burst_3_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_3_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_3_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_3_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_3_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_3_upstream & ~system_0_burst_3_upstream_non_bursting_master_requests))
          system_0_burst_3_upstream_slavearbiterlockenable <= |system_0_burst_3_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_3/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_3_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_3_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_3_upstream_slavearbiterlockenable2 = |system_0_burst_3_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_3/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_3_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_3_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_3_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_3_upstream = cpu_0_data_master_requests_system_0_burst_3_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_3_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_3_upstream_move_on_to_next_transaction = system_0_burst_3_upstream_this_cycle_is_the_last_burst & system_0_burst_3_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_3_upstream, which is an e_mux
  assign system_0_burst_3_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_3_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_3_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_3_upstream_module burstcount_fifo_for_system_0_burst_3_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_3_upstream_selected_burstcount),
      .data_out             (system_0_burst_3_upstream_transaction_burst_count),
      .empty                (system_0_burst_3_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_3_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_3_upstream_waits_for_read & system_0_burst_3_upstream_load_fifo & ~(system_0_burst_3_upstream_this_cycle_is_the_last_burst & system_0_burst_3_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_3_upstream current burst minus one, which is an e_assign
  assign system_0_burst_3_upstream_current_burst_minus_one = system_0_burst_3_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_3_upstream, which is an e_mux
  assign system_0_burst_3_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_3_upstream_waits_for_read) & ~system_0_burst_3_upstream_load_fifo))? {system_0_burst_3_upstream_selected_burstcount, 2'b0} :
    ((in_a_read_cycle & ~system_0_burst_3_upstream_waits_for_read & system_0_burst_3_upstream_this_cycle_is_the_last_burst & system_0_burst_3_upstream_burstcount_fifo_empty))? {system_0_burst_3_upstream_selected_burstcount, 2'b0} :
    (system_0_burst_3_upstream_this_cycle_is_the_last_burst)? {system_0_burst_3_upstream_transaction_burst_count,  2'b0} :
    system_0_burst_3_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_3_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_3_upstream_current_burst <= 0;
      else if (system_0_burst_3_upstream_readdatavalid_from_sa | (~system_0_burst_3_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_3_upstream_waits_for_read)))
          system_0_burst_3_upstream_current_burst <= system_0_burst_3_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_3_upstream_load_fifo = (~system_0_burst_3_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_3_upstream_waits_for_read) & system_0_burst_3_upstream_load_fifo))? 1 :
    ~system_0_burst_3_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_3_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_3_upstream_waits_for_read) & ~system_0_burst_3_upstream_load_fifo | system_0_burst_3_upstream_this_cycle_is_the_last_burst)
          system_0_burst_3_upstream_load_fifo <= p0_system_0_burst_3_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_3_upstream, which is an e_assign
  assign system_0_burst_3_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_3_upstream_current_burst_minus_one) & system_0_burst_3_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_3_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_3_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_3_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_3_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_3_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_3_upstream),
      .full                 (),
      .read                 (system_0_burst_3_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_3_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_3_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_3_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_3_upstream = system_0_burst_3_upstream_readdatavalid_from_sa;

  //system_0_burst_3_upstream_writedata mux, which is an e_mux
  assign system_0_burst_3_upstream_writedata = cpu_0_data_master_dbs_write_8;

  //byteaddress mux for system_0_burst_3/upstream, which is an e_mux
  assign system_0_burst_3_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_3_upstream = cpu_0_data_master_qualified_request_system_0_burst_3_upstream;

  //cpu_0/data_master saved-grant system_0_burst_3/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_3_upstream = cpu_0_data_master_requests_system_0_burst_3_upstream;

  //allow new arb cycle for system_0_burst_3/upstream, which is an e_assign
  assign system_0_burst_3_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_3_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_3_upstream_master_qreq_vector = 1;

  //system_0_burst_3_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_3_upstream_firsttransfer = system_0_burst_3_upstream_begins_xfer ? system_0_burst_3_upstream_unreg_firsttransfer : system_0_burst_3_upstream_reg_firsttransfer;

  //system_0_burst_3_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_3_upstream_unreg_firsttransfer = ~(system_0_burst_3_upstream_slavearbiterlockenable & system_0_burst_3_upstream_any_continuerequest);

  //system_0_burst_3_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_3_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_3_upstream_begins_xfer)
          system_0_burst_3_upstream_reg_firsttransfer <= system_0_burst_3_upstream_unreg_firsttransfer;
    end


  //system_0_burst_3_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_3_upstream_next_bbt_burstcount = ((((system_0_burst_3_upstream_write) && (system_0_burst_3_upstream_bbt_burstcounter == 0))))? (system_0_burst_3_upstream_burstcount - 1) :
    ((((system_0_burst_3_upstream_read) && (system_0_burst_3_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_3_upstream_bbt_burstcounter - 1);

  //system_0_burst_3_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_3_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_3_upstream_begins_xfer)
          system_0_burst_3_upstream_bbt_burstcounter <= system_0_burst_3_upstream_next_bbt_burstcount;
    end


  //system_0_burst_3_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_3_upstream_beginbursttransfer_internal = system_0_burst_3_upstream_begins_xfer & (system_0_burst_3_upstream_bbt_burstcounter == 0);

  //system_0_burst_3_upstream_read assignment, which is an e_mux
  assign system_0_burst_3_upstream_read = cpu_0_data_master_granted_system_0_burst_3_upstream & cpu_0_data_master_read;

  //system_0_burst_3_upstream_write assignment, which is an e_mux
  assign system_0_burst_3_upstream_write = cpu_0_data_master_granted_system_0_burst_3_upstream & cpu_0_data_master_write;

  //system_0_burst_3_upstream_address mux, which is an e_mux
  assign system_0_burst_3_upstream_address = {cpu_0_data_master_address_to_slave >> 2,
    cpu_0_data_master_dbs_address[1 : 0]};

  //d1_system_0_burst_3_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_3_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_3_upstream_end_xfer <= system_0_burst_3_upstream_end_xfer;
    end


  //system_0_burst_3_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_3_upstream_waits_for_read = system_0_burst_3_upstream_in_a_read_cycle & system_0_burst_3_upstream_waitrequest_from_sa;

  //system_0_burst_3_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_3_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_3_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_3_upstream_in_a_read_cycle;

  //system_0_burst_3_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_3_upstream_waits_for_write = system_0_burst_3_upstream_in_a_write_cycle & system_0_burst_3_upstream_waitrequest_from_sa;

  //system_0_burst_3_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_3_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_3_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_3_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_3_upstream_counter = 0;
  //system_0_burst_3_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_3_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_3_upstream)? cpu_0_data_master_byteenable_system_0_burst_3_upstream :
    -1;

  assign {cpu_0_data_master_byteenable_system_0_burst_3_upstream_segment_3,
cpu_0_data_master_byteenable_system_0_burst_3_upstream_segment_2,
cpu_0_data_master_byteenable_system_0_burst_3_upstream_segment_1,
cpu_0_data_master_byteenable_system_0_burst_3_upstream_segment_0} = cpu_0_data_master_byteenable;
  assign cpu_0_data_master_byteenable_system_0_burst_3_upstream = ((cpu_0_data_master_dbs_address[1 : 0] == 0))? cpu_0_data_master_byteenable_system_0_burst_3_upstream_segment_0 :
    ((cpu_0_data_master_dbs_address[1 : 0] == 1))? cpu_0_data_master_byteenable_system_0_burst_3_upstream_segment_1 :
    ((cpu_0_data_master_dbs_address[1 : 0] == 2))? cpu_0_data_master_byteenable_system_0_burst_3_upstream_segment_2 :
    cpu_0_data_master_byteenable_system_0_burst_3_upstream_segment_3;

  //burstcount mux, which is an e_mux
  assign system_0_burst_3_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_3_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_3_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_3_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_3/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_3_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_3/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_3_downstream_arbitrator (
                                                // inputs:
                                                 cfi_flash_0_s1_wait_counter_eq_0,
                                                 clk,
                                                 d1_tri_state_bridge_0_avalon_slave_end_xfer,
                                                 incoming_tri_state_bridge_0_data_with_Xs_converted_to_0,
                                                 reset_n,
                                                 system_0_burst_3_downstream_address,
                                                 system_0_burst_3_downstream_burstcount,
                                                 system_0_burst_3_downstream_byteenable,
                                                 system_0_burst_3_downstream_granted_cfi_flash_0_s1,
                                                 system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1,
                                                 system_0_burst_3_downstream_read,
                                                 system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1,
                                                 system_0_burst_3_downstream_requests_cfi_flash_0_s1,
                                                 system_0_burst_3_downstream_write,
                                                 system_0_burst_3_downstream_writedata,

                                                // outputs:
                                                 system_0_burst_3_downstream_address_to_slave,
                                                 system_0_burst_3_downstream_latency_counter,
                                                 system_0_burst_3_downstream_readdata,
                                                 system_0_burst_3_downstream_readdatavalid,
                                                 system_0_burst_3_downstream_reset_n,
                                                 system_0_burst_3_downstream_waitrequest
                                              )
;

  output  [ 21: 0] system_0_burst_3_downstream_address_to_slave;
  output  [  1: 0] system_0_burst_3_downstream_latency_counter;
  output  [  7: 0] system_0_burst_3_downstream_readdata;
  output           system_0_burst_3_downstream_readdatavalid;
  output           system_0_burst_3_downstream_reset_n;
  output           system_0_burst_3_downstream_waitrequest;
  input            cfi_flash_0_s1_wait_counter_eq_0;
  input            clk;
  input            d1_tri_state_bridge_0_avalon_slave_end_xfer;
  input   [  7: 0] incoming_tri_state_bridge_0_data_with_Xs_converted_to_0;
  input            reset_n;
  input   [ 21: 0] system_0_burst_3_downstream_address;
  input            system_0_burst_3_downstream_burstcount;
  input            system_0_burst_3_downstream_byteenable;
  input            system_0_burst_3_downstream_granted_cfi_flash_0_s1;
  input            system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1;
  input            system_0_burst_3_downstream_read;
  input            system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1;
  input            system_0_burst_3_downstream_requests_cfi_flash_0_s1;
  input            system_0_burst_3_downstream_write;
  input   [  7: 0] system_0_burst_3_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire    [  1: 0] latency_load_value;
  wire    [  1: 0] p1_system_0_burst_3_downstream_latency_counter;
  wire             pre_flush_system_0_burst_3_downstream_readdatavalid;
  wire             r_6;
  reg     [ 21: 0] system_0_burst_3_downstream_address_last_time;
  wire    [ 21: 0] system_0_burst_3_downstream_address_to_slave;
  reg              system_0_burst_3_downstream_burstcount_last_time;
  reg              system_0_burst_3_downstream_byteenable_last_time;
  wire             system_0_burst_3_downstream_is_granted_some_slave;
  reg     [  1: 0] system_0_burst_3_downstream_latency_counter;
  reg              system_0_burst_3_downstream_read_but_no_slave_selected;
  reg              system_0_burst_3_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_3_downstream_readdata;
  wire             system_0_burst_3_downstream_readdatavalid;
  wire             system_0_burst_3_downstream_reset_n;
  wire             system_0_burst_3_downstream_run;
  wire             system_0_burst_3_downstream_waitrequest;
  reg              system_0_burst_3_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_3_downstream_writedata_last_time;
  //r_6 master_run cascaded wait assignment, which is an e_assign
  assign r_6 = 1 & (system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1 | ~system_0_burst_3_downstream_requests_cfi_flash_0_s1) & (system_0_burst_3_downstream_granted_cfi_flash_0_s1 | ~system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1) & ((~system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1 | ~system_0_burst_3_downstream_read | (1 & ((cfi_flash_0_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_0_avalon_slave_end_xfer)) & system_0_burst_3_downstream_read))) & ((~system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1 | ~system_0_burst_3_downstream_write | (1 & ((cfi_flash_0_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_0_avalon_slave_end_xfer)) & system_0_burst_3_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_3_downstream_run = r_6;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_3_downstream_address_to_slave = system_0_burst_3_downstream_address;

  //system_0_burst_3_downstream_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_3_downstream_read_but_no_slave_selected <= 0;
      else 
        system_0_burst_3_downstream_read_but_no_slave_selected <= system_0_burst_3_downstream_read & system_0_burst_3_downstream_run & ~system_0_burst_3_downstream_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign system_0_burst_3_downstream_is_granted_some_slave = system_0_burst_3_downstream_granted_cfi_flash_0_s1;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_3_downstream_readdatavalid = system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_3_downstream_readdatavalid = system_0_burst_3_downstream_read_but_no_slave_selected |
    pre_flush_system_0_burst_3_downstream_readdatavalid;

  //system_0_burst_3/downstream readdata mux, which is an e_mux
  assign system_0_burst_3_downstream_readdata = incoming_tri_state_bridge_0_data_with_Xs_converted_to_0;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_3_downstream_waitrequest = ~system_0_burst_3_downstream_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_3_downstream_latency_counter <= 0;
      else 
        system_0_burst_3_downstream_latency_counter <= p1_system_0_burst_3_downstream_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_system_0_burst_3_downstream_latency_counter = ((system_0_burst_3_downstream_run & system_0_burst_3_downstream_read))? latency_load_value :
    (system_0_burst_3_downstream_latency_counter)? system_0_burst_3_downstream_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = {2 {system_0_burst_3_downstream_requests_cfi_flash_0_s1}} & 2;

  //system_0_burst_3_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_3_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_3_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_3_downstream_address_last_time <= 0;
      else 
        system_0_burst_3_downstream_address_last_time <= system_0_burst_3_downstream_address;
    end


  //system_0_burst_3/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_3_downstream_waitrequest & (system_0_burst_3_downstream_read | system_0_burst_3_downstream_write);
    end


  //system_0_burst_3_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_3_downstream_address != system_0_burst_3_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_3_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_3_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_3_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_3_downstream_burstcount_last_time <= system_0_burst_3_downstream_burstcount;
    end


  //system_0_burst_3_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_3_downstream_burstcount != system_0_burst_3_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_3_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_3_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_3_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_3_downstream_byteenable_last_time <= system_0_burst_3_downstream_byteenable;
    end


  //system_0_burst_3_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_3_downstream_byteenable != system_0_burst_3_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_3_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_3_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_3_downstream_read_last_time <= 0;
      else 
        system_0_burst_3_downstream_read_last_time <= system_0_burst_3_downstream_read;
    end


  //system_0_burst_3_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_3_downstream_read != system_0_burst_3_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_3_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_3_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_3_downstream_write_last_time <= 0;
      else 
        system_0_burst_3_downstream_write_last_time <= system_0_burst_3_downstream_write;
    end


  //system_0_burst_3_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_3_downstream_write != system_0_burst_3_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_3_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_3_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_3_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_3_downstream_writedata_last_time <= system_0_burst_3_downstream_writedata;
    end


  //system_0_burst_3_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_3_downstream_writedata != system_0_burst_3_downstream_writedata_last_time) & system_0_burst_3_downstream_write)
        begin
          $write("%0d ns: system_0_burst_3_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_30_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_30_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_30_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_30_upstream_readdata,
                                                system_0_burst_30_upstream_readdatavalid,
                                                system_0_burst_30_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_30_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_30_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_30_upstream,
                                                d1_system_0_burst_30_upstream_end_xfer,
                                                system_0_burst_30_upstream_address,
                                                system_0_burst_30_upstream_burstcount,
                                                system_0_burst_30_upstream_byteaddress,
                                                system_0_burst_30_upstream_byteenable,
                                                system_0_burst_30_upstream_debugaccess,
                                                system_0_burst_30_upstream_read,
                                                system_0_burst_30_upstream_readdata_from_sa,
                                                system_0_burst_30_upstream_waitrequest_from_sa,
                                                system_0_burst_30_upstream_write,
                                                system_0_burst_30_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_30_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_30_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_30_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_30_upstream;
  output           d1_system_0_burst_30_upstream_end_xfer;
  output  [  1: 0] system_0_burst_30_upstream_address;
  output  [  3: 0] system_0_burst_30_upstream_burstcount;
  output  [  1: 0] system_0_burst_30_upstream_byteaddress;
  output           system_0_burst_30_upstream_byteenable;
  output           system_0_burst_30_upstream_debugaccess;
  output           system_0_burst_30_upstream_read;
  output  [  7: 0] system_0_burst_30_upstream_readdata_from_sa;
  output           system_0_burst_30_upstream_waitrequest_from_sa;
  output           system_0_burst_30_upstream_write;
  output  [  7: 0] system_0_burst_30_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_30_upstream_readdata;
  input            system_0_burst_30_upstream_readdatavalid;
  input            system_0_burst_30_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_30_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_30_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_30_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_30_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_30_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_30_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_30_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_30_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_30_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_30_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_30_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_30_upstream_address;
  wire             system_0_burst_30_upstream_allgrants;
  wire             system_0_burst_30_upstream_allow_new_arb_cycle;
  wire             system_0_burst_30_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_30_upstream_any_continuerequest;
  wire             system_0_burst_30_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_30_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_30_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_30_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_30_upstream_bbt_burstcounter;
  wire             system_0_burst_30_upstream_beginbursttransfer_internal;
  wire             system_0_burst_30_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_30_upstream_burstcount;
  wire             system_0_burst_30_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_30_upstream_byteaddress;
  wire             system_0_burst_30_upstream_byteenable;
  reg     [  3: 0] system_0_burst_30_upstream_current_burst;
  wire    [  3: 0] system_0_burst_30_upstream_current_burst_minus_one;
  wire             system_0_burst_30_upstream_debugaccess;
  wire             system_0_burst_30_upstream_end_xfer;
  wire             system_0_burst_30_upstream_firsttransfer;
  wire             system_0_burst_30_upstream_grant_vector;
  wire             system_0_burst_30_upstream_in_a_read_cycle;
  wire             system_0_burst_30_upstream_in_a_write_cycle;
  reg              system_0_burst_30_upstream_load_fifo;
  wire             system_0_burst_30_upstream_master_qreq_vector;
  wire             system_0_burst_30_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_30_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_30_upstream_next_burst_count;
  wire             system_0_burst_30_upstream_non_bursting_master_requests;
  wire             system_0_burst_30_upstream_read;
  wire    [  7: 0] system_0_burst_30_upstream_readdata_from_sa;
  wire             system_0_burst_30_upstream_readdatavalid_from_sa;
  reg              system_0_burst_30_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_30_upstream_selected_burstcount;
  reg              system_0_burst_30_upstream_slavearbiterlockenable;
  wire             system_0_burst_30_upstream_slavearbiterlockenable2;
  wire             system_0_burst_30_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_30_upstream_transaction_burst_count;
  wire             system_0_burst_30_upstream_unreg_firsttransfer;
  wire             system_0_burst_30_upstream_waitrequest_from_sa;
  wire             system_0_burst_30_upstream_waits_for_read;
  wire             system_0_burst_30_upstream_waits_for_write;
  wire             system_0_burst_30_upstream_write;
  wire    [  7: 0] system_0_burst_30_upstream_writedata;
  wire             wait_for_system_0_burst_30_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_30_upstream_end_xfer;
    end


  assign system_0_burst_30_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_30_upstream));
  //assign system_0_burst_30_upstream_readdatavalid_from_sa = system_0_burst_30_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_30_upstream_readdatavalid_from_sa = system_0_burst_30_upstream_readdatavalid;

  //assign system_0_burst_30_upstream_readdata_from_sa = system_0_burst_30_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_30_upstream_readdata_from_sa = system_0_burst_30_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_30_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a1a0) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_30_upstream_waitrequest_from_sa = system_0_burst_30_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_30_upstream_waitrequest_from_sa = system_0_burst_30_upstream_waitrequest;

  //system_0_burst_30_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_30_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_30_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_30_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_30_upstream_non_bursting_master_requests = 0;

  //system_0_burst_30_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_30_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_30_upstream;

  //system_0_burst_30_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_30_upstream_arb_share_counter_next_value = system_0_burst_30_upstream_firsttransfer ? (system_0_burst_30_upstream_arb_share_set_values - 1) : |system_0_burst_30_upstream_arb_share_counter ? (system_0_burst_30_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_30_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_30_upstream_allgrants = |system_0_burst_30_upstream_grant_vector;

  //system_0_burst_30_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_30_upstream_end_xfer = ~(system_0_burst_30_upstream_waits_for_read | system_0_burst_30_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_30_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_30_upstream = system_0_burst_30_upstream_end_xfer & (~system_0_burst_30_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_30_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_30_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_30_upstream & system_0_burst_30_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_30_upstream & ~system_0_burst_30_upstream_non_bursting_master_requests);

  //system_0_burst_30_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_30_upstream_arb_share_counter <= 0;
      else if (system_0_burst_30_upstream_arb_counter_enable)
          system_0_burst_30_upstream_arb_share_counter <= system_0_burst_30_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_30_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_30_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_30_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_30_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_30_upstream & ~system_0_burst_30_upstream_non_bursting_master_requests))
          system_0_burst_30_upstream_slavearbiterlockenable <= |system_0_burst_30_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_30/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_30_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_30_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_30_upstream_slavearbiterlockenable2 = |system_0_burst_30_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_30/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_30_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_30_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_30_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_30_upstream = cpu_0_data_master_requests_system_0_burst_30_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_30_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_30_upstream_move_on_to_next_transaction = system_0_burst_30_upstream_this_cycle_is_the_last_burst & system_0_burst_30_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_30_upstream, which is an e_mux
  assign system_0_burst_30_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_30_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_30_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_30_upstream_module burstcount_fifo_for_system_0_burst_30_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_30_upstream_selected_burstcount),
      .data_out             (system_0_burst_30_upstream_transaction_burst_count),
      .empty                (system_0_burst_30_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_30_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_30_upstream_waits_for_read & system_0_burst_30_upstream_load_fifo & ~(system_0_burst_30_upstream_this_cycle_is_the_last_burst & system_0_burst_30_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_30_upstream current burst minus one, which is an e_assign
  assign system_0_burst_30_upstream_current_burst_minus_one = system_0_burst_30_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_30_upstream, which is an e_mux
  assign system_0_burst_30_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_30_upstream_waits_for_read) & ~system_0_burst_30_upstream_load_fifo))? system_0_burst_30_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_30_upstream_waits_for_read & system_0_burst_30_upstream_this_cycle_is_the_last_burst & system_0_burst_30_upstream_burstcount_fifo_empty))? system_0_burst_30_upstream_selected_burstcount :
    (system_0_burst_30_upstream_this_cycle_is_the_last_burst)? system_0_burst_30_upstream_transaction_burst_count :
    system_0_burst_30_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_30_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_30_upstream_current_burst <= 0;
      else if (system_0_burst_30_upstream_readdatavalid_from_sa | (~system_0_burst_30_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_30_upstream_waits_for_read)))
          system_0_burst_30_upstream_current_burst <= system_0_burst_30_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_30_upstream_load_fifo = (~system_0_burst_30_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_30_upstream_waits_for_read) & system_0_burst_30_upstream_load_fifo))? 1 :
    ~system_0_burst_30_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_30_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_30_upstream_waits_for_read) & ~system_0_burst_30_upstream_load_fifo | system_0_burst_30_upstream_this_cycle_is_the_last_burst)
          system_0_burst_30_upstream_load_fifo <= p0_system_0_burst_30_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_30_upstream, which is an e_assign
  assign system_0_burst_30_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_30_upstream_current_burst_minus_one) & system_0_burst_30_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_30_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_30_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_30_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_30_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_30_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_30_upstream),
      .full                 (),
      .read                 (system_0_burst_30_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_30_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_30_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_30_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_30_upstream = system_0_burst_30_upstream_readdatavalid_from_sa;

  //system_0_burst_30_upstream_writedata mux, which is an e_mux
  assign system_0_burst_30_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_30/upstream, which is an e_mux
  assign system_0_burst_30_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_30_upstream = cpu_0_data_master_qualified_request_system_0_burst_30_upstream;

  //cpu_0/data_master saved-grant system_0_burst_30/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_30_upstream = cpu_0_data_master_requests_system_0_burst_30_upstream;

  //allow new arb cycle for system_0_burst_30/upstream, which is an e_assign
  assign system_0_burst_30_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_30_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_30_upstream_master_qreq_vector = 1;

  //system_0_burst_30_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_30_upstream_firsttransfer = system_0_burst_30_upstream_begins_xfer ? system_0_burst_30_upstream_unreg_firsttransfer : system_0_burst_30_upstream_reg_firsttransfer;

  //system_0_burst_30_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_30_upstream_unreg_firsttransfer = ~(system_0_burst_30_upstream_slavearbiterlockenable & system_0_burst_30_upstream_any_continuerequest);

  //system_0_burst_30_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_30_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_30_upstream_begins_xfer)
          system_0_burst_30_upstream_reg_firsttransfer <= system_0_burst_30_upstream_unreg_firsttransfer;
    end


  //system_0_burst_30_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_30_upstream_next_bbt_burstcount = ((((system_0_burst_30_upstream_write) && (system_0_burst_30_upstream_bbt_burstcounter == 0))))? (system_0_burst_30_upstream_burstcount - 1) :
    ((((system_0_burst_30_upstream_read) && (system_0_burst_30_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_30_upstream_bbt_burstcounter - 1);

  //system_0_burst_30_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_30_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_30_upstream_begins_xfer)
          system_0_burst_30_upstream_bbt_burstcounter <= system_0_burst_30_upstream_next_bbt_burstcount;
    end


  //system_0_burst_30_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_30_upstream_beginbursttransfer_internal = system_0_burst_30_upstream_begins_xfer & (system_0_burst_30_upstream_bbt_burstcounter == 0);

  //system_0_burst_30_upstream_read assignment, which is an e_mux
  assign system_0_burst_30_upstream_read = cpu_0_data_master_granted_system_0_burst_30_upstream & cpu_0_data_master_read;

  //system_0_burst_30_upstream_write assignment, which is an e_mux
  assign system_0_burst_30_upstream_write = cpu_0_data_master_granted_system_0_burst_30_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_30_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_30_upstream_address mux, which is an e_mux
  assign system_0_burst_30_upstream_address = shifted_address_to_system_0_burst_30_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_30_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_30_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_30_upstream_end_xfer <= system_0_burst_30_upstream_end_xfer;
    end


  //system_0_burst_30_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_30_upstream_waits_for_read = system_0_burst_30_upstream_in_a_read_cycle & system_0_burst_30_upstream_waitrequest_from_sa;

  //system_0_burst_30_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_30_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_30_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_30_upstream_in_a_read_cycle;

  //system_0_burst_30_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_30_upstream_waits_for_write = system_0_burst_30_upstream_in_a_write_cycle & system_0_burst_30_upstream_waitrequest_from_sa;

  //system_0_burst_30_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_30_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_30_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_30_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_30_upstream_counter = 0;
  //system_0_burst_30_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_30_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_30_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_30_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_30_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_30_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_30_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_30/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_30_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_30/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_30_downstream_arbitrator (
                                                 // inputs:
                                                  Oct_UP_s1_readdata_from_sa,
                                                  clk,
                                                  d1_Oct_UP_s1_end_xfer,
                                                  reset_n,
                                                  system_0_burst_30_downstream_address,
                                                  system_0_burst_30_downstream_burstcount,
                                                  system_0_burst_30_downstream_byteenable,
                                                  system_0_burst_30_downstream_granted_Oct_UP_s1,
                                                  system_0_burst_30_downstream_qualified_request_Oct_UP_s1,
                                                  system_0_burst_30_downstream_read,
                                                  system_0_burst_30_downstream_read_data_valid_Oct_UP_s1,
                                                  system_0_burst_30_downstream_requests_Oct_UP_s1,
                                                  system_0_burst_30_downstream_write,
                                                  system_0_burst_30_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_30_downstream_address_to_slave,
                                                  system_0_burst_30_downstream_latency_counter,
                                                  system_0_burst_30_downstream_readdata,
                                                  system_0_burst_30_downstream_readdatavalid,
                                                  system_0_burst_30_downstream_reset_n,
                                                  system_0_burst_30_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_30_downstream_address_to_slave;
  output           system_0_burst_30_downstream_latency_counter;
  output  [  7: 0] system_0_burst_30_downstream_readdata;
  output           system_0_burst_30_downstream_readdatavalid;
  output           system_0_burst_30_downstream_reset_n;
  output           system_0_burst_30_downstream_waitrequest;
  input            Oct_UP_s1_readdata_from_sa;
  input            clk;
  input            d1_Oct_UP_s1_end_xfer;
  input            reset_n;
  input   [  1: 0] system_0_burst_30_downstream_address;
  input            system_0_burst_30_downstream_burstcount;
  input            system_0_burst_30_downstream_byteenable;
  input            system_0_burst_30_downstream_granted_Oct_UP_s1;
  input            system_0_burst_30_downstream_qualified_request_Oct_UP_s1;
  input            system_0_burst_30_downstream_read;
  input            system_0_burst_30_downstream_read_data_valid_Oct_UP_s1;
  input            system_0_burst_30_downstream_requests_Oct_UP_s1;
  input            system_0_burst_30_downstream_write;
  input   [  7: 0] system_0_burst_30_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_30_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_30_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_30_downstream_address_to_slave;
  reg              system_0_burst_30_downstream_burstcount_last_time;
  reg              system_0_burst_30_downstream_byteenable_last_time;
  wire             system_0_burst_30_downstream_latency_counter;
  reg              system_0_burst_30_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_30_downstream_readdata;
  wire             system_0_burst_30_downstream_readdatavalid;
  wire             system_0_burst_30_downstream_reset_n;
  wire             system_0_burst_30_downstream_run;
  wire             system_0_burst_30_downstream_waitrequest;
  reg              system_0_burst_30_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_30_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_30_downstream_qualified_request_Oct_UP_s1 | ~system_0_burst_30_downstream_requests_Oct_UP_s1) & ((~system_0_burst_30_downstream_qualified_request_Oct_UP_s1 | ~system_0_burst_30_downstream_read | (1 & ~d1_Oct_UP_s1_end_xfer & system_0_burst_30_downstream_read))) & ((~system_0_burst_30_downstream_qualified_request_Oct_UP_s1 | ~system_0_burst_30_downstream_write | (1 & system_0_burst_30_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_30_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_30_downstream_address_to_slave = system_0_burst_30_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_30_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_30_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_30_downstream_readdatavalid |
    system_0_burst_30_downstream_read_data_valid_Oct_UP_s1;

  //system_0_burst_30/downstream readdata mux, which is an e_mux
  assign system_0_burst_30_downstream_readdata = Oct_UP_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_30_downstream_waitrequest = ~system_0_burst_30_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_30_downstream_latency_counter = 0;

  //system_0_burst_30_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_30_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_30_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_30_downstream_address_last_time <= 0;
      else 
        system_0_burst_30_downstream_address_last_time <= system_0_burst_30_downstream_address;
    end


  //system_0_burst_30/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_30_downstream_waitrequest & (system_0_burst_30_downstream_read | system_0_burst_30_downstream_write);
    end


  //system_0_burst_30_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_30_downstream_address != system_0_burst_30_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_30_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_30_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_30_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_30_downstream_burstcount_last_time <= system_0_burst_30_downstream_burstcount;
    end


  //system_0_burst_30_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_30_downstream_burstcount != system_0_burst_30_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_30_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_30_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_30_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_30_downstream_byteenable_last_time <= system_0_burst_30_downstream_byteenable;
    end


  //system_0_burst_30_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_30_downstream_byteenable != system_0_burst_30_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_30_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_30_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_30_downstream_read_last_time <= 0;
      else 
        system_0_burst_30_downstream_read_last_time <= system_0_burst_30_downstream_read;
    end


  //system_0_burst_30_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_30_downstream_read != system_0_burst_30_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_30_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_30_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_30_downstream_write_last_time <= 0;
      else 
        system_0_burst_30_downstream_write_last_time <= system_0_burst_30_downstream_write;
    end


  //system_0_burst_30_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_30_downstream_write != system_0_burst_30_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_30_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_30_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_30_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_30_downstream_writedata_last_time <= system_0_burst_30_downstream_writedata;
    end


  //system_0_burst_30_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_30_downstream_writedata != system_0_burst_30_downstream_writedata_last_time) & system_0_burst_30_downstream_write)
        begin
          $write("%0d ns: system_0_burst_30_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_31_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_31_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_31_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_31_upstream_readdata,
                                                system_0_burst_31_upstream_readdatavalid,
                                                system_0_burst_31_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_31_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_31_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_31_upstream,
                                                d1_system_0_burst_31_upstream_end_xfer,
                                                system_0_burst_31_upstream_address,
                                                system_0_burst_31_upstream_burstcount,
                                                system_0_burst_31_upstream_byteaddress,
                                                system_0_burst_31_upstream_byteenable,
                                                system_0_burst_31_upstream_debugaccess,
                                                system_0_burst_31_upstream_read,
                                                system_0_burst_31_upstream_readdata_from_sa,
                                                system_0_burst_31_upstream_waitrequest_from_sa,
                                                system_0_burst_31_upstream_write,
                                                system_0_burst_31_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_31_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_31_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_31_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_31_upstream;
  output           d1_system_0_burst_31_upstream_end_xfer;
  output  [  1: 0] system_0_burst_31_upstream_address;
  output  [  3: 0] system_0_burst_31_upstream_burstcount;
  output  [  1: 0] system_0_burst_31_upstream_byteaddress;
  output           system_0_burst_31_upstream_byteenable;
  output           system_0_burst_31_upstream_debugaccess;
  output           system_0_burst_31_upstream_read;
  output  [  7: 0] system_0_burst_31_upstream_readdata_from_sa;
  output           system_0_burst_31_upstream_waitrequest_from_sa;
  output           system_0_burst_31_upstream_write;
  output  [  7: 0] system_0_burst_31_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [  7: 0] system_0_burst_31_upstream_readdata;
  input            system_0_burst_31_upstream_readdatavalid;
  input            system_0_burst_31_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_31_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_31_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_31_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_31_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_31_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_31_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_31_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_31_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_31_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_31_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_31_upstream_from_cpu_0_data_master;
  wire    [  1: 0] system_0_burst_31_upstream_address;
  wire             system_0_burst_31_upstream_allgrants;
  wire             system_0_burst_31_upstream_allow_new_arb_cycle;
  wire             system_0_burst_31_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_31_upstream_any_continuerequest;
  wire             system_0_burst_31_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_31_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_31_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_31_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_31_upstream_bbt_burstcounter;
  wire             system_0_burst_31_upstream_beginbursttransfer_internal;
  wire             system_0_burst_31_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_31_upstream_burstcount;
  wire             system_0_burst_31_upstream_burstcount_fifo_empty;
  wire    [  1: 0] system_0_burst_31_upstream_byteaddress;
  wire             system_0_burst_31_upstream_byteenable;
  reg     [  3: 0] system_0_burst_31_upstream_current_burst;
  wire    [  3: 0] system_0_burst_31_upstream_current_burst_minus_one;
  wire             system_0_burst_31_upstream_debugaccess;
  wire             system_0_burst_31_upstream_end_xfer;
  wire             system_0_burst_31_upstream_firsttransfer;
  wire             system_0_burst_31_upstream_grant_vector;
  wire             system_0_burst_31_upstream_in_a_read_cycle;
  wire             system_0_burst_31_upstream_in_a_write_cycle;
  reg              system_0_burst_31_upstream_load_fifo;
  wire             system_0_burst_31_upstream_master_qreq_vector;
  wire             system_0_burst_31_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_31_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_31_upstream_next_burst_count;
  wire             system_0_burst_31_upstream_non_bursting_master_requests;
  wire             system_0_burst_31_upstream_read;
  wire    [  7: 0] system_0_burst_31_upstream_readdata_from_sa;
  wire             system_0_burst_31_upstream_readdatavalid_from_sa;
  reg              system_0_burst_31_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_31_upstream_selected_burstcount;
  reg              system_0_burst_31_upstream_slavearbiterlockenable;
  wire             system_0_burst_31_upstream_slavearbiterlockenable2;
  wire             system_0_burst_31_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_31_upstream_transaction_burst_count;
  wire             system_0_burst_31_upstream_unreg_firsttransfer;
  wire             system_0_burst_31_upstream_waitrequest_from_sa;
  wire             system_0_burst_31_upstream_waits_for_read;
  wire             system_0_burst_31_upstream_waits_for_write;
  wire             system_0_burst_31_upstream_write;
  wire    [  7: 0] system_0_burst_31_upstream_writedata;
  wire             wait_for_system_0_burst_31_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_31_upstream_end_xfer;
    end


  assign system_0_burst_31_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_31_upstream));
  //assign system_0_burst_31_upstream_readdatavalid_from_sa = system_0_burst_31_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_31_upstream_readdatavalid_from_sa = system_0_burst_31_upstream_readdatavalid;

  //assign system_0_burst_31_upstream_readdata_from_sa = system_0_burst_31_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_31_upstream_readdata_from_sa = system_0_burst_31_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_31_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a1b0) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_31_upstream_waitrequest_from_sa = system_0_burst_31_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_31_upstream_waitrequest_from_sa = system_0_burst_31_upstream_waitrequest;

  //system_0_burst_31_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_31_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_31_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_31_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_31_upstream_non_bursting_master_requests = 0;

  //system_0_burst_31_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_31_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_31_upstream;

  //system_0_burst_31_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_31_upstream_arb_share_counter_next_value = system_0_burst_31_upstream_firsttransfer ? (system_0_burst_31_upstream_arb_share_set_values - 1) : |system_0_burst_31_upstream_arb_share_counter ? (system_0_burst_31_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_31_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_31_upstream_allgrants = |system_0_burst_31_upstream_grant_vector;

  //system_0_burst_31_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_31_upstream_end_xfer = ~(system_0_burst_31_upstream_waits_for_read | system_0_burst_31_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_31_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_31_upstream = system_0_burst_31_upstream_end_xfer & (~system_0_burst_31_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_31_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_31_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_31_upstream & system_0_burst_31_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_31_upstream & ~system_0_burst_31_upstream_non_bursting_master_requests);

  //system_0_burst_31_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_31_upstream_arb_share_counter <= 0;
      else if (system_0_burst_31_upstream_arb_counter_enable)
          system_0_burst_31_upstream_arb_share_counter <= system_0_burst_31_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_31_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_31_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_31_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_31_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_31_upstream & ~system_0_burst_31_upstream_non_bursting_master_requests))
          system_0_burst_31_upstream_slavearbiterlockenable <= |system_0_burst_31_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_31/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_31_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_31_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_31_upstream_slavearbiterlockenable2 = |system_0_burst_31_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_31/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_31_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_31_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_31_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_31_upstream = cpu_0_data_master_requests_system_0_burst_31_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_31_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_31_upstream_move_on_to_next_transaction = system_0_burst_31_upstream_this_cycle_is_the_last_burst & system_0_burst_31_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_31_upstream, which is an e_mux
  assign system_0_burst_31_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_31_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_31_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_31_upstream_module burstcount_fifo_for_system_0_burst_31_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_31_upstream_selected_burstcount),
      .data_out             (system_0_burst_31_upstream_transaction_burst_count),
      .empty                (system_0_burst_31_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_31_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_31_upstream_waits_for_read & system_0_burst_31_upstream_load_fifo & ~(system_0_burst_31_upstream_this_cycle_is_the_last_burst & system_0_burst_31_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_31_upstream current burst minus one, which is an e_assign
  assign system_0_burst_31_upstream_current_burst_minus_one = system_0_burst_31_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_31_upstream, which is an e_mux
  assign system_0_burst_31_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_31_upstream_waits_for_read) & ~system_0_burst_31_upstream_load_fifo))? system_0_burst_31_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_31_upstream_waits_for_read & system_0_burst_31_upstream_this_cycle_is_the_last_burst & system_0_burst_31_upstream_burstcount_fifo_empty))? system_0_burst_31_upstream_selected_burstcount :
    (system_0_burst_31_upstream_this_cycle_is_the_last_burst)? system_0_burst_31_upstream_transaction_burst_count :
    system_0_burst_31_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_31_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_31_upstream_current_burst <= 0;
      else if (system_0_burst_31_upstream_readdatavalid_from_sa | (~system_0_burst_31_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_31_upstream_waits_for_read)))
          system_0_burst_31_upstream_current_burst <= system_0_burst_31_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_31_upstream_load_fifo = (~system_0_burst_31_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_31_upstream_waits_for_read) & system_0_burst_31_upstream_load_fifo))? 1 :
    ~system_0_burst_31_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_31_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_31_upstream_waits_for_read) & ~system_0_burst_31_upstream_load_fifo | system_0_burst_31_upstream_this_cycle_is_the_last_burst)
          system_0_burst_31_upstream_load_fifo <= p0_system_0_burst_31_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_31_upstream, which is an e_assign
  assign system_0_burst_31_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_31_upstream_current_burst_minus_one) & system_0_burst_31_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_31_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_31_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_31_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_31_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_31_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_31_upstream),
      .full                 (),
      .read                 (system_0_burst_31_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_31_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_31_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_31_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_31_upstream = system_0_burst_31_upstream_readdatavalid_from_sa;

  //system_0_burst_31_upstream_writedata mux, which is an e_mux
  assign system_0_burst_31_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_31/upstream, which is an e_mux
  assign system_0_burst_31_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_31_upstream = cpu_0_data_master_qualified_request_system_0_burst_31_upstream;

  //cpu_0/data_master saved-grant system_0_burst_31/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_31_upstream = cpu_0_data_master_requests_system_0_burst_31_upstream;

  //allow new arb cycle for system_0_burst_31/upstream, which is an e_assign
  assign system_0_burst_31_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_31_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_31_upstream_master_qreq_vector = 1;

  //system_0_burst_31_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_31_upstream_firsttransfer = system_0_burst_31_upstream_begins_xfer ? system_0_burst_31_upstream_unreg_firsttransfer : system_0_burst_31_upstream_reg_firsttransfer;

  //system_0_burst_31_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_31_upstream_unreg_firsttransfer = ~(system_0_burst_31_upstream_slavearbiterlockenable & system_0_burst_31_upstream_any_continuerequest);

  //system_0_burst_31_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_31_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_31_upstream_begins_xfer)
          system_0_burst_31_upstream_reg_firsttransfer <= system_0_burst_31_upstream_unreg_firsttransfer;
    end


  //system_0_burst_31_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_31_upstream_next_bbt_burstcount = ((((system_0_burst_31_upstream_write) && (system_0_burst_31_upstream_bbt_burstcounter == 0))))? (system_0_burst_31_upstream_burstcount - 1) :
    ((((system_0_burst_31_upstream_read) && (system_0_burst_31_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_31_upstream_bbt_burstcounter - 1);

  //system_0_burst_31_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_31_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_31_upstream_begins_xfer)
          system_0_burst_31_upstream_bbt_burstcounter <= system_0_burst_31_upstream_next_bbt_burstcount;
    end


  //system_0_burst_31_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_31_upstream_beginbursttransfer_internal = system_0_burst_31_upstream_begins_xfer & (system_0_burst_31_upstream_bbt_burstcounter == 0);

  //system_0_burst_31_upstream_read assignment, which is an e_mux
  assign system_0_burst_31_upstream_read = cpu_0_data_master_granted_system_0_burst_31_upstream & cpu_0_data_master_read;

  //system_0_burst_31_upstream_write assignment, which is an e_mux
  assign system_0_burst_31_upstream_write = cpu_0_data_master_granted_system_0_burst_31_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_31_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_31_upstream_address mux, which is an e_mux
  assign system_0_burst_31_upstream_address = shifted_address_to_system_0_burst_31_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_31_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_31_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_31_upstream_end_xfer <= system_0_burst_31_upstream_end_xfer;
    end


  //system_0_burst_31_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_31_upstream_waits_for_read = system_0_burst_31_upstream_in_a_read_cycle & system_0_burst_31_upstream_waitrequest_from_sa;

  //system_0_burst_31_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_31_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_31_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_31_upstream_in_a_read_cycle;

  //system_0_burst_31_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_31_upstream_waits_for_write = system_0_burst_31_upstream_in_a_write_cycle & system_0_burst_31_upstream_waitrequest_from_sa;

  //system_0_burst_31_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_31_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_31_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_31_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_31_upstream_counter = 0;
  //system_0_burst_31_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_31_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_31_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_31_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_31_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_31_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_31_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_31/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_31_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_31/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_31_downstream_arbitrator (
                                                 // inputs:
                                                  Oct_DOWN_s1_readdata_from_sa,
                                                  clk,
                                                  d1_Oct_DOWN_s1_end_xfer,
                                                  reset_n,
                                                  system_0_burst_31_downstream_address,
                                                  system_0_burst_31_downstream_burstcount,
                                                  system_0_burst_31_downstream_byteenable,
                                                  system_0_burst_31_downstream_granted_Oct_DOWN_s1,
                                                  system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1,
                                                  system_0_burst_31_downstream_read,
                                                  system_0_burst_31_downstream_read_data_valid_Oct_DOWN_s1,
                                                  system_0_burst_31_downstream_requests_Oct_DOWN_s1,
                                                  system_0_burst_31_downstream_write,
                                                  system_0_burst_31_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_31_downstream_address_to_slave,
                                                  system_0_burst_31_downstream_latency_counter,
                                                  system_0_burst_31_downstream_readdata,
                                                  system_0_burst_31_downstream_readdatavalid,
                                                  system_0_burst_31_downstream_reset_n,
                                                  system_0_burst_31_downstream_waitrequest
                                               )
;

  output  [  1: 0] system_0_burst_31_downstream_address_to_slave;
  output           system_0_burst_31_downstream_latency_counter;
  output  [  7: 0] system_0_burst_31_downstream_readdata;
  output           system_0_burst_31_downstream_readdatavalid;
  output           system_0_burst_31_downstream_reset_n;
  output           system_0_burst_31_downstream_waitrequest;
  input            Oct_DOWN_s1_readdata_from_sa;
  input            clk;
  input            d1_Oct_DOWN_s1_end_xfer;
  input            reset_n;
  input   [  1: 0] system_0_burst_31_downstream_address;
  input            system_0_burst_31_downstream_burstcount;
  input            system_0_burst_31_downstream_byteenable;
  input            system_0_burst_31_downstream_granted_Oct_DOWN_s1;
  input            system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1;
  input            system_0_burst_31_downstream_read;
  input            system_0_burst_31_downstream_read_data_valid_Oct_DOWN_s1;
  input            system_0_burst_31_downstream_requests_Oct_DOWN_s1;
  input            system_0_burst_31_downstream_write;
  input   [  7: 0] system_0_burst_31_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_31_downstream_readdatavalid;
  wire             r_0;
  reg     [  1: 0] system_0_burst_31_downstream_address_last_time;
  wire    [  1: 0] system_0_burst_31_downstream_address_to_slave;
  reg              system_0_burst_31_downstream_burstcount_last_time;
  reg              system_0_burst_31_downstream_byteenable_last_time;
  wire             system_0_burst_31_downstream_latency_counter;
  reg              system_0_burst_31_downstream_read_last_time;
  wire    [  7: 0] system_0_burst_31_downstream_readdata;
  wire             system_0_burst_31_downstream_readdatavalid;
  wire             system_0_burst_31_downstream_reset_n;
  wire             system_0_burst_31_downstream_run;
  wire             system_0_burst_31_downstream_waitrequest;
  reg              system_0_burst_31_downstream_write_last_time;
  reg     [  7: 0] system_0_burst_31_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1 | ~system_0_burst_31_downstream_requests_Oct_DOWN_s1) & ((~system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1 | ~system_0_burst_31_downstream_read | (1 & ~d1_Oct_DOWN_s1_end_xfer & system_0_burst_31_downstream_read))) & ((~system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1 | ~system_0_burst_31_downstream_write | (1 & system_0_burst_31_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_31_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_31_downstream_address_to_slave = system_0_burst_31_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_31_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_31_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_31_downstream_readdatavalid |
    system_0_burst_31_downstream_read_data_valid_Oct_DOWN_s1;

  //system_0_burst_31/downstream readdata mux, which is an e_mux
  assign system_0_burst_31_downstream_readdata = Oct_DOWN_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_31_downstream_waitrequest = ~system_0_burst_31_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_31_downstream_latency_counter = 0;

  //system_0_burst_31_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_31_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_31_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_31_downstream_address_last_time <= 0;
      else 
        system_0_burst_31_downstream_address_last_time <= system_0_burst_31_downstream_address;
    end


  //system_0_burst_31/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_31_downstream_waitrequest & (system_0_burst_31_downstream_read | system_0_burst_31_downstream_write);
    end


  //system_0_burst_31_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_31_downstream_address != system_0_burst_31_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_31_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_31_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_31_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_31_downstream_burstcount_last_time <= system_0_burst_31_downstream_burstcount;
    end


  //system_0_burst_31_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_31_downstream_burstcount != system_0_burst_31_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_31_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_31_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_31_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_31_downstream_byteenable_last_time <= system_0_burst_31_downstream_byteenable;
    end


  //system_0_burst_31_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_31_downstream_byteenable != system_0_burst_31_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_31_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_31_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_31_downstream_read_last_time <= 0;
      else 
        system_0_burst_31_downstream_read_last_time <= system_0_burst_31_downstream_read;
    end


  //system_0_burst_31_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_31_downstream_read != system_0_burst_31_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_31_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_31_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_31_downstream_write_last_time <= 0;
      else 
        system_0_burst_31_downstream_write_last_time <= system_0_burst_31_downstream_write;
    end


  //system_0_burst_31_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_31_downstream_write != system_0_burst_31_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_31_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_31_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_31_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_31_downstream_writedata_last_time <= system_0_burst_31_downstream_writedata;
    end


  //system_0_burst_31_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_31_downstream_writedata != system_0_burst_31_downstream_writedata_last_time) & system_0_burst_31_downstream_write)
        begin
          $write("%0d ns: system_0_burst_31_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_32_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_32_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_32_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_32_upstream_readdata,
                                                system_0_burst_32_upstream_readdatavalid,
                                                system_0_burst_32_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_32_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_32_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_32_upstream,
                                                d1_system_0_burst_32_upstream_end_xfer,
                                                system_0_burst_32_upstream_address,
                                                system_0_burst_32_upstream_burstcount,
                                                system_0_burst_32_upstream_byteaddress,
                                                system_0_burst_32_upstream_byteenable,
                                                system_0_burst_32_upstream_debugaccess,
                                                system_0_burst_32_upstream_read,
                                                system_0_burst_32_upstream_readdata_from_sa,
                                                system_0_burst_32_upstream_waitrequest_from_sa,
                                                system_0_burst_32_upstream_write,
                                                system_0_burst_32_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_32_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_32_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_32_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_32_upstream;
  output           d1_system_0_burst_32_upstream_end_xfer;
  output  [  4: 0] system_0_burst_32_upstream_address;
  output  [  3: 0] system_0_burst_32_upstream_burstcount;
  output  [  6: 0] system_0_burst_32_upstream_byteaddress;
  output  [  3: 0] system_0_burst_32_upstream_byteenable;
  output           system_0_burst_32_upstream_debugaccess;
  output           system_0_burst_32_upstream_read;
  output  [ 31: 0] system_0_burst_32_upstream_readdata_from_sa;
  output           system_0_burst_32_upstream_waitrequest_from_sa;
  output           system_0_burst_32_upstream_write;
  output  [ 31: 0] system_0_burst_32_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [ 31: 0] system_0_burst_32_upstream_readdata;
  input            system_0_burst_32_upstream_readdatavalid;
  input            system_0_burst_32_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_32_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_32_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_32_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_32_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_32_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_32_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_32_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_32_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_32_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_32_upstream_load_fifo;
  wire    [  4: 0] system_0_burst_32_upstream_address;
  wire             system_0_burst_32_upstream_allgrants;
  wire             system_0_burst_32_upstream_allow_new_arb_cycle;
  wire             system_0_burst_32_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_32_upstream_any_continuerequest;
  wire             system_0_burst_32_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_32_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_32_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_32_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_32_upstream_bbt_burstcounter;
  wire             system_0_burst_32_upstream_beginbursttransfer_internal;
  wire             system_0_burst_32_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_32_upstream_burstcount;
  wire             system_0_burst_32_upstream_burstcount_fifo_empty;
  wire    [  6: 0] system_0_burst_32_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_32_upstream_byteenable;
  reg     [  3: 0] system_0_burst_32_upstream_current_burst;
  wire    [  3: 0] system_0_burst_32_upstream_current_burst_minus_one;
  wire             system_0_burst_32_upstream_debugaccess;
  wire             system_0_burst_32_upstream_end_xfer;
  wire             system_0_burst_32_upstream_firsttransfer;
  wire             system_0_burst_32_upstream_grant_vector;
  wire             system_0_burst_32_upstream_in_a_read_cycle;
  wire             system_0_burst_32_upstream_in_a_write_cycle;
  reg              system_0_burst_32_upstream_load_fifo;
  wire             system_0_burst_32_upstream_master_qreq_vector;
  wire             system_0_burst_32_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_32_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_32_upstream_next_burst_count;
  wire             system_0_burst_32_upstream_non_bursting_master_requests;
  wire             system_0_burst_32_upstream_read;
  wire    [ 31: 0] system_0_burst_32_upstream_readdata_from_sa;
  wire             system_0_burst_32_upstream_readdatavalid_from_sa;
  reg              system_0_burst_32_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_32_upstream_selected_burstcount;
  reg              system_0_burst_32_upstream_slavearbiterlockenable;
  wire             system_0_burst_32_upstream_slavearbiterlockenable2;
  wire             system_0_burst_32_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_32_upstream_transaction_burst_count;
  wire             system_0_burst_32_upstream_unreg_firsttransfer;
  wire             system_0_burst_32_upstream_waitrequest_from_sa;
  wire             system_0_burst_32_upstream_waits_for_read;
  wire             system_0_burst_32_upstream_waits_for_write;
  wire             system_0_burst_32_upstream_write;
  wire    [ 31: 0] system_0_burst_32_upstream_writedata;
  wire             wait_for_system_0_burst_32_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_32_upstream_end_xfer;
    end


  assign system_0_burst_32_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_32_upstream));
  //assign system_0_burst_32_upstream_readdatavalid_from_sa = system_0_burst_32_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_32_upstream_readdatavalid_from_sa = system_0_burst_32_upstream_readdatavalid;

  //assign system_0_burst_32_upstream_readdata_from_sa = system_0_burst_32_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_32_upstream_readdata_from_sa = system_0_burst_32_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_32_upstream = ({cpu_0_data_master_address_to_slave[24 : 5] , 5'b0} == 25'h190a080) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_32_upstream_waitrequest_from_sa = system_0_burst_32_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_32_upstream_waitrequest_from_sa = system_0_burst_32_upstream_waitrequest;

  //system_0_burst_32_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_32_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_32_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_32_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_32_upstream_non_bursting_master_requests = 0;

  //system_0_burst_32_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_32_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_32_upstream;

  //system_0_burst_32_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_32_upstream_arb_share_counter_next_value = system_0_burst_32_upstream_firsttransfer ? (system_0_burst_32_upstream_arb_share_set_values - 1) : |system_0_burst_32_upstream_arb_share_counter ? (system_0_burst_32_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_32_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_32_upstream_allgrants = |system_0_burst_32_upstream_grant_vector;

  //system_0_burst_32_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_32_upstream_end_xfer = ~(system_0_burst_32_upstream_waits_for_read | system_0_burst_32_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_32_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_32_upstream = system_0_burst_32_upstream_end_xfer & (~system_0_burst_32_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_32_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_32_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_32_upstream & system_0_burst_32_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_32_upstream & ~system_0_burst_32_upstream_non_bursting_master_requests);

  //system_0_burst_32_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_32_upstream_arb_share_counter <= 0;
      else if (system_0_burst_32_upstream_arb_counter_enable)
          system_0_burst_32_upstream_arb_share_counter <= system_0_burst_32_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_32_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_32_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_32_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_32_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_32_upstream & ~system_0_burst_32_upstream_non_bursting_master_requests))
          system_0_burst_32_upstream_slavearbiterlockenable <= |system_0_burst_32_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_32/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_32_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_32_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_32_upstream_slavearbiterlockenable2 = |system_0_burst_32_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_32/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_32_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_32_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_32_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_32_upstream = cpu_0_data_master_requests_system_0_burst_32_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_32_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_32_upstream_move_on_to_next_transaction = system_0_burst_32_upstream_this_cycle_is_the_last_burst & system_0_burst_32_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_32_upstream, which is an e_mux
  assign system_0_burst_32_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_32_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_32_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_32_upstream_module burstcount_fifo_for_system_0_burst_32_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_32_upstream_selected_burstcount),
      .data_out             (system_0_burst_32_upstream_transaction_burst_count),
      .empty                (system_0_burst_32_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_32_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_32_upstream_waits_for_read & system_0_burst_32_upstream_load_fifo & ~(system_0_burst_32_upstream_this_cycle_is_the_last_burst & system_0_burst_32_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_32_upstream current burst minus one, which is an e_assign
  assign system_0_burst_32_upstream_current_burst_minus_one = system_0_burst_32_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_32_upstream, which is an e_mux
  assign system_0_burst_32_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_32_upstream_waits_for_read) & ~system_0_burst_32_upstream_load_fifo))? system_0_burst_32_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_32_upstream_waits_for_read & system_0_burst_32_upstream_this_cycle_is_the_last_burst & system_0_burst_32_upstream_burstcount_fifo_empty))? system_0_burst_32_upstream_selected_burstcount :
    (system_0_burst_32_upstream_this_cycle_is_the_last_burst)? system_0_burst_32_upstream_transaction_burst_count :
    system_0_burst_32_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_32_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_32_upstream_current_burst <= 0;
      else if (system_0_burst_32_upstream_readdatavalid_from_sa | (~system_0_burst_32_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_32_upstream_waits_for_read)))
          system_0_burst_32_upstream_current_burst <= system_0_burst_32_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_32_upstream_load_fifo = (~system_0_burst_32_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_32_upstream_waits_for_read) & system_0_burst_32_upstream_load_fifo))? 1 :
    ~system_0_burst_32_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_32_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_32_upstream_waits_for_read) & ~system_0_burst_32_upstream_load_fifo | system_0_burst_32_upstream_this_cycle_is_the_last_burst)
          system_0_burst_32_upstream_load_fifo <= p0_system_0_burst_32_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_32_upstream, which is an e_assign
  assign system_0_burst_32_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_32_upstream_current_burst_minus_one) & system_0_burst_32_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_32_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_32_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_32_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_32_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_32_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_32_upstream),
      .full                 (),
      .read                 (system_0_burst_32_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_32_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_32_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_32_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_32_upstream = system_0_burst_32_upstream_readdatavalid_from_sa;

  //system_0_burst_32_upstream_writedata mux, which is an e_mux
  assign system_0_burst_32_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_32/upstream, which is an e_mux
  assign system_0_burst_32_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_32_upstream = cpu_0_data_master_qualified_request_system_0_burst_32_upstream;

  //cpu_0/data_master saved-grant system_0_burst_32/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_32_upstream = cpu_0_data_master_requests_system_0_burst_32_upstream;

  //allow new arb cycle for system_0_burst_32/upstream, which is an e_assign
  assign system_0_burst_32_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_32_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_32_upstream_master_qreq_vector = 1;

  //system_0_burst_32_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_32_upstream_firsttransfer = system_0_burst_32_upstream_begins_xfer ? system_0_burst_32_upstream_unreg_firsttransfer : system_0_burst_32_upstream_reg_firsttransfer;

  //system_0_burst_32_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_32_upstream_unreg_firsttransfer = ~(system_0_burst_32_upstream_slavearbiterlockenable & system_0_burst_32_upstream_any_continuerequest);

  //system_0_burst_32_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_32_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_32_upstream_begins_xfer)
          system_0_burst_32_upstream_reg_firsttransfer <= system_0_burst_32_upstream_unreg_firsttransfer;
    end


  //system_0_burst_32_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_32_upstream_next_bbt_burstcount = ((((system_0_burst_32_upstream_write) && (system_0_burst_32_upstream_bbt_burstcounter == 0))))? (system_0_burst_32_upstream_burstcount - 1) :
    ((((system_0_burst_32_upstream_read) && (system_0_burst_32_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_32_upstream_bbt_burstcounter - 1);

  //system_0_burst_32_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_32_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_32_upstream_begins_xfer)
          system_0_burst_32_upstream_bbt_burstcounter <= system_0_burst_32_upstream_next_bbt_burstcount;
    end


  //system_0_burst_32_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_32_upstream_beginbursttransfer_internal = system_0_burst_32_upstream_begins_xfer & (system_0_burst_32_upstream_bbt_burstcounter == 0);

  //system_0_burst_32_upstream_read assignment, which is an e_mux
  assign system_0_burst_32_upstream_read = cpu_0_data_master_granted_system_0_burst_32_upstream & cpu_0_data_master_read;

  //system_0_burst_32_upstream_write assignment, which is an e_mux
  assign system_0_burst_32_upstream_write = cpu_0_data_master_granted_system_0_burst_32_upstream & cpu_0_data_master_write;

  //system_0_burst_32_upstream_address mux, which is an e_mux
  assign system_0_burst_32_upstream_address = cpu_0_data_master_address_to_slave;

  //d1_system_0_burst_32_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_32_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_32_upstream_end_xfer <= system_0_burst_32_upstream_end_xfer;
    end


  //system_0_burst_32_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_32_upstream_waits_for_read = system_0_burst_32_upstream_in_a_read_cycle & system_0_burst_32_upstream_waitrequest_from_sa;

  //system_0_burst_32_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_32_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_32_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_32_upstream_in_a_read_cycle;

  //system_0_burst_32_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_32_upstream_waits_for_write = system_0_burst_32_upstream_in_a_write_cycle & system_0_burst_32_upstream_waitrequest_from_sa;

  //system_0_burst_32_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_32_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_32_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_32_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_32_upstream_counter = 0;
  //system_0_burst_32_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_32_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_32_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_32_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_32_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_32_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_32_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_32/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_32_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_32/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_32_downstream_arbitrator (
                                                 // inputs:
                                                  Accel_Control_avalon_slave_readdata_from_sa,
                                                  clk,
                                                  d1_Accel_Control_avalon_slave_end_xfer,
                                                  reset_n,
                                                  system_0_burst_32_downstream_address,
                                                  system_0_burst_32_downstream_burstcount,
                                                  system_0_burst_32_downstream_byteenable,
                                                  system_0_burst_32_downstream_granted_Accel_Control_avalon_slave,
                                                  system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave,
                                                  system_0_burst_32_downstream_read,
                                                  system_0_burst_32_downstream_read_data_valid_Accel_Control_avalon_slave,
                                                  system_0_burst_32_downstream_requests_Accel_Control_avalon_slave,
                                                  system_0_burst_32_downstream_write,
                                                  system_0_burst_32_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_32_downstream_address_to_slave,
                                                  system_0_burst_32_downstream_latency_counter,
                                                  system_0_burst_32_downstream_readdata,
                                                  system_0_burst_32_downstream_readdatavalid,
                                                  system_0_burst_32_downstream_reset_n,
                                                  system_0_burst_32_downstream_waitrequest
                                               )
;

  output  [  4: 0] system_0_burst_32_downstream_address_to_slave;
  output           system_0_burst_32_downstream_latency_counter;
  output  [ 31: 0] system_0_burst_32_downstream_readdata;
  output           system_0_burst_32_downstream_readdatavalid;
  output           system_0_burst_32_downstream_reset_n;
  output           system_0_burst_32_downstream_waitrequest;
  input   [ 31: 0] Accel_Control_avalon_slave_readdata_from_sa;
  input            clk;
  input            d1_Accel_Control_avalon_slave_end_xfer;
  input            reset_n;
  input   [  4: 0] system_0_burst_32_downstream_address;
  input            system_0_burst_32_downstream_burstcount;
  input   [  3: 0] system_0_burst_32_downstream_byteenable;
  input            system_0_burst_32_downstream_granted_Accel_Control_avalon_slave;
  input            system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave;
  input            system_0_burst_32_downstream_read;
  input            system_0_burst_32_downstream_read_data_valid_Accel_Control_avalon_slave;
  input            system_0_burst_32_downstream_requests_Accel_Control_avalon_slave;
  input            system_0_burst_32_downstream_write;
  input   [ 31: 0] system_0_burst_32_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_32_downstream_readdatavalid;
  wire             r_0;
  reg     [  4: 0] system_0_burst_32_downstream_address_last_time;
  wire    [  4: 0] system_0_burst_32_downstream_address_to_slave;
  reg              system_0_burst_32_downstream_burstcount_last_time;
  reg     [  3: 0] system_0_burst_32_downstream_byteenable_last_time;
  wire             system_0_burst_32_downstream_latency_counter;
  reg              system_0_burst_32_downstream_read_last_time;
  wire    [ 31: 0] system_0_burst_32_downstream_readdata;
  wire             system_0_burst_32_downstream_readdatavalid;
  wire             system_0_burst_32_downstream_reset_n;
  wire             system_0_burst_32_downstream_run;
  wire             system_0_burst_32_downstream_waitrequest;
  reg              system_0_burst_32_downstream_write_last_time;
  reg     [ 31: 0] system_0_burst_32_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave | ~system_0_burst_32_downstream_requests_Accel_Control_avalon_slave) & ((~system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave | ~system_0_burst_32_downstream_read | (1 & ~d1_Accel_Control_avalon_slave_end_xfer & system_0_burst_32_downstream_read))) & ((~system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave | ~system_0_burst_32_downstream_write | (1 & system_0_burst_32_downstream_write)));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_32_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_32_downstream_address_to_slave = system_0_burst_32_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_32_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_32_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_32_downstream_readdatavalid |
    system_0_burst_32_downstream_read_data_valid_Accel_Control_avalon_slave;

  //system_0_burst_32/downstream readdata mux, which is an e_mux
  assign system_0_burst_32_downstream_readdata = Accel_Control_avalon_slave_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_32_downstream_waitrequest = ~system_0_burst_32_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_32_downstream_latency_counter = 0;

  //system_0_burst_32_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_32_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_32_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_32_downstream_address_last_time <= 0;
      else 
        system_0_burst_32_downstream_address_last_time <= system_0_burst_32_downstream_address;
    end


  //system_0_burst_32/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_32_downstream_waitrequest & (system_0_burst_32_downstream_read | system_0_burst_32_downstream_write);
    end


  //system_0_burst_32_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_32_downstream_address != system_0_burst_32_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_32_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_32_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_32_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_32_downstream_burstcount_last_time <= system_0_burst_32_downstream_burstcount;
    end


  //system_0_burst_32_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_32_downstream_burstcount != system_0_burst_32_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_32_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_32_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_32_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_32_downstream_byteenable_last_time <= system_0_burst_32_downstream_byteenable;
    end


  //system_0_burst_32_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_32_downstream_byteenable != system_0_burst_32_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_32_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_32_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_32_downstream_read_last_time <= 0;
      else 
        system_0_burst_32_downstream_read_last_time <= system_0_burst_32_downstream_read;
    end


  //system_0_burst_32_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_32_downstream_read != system_0_burst_32_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_32_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_32_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_32_downstream_write_last_time <= 0;
      else 
        system_0_burst_32_downstream_write_last_time <= system_0_burst_32_downstream_write;
    end


  //system_0_burst_32_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_32_downstream_write != system_0_burst_32_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_32_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_32_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_32_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_32_downstream_writedata_last_time <= system_0_burst_32_downstream_writedata;
    end


  //system_0_burst_32_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_32_downstream_writedata != system_0_burst_32_downstream_writedata_last_time) & system_0_burst_32_downstream_write)
        begin
          $write("%0d ns: system_0_burst_32_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_33_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_33_upstream_module (
                                                                                    // inputs:
                                                                                     clear_fifo,
                                                                                     clk,
                                                                                     data_in,
                                                                                     read,
                                                                                     reset_n,
                                                                                     sync_reset,
                                                                                     write,

                                                                                    // outputs:
                                                                                     data_out,
                                                                                     empty,
                                                                                     fifo_contains_ones_n,
                                                                                     full
                                                                                  )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_33_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_instruction_master_address_to_slave,
                                                cpu_0_instruction_master_burstcount,
                                                cpu_0_instruction_master_latency_counter,
                                                cpu_0_instruction_master_read,
                                                cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register,
                                                cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register,
                                                cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register,
                                                cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register,
                                                cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register,
                                                reset_n,
                                                system_0_burst_33_upstream_readdata,
                                                system_0_burst_33_upstream_readdatavalid,
                                                system_0_burst_33_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_instruction_master_granted_system_0_burst_33_upstream,
                                                cpu_0_instruction_master_qualified_request_system_0_burst_33_upstream,
                                                cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream,
                                                cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register,
                                                cpu_0_instruction_master_requests_system_0_burst_33_upstream,
                                                d1_system_0_burst_33_upstream_end_xfer,
                                                system_0_burst_33_upstream_address,
                                                system_0_burst_33_upstream_byteaddress,
                                                system_0_burst_33_upstream_byteenable,
                                                system_0_burst_33_upstream_debugaccess,
                                                system_0_burst_33_upstream_read,
                                                system_0_burst_33_upstream_readdata_from_sa,
                                                system_0_burst_33_upstream_waitrequest_from_sa,
                                                system_0_burst_33_upstream_write
                                             )
;

  output           cpu_0_instruction_master_granted_system_0_burst_33_upstream;
  output           cpu_0_instruction_master_qualified_request_system_0_burst_33_upstream;
  output           cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream;
  output           cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register;
  output           cpu_0_instruction_master_requests_system_0_burst_33_upstream;
  output           d1_system_0_burst_33_upstream_end_xfer;
  output  [  4: 0] system_0_burst_33_upstream_address;
  output  [  6: 0] system_0_burst_33_upstream_byteaddress;
  output  [  3: 0] system_0_burst_33_upstream_byteenable;
  output           system_0_burst_33_upstream_debugaccess;
  output           system_0_burst_33_upstream_read;
  output  [ 31: 0] system_0_burst_33_upstream_readdata_from_sa;
  output           system_0_burst_33_upstream_waitrequest_from_sa;
  output           system_0_burst_33_upstream_write;
  input            clk;
  input   [ 24: 0] cpu_0_instruction_master_address_to_slave;
  input   [  3: 0] cpu_0_instruction_master_burstcount;
  input            cpu_0_instruction_master_latency_counter;
  input            cpu_0_instruction_master_read;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register;
  input            reset_n;
  input   [ 31: 0] system_0_burst_33_upstream_readdata;
  input            system_0_burst_33_upstream_readdatavalid;
  input            system_0_burst_33_upstream_waitrequest;

  wire             cpu_0_instruction_master_arbiterlock;
  wire             cpu_0_instruction_master_arbiterlock2;
  wire             cpu_0_instruction_master_continuerequest;
  wire             cpu_0_instruction_master_granted_system_0_burst_33_upstream;
  wire             cpu_0_instruction_master_qualified_request_system_0_burst_33_upstream;
  wire             cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_33_upstream;
  wire             cpu_0_instruction_master_rdv_fifo_output_from_system_0_burst_33_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register;
  wire             cpu_0_instruction_master_requests_system_0_burst_33_upstream;
  wire             cpu_0_instruction_master_saved_grant_system_0_burst_33_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_33_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_33_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_33_upstream_load_fifo;
  wire    [  4: 0] system_0_burst_33_upstream_address;
  wire             system_0_burst_33_upstream_allgrants;
  wire             system_0_burst_33_upstream_allow_new_arb_cycle;
  wire             system_0_burst_33_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_33_upstream_any_continuerequest;
  wire             system_0_burst_33_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_33_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_33_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_33_upstream_arb_share_set_values;
  wire             system_0_burst_33_upstream_beginbursttransfer_internal;
  wire             system_0_burst_33_upstream_begins_xfer;
  wire             system_0_burst_33_upstream_burstcount_fifo_empty;
  wire    [  6: 0] system_0_burst_33_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_33_upstream_byteenable;
  reg     [  3: 0] system_0_burst_33_upstream_current_burst;
  wire    [  3: 0] system_0_burst_33_upstream_current_burst_minus_one;
  wire             system_0_burst_33_upstream_debugaccess;
  wire             system_0_burst_33_upstream_end_xfer;
  wire             system_0_burst_33_upstream_firsttransfer;
  wire             system_0_burst_33_upstream_grant_vector;
  wire             system_0_burst_33_upstream_in_a_read_cycle;
  wire             system_0_burst_33_upstream_in_a_write_cycle;
  reg              system_0_burst_33_upstream_load_fifo;
  wire             system_0_burst_33_upstream_master_qreq_vector;
  wire             system_0_burst_33_upstream_move_on_to_next_transaction;
  wire    [  3: 0] system_0_burst_33_upstream_next_burst_count;
  wire             system_0_burst_33_upstream_non_bursting_master_requests;
  wire             system_0_burst_33_upstream_read;
  wire    [ 31: 0] system_0_burst_33_upstream_readdata_from_sa;
  wire             system_0_burst_33_upstream_readdatavalid_from_sa;
  reg              system_0_burst_33_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_33_upstream_selected_burstcount;
  reg              system_0_burst_33_upstream_slavearbiterlockenable;
  wire             system_0_burst_33_upstream_slavearbiterlockenable2;
  wire             system_0_burst_33_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_33_upstream_transaction_burst_count;
  wire             system_0_burst_33_upstream_unreg_firsttransfer;
  wire             system_0_burst_33_upstream_waitrequest_from_sa;
  wire             system_0_burst_33_upstream_waits_for_read;
  wire             system_0_burst_33_upstream_waits_for_write;
  wire             system_0_burst_33_upstream_write;
  wire             wait_for_system_0_burst_33_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_33_upstream_end_xfer;
    end


  assign system_0_burst_33_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_instruction_master_qualified_request_system_0_burst_33_upstream));
  //assign system_0_burst_33_upstream_readdatavalid_from_sa = system_0_burst_33_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_33_upstream_readdatavalid_from_sa = system_0_burst_33_upstream_readdatavalid;

  //assign system_0_burst_33_upstream_readdata_from_sa = system_0_burst_33_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_33_upstream_readdata_from_sa = system_0_burst_33_upstream_readdata;

  assign cpu_0_instruction_master_requests_system_0_burst_33_upstream = (({cpu_0_instruction_master_address_to_slave[24 : 5] , 5'b0} == 25'h190a0a0) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
  //assign system_0_burst_33_upstream_waitrequest_from_sa = system_0_burst_33_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_33_upstream_waitrequest_from_sa = system_0_burst_33_upstream_waitrequest;

  //system_0_burst_33_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_33_upstream_arb_share_set_values = 1;

  //system_0_burst_33_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_33_upstream_non_bursting_master_requests = 0;

  //system_0_burst_33_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_33_upstream_any_bursting_master_saved_grant = cpu_0_instruction_master_saved_grant_system_0_burst_33_upstream;

  //system_0_burst_33_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_33_upstream_arb_share_counter_next_value = system_0_burst_33_upstream_firsttransfer ? (system_0_burst_33_upstream_arb_share_set_values - 1) : |system_0_burst_33_upstream_arb_share_counter ? (system_0_burst_33_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_33_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_33_upstream_allgrants = |system_0_burst_33_upstream_grant_vector;

  //system_0_burst_33_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_33_upstream_end_xfer = ~(system_0_burst_33_upstream_waits_for_read | system_0_burst_33_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_33_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_33_upstream = system_0_burst_33_upstream_end_xfer & (~system_0_burst_33_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_33_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_33_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_33_upstream & system_0_burst_33_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_33_upstream & ~system_0_burst_33_upstream_non_bursting_master_requests);

  //system_0_burst_33_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_33_upstream_arb_share_counter <= 0;
      else if (system_0_burst_33_upstream_arb_counter_enable)
          system_0_burst_33_upstream_arb_share_counter <= system_0_burst_33_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_33_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_33_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_33_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_33_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_33_upstream & ~system_0_burst_33_upstream_non_bursting_master_requests))
          system_0_burst_33_upstream_slavearbiterlockenable <= |system_0_burst_33_upstream_arb_share_counter_next_value;
    end


  //cpu_0/instruction_master system_0_burst_33/upstream arbiterlock, which is an e_assign
  assign cpu_0_instruction_master_arbiterlock = system_0_burst_33_upstream_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;

  //system_0_burst_33_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_33_upstream_slavearbiterlockenable2 = |system_0_burst_33_upstream_arb_share_counter_next_value;

  //cpu_0/instruction_master system_0_burst_33/upstream arbiterlock2, which is an e_assign
  assign cpu_0_instruction_master_arbiterlock2 = system_0_burst_33_upstream_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;

  //system_0_burst_33_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_33_upstream_any_continuerequest = 1;

  //cpu_0_instruction_master_continuerequest continued request, which is an e_assign
  assign cpu_0_instruction_master_continuerequest = 1;

  assign cpu_0_instruction_master_qualified_request_system_0_burst_33_upstream = cpu_0_instruction_master_requests_system_0_burst_33_upstream & ~((cpu_0_instruction_master_read & ((cpu_0_instruction_master_latency_counter != 0) | (1 < cpu_0_instruction_master_latency_counter) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register))));
  //unique name for system_0_burst_33_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_33_upstream_move_on_to_next_transaction = system_0_burst_33_upstream_this_cycle_is_the_last_burst & system_0_burst_33_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_33_upstream, which is an e_mux
  assign system_0_burst_33_upstream_selected_burstcount = (cpu_0_instruction_master_granted_system_0_burst_33_upstream)? cpu_0_instruction_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_33_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_33_upstream_module burstcount_fifo_for_system_0_burst_33_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_33_upstream_selected_burstcount),
      .data_out             (system_0_burst_33_upstream_transaction_burst_count),
      .empty                (system_0_burst_33_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_33_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_33_upstream_waits_for_read & system_0_burst_33_upstream_load_fifo & ~(system_0_burst_33_upstream_this_cycle_is_the_last_burst & system_0_burst_33_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_33_upstream current burst minus one, which is an e_assign
  assign system_0_burst_33_upstream_current_burst_minus_one = system_0_burst_33_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_33_upstream, which is an e_mux
  assign system_0_burst_33_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_33_upstream_waits_for_read) & ~system_0_burst_33_upstream_load_fifo))? system_0_burst_33_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_33_upstream_waits_for_read & system_0_burst_33_upstream_this_cycle_is_the_last_burst & system_0_burst_33_upstream_burstcount_fifo_empty))? system_0_burst_33_upstream_selected_burstcount :
    (system_0_burst_33_upstream_this_cycle_is_the_last_burst)? system_0_burst_33_upstream_transaction_burst_count :
    system_0_burst_33_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_33_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_33_upstream_current_burst <= 0;
      else if (system_0_burst_33_upstream_readdatavalid_from_sa | (~system_0_burst_33_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_33_upstream_waits_for_read)))
          system_0_burst_33_upstream_current_burst <= system_0_burst_33_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_33_upstream_load_fifo = (~system_0_burst_33_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_33_upstream_waits_for_read) & system_0_burst_33_upstream_load_fifo))? 1 :
    ~system_0_burst_33_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_33_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_33_upstream_waits_for_read) & ~system_0_burst_33_upstream_load_fifo | system_0_burst_33_upstream_this_cycle_is_the_last_burst)
          system_0_burst_33_upstream_load_fifo <= p0_system_0_burst_33_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_33_upstream, which is an e_assign
  assign system_0_burst_33_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_33_upstream_current_burst_minus_one) & system_0_burst_33_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_33_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_33_upstream_module rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_33_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_instruction_master_granted_system_0_burst_33_upstream),
      .data_out             (cpu_0_instruction_master_rdv_fifo_output_from_system_0_burst_33_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_33_upstream),
      .full                 (),
      .read                 (system_0_burst_33_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_33_upstream_waits_for_read)
    );

  assign cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register = ~cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_33_upstream;
  //local readdatavalid cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream, which is an e_mux
  assign cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream = system_0_burst_33_upstream_readdatavalid_from_sa;

  //byteaddress mux for system_0_burst_33/upstream, which is an e_mux
  assign system_0_burst_33_upstream_byteaddress = cpu_0_instruction_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_instruction_master_granted_system_0_burst_33_upstream = cpu_0_instruction_master_qualified_request_system_0_burst_33_upstream;

  //cpu_0/instruction_master saved-grant system_0_burst_33/upstream, which is an e_assign
  assign cpu_0_instruction_master_saved_grant_system_0_burst_33_upstream = cpu_0_instruction_master_requests_system_0_burst_33_upstream;

  //allow new arb cycle for system_0_burst_33/upstream, which is an e_assign
  assign system_0_burst_33_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_33_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_33_upstream_master_qreq_vector = 1;

  //system_0_burst_33_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_33_upstream_firsttransfer = system_0_burst_33_upstream_begins_xfer ? system_0_burst_33_upstream_unreg_firsttransfer : system_0_burst_33_upstream_reg_firsttransfer;

  //system_0_burst_33_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_33_upstream_unreg_firsttransfer = ~(system_0_burst_33_upstream_slavearbiterlockenable & system_0_burst_33_upstream_any_continuerequest);

  //system_0_burst_33_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_33_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_33_upstream_begins_xfer)
          system_0_burst_33_upstream_reg_firsttransfer <= system_0_burst_33_upstream_unreg_firsttransfer;
    end


  //system_0_burst_33_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_33_upstream_beginbursttransfer_internal = system_0_burst_33_upstream_begins_xfer;

  //system_0_burst_33_upstream_read assignment, which is an e_mux
  assign system_0_burst_33_upstream_read = cpu_0_instruction_master_granted_system_0_burst_33_upstream & cpu_0_instruction_master_read;

  //system_0_burst_33_upstream_write assignment, which is an e_mux
  assign system_0_burst_33_upstream_write = 0;

  //system_0_burst_33_upstream_address mux, which is an e_mux
  assign system_0_burst_33_upstream_address = cpu_0_instruction_master_address_to_slave;

  //d1_system_0_burst_33_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_33_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_33_upstream_end_xfer <= system_0_burst_33_upstream_end_xfer;
    end


  //system_0_burst_33_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_33_upstream_waits_for_read = system_0_burst_33_upstream_in_a_read_cycle & system_0_burst_33_upstream_waitrequest_from_sa;

  //system_0_burst_33_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_33_upstream_in_a_read_cycle = cpu_0_instruction_master_granted_system_0_burst_33_upstream & cpu_0_instruction_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_33_upstream_in_a_read_cycle;

  //system_0_burst_33_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_33_upstream_waits_for_write = system_0_burst_33_upstream_in_a_write_cycle & system_0_burst_33_upstream_waitrequest_from_sa;

  //system_0_burst_33_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_33_upstream_in_a_write_cycle = 0;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_33_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_33_upstream_counter = 0;
  //system_0_burst_33_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_33_upstream_byteenable = -1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_33_upstream_debugaccess = 0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_33/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/instruction_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_instruction_master_requests_system_0_burst_33_upstream && (cpu_0_instruction_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/instruction_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_33/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_33_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_i2c_master_avalon_slave_0_end_xfer,
                                                  i2c_master_avalon_slave_0_readdata_from_sa,
                                                  i2c_master_avalon_slave_0_waitrequest_n_from_sa,
                                                  reset_n,
                                                  system_0_burst_33_downstream_address,
                                                  system_0_burst_33_downstream_burstcount,
                                                  system_0_burst_33_downstream_byteenable,
                                                  system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0,
                                                  system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0,
                                                  system_0_burst_33_downstream_read,
                                                  system_0_burst_33_downstream_read_data_valid_i2c_master_avalon_slave_0,
                                                  system_0_burst_33_downstream_requests_i2c_master_avalon_slave_0,
                                                  system_0_burst_33_downstream_write,
                                                  system_0_burst_33_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_33_downstream_address_to_slave,
                                                  system_0_burst_33_downstream_latency_counter,
                                                  system_0_burst_33_downstream_readdata,
                                                  system_0_burst_33_downstream_readdatavalid,
                                                  system_0_burst_33_downstream_reset_n,
                                                  system_0_burst_33_downstream_waitrequest
                                               )
;

  output  [  4: 0] system_0_burst_33_downstream_address_to_slave;
  output           system_0_burst_33_downstream_latency_counter;
  output  [ 31: 0] system_0_burst_33_downstream_readdata;
  output           system_0_burst_33_downstream_readdatavalid;
  output           system_0_burst_33_downstream_reset_n;
  output           system_0_burst_33_downstream_waitrequest;
  input            clk;
  input            d1_i2c_master_avalon_slave_0_end_xfer;
  input   [ 31: 0] i2c_master_avalon_slave_0_readdata_from_sa;
  input            i2c_master_avalon_slave_0_waitrequest_n_from_sa;
  input            reset_n;
  input   [  4: 0] system_0_burst_33_downstream_address;
  input            system_0_burst_33_downstream_burstcount;
  input   [  3: 0] system_0_burst_33_downstream_byteenable;
  input            system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0;
  input            system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0;
  input            system_0_burst_33_downstream_read;
  input            system_0_burst_33_downstream_read_data_valid_i2c_master_avalon_slave_0;
  input            system_0_burst_33_downstream_requests_i2c_master_avalon_slave_0;
  input            system_0_burst_33_downstream_write;
  input   [ 31: 0] system_0_burst_33_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             latency_load_value;
  wire             p1_system_0_burst_33_downstream_latency_counter;
  wire             pre_flush_system_0_burst_33_downstream_readdatavalid;
  wire             r_0;
  reg     [  4: 0] system_0_burst_33_downstream_address_last_time;
  wire    [  4: 0] system_0_burst_33_downstream_address_to_slave;
  reg              system_0_burst_33_downstream_burstcount_last_time;
  reg     [  3: 0] system_0_burst_33_downstream_byteenable_last_time;
  wire             system_0_burst_33_downstream_is_granted_some_slave;
  reg              system_0_burst_33_downstream_latency_counter;
  reg              system_0_burst_33_downstream_read_but_no_slave_selected;
  reg              system_0_burst_33_downstream_read_last_time;
  wire    [ 31: 0] system_0_burst_33_downstream_readdata;
  wire             system_0_burst_33_downstream_readdatavalid;
  wire             system_0_burst_33_downstream_reset_n;
  wire             system_0_burst_33_downstream_run;
  wire             system_0_burst_33_downstream_waitrequest;
  reg              system_0_burst_33_downstream_write_last_time;
  reg     [ 31: 0] system_0_burst_33_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0 | ~system_0_burst_33_downstream_requests_i2c_master_avalon_slave_0) & (system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0 | ~system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0) & ((~system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0 | ~(system_0_burst_33_downstream_read | system_0_burst_33_downstream_write) | (1 & i2c_master_avalon_slave_0_waitrequest_n_from_sa & (system_0_burst_33_downstream_read | system_0_burst_33_downstream_write)))) & ((~system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0 | ~(system_0_burst_33_downstream_read | system_0_burst_33_downstream_write) | (1 & i2c_master_avalon_slave_0_waitrequest_n_from_sa & (system_0_burst_33_downstream_read | system_0_burst_33_downstream_write))));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_33_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_33_downstream_address_to_slave = system_0_burst_33_downstream_address;

  //system_0_burst_33_downstream_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_33_downstream_read_but_no_slave_selected <= 0;
      else 
        system_0_burst_33_downstream_read_but_no_slave_selected <= system_0_burst_33_downstream_read & system_0_burst_33_downstream_run & ~system_0_burst_33_downstream_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign system_0_burst_33_downstream_is_granted_some_slave = system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_33_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_33_downstream_readdatavalid = system_0_burst_33_downstream_read_but_no_slave_selected |
    pre_flush_system_0_burst_33_downstream_readdatavalid |
    system_0_burst_33_downstream_read_data_valid_i2c_master_avalon_slave_0;

  //system_0_burst_33/downstream readdata mux, which is an e_mux
  assign system_0_burst_33_downstream_readdata = i2c_master_avalon_slave_0_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_33_downstream_waitrequest = ~system_0_burst_33_downstream_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_33_downstream_latency_counter <= 0;
      else 
        system_0_burst_33_downstream_latency_counter <= p1_system_0_burst_33_downstream_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_system_0_burst_33_downstream_latency_counter = ((system_0_burst_33_downstream_run & system_0_burst_33_downstream_read))? latency_load_value :
    (system_0_burst_33_downstream_latency_counter)? system_0_burst_33_downstream_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = 0;

  //system_0_burst_33_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_33_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_33_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_33_downstream_address_last_time <= 0;
      else 
        system_0_burst_33_downstream_address_last_time <= system_0_burst_33_downstream_address;
    end


  //system_0_burst_33/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_33_downstream_waitrequest & (system_0_burst_33_downstream_read | system_0_burst_33_downstream_write);
    end


  //system_0_burst_33_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_33_downstream_address != system_0_burst_33_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_33_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_33_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_33_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_33_downstream_burstcount_last_time <= system_0_burst_33_downstream_burstcount;
    end


  //system_0_burst_33_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_33_downstream_burstcount != system_0_burst_33_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_33_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_33_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_33_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_33_downstream_byteenable_last_time <= system_0_burst_33_downstream_byteenable;
    end


  //system_0_burst_33_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_33_downstream_byteenable != system_0_burst_33_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_33_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_33_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_33_downstream_read_last_time <= 0;
      else 
        system_0_burst_33_downstream_read_last_time <= system_0_burst_33_downstream_read;
    end


  //system_0_burst_33_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_33_downstream_read != system_0_burst_33_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_33_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_33_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_33_downstream_write_last_time <= 0;
      else 
        system_0_burst_33_downstream_write_last_time <= system_0_burst_33_downstream_write;
    end


  //system_0_burst_33_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_33_downstream_write != system_0_burst_33_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_33_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_33_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_33_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_33_downstream_writedata_last_time <= system_0_burst_33_downstream_writedata;
    end


  //system_0_burst_33_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_33_downstream_writedata != system_0_burst_33_downstream_writedata_last_time) & system_0_burst_33_downstream_write)
        begin
          $write("%0d ns: system_0_burst_33_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_34_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_34_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_34_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_34_upstream_readdata,
                                                system_0_burst_34_upstream_readdatavalid,
                                                system_0_burst_34_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_34_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_34_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_34_upstream,
                                                d1_system_0_burst_34_upstream_end_xfer,
                                                system_0_burst_34_upstream_address,
                                                system_0_burst_34_upstream_burstcount,
                                                system_0_burst_34_upstream_byteaddress,
                                                system_0_burst_34_upstream_byteenable,
                                                system_0_burst_34_upstream_debugaccess,
                                                system_0_burst_34_upstream_read,
                                                system_0_burst_34_upstream_readdata_from_sa,
                                                system_0_burst_34_upstream_waitrequest_from_sa,
                                                system_0_burst_34_upstream_write,
                                                system_0_burst_34_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_34_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_34_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_34_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_34_upstream;
  output           d1_system_0_burst_34_upstream_end_xfer;
  output  [  4: 0] system_0_burst_34_upstream_address;
  output  [  3: 0] system_0_burst_34_upstream_burstcount;
  output  [  6: 0] system_0_burst_34_upstream_byteaddress;
  output  [  3: 0] system_0_burst_34_upstream_byteenable;
  output           system_0_burst_34_upstream_debugaccess;
  output           system_0_burst_34_upstream_read;
  output  [ 31: 0] system_0_burst_34_upstream_readdata_from_sa;
  output           system_0_burst_34_upstream_waitrequest_from_sa;
  output           system_0_burst_34_upstream_write;
  output  [ 31: 0] system_0_burst_34_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [ 31: 0] system_0_burst_34_upstream_readdata;
  input            system_0_burst_34_upstream_readdatavalid;
  input            system_0_burst_34_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_34_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_34_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_34_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_34_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_34_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_34_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_34_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_34_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_34_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_34_upstream_load_fifo;
  wire    [  4: 0] system_0_burst_34_upstream_address;
  wire             system_0_burst_34_upstream_allgrants;
  wire             system_0_burst_34_upstream_allow_new_arb_cycle;
  wire             system_0_burst_34_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_34_upstream_any_continuerequest;
  wire             system_0_burst_34_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_34_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_34_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_34_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_34_upstream_bbt_burstcounter;
  wire             system_0_burst_34_upstream_beginbursttransfer_internal;
  wire             system_0_burst_34_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_34_upstream_burstcount;
  wire             system_0_burst_34_upstream_burstcount_fifo_empty;
  wire    [  6: 0] system_0_burst_34_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_34_upstream_byteenable;
  reg     [  3: 0] system_0_burst_34_upstream_current_burst;
  wire    [  3: 0] system_0_burst_34_upstream_current_burst_minus_one;
  wire             system_0_burst_34_upstream_debugaccess;
  wire             system_0_burst_34_upstream_end_xfer;
  wire             system_0_burst_34_upstream_firsttransfer;
  wire             system_0_burst_34_upstream_grant_vector;
  wire             system_0_burst_34_upstream_in_a_read_cycle;
  wire             system_0_burst_34_upstream_in_a_write_cycle;
  reg              system_0_burst_34_upstream_load_fifo;
  wire             system_0_burst_34_upstream_master_qreq_vector;
  wire             system_0_burst_34_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_34_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_34_upstream_next_burst_count;
  wire             system_0_burst_34_upstream_non_bursting_master_requests;
  wire             system_0_burst_34_upstream_read;
  wire    [ 31: 0] system_0_burst_34_upstream_readdata_from_sa;
  wire             system_0_burst_34_upstream_readdatavalid_from_sa;
  reg              system_0_burst_34_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_34_upstream_selected_burstcount;
  reg              system_0_burst_34_upstream_slavearbiterlockenable;
  wire             system_0_burst_34_upstream_slavearbiterlockenable2;
  wire             system_0_burst_34_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_34_upstream_transaction_burst_count;
  wire             system_0_burst_34_upstream_unreg_firsttransfer;
  wire             system_0_burst_34_upstream_waitrequest_from_sa;
  wire             system_0_burst_34_upstream_waits_for_read;
  wire             system_0_burst_34_upstream_waits_for_write;
  wire             system_0_burst_34_upstream_write;
  wire    [ 31: 0] system_0_burst_34_upstream_writedata;
  wire             wait_for_system_0_burst_34_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_34_upstream_end_xfer;
    end


  assign system_0_burst_34_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_34_upstream));
  //assign system_0_burst_34_upstream_readdatavalid_from_sa = system_0_burst_34_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_34_upstream_readdatavalid_from_sa = system_0_burst_34_upstream_readdatavalid;

  //assign system_0_burst_34_upstream_readdata_from_sa = system_0_burst_34_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_34_upstream_readdata_from_sa = system_0_burst_34_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_34_upstream = ({cpu_0_data_master_address_to_slave[24 : 5] , 5'b0} == 25'h190a0a0) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_34_upstream_waitrequest_from_sa = system_0_burst_34_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_34_upstream_waitrequest_from_sa = system_0_burst_34_upstream_waitrequest;

  //system_0_burst_34_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_34_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_34_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_34_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_34_upstream_non_bursting_master_requests = 0;

  //system_0_burst_34_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_34_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_34_upstream;

  //system_0_burst_34_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_34_upstream_arb_share_counter_next_value = system_0_burst_34_upstream_firsttransfer ? (system_0_burst_34_upstream_arb_share_set_values - 1) : |system_0_burst_34_upstream_arb_share_counter ? (system_0_burst_34_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_34_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_34_upstream_allgrants = |system_0_burst_34_upstream_grant_vector;

  //system_0_burst_34_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_34_upstream_end_xfer = ~(system_0_burst_34_upstream_waits_for_read | system_0_burst_34_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_34_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_34_upstream = system_0_burst_34_upstream_end_xfer & (~system_0_burst_34_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_34_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_34_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_34_upstream & system_0_burst_34_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_34_upstream & ~system_0_burst_34_upstream_non_bursting_master_requests);

  //system_0_burst_34_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_34_upstream_arb_share_counter <= 0;
      else if (system_0_burst_34_upstream_arb_counter_enable)
          system_0_burst_34_upstream_arb_share_counter <= system_0_burst_34_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_34_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_34_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_34_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_34_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_34_upstream & ~system_0_burst_34_upstream_non_bursting_master_requests))
          system_0_burst_34_upstream_slavearbiterlockenable <= |system_0_burst_34_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_34/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_34_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_34_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_34_upstream_slavearbiterlockenable2 = |system_0_burst_34_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_34/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_34_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_34_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_34_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_34_upstream = cpu_0_data_master_requests_system_0_burst_34_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_34_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_34_upstream_move_on_to_next_transaction = system_0_burst_34_upstream_this_cycle_is_the_last_burst & system_0_burst_34_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_34_upstream, which is an e_mux
  assign system_0_burst_34_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_34_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_34_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_34_upstream_module burstcount_fifo_for_system_0_burst_34_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_34_upstream_selected_burstcount),
      .data_out             (system_0_burst_34_upstream_transaction_burst_count),
      .empty                (system_0_burst_34_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_34_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_34_upstream_waits_for_read & system_0_burst_34_upstream_load_fifo & ~(system_0_burst_34_upstream_this_cycle_is_the_last_burst & system_0_burst_34_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_34_upstream current burst minus one, which is an e_assign
  assign system_0_burst_34_upstream_current_burst_minus_one = system_0_burst_34_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_34_upstream, which is an e_mux
  assign system_0_burst_34_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_34_upstream_waits_for_read) & ~system_0_burst_34_upstream_load_fifo))? system_0_burst_34_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_34_upstream_waits_for_read & system_0_burst_34_upstream_this_cycle_is_the_last_burst & system_0_burst_34_upstream_burstcount_fifo_empty))? system_0_burst_34_upstream_selected_burstcount :
    (system_0_burst_34_upstream_this_cycle_is_the_last_burst)? system_0_burst_34_upstream_transaction_burst_count :
    system_0_burst_34_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_34_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_34_upstream_current_burst <= 0;
      else if (system_0_burst_34_upstream_readdatavalid_from_sa | (~system_0_burst_34_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_34_upstream_waits_for_read)))
          system_0_burst_34_upstream_current_burst <= system_0_burst_34_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_34_upstream_load_fifo = (~system_0_burst_34_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_34_upstream_waits_for_read) & system_0_burst_34_upstream_load_fifo))? 1 :
    ~system_0_burst_34_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_34_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_34_upstream_waits_for_read) & ~system_0_burst_34_upstream_load_fifo | system_0_burst_34_upstream_this_cycle_is_the_last_burst)
          system_0_burst_34_upstream_load_fifo <= p0_system_0_burst_34_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_34_upstream, which is an e_assign
  assign system_0_burst_34_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_34_upstream_current_burst_minus_one) & system_0_burst_34_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_34_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_34_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_34_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_34_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_34_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_34_upstream),
      .full                 (),
      .read                 (system_0_burst_34_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_34_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_34_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_34_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_34_upstream = system_0_burst_34_upstream_readdatavalid_from_sa;

  //system_0_burst_34_upstream_writedata mux, which is an e_mux
  assign system_0_burst_34_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_34/upstream, which is an e_mux
  assign system_0_burst_34_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_34_upstream = cpu_0_data_master_qualified_request_system_0_burst_34_upstream;

  //cpu_0/data_master saved-grant system_0_burst_34/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_34_upstream = cpu_0_data_master_requests_system_0_burst_34_upstream;

  //allow new arb cycle for system_0_burst_34/upstream, which is an e_assign
  assign system_0_burst_34_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_34_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_34_upstream_master_qreq_vector = 1;

  //system_0_burst_34_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_34_upstream_firsttransfer = system_0_burst_34_upstream_begins_xfer ? system_0_burst_34_upstream_unreg_firsttransfer : system_0_burst_34_upstream_reg_firsttransfer;

  //system_0_burst_34_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_34_upstream_unreg_firsttransfer = ~(system_0_burst_34_upstream_slavearbiterlockenable & system_0_burst_34_upstream_any_continuerequest);

  //system_0_burst_34_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_34_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_34_upstream_begins_xfer)
          system_0_burst_34_upstream_reg_firsttransfer <= system_0_burst_34_upstream_unreg_firsttransfer;
    end


  //system_0_burst_34_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_34_upstream_next_bbt_burstcount = ((((system_0_burst_34_upstream_write) && (system_0_burst_34_upstream_bbt_burstcounter == 0))))? (system_0_burst_34_upstream_burstcount - 1) :
    ((((system_0_burst_34_upstream_read) && (system_0_burst_34_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_34_upstream_bbt_burstcounter - 1);

  //system_0_burst_34_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_34_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_34_upstream_begins_xfer)
          system_0_burst_34_upstream_bbt_burstcounter <= system_0_burst_34_upstream_next_bbt_burstcount;
    end


  //system_0_burst_34_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_34_upstream_beginbursttransfer_internal = system_0_burst_34_upstream_begins_xfer & (system_0_burst_34_upstream_bbt_burstcounter == 0);

  //system_0_burst_34_upstream_read assignment, which is an e_mux
  assign system_0_burst_34_upstream_read = cpu_0_data_master_granted_system_0_burst_34_upstream & cpu_0_data_master_read;

  //system_0_burst_34_upstream_write assignment, which is an e_mux
  assign system_0_burst_34_upstream_write = cpu_0_data_master_granted_system_0_burst_34_upstream & cpu_0_data_master_write;

  //system_0_burst_34_upstream_address mux, which is an e_mux
  assign system_0_burst_34_upstream_address = cpu_0_data_master_address_to_slave;

  //d1_system_0_burst_34_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_34_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_34_upstream_end_xfer <= system_0_burst_34_upstream_end_xfer;
    end


  //system_0_burst_34_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_34_upstream_waits_for_read = system_0_burst_34_upstream_in_a_read_cycle & system_0_burst_34_upstream_waitrequest_from_sa;

  //system_0_burst_34_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_34_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_34_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_34_upstream_in_a_read_cycle;

  //system_0_burst_34_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_34_upstream_waits_for_write = system_0_burst_34_upstream_in_a_write_cycle & system_0_burst_34_upstream_waitrequest_from_sa;

  //system_0_burst_34_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_34_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_34_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_34_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_34_upstream_counter = 0;
  //system_0_burst_34_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_34_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_34_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_34_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_34_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_34_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_34_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_34/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_34_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_34/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_34_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_i2c_master_avalon_slave_0_end_xfer,
                                                  i2c_master_avalon_slave_0_readdata_from_sa,
                                                  i2c_master_avalon_slave_0_waitrequest_n_from_sa,
                                                  reset_n,
                                                  system_0_burst_34_downstream_address,
                                                  system_0_burst_34_downstream_burstcount,
                                                  system_0_burst_34_downstream_byteenable,
                                                  system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0,
                                                  system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0,
                                                  system_0_burst_34_downstream_read,
                                                  system_0_burst_34_downstream_read_data_valid_i2c_master_avalon_slave_0,
                                                  system_0_burst_34_downstream_requests_i2c_master_avalon_slave_0,
                                                  system_0_burst_34_downstream_write,
                                                  system_0_burst_34_downstream_writedata,

                                                 // outputs:
                                                  system_0_burst_34_downstream_address_to_slave,
                                                  system_0_burst_34_downstream_latency_counter,
                                                  system_0_burst_34_downstream_readdata,
                                                  system_0_burst_34_downstream_readdatavalid,
                                                  system_0_burst_34_downstream_reset_n,
                                                  system_0_burst_34_downstream_waitrequest
                                               )
;

  output  [  4: 0] system_0_burst_34_downstream_address_to_slave;
  output           system_0_burst_34_downstream_latency_counter;
  output  [ 31: 0] system_0_burst_34_downstream_readdata;
  output           system_0_burst_34_downstream_readdatavalid;
  output           system_0_burst_34_downstream_reset_n;
  output           system_0_burst_34_downstream_waitrequest;
  input            clk;
  input            d1_i2c_master_avalon_slave_0_end_xfer;
  input   [ 31: 0] i2c_master_avalon_slave_0_readdata_from_sa;
  input            i2c_master_avalon_slave_0_waitrequest_n_from_sa;
  input            reset_n;
  input   [  4: 0] system_0_burst_34_downstream_address;
  input            system_0_burst_34_downstream_burstcount;
  input   [  3: 0] system_0_burst_34_downstream_byteenable;
  input            system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0;
  input            system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0;
  input            system_0_burst_34_downstream_read;
  input            system_0_burst_34_downstream_read_data_valid_i2c_master_avalon_slave_0;
  input            system_0_burst_34_downstream_requests_i2c_master_avalon_slave_0;
  input            system_0_burst_34_downstream_write;
  input   [ 31: 0] system_0_burst_34_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             latency_load_value;
  wire             p1_system_0_burst_34_downstream_latency_counter;
  wire             pre_flush_system_0_burst_34_downstream_readdatavalid;
  wire             r_0;
  reg     [  4: 0] system_0_burst_34_downstream_address_last_time;
  wire    [  4: 0] system_0_burst_34_downstream_address_to_slave;
  reg              system_0_burst_34_downstream_burstcount_last_time;
  reg     [  3: 0] system_0_burst_34_downstream_byteenable_last_time;
  wire             system_0_burst_34_downstream_is_granted_some_slave;
  reg              system_0_burst_34_downstream_latency_counter;
  reg              system_0_burst_34_downstream_read_but_no_slave_selected;
  reg              system_0_burst_34_downstream_read_last_time;
  wire    [ 31: 0] system_0_burst_34_downstream_readdata;
  wire             system_0_burst_34_downstream_readdatavalid;
  wire             system_0_burst_34_downstream_reset_n;
  wire             system_0_burst_34_downstream_run;
  wire             system_0_burst_34_downstream_waitrequest;
  reg              system_0_burst_34_downstream_write_last_time;
  reg     [ 31: 0] system_0_burst_34_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0 | ~system_0_burst_34_downstream_requests_i2c_master_avalon_slave_0) & (system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0 | ~system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0) & ((~system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0 | ~(system_0_burst_34_downstream_read | system_0_burst_34_downstream_write) | (1 & i2c_master_avalon_slave_0_waitrequest_n_from_sa & (system_0_burst_34_downstream_read | system_0_burst_34_downstream_write)))) & ((~system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0 | ~(system_0_burst_34_downstream_read | system_0_burst_34_downstream_write) | (1 & i2c_master_avalon_slave_0_waitrequest_n_from_sa & (system_0_burst_34_downstream_read | system_0_burst_34_downstream_write))));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_34_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_34_downstream_address_to_slave = system_0_burst_34_downstream_address;

  //system_0_burst_34_downstream_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_34_downstream_read_but_no_slave_selected <= 0;
      else 
        system_0_burst_34_downstream_read_but_no_slave_selected <= system_0_burst_34_downstream_read & system_0_burst_34_downstream_run & ~system_0_burst_34_downstream_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign system_0_burst_34_downstream_is_granted_some_slave = system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_34_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_34_downstream_readdatavalid = system_0_burst_34_downstream_read_but_no_slave_selected |
    pre_flush_system_0_burst_34_downstream_readdatavalid |
    system_0_burst_34_downstream_read_data_valid_i2c_master_avalon_slave_0;

  //system_0_burst_34/downstream readdata mux, which is an e_mux
  assign system_0_burst_34_downstream_readdata = i2c_master_avalon_slave_0_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_34_downstream_waitrequest = ~system_0_burst_34_downstream_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_34_downstream_latency_counter <= 0;
      else 
        system_0_burst_34_downstream_latency_counter <= p1_system_0_burst_34_downstream_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_system_0_burst_34_downstream_latency_counter = ((system_0_burst_34_downstream_run & system_0_burst_34_downstream_read))? latency_load_value :
    (system_0_burst_34_downstream_latency_counter)? system_0_burst_34_downstream_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = 0;

  //system_0_burst_34_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_34_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_34_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_34_downstream_address_last_time <= 0;
      else 
        system_0_burst_34_downstream_address_last_time <= system_0_burst_34_downstream_address;
    end


  //system_0_burst_34/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_34_downstream_waitrequest & (system_0_burst_34_downstream_read | system_0_burst_34_downstream_write);
    end


  //system_0_burst_34_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_34_downstream_address != system_0_burst_34_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_34_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_34_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_34_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_34_downstream_burstcount_last_time <= system_0_burst_34_downstream_burstcount;
    end


  //system_0_burst_34_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_34_downstream_burstcount != system_0_burst_34_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_34_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_34_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_34_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_34_downstream_byteenable_last_time <= system_0_burst_34_downstream_byteenable;
    end


  //system_0_burst_34_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_34_downstream_byteenable != system_0_burst_34_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_34_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_34_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_34_downstream_read_last_time <= 0;
      else 
        system_0_burst_34_downstream_read_last_time <= system_0_burst_34_downstream_read;
    end


  //system_0_burst_34_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_34_downstream_read != system_0_burst_34_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_34_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_34_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_34_downstream_write_last_time <= 0;
      else 
        system_0_burst_34_downstream_write_last_time <= system_0_burst_34_downstream_write;
    end


  //system_0_burst_34_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_34_downstream_write != system_0_burst_34_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_34_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_34_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_34_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_34_downstream_writedata_last_time <= system_0_burst_34_downstream_writedata;
    end


  //system_0_burst_34_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_34_downstream_writedata != system_0_burst_34_downstream_writedata_last_time) & system_0_burst_34_downstream_write)
        begin
          $write("%0d ns: system_0_burst_34_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_35_upstream_module (
                                                               // inputs:
                                                                clear_fifo,
                                                                clk,
                                                                data_in,
                                                                read,
                                                                reset_n,
                                                                sync_reset,
                                                                write,

                                                               // outputs:
                                                                data_out,
                                                                empty,
                                                                fifo_contains_ones_n,
                                                                full
                                                             )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_35_upstream_module (
                                                                             // inputs:
                                                                              clear_fifo,
                                                                              clk,
                                                                              data_in,
                                                                              read,
                                                                              reset_n,
                                                                              sync_reset,
                                                                              write,

                                                                             // outputs:
                                                                              data_out,
                                                                              empty,
                                                                              fifo_contains_ones_n,
                                                                              full
                                                                           )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_35_upstream_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_0_data_master_address_to_slave,
                                                cpu_0_data_master_burstcount,
                                                cpu_0_data_master_byteenable,
                                                cpu_0_data_master_debugaccess,
                                                cpu_0_data_master_latency_counter,
                                                cpu_0_data_master_read,
                                                cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                                cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                                cpu_0_data_master_write,
                                                cpu_0_data_master_writedata,
                                                reset_n,
                                                system_0_burst_35_upstream_readdata,
                                                system_0_burst_35_upstream_readdatavalid,
                                                system_0_burst_35_upstream_waitrequest,

                                               // outputs:
                                                cpu_0_data_master_granted_system_0_burst_35_upstream,
                                                cpu_0_data_master_qualified_request_system_0_burst_35_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream,
                                                cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                                cpu_0_data_master_requests_system_0_burst_35_upstream,
                                                d1_system_0_burst_35_upstream_end_xfer,
                                                system_0_burst_35_upstream_address,
                                                system_0_burst_35_upstream_burstcount,
                                                system_0_burst_35_upstream_byteaddress,
                                                system_0_burst_35_upstream_byteenable,
                                                system_0_burst_35_upstream_debugaccess,
                                                system_0_burst_35_upstream_read,
                                                system_0_burst_35_upstream_readdata_from_sa,
                                                system_0_burst_35_upstream_waitrequest_from_sa,
                                                system_0_burst_35_upstream_write,
                                                system_0_burst_35_upstream_writedata
                                             )
;

  output           cpu_0_data_master_granted_system_0_burst_35_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_35_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_35_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_35_upstream;
  output           d1_system_0_burst_35_upstream_end_xfer;
  output  [  3: 0] system_0_burst_35_upstream_address;
  output  [  3: 0] system_0_burst_35_upstream_burstcount;
  output  [  5: 0] system_0_burst_35_upstream_byteaddress;
  output  [  3: 0] system_0_burst_35_upstream_byteenable;
  output           system_0_burst_35_upstream_debugaccess;
  output           system_0_burst_35_upstream_read;
  output  [ 31: 0] system_0_burst_35_upstream_readdata_from_sa;
  output           system_0_burst_35_upstream_waitrequest_from_sa;
  output           system_0_burst_35_upstream_write;
  output  [ 31: 0] system_0_burst_35_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [ 31: 0] system_0_burst_35_upstream_readdata;
  input            system_0_burst_35_upstream_readdatavalid;
  input            system_0_burst_35_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_35_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_35_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_35_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_35_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_35_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_35_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_35_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_35_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_35_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_35_upstream_load_fifo;
  wire    [  3: 0] system_0_burst_35_upstream_address;
  wire             system_0_burst_35_upstream_allgrants;
  wire             system_0_burst_35_upstream_allow_new_arb_cycle;
  wire             system_0_burst_35_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_35_upstream_any_continuerequest;
  wire             system_0_burst_35_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_35_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_35_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_35_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_35_upstream_bbt_burstcounter;
  wire             system_0_burst_35_upstream_beginbursttransfer_internal;
  wire             system_0_burst_35_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_35_upstream_burstcount;
  wire             system_0_burst_35_upstream_burstcount_fifo_empty;
  wire    [  5: 0] system_0_burst_35_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_35_upstream_byteenable;
  reg     [  3: 0] system_0_burst_35_upstream_current_burst;
  wire    [  3: 0] system_0_burst_35_upstream_current_burst_minus_one;
  wire             system_0_burst_35_upstream_debugaccess;
  wire             system_0_burst_35_upstream_end_xfer;
  wire             system_0_burst_35_upstream_firsttransfer;
  wire             system_0_burst_35_upstream_grant_vector;
  wire             system_0_burst_35_upstream_in_a_read_cycle;
  wire             system_0_burst_35_upstream_in_a_write_cycle;
  reg              system_0_burst_35_upstream_load_fifo;
  wire             system_0_burst_35_upstream_master_qreq_vector;
  wire             system_0_burst_35_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_35_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_35_upstream_next_burst_count;
  wire             system_0_burst_35_upstream_non_bursting_master_requests;
  wire             system_0_burst_35_upstream_read;
  wire    [ 31: 0] system_0_burst_35_upstream_readdata_from_sa;
  wire             system_0_burst_35_upstream_readdatavalid_from_sa;
  reg              system_0_burst_35_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_35_upstream_selected_burstcount;
  reg              system_0_burst_35_upstream_slavearbiterlockenable;
  wire             system_0_burst_35_upstream_slavearbiterlockenable2;
  wire             system_0_burst_35_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_35_upstream_transaction_burst_count;
  wire             system_0_burst_35_upstream_unreg_firsttransfer;
  wire             system_0_burst_35_upstream_waitrequest_from_sa;
  wire             system_0_burst_35_upstream_waits_for_read;
  wire             system_0_burst_35_upstream_waits_for_write;
  wire             system_0_burst_35_upstream_write;
  wire    [ 31: 0] system_0_burst_35_upstream_writedata;
  wire             wait_for_system_0_burst_35_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_35_upstream_end_xfer;
    end


  assign system_0_burst_35_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_35_upstream));
  //assign system_0_burst_35_upstream_readdatavalid_from_sa = system_0_burst_35_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_35_upstream_readdatavalid_from_sa = system_0_burst_35_upstream_readdatavalid;

  //assign system_0_burst_35_upstream_readdata_from_sa = system_0_burst_35_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_35_upstream_readdata_from_sa = system_0_burst_35_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_35_upstream = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h190a1c0) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_35_upstream_waitrequest_from_sa = system_0_burst_35_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_35_upstream_waitrequest_from_sa = system_0_burst_35_upstream_waitrequest;

  //system_0_burst_35_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_35_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_35_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_35_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_35_upstream_non_bursting_master_requests = 0;

  //system_0_burst_35_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_35_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_35_upstream;

  //system_0_burst_35_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_35_upstream_arb_share_counter_next_value = system_0_burst_35_upstream_firsttransfer ? (system_0_burst_35_upstream_arb_share_set_values - 1) : |system_0_burst_35_upstream_arb_share_counter ? (system_0_burst_35_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_35_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_35_upstream_allgrants = |system_0_burst_35_upstream_grant_vector;

  //system_0_burst_35_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_35_upstream_end_xfer = ~(system_0_burst_35_upstream_waits_for_read | system_0_burst_35_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_35_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_35_upstream = system_0_burst_35_upstream_end_xfer & (~system_0_burst_35_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_35_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_35_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_35_upstream & system_0_burst_35_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_35_upstream & ~system_0_burst_35_upstream_non_bursting_master_requests);

  //system_0_burst_35_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_35_upstream_arb_share_counter <= 0;
      else if (system_0_burst_35_upstream_arb_counter_enable)
          system_0_burst_35_upstream_arb_share_counter <= system_0_burst_35_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_35_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_35_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_35_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_35_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_35_upstream & ~system_0_burst_35_upstream_non_bursting_master_requests))
          system_0_burst_35_upstream_slavearbiterlockenable <= |system_0_burst_35_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_35/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_35_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_35_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_35_upstream_slavearbiterlockenable2 = |system_0_burst_35_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_35/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_35_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_35_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_35_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_35_upstream = cpu_0_data_master_requests_system_0_burst_35_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_35_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_35_upstream_move_on_to_next_transaction = system_0_burst_35_upstream_this_cycle_is_the_last_burst & system_0_burst_35_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_35_upstream, which is an e_mux
  assign system_0_burst_35_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_35_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_35_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_35_upstream_module burstcount_fifo_for_system_0_burst_35_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_35_upstream_selected_burstcount),
      .data_out             (system_0_burst_35_upstream_transaction_burst_count),
      .empty                (system_0_burst_35_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_35_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_35_upstream_waits_for_read & system_0_burst_35_upstream_load_fifo & ~(system_0_burst_35_upstream_this_cycle_is_the_last_burst & system_0_burst_35_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_35_upstream current burst minus one, which is an e_assign
  assign system_0_burst_35_upstream_current_burst_minus_one = system_0_burst_35_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_35_upstream, which is an e_mux
  assign system_0_burst_35_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_35_upstream_waits_for_read) & ~system_0_burst_35_upstream_load_fifo))? system_0_burst_35_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_35_upstream_waits_for_read & system_0_burst_35_upstream_this_cycle_is_the_last_burst & system_0_burst_35_upstream_burstcount_fifo_empty))? system_0_burst_35_upstream_selected_burstcount :
    (system_0_burst_35_upstream_this_cycle_is_the_last_burst)? system_0_burst_35_upstream_transaction_burst_count :
    system_0_burst_35_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_35_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_35_upstream_current_burst <= 0;
      else if (system_0_burst_35_upstream_readdatavalid_from_sa | (~system_0_burst_35_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_35_upstream_waits_for_read)))
          system_0_burst_35_upstream_current_burst <= system_0_burst_35_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_35_upstream_load_fifo = (~system_0_burst_35_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_35_upstream_waits_for_read) & system_0_burst_35_upstream_load_fifo))? 1 :
    ~system_0_burst_35_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_35_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_35_upstream_waits_for_read) & ~system_0_burst_35_upstream_load_fifo | system_0_burst_35_upstream_this_cycle_is_the_last_burst)
          system_0_burst_35_upstream_load_fifo <= p0_system_0_burst_35_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_35_upstream, which is an e_assign
  assign system_0_burst_35_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_35_upstream_current_burst_minus_one) & system_0_burst_35_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_35_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_35_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_35_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_35_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_35_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_35_upstream),
      .full                 (),
      .read                 (system_0_burst_35_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_35_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_35_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_35_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_35_upstream = system_0_burst_35_upstream_readdatavalid_from_sa;

  //system_0_burst_35_upstream_writedata mux, which is an e_mux
  assign system_0_burst_35_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_35/upstream, which is an e_mux
  assign system_0_burst_35_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_35_upstream = cpu_0_data_master_qualified_request_system_0_burst_35_upstream;

  //cpu_0/data_master saved-grant system_0_burst_35/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_35_upstream = cpu_0_data_master_requests_system_0_burst_35_upstream;

  //allow new arb cycle for system_0_burst_35/upstream, which is an e_assign
  assign system_0_burst_35_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_35_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_35_upstream_master_qreq_vector = 1;

  //system_0_burst_35_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_35_upstream_firsttransfer = system_0_burst_35_upstream_begins_xfer ? system_0_burst_35_upstream_unreg_firsttransfer : system_0_burst_35_upstream_reg_firsttransfer;

  //system_0_burst_35_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_35_upstream_unreg_firsttransfer = ~(system_0_burst_35_upstream_slavearbiterlockenable & system_0_burst_35_upstream_any_continuerequest);

  //system_0_burst_35_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_35_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_35_upstream_begins_xfer)
          system_0_burst_35_upstream_reg_firsttransfer <= system_0_burst_35_upstream_unreg_firsttransfer;
    end


  //system_0_burst_35_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_35_upstream_next_bbt_burstcount = ((((system_0_burst_35_upstream_write) && (system_0_burst_35_upstream_bbt_burstcounter == 0))))? (system_0_burst_35_upstream_burstcount - 1) :
    ((((system_0_burst_35_upstream_read) && (system_0_burst_35_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_35_upstream_bbt_burstcounter - 1);

  //system_0_burst_35_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_35_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_35_upstream_begins_xfer)
          system_0_burst_35_upstream_bbt_burstcounter <= system_0_burst_35_upstream_next_bbt_burstcount;
    end


  //system_0_burst_35_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_35_upstream_beginbursttransfer_internal = system_0_burst_35_upstream_begins_xfer & (system_0_burst_35_upstream_bbt_burstcounter == 0);

  //system_0_burst_35_upstream_read assignment, which is an e_mux
  assign system_0_burst_35_upstream_read = cpu_0_data_master_granted_system_0_burst_35_upstream & cpu_0_data_master_read;

  //system_0_burst_35_upstream_write assignment, which is an e_mux
  assign system_0_burst_35_upstream_write = cpu_0_data_master_granted_system_0_burst_35_upstream & cpu_0_data_master_write;

  //system_0_burst_35_upstream_address mux, which is an e_mux
  assign system_0_burst_35_upstream_address = cpu_0_data_master_address_to_slave;

  //d1_system_0_burst_35_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_35_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_35_upstream_end_xfer <= system_0_burst_35_upstream_end_xfer;
    end


  //system_0_burst_35_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_35_upstream_waits_for_read = system_0_burst_35_upstream_in_a_read_cycle & system_0_burst_35_upstream_waitrequest_from_sa;

  //system_0_burst_35_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_35_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_35_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_35_upstream_in_a_read_cycle;

  //system_0_burst_35_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_35_upstream_waits_for_write = system_0_burst_35_upstream_in_a_write_cycle & system_0_burst_35_upstream_waitrequest_from_sa;

  //system_0_burst_35_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_35_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_35_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_35_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_35_upstream_counter = 0;
  //system_0_burst_35_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_35_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_35_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_35_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_35_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_35_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_35_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_35/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_35_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_35/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_35_downstream_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  d1_system_0_clock_0_in_end_xfer,
                                                  reset_n,
                                                  system_0_burst_35_downstream_address,
                                                  system_0_burst_35_downstream_burstcount,
                                                  system_0_burst_35_downstream_byteenable,
                                                  system_0_burst_35_downstream_granted_system_0_clock_0_in,
                                                  system_0_burst_35_downstream_qualified_request_system_0_clock_0_in,
                                                  system_0_burst_35_downstream_read,
                                                  system_0_burst_35_downstream_read_data_valid_system_0_clock_0_in,
                                                  system_0_burst_35_downstream_requests_system_0_clock_0_in,
                                                  system_0_burst_35_downstream_write,
                                                  system_0_burst_35_downstream_writedata,
                                                  system_0_clock_0_in_readdata_from_sa,
                                                  system_0_clock_0_in_waitrequest_from_sa,

                                                 // outputs:
                                                  system_0_burst_35_downstream_address_to_slave,
                                                  system_0_burst_35_downstream_latency_counter,
                                                  system_0_burst_35_downstream_readdata,
                                                  system_0_burst_35_downstream_readdatavalid,
                                                  system_0_burst_35_downstream_reset_n,
                                                  system_0_burst_35_downstream_waitrequest
                                               )
;

  output  [  3: 0] system_0_burst_35_downstream_address_to_slave;
  output           system_0_burst_35_downstream_latency_counter;
  output  [ 31: 0] system_0_burst_35_downstream_readdata;
  output           system_0_burst_35_downstream_readdatavalid;
  output           system_0_burst_35_downstream_reset_n;
  output           system_0_burst_35_downstream_waitrequest;
  input            clk;
  input            d1_system_0_clock_0_in_end_xfer;
  input            reset_n;
  input   [  3: 0] system_0_burst_35_downstream_address;
  input            system_0_burst_35_downstream_burstcount;
  input   [  3: 0] system_0_burst_35_downstream_byteenable;
  input            system_0_burst_35_downstream_granted_system_0_clock_0_in;
  input            system_0_burst_35_downstream_qualified_request_system_0_clock_0_in;
  input            system_0_burst_35_downstream_read;
  input            system_0_burst_35_downstream_read_data_valid_system_0_clock_0_in;
  input            system_0_burst_35_downstream_requests_system_0_clock_0_in;
  input            system_0_burst_35_downstream_write;
  input   [ 31: 0] system_0_burst_35_downstream_writedata;
  input   [ 31: 0] system_0_clock_0_in_readdata_from_sa;
  input            system_0_clock_0_in_waitrequest_from_sa;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_35_downstream_readdatavalid;
  wire             r_6;
  reg     [  3: 0] system_0_burst_35_downstream_address_last_time;
  wire    [  3: 0] system_0_burst_35_downstream_address_to_slave;
  reg              system_0_burst_35_downstream_burstcount_last_time;
  reg     [  3: 0] system_0_burst_35_downstream_byteenable_last_time;
  wire             system_0_burst_35_downstream_latency_counter;
  reg              system_0_burst_35_downstream_read_last_time;
  wire    [ 31: 0] system_0_burst_35_downstream_readdata;
  wire             system_0_burst_35_downstream_readdatavalid;
  wire             system_0_burst_35_downstream_reset_n;
  wire             system_0_burst_35_downstream_run;
  wire             system_0_burst_35_downstream_waitrequest;
  reg              system_0_burst_35_downstream_write_last_time;
  reg     [ 31: 0] system_0_burst_35_downstream_writedata_last_time;
  //r_6 master_run cascaded wait assignment, which is an e_assign
  assign r_6 = 1 & (system_0_burst_35_downstream_qualified_request_system_0_clock_0_in | ~system_0_burst_35_downstream_requests_system_0_clock_0_in) & ((~system_0_burst_35_downstream_qualified_request_system_0_clock_0_in | ~(system_0_burst_35_downstream_read | system_0_burst_35_downstream_write) | (1 & ~system_0_clock_0_in_waitrequest_from_sa & (system_0_burst_35_downstream_read | system_0_burst_35_downstream_write)))) & ((~system_0_burst_35_downstream_qualified_request_system_0_clock_0_in | ~(system_0_burst_35_downstream_read | system_0_burst_35_downstream_write) | (1 & ~system_0_clock_0_in_waitrequest_from_sa & (system_0_burst_35_downstream_read | system_0_burst_35_downstream_write))));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_35_downstream_run = r_6;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_35_downstream_address_to_slave = system_0_burst_35_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_35_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_35_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_35_downstream_readdatavalid |
    system_0_burst_35_downstream_read_data_valid_system_0_clock_0_in;

  //system_0_burst_35/downstream readdata mux, which is an e_mux
  assign system_0_burst_35_downstream_readdata = system_0_clock_0_in_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_35_downstream_waitrequest = ~system_0_burst_35_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_35_downstream_latency_counter = 0;

  //system_0_burst_35_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_35_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_35_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_35_downstream_address_last_time <= 0;
      else 
        system_0_burst_35_downstream_address_last_time <= system_0_burst_35_downstream_address;
    end


  //system_0_burst_35/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_35_downstream_waitrequest & (system_0_burst_35_downstream_read | system_0_burst_35_downstream_write);
    end


  //system_0_burst_35_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_35_downstream_address != system_0_burst_35_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_35_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_35_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_35_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_35_downstream_burstcount_last_time <= system_0_burst_35_downstream_burstcount;
    end


  //system_0_burst_35_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_35_downstream_burstcount != system_0_burst_35_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_35_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_35_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_35_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_35_downstream_byteenable_last_time <= system_0_burst_35_downstream_byteenable;
    end


  //system_0_burst_35_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_35_downstream_byteenable != system_0_burst_35_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_35_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_35_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_35_downstream_read_last_time <= 0;
      else 
        system_0_burst_35_downstream_read_last_time <= system_0_burst_35_downstream_read;
    end


  //system_0_burst_35_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_35_downstream_read != system_0_burst_35_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_35_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_35_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_35_downstream_write_last_time <= 0;
      else 
        system_0_burst_35_downstream_write_last_time <= system_0_burst_35_downstream_write;
    end


  //system_0_burst_35_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_35_downstream_write != system_0_burst_35_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_35_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_35_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_35_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_35_downstream_writedata_last_time <= system_0_burst_35_downstream_writedata;
    end


  //system_0_burst_35_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_35_downstream_writedata != system_0_burst_35_downstream_writedata_last_time) & system_0_burst_35_downstream_write)
        begin
          $write("%0d ns: system_0_burst_35_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_4_upstream_module (
                                                              // inputs:
                                                               clear_fifo,
                                                               clk,
                                                               data_in,
                                                               read,
                                                               reset_n,
                                                               sync_reset,
                                                               write,

                                                              // outputs:
                                                               data_out,
                                                               empty,
                                                               fifo_contains_ones_n,
                                                               full
                                                            )
;

  output  [  4: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  4: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  4: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  reg              full_2;
  reg              full_3;
  reg              full_4;
  reg              full_5;
  reg              full_6;
  reg              full_7;
  reg              full_8;
  wire             full_9;
  reg     [  4: 0] how_many_ones;
  wire    [  4: 0] one_count_minus_one;
  wire    [  4: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  4: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  4: 0] p1_stage_1;
  wire             p2_full_2;
  wire    [  4: 0] p2_stage_2;
  wire             p3_full_3;
  wire    [  4: 0] p3_stage_3;
  wire             p4_full_4;
  wire    [  4: 0] p4_stage_4;
  wire             p5_full_5;
  wire    [  4: 0] p5_stage_5;
  wire             p6_full_6;
  wire    [  4: 0] p6_stage_6;
  wire             p7_full_7;
  wire    [  4: 0] p7_stage_7;
  wire             p8_full_8;
  wire    [  4: 0] p8_stage_8;
  reg     [  4: 0] stage_0;
  reg     [  4: 0] stage_1;
  reg     [  4: 0] stage_2;
  reg     [  4: 0] stage_3;
  reg     [  4: 0] stage_4;
  reg     [  4: 0] stage_5;
  reg     [  4: 0] stage_6;
  reg     [  4: 0] stage_7;
  reg     [  4: 0] stage_8;
  wire    [  4: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_8;
  assign empty = !full_0;
  assign full_9 = 0;
  //data_8, which is an e_mux
  assign p8_stage_8 = ((full_9 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_8, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_8 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_8))
          if (sync_reset & full_8 & !((full_9 == 0) & read & write))
              stage_8 <= 0;
          else 
            stage_8 <= p8_stage_8;
    end


  //control_8, which is an e_mux
  assign p8_full_8 = ((read & !write) == 0)? full_7 :
    0;

  //control_reg_8, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_8 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_8 <= 0;
          else 
            full_8 <= p8_full_8;
    end


  //data_7, which is an e_mux
  assign p7_stage_7 = ((full_8 & ~clear_fifo) == 0)? data_in :
    stage_8;

  //data_reg_7, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_7 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_7))
          if (sync_reset & full_7 & !((full_8 == 0) & read & write))
              stage_7 <= 0;
          else 
            stage_7 <= p7_stage_7;
    end


  //control_7, which is an e_mux
  assign p7_full_7 = ((read & !write) == 0)? full_6 :
    full_8;

  //control_reg_7, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_7 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_7 <= 0;
          else 
            full_7 <= p7_full_7;
    end


  //data_6, which is an e_mux
  assign p6_stage_6 = ((full_7 & ~clear_fifo) == 0)? data_in :
    stage_7;

  //data_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_6 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_6))
          if (sync_reset & full_6 & !((full_7 == 0) & read & write))
              stage_6 <= 0;
          else 
            stage_6 <= p6_stage_6;
    end


  //control_6, which is an e_mux
  assign p6_full_6 = ((read & !write) == 0)? full_5 :
    full_7;

  //control_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_6 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_6 <= 0;
          else 
            full_6 <= p6_full_6;
    end


  //data_5, which is an e_mux
  assign p5_stage_5 = ((full_6 & ~clear_fifo) == 0)? data_in :
    stage_6;

  //data_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_5 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_5))
          if (sync_reset & full_5 & !((full_6 == 0) & read & write))
              stage_5 <= 0;
          else 
            stage_5 <= p5_stage_5;
    end


  //control_5, which is an e_mux
  assign p5_full_5 = ((read & !write) == 0)? full_4 :
    full_6;

  //control_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_5 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_5 <= 0;
          else 
            full_5 <= p5_full_5;
    end


  //data_4, which is an e_mux
  assign p4_stage_4 = ((full_5 & ~clear_fifo) == 0)? data_in :
    stage_5;

  //data_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_4 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_4))
          if (sync_reset & full_4 & !((full_5 == 0) & read & write))
              stage_4 <= 0;
          else 
            stage_4 <= p4_stage_4;
    end


  //control_4, which is an e_mux
  assign p4_full_4 = ((read & !write) == 0)? full_3 :
    full_5;

  //control_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_4 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_4 <= 0;
          else 
            full_4 <= p4_full_4;
    end


  //data_3, which is an e_mux
  assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
    stage_4;

  //data_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_3 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_3))
          if (sync_reset & full_3 & !((full_4 == 0) & read & write))
              stage_3 <= 0;
          else 
            stage_3 <= p3_stage_3;
    end


  //control_3, which is an e_mux
  assign p3_full_3 = ((read & !write) == 0)? full_2 :
    full_4;

  //control_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_4_upstream_module (
                                                                                   // inputs:
                                                                                    clear_fifo,
                                                                                    clk,
                                                                                    data_in,
                                                                                    read,
                                                                                    reset_n,
                                                                                    sync_reset,
                                                                                    write,

                                                                                   // outputs:
                                                                                    data_out,
                                                                                    empty,
                                                                                    fifo_contains_ones_n,
                                                                                    full
                                                                                 )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  reg              full_2;
  reg              full_3;
  reg              full_4;
  reg              full_5;
  reg              full_6;
  reg              full_7;
  reg              full_8;
  wire             full_9;
  reg     [  4: 0] how_many_ones;
  wire    [  4: 0] one_count_minus_one;
  wire    [  4: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  wire             p2_full_2;
  wire             p2_stage_2;
  wire             p3_full_3;
  wire             p3_stage_3;
  wire             p4_full_4;
  wire             p4_stage_4;
  wire             p5_full_5;
  wire             p5_stage_5;
  wire             p6_full_6;
  wire             p6_stage_6;
  wire             p7_full_7;
  wire             p7_stage_7;
  wire             p8_full_8;
  wire             p8_stage_8;
  reg              stage_0;
  reg              stage_1;
  reg              stage_2;
  reg              stage_3;
  reg              stage_4;
  reg              stage_5;
  reg              stage_6;
  reg              stage_7;
  reg              stage_8;
  wire    [  4: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_8;
  assign empty = !full_0;
  assign full_9 = 0;
  //data_8, which is an e_mux
  assign p8_stage_8 = ((full_9 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_8, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_8 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_8))
          if (sync_reset & full_8 & !((full_9 == 0) & read & write))
              stage_8 <= 0;
          else 
            stage_8 <= p8_stage_8;
    end


  //control_8, which is an e_mux
  assign p8_full_8 = ((read & !write) == 0)? full_7 :
    0;

  //control_reg_8, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_8 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_8 <= 0;
          else 
            full_8 <= p8_full_8;
    end


  //data_7, which is an e_mux
  assign p7_stage_7 = ((full_8 & ~clear_fifo) == 0)? data_in :
    stage_8;

  //data_reg_7, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_7 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_7))
          if (sync_reset & full_7 & !((full_8 == 0) & read & write))
              stage_7 <= 0;
          else 
            stage_7 <= p7_stage_7;
    end


  //control_7, which is an e_mux
  assign p7_full_7 = ((read & !write) == 0)? full_6 :
    full_8;

  //control_reg_7, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_7 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_7 <= 0;
          else 
            full_7 <= p7_full_7;
    end


  //data_6, which is an e_mux
  assign p6_stage_6 = ((full_7 & ~clear_fifo) == 0)? data_in :
    stage_7;

  //data_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_6 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_6))
          if (sync_reset & full_6 & !((full_7 == 0) & read & write))
              stage_6 <= 0;
          else 
            stage_6 <= p6_stage_6;
    end


  //control_6, which is an e_mux
  assign p6_full_6 = ((read & !write) == 0)? full_5 :
    full_7;

  //control_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_6 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_6 <= 0;
          else 
            full_6 <= p6_full_6;
    end


  //data_5, which is an e_mux
  assign p5_stage_5 = ((full_6 & ~clear_fifo) == 0)? data_in :
    stage_6;

  //data_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_5 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_5))
          if (sync_reset & full_5 & !((full_6 == 0) & read & write))
              stage_5 <= 0;
          else 
            stage_5 <= p5_stage_5;
    end


  //control_5, which is an e_mux
  assign p5_full_5 = ((read & !write) == 0)? full_4 :
    full_6;

  //control_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_5 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_5 <= 0;
          else 
            full_5 <= p5_full_5;
    end


  //data_4, which is an e_mux
  assign p4_stage_4 = ((full_5 & ~clear_fifo) == 0)? data_in :
    stage_5;

  //data_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_4 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_4))
          if (sync_reset & full_4 & !((full_5 == 0) & read & write))
              stage_4 <= 0;
          else 
            stage_4 <= p4_stage_4;
    end


  //control_4, which is an e_mux
  assign p4_full_4 = ((read & !write) == 0)? full_3 :
    full_5;

  //control_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_4 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_4 <= 0;
          else 
            full_4 <= p4_full_4;
    end


  //data_3, which is an e_mux
  assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
    stage_4;

  //data_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_3 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_3))
          if (sync_reset & full_3 & !((full_4 == 0) & read & write))
              stage_3 <= 0;
          else 
            stage_3 <= p3_stage_3;
    end


  //control_3, which is an e_mux
  assign p3_full_3 = ((read & !write) == 0)? full_2 :
    full_4;

  //control_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_4_upstream_arbitrator (
                                              // inputs:
                                               clk,
                                               cpu_0_instruction_master_address_to_slave,
                                               cpu_0_instruction_master_burstcount,
                                               cpu_0_instruction_master_dbs_address,
                                               cpu_0_instruction_master_latency_counter,
                                               cpu_0_instruction_master_read,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register,
                                               reset_n,
                                               system_0_burst_4_upstream_readdata,
                                               system_0_burst_4_upstream_readdatavalid,
                                               system_0_burst_4_upstream_waitrequest,

                                              // outputs:
                                               cpu_0_instruction_master_granted_system_0_burst_4_upstream,
                                               cpu_0_instruction_master_qualified_request_system_0_burst_4_upstream,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register,
                                               cpu_0_instruction_master_requests_system_0_burst_4_upstream,
                                               d1_system_0_burst_4_upstream_end_xfer,
                                               system_0_burst_4_upstream_address,
                                               system_0_burst_4_upstream_byteaddress,
                                               system_0_burst_4_upstream_byteenable,
                                               system_0_burst_4_upstream_debugaccess,
                                               system_0_burst_4_upstream_read,
                                               system_0_burst_4_upstream_readdata_from_sa,
                                               system_0_burst_4_upstream_waitrequest_from_sa,
                                               system_0_burst_4_upstream_write
                                            )
;

  output           cpu_0_instruction_master_granted_system_0_burst_4_upstream;
  output           cpu_0_instruction_master_qualified_request_system_0_burst_4_upstream;
  output           cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream;
  output           cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register;
  output           cpu_0_instruction_master_requests_system_0_burst_4_upstream;
  output           d1_system_0_burst_4_upstream_end_xfer;
  output  [ 22: 0] system_0_burst_4_upstream_address;
  output  [ 23: 0] system_0_burst_4_upstream_byteaddress;
  output  [  1: 0] system_0_burst_4_upstream_byteenable;
  output           system_0_burst_4_upstream_debugaccess;
  output           system_0_burst_4_upstream_read;
  output  [ 15: 0] system_0_burst_4_upstream_readdata_from_sa;
  output           system_0_burst_4_upstream_waitrequest_from_sa;
  output           system_0_burst_4_upstream_write;
  input            clk;
  input   [ 24: 0] cpu_0_instruction_master_address_to_slave;
  input   [  3: 0] cpu_0_instruction_master_burstcount;
  input   [  1: 0] cpu_0_instruction_master_dbs_address;
  input            cpu_0_instruction_master_latency_counter;
  input            cpu_0_instruction_master_read;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register;
  input            reset_n;
  input   [ 15: 0] system_0_burst_4_upstream_readdata;
  input            system_0_burst_4_upstream_readdatavalid;
  input            system_0_burst_4_upstream_waitrequest;

  wire             cpu_0_instruction_master_arbiterlock;
  wire             cpu_0_instruction_master_arbiterlock2;
  wire             cpu_0_instruction_master_continuerequest;
  wire             cpu_0_instruction_master_granted_system_0_burst_4_upstream;
  wire             cpu_0_instruction_master_qualified_request_system_0_burst_4_upstream;
  wire             cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_4_upstream;
  wire             cpu_0_instruction_master_rdv_fifo_output_from_system_0_burst_4_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register;
  wire             cpu_0_instruction_master_requests_system_0_burst_4_upstream;
  wire             cpu_0_instruction_master_saved_grant_system_0_burst_4_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_4_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_4_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_4_upstream_load_fifo;
  wire    [ 22: 0] system_0_burst_4_upstream_address;
  wire             system_0_burst_4_upstream_allgrants;
  wire             system_0_burst_4_upstream_allow_new_arb_cycle;
  wire             system_0_burst_4_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_4_upstream_any_continuerequest;
  wire             system_0_burst_4_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_4_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_4_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_4_upstream_arb_share_set_values;
  wire             system_0_burst_4_upstream_beginbursttransfer_internal;
  wire             system_0_burst_4_upstream_begins_xfer;
  wire             system_0_burst_4_upstream_burstcount_fifo_empty;
  wire    [ 23: 0] system_0_burst_4_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_4_upstream_byteenable;
  reg     [  4: 0] system_0_burst_4_upstream_current_burst;
  wire    [  4: 0] system_0_burst_4_upstream_current_burst_minus_one;
  wire             system_0_burst_4_upstream_debugaccess;
  wire             system_0_burst_4_upstream_end_xfer;
  wire             system_0_burst_4_upstream_firsttransfer;
  wire             system_0_burst_4_upstream_grant_vector;
  wire             system_0_burst_4_upstream_in_a_read_cycle;
  wire             system_0_burst_4_upstream_in_a_write_cycle;
  reg              system_0_burst_4_upstream_load_fifo;
  wire             system_0_burst_4_upstream_master_qreq_vector;
  wire             system_0_burst_4_upstream_move_on_to_next_transaction;
  wire    [  4: 0] system_0_burst_4_upstream_next_burst_count;
  wire             system_0_burst_4_upstream_non_bursting_master_requests;
  wire             system_0_burst_4_upstream_read;
  wire    [ 15: 0] system_0_burst_4_upstream_readdata_from_sa;
  wire             system_0_burst_4_upstream_readdatavalid_from_sa;
  reg              system_0_burst_4_upstream_reg_firsttransfer;
  wire    [  4: 0] system_0_burst_4_upstream_selected_burstcount;
  reg              system_0_burst_4_upstream_slavearbiterlockenable;
  wire             system_0_burst_4_upstream_slavearbiterlockenable2;
  wire             system_0_burst_4_upstream_this_cycle_is_the_last_burst;
  wire    [  4: 0] system_0_burst_4_upstream_transaction_burst_count;
  wire             system_0_burst_4_upstream_unreg_firsttransfer;
  wire             system_0_burst_4_upstream_waitrequest_from_sa;
  wire             system_0_burst_4_upstream_waits_for_read;
  wire             system_0_burst_4_upstream_waits_for_write;
  wire             system_0_burst_4_upstream_write;
  wire             wait_for_system_0_burst_4_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_4_upstream_end_xfer;
    end


  assign system_0_burst_4_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_instruction_master_qualified_request_system_0_burst_4_upstream));
  //assign system_0_burst_4_upstream_readdatavalid_from_sa = system_0_burst_4_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_4_upstream_readdatavalid_from_sa = system_0_burst_4_upstream_readdatavalid;

  //assign system_0_burst_4_upstream_readdata_from_sa = system_0_burst_4_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_4_upstream_readdata_from_sa = system_0_burst_4_upstream_readdata;

  assign cpu_0_instruction_master_requests_system_0_burst_4_upstream = (({cpu_0_instruction_master_address_to_slave[24 : 23] , 23'b0} == 25'h800000) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
  //assign system_0_burst_4_upstream_waitrequest_from_sa = system_0_burst_4_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_4_upstream_waitrequest_from_sa = system_0_burst_4_upstream_waitrequest;

  //system_0_burst_4_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_4_upstream_arb_share_set_values = 1;

  //system_0_burst_4_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_4_upstream_non_bursting_master_requests = 0;

  //system_0_burst_4_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_4_upstream_any_bursting_master_saved_grant = cpu_0_instruction_master_saved_grant_system_0_burst_4_upstream;

  //system_0_burst_4_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_4_upstream_arb_share_counter_next_value = system_0_burst_4_upstream_firsttransfer ? (system_0_burst_4_upstream_arb_share_set_values - 1) : |system_0_burst_4_upstream_arb_share_counter ? (system_0_burst_4_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_4_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_4_upstream_allgrants = |system_0_burst_4_upstream_grant_vector;

  //system_0_burst_4_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_4_upstream_end_xfer = ~(system_0_burst_4_upstream_waits_for_read | system_0_burst_4_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_4_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_4_upstream = system_0_burst_4_upstream_end_xfer & (~system_0_burst_4_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_4_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_4_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_4_upstream & system_0_burst_4_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_4_upstream & ~system_0_burst_4_upstream_non_bursting_master_requests);

  //system_0_burst_4_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_4_upstream_arb_share_counter <= 0;
      else if (system_0_burst_4_upstream_arb_counter_enable)
          system_0_burst_4_upstream_arb_share_counter <= system_0_burst_4_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_4_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_4_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_4_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_4_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_4_upstream & ~system_0_burst_4_upstream_non_bursting_master_requests))
          system_0_burst_4_upstream_slavearbiterlockenable <= |system_0_burst_4_upstream_arb_share_counter_next_value;
    end


  //cpu_0/instruction_master system_0_burst_4/upstream arbiterlock, which is an e_assign
  assign cpu_0_instruction_master_arbiterlock = system_0_burst_4_upstream_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;

  //system_0_burst_4_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_4_upstream_slavearbiterlockenable2 = |system_0_burst_4_upstream_arb_share_counter_next_value;

  //cpu_0/instruction_master system_0_burst_4/upstream arbiterlock2, which is an e_assign
  assign cpu_0_instruction_master_arbiterlock2 = system_0_burst_4_upstream_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;

  //system_0_burst_4_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_4_upstream_any_continuerequest = 1;

  //cpu_0_instruction_master_continuerequest continued request, which is an e_assign
  assign cpu_0_instruction_master_continuerequest = 1;

  assign cpu_0_instruction_master_qualified_request_system_0_burst_4_upstream = cpu_0_instruction_master_requests_system_0_burst_4_upstream & ~((cpu_0_instruction_master_read & ((cpu_0_instruction_master_latency_counter != 0) | (1 < cpu_0_instruction_master_latency_counter) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register))));
  //unique name for system_0_burst_4_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_4_upstream_move_on_to_next_transaction = system_0_burst_4_upstream_this_cycle_is_the_last_burst & system_0_burst_4_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_4_upstream, which is an e_mux
  assign system_0_burst_4_upstream_selected_burstcount = (cpu_0_instruction_master_granted_system_0_burst_4_upstream)? cpu_0_instruction_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_4_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_4_upstream_module burstcount_fifo_for_system_0_burst_4_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_4_upstream_selected_burstcount),
      .data_out             (system_0_burst_4_upstream_transaction_burst_count),
      .empty                (system_0_burst_4_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_4_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_4_upstream_waits_for_read & system_0_burst_4_upstream_load_fifo & ~(system_0_burst_4_upstream_this_cycle_is_the_last_burst & system_0_burst_4_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_4_upstream current burst minus one, which is an e_assign
  assign system_0_burst_4_upstream_current_burst_minus_one = system_0_burst_4_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_4_upstream, which is an e_mux
  assign system_0_burst_4_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_4_upstream_waits_for_read) & ~system_0_burst_4_upstream_load_fifo))? {system_0_burst_4_upstream_selected_burstcount, 1'b0} :
    ((in_a_read_cycle & ~system_0_burst_4_upstream_waits_for_read & system_0_burst_4_upstream_this_cycle_is_the_last_burst & system_0_burst_4_upstream_burstcount_fifo_empty))? {system_0_burst_4_upstream_selected_burstcount, 1'b0} :
    (system_0_burst_4_upstream_this_cycle_is_the_last_burst)? {system_0_burst_4_upstream_transaction_burst_count,  1'b0} :
    system_0_burst_4_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_4_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_4_upstream_current_burst <= 0;
      else if (system_0_burst_4_upstream_readdatavalid_from_sa | (~system_0_burst_4_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_4_upstream_waits_for_read)))
          system_0_burst_4_upstream_current_burst <= system_0_burst_4_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_4_upstream_load_fifo = (~system_0_burst_4_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_4_upstream_waits_for_read) & system_0_burst_4_upstream_load_fifo))? 1 :
    ~system_0_burst_4_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_4_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_4_upstream_waits_for_read) & ~system_0_burst_4_upstream_load_fifo | system_0_burst_4_upstream_this_cycle_is_the_last_burst)
          system_0_burst_4_upstream_load_fifo <= p0_system_0_burst_4_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_4_upstream, which is an e_assign
  assign system_0_burst_4_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_4_upstream_current_burst_minus_one) & system_0_burst_4_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_4_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_4_upstream_module rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_4_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_instruction_master_granted_system_0_burst_4_upstream),
      .data_out             (cpu_0_instruction_master_rdv_fifo_output_from_system_0_burst_4_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_4_upstream),
      .full                 (),
      .read                 (system_0_burst_4_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_4_upstream_waits_for_read)
    );

  assign cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register = ~cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_4_upstream;
  //local readdatavalid cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream, which is an e_mux
  assign cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream = system_0_burst_4_upstream_readdatavalid_from_sa;

  //byteaddress mux for system_0_burst_4/upstream, which is an e_mux
  assign system_0_burst_4_upstream_byteaddress = cpu_0_instruction_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_instruction_master_granted_system_0_burst_4_upstream = cpu_0_instruction_master_qualified_request_system_0_burst_4_upstream;

  //cpu_0/instruction_master saved-grant system_0_burst_4/upstream, which is an e_assign
  assign cpu_0_instruction_master_saved_grant_system_0_burst_4_upstream = cpu_0_instruction_master_requests_system_0_burst_4_upstream;

  //allow new arb cycle for system_0_burst_4/upstream, which is an e_assign
  assign system_0_burst_4_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_4_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_4_upstream_master_qreq_vector = 1;

  //system_0_burst_4_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_4_upstream_firsttransfer = system_0_burst_4_upstream_begins_xfer ? system_0_burst_4_upstream_unreg_firsttransfer : system_0_burst_4_upstream_reg_firsttransfer;

  //system_0_burst_4_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_4_upstream_unreg_firsttransfer = ~(system_0_burst_4_upstream_slavearbiterlockenable & system_0_burst_4_upstream_any_continuerequest);

  //system_0_burst_4_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_4_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_4_upstream_begins_xfer)
          system_0_burst_4_upstream_reg_firsttransfer <= system_0_burst_4_upstream_unreg_firsttransfer;
    end


  //system_0_burst_4_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_4_upstream_beginbursttransfer_internal = system_0_burst_4_upstream_begins_xfer;

  //system_0_burst_4_upstream_read assignment, which is an e_mux
  assign system_0_burst_4_upstream_read = cpu_0_instruction_master_granted_system_0_burst_4_upstream & cpu_0_instruction_master_read;

  //system_0_burst_4_upstream_write assignment, which is an e_mux
  assign system_0_burst_4_upstream_write = 0;

  //system_0_burst_4_upstream_address mux, which is an e_mux
  assign system_0_burst_4_upstream_address = {cpu_0_instruction_master_address_to_slave >> 2,
    cpu_0_instruction_master_dbs_address[1],
    {1 {1'b0}}};

  //d1_system_0_burst_4_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_4_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_4_upstream_end_xfer <= system_0_burst_4_upstream_end_xfer;
    end


  //system_0_burst_4_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_4_upstream_waits_for_read = system_0_burst_4_upstream_in_a_read_cycle & system_0_burst_4_upstream_waitrequest_from_sa;

  //system_0_burst_4_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_4_upstream_in_a_read_cycle = cpu_0_instruction_master_granted_system_0_burst_4_upstream & cpu_0_instruction_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_4_upstream_in_a_read_cycle;

  //system_0_burst_4_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_4_upstream_waits_for_write = system_0_burst_4_upstream_in_a_write_cycle & system_0_burst_4_upstream_waitrequest_from_sa;

  //system_0_burst_4_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_4_upstream_in_a_write_cycle = 0;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_4_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_4_upstream_counter = 0;
  //system_0_burst_4_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_4_upstream_byteenable = -1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_4_upstream_debugaccess = 0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_4/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/instruction_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_instruction_master_requests_system_0_burst_4_upstream && (cpu_0_instruction_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/instruction_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_4/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_4_downstream_arbitrator (
                                                // inputs:
                                                 clk,
                                                 d1_sdram_0_s1_end_xfer,
                                                 reset_n,
                                                 sdram_0_s1_readdata_from_sa,
                                                 sdram_0_s1_waitrequest_from_sa,
                                                 system_0_burst_4_downstream_address,
                                                 system_0_burst_4_downstream_burstcount,
                                                 system_0_burst_4_downstream_byteenable,
                                                 system_0_burst_4_downstream_granted_sdram_0_s1,
                                                 system_0_burst_4_downstream_qualified_request_sdram_0_s1,
                                                 system_0_burst_4_downstream_read,
                                                 system_0_burst_4_downstream_read_data_valid_sdram_0_s1,
                                                 system_0_burst_4_downstream_read_data_valid_sdram_0_s1_shift_register,
                                                 system_0_burst_4_downstream_requests_sdram_0_s1,
                                                 system_0_burst_4_downstream_write,
                                                 system_0_burst_4_downstream_writedata,

                                                // outputs:
                                                 system_0_burst_4_downstream_address_to_slave,
                                                 system_0_burst_4_downstream_latency_counter,
                                                 system_0_burst_4_downstream_readdata,
                                                 system_0_burst_4_downstream_readdatavalid,
                                                 system_0_burst_4_downstream_reset_n,
                                                 system_0_burst_4_downstream_waitrequest
                                              )
;

  output  [ 22: 0] system_0_burst_4_downstream_address_to_slave;
  output           system_0_burst_4_downstream_latency_counter;
  output  [ 15: 0] system_0_burst_4_downstream_readdata;
  output           system_0_burst_4_downstream_readdatavalid;
  output           system_0_burst_4_downstream_reset_n;
  output           system_0_burst_4_downstream_waitrequest;
  input            clk;
  input            d1_sdram_0_s1_end_xfer;
  input            reset_n;
  input   [ 15: 0] sdram_0_s1_readdata_from_sa;
  input            sdram_0_s1_waitrequest_from_sa;
  input   [ 22: 0] system_0_burst_4_downstream_address;
  input            system_0_burst_4_downstream_burstcount;
  input   [  1: 0] system_0_burst_4_downstream_byteenable;
  input            system_0_burst_4_downstream_granted_sdram_0_s1;
  input            system_0_burst_4_downstream_qualified_request_sdram_0_s1;
  input            system_0_burst_4_downstream_read;
  input            system_0_burst_4_downstream_read_data_valid_sdram_0_s1;
  input            system_0_burst_4_downstream_read_data_valid_sdram_0_s1_shift_register;
  input            system_0_burst_4_downstream_requests_sdram_0_s1;
  input            system_0_burst_4_downstream_write;
  input   [ 15: 0] system_0_burst_4_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             latency_load_value;
  wire             p1_system_0_burst_4_downstream_latency_counter;
  wire             pre_flush_system_0_burst_4_downstream_readdatavalid;
  wire             r_0;
  reg     [ 22: 0] system_0_burst_4_downstream_address_last_time;
  wire    [ 22: 0] system_0_burst_4_downstream_address_to_slave;
  reg              system_0_burst_4_downstream_burstcount_last_time;
  reg     [  1: 0] system_0_burst_4_downstream_byteenable_last_time;
  wire             system_0_burst_4_downstream_is_granted_some_slave;
  reg              system_0_burst_4_downstream_latency_counter;
  reg              system_0_burst_4_downstream_read_but_no_slave_selected;
  reg              system_0_burst_4_downstream_read_last_time;
  wire    [ 15: 0] system_0_burst_4_downstream_readdata;
  wire             system_0_burst_4_downstream_readdatavalid;
  wire             system_0_burst_4_downstream_reset_n;
  wire             system_0_burst_4_downstream_run;
  wire             system_0_burst_4_downstream_waitrequest;
  reg              system_0_burst_4_downstream_write_last_time;
  reg     [ 15: 0] system_0_burst_4_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_4_downstream_qualified_request_sdram_0_s1 | ~system_0_burst_4_downstream_requests_sdram_0_s1) & (system_0_burst_4_downstream_granted_sdram_0_s1 | ~system_0_burst_4_downstream_qualified_request_sdram_0_s1) & ((~system_0_burst_4_downstream_qualified_request_sdram_0_s1 | ~(system_0_burst_4_downstream_read | system_0_burst_4_downstream_write) | (1 & ~sdram_0_s1_waitrequest_from_sa & (system_0_burst_4_downstream_read | system_0_burst_4_downstream_write)))) & ((~system_0_burst_4_downstream_qualified_request_sdram_0_s1 | ~(system_0_burst_4_downstream_read | system_0_burst_4_downstream_write) | (1 & ~sdram_0_s1_waitrequest_from_sa & (system_0_burst_4_downstream_read | system_0_burst_4_downstream_write))));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_4_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_4_downstream_address_to_slave = system_0_burst_4_downstream_address;

  //system_0_burst_4_downstream_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_4_downstream_read_but_no_slave_selected <= 0;
      else 
        system_0_burst_4_downstream_read_but_no_slave_selected <= system_0_burst_4_downstream_read & system_0_burst_4_downstream_run & ~system_0_burst_4_downstream_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign system_0_burst_4_downstream_is_granted_some_slave = system_0_burst_4_downstream_granted_sdram_0_s1;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_4_downstream_readdatavalid = system_0_burst_4_downstream_read_data_valid_sdram_0_s1;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_4_downstream_readdatavalid = system_0_burst_4_downstream_read_but_no_slave_selected |
    pre_flush_system_0_burst_4_downstream_readdatavalid;

  //system_0_burst_4/downstream readdata mux, which is an e_mux
  assign system_0_burst_4_downstream_readdata = sdram_0_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_4_downstream_waitrequest = ~system_0_burst_4_downstream_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_4_downstream_latency_counter <= 0;
      else 
        system_0_burst_4_downstream_latency_counter <= p1_system_0_burst_4_downstream_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_system_0_burst_4_downstream_latency_counter = ((system_0_burst_4_downstream_run & system_0_burst_4_downstream_read))? latency_load_value :
    (system_0_burst_4_downstream_latency_counter)? system_0_burst_4_downstream_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = 0;

  //system_0_burst_4_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_4_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_4_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_4_downstream_address_last_time <= 0;
      else 
        system_0_burst_4_downstream_address_last_time <= system_0_burst_4_downstream_address;
    end


  //system_0_burst_4/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_4_downstream_waitrequest & (system_0_burst_4_downstream_read | system_0_burst_4_downstream_write);
    end


  //system_0_burst_4_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_4_downstream_address != system_0_burst_4_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_4_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_4_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_4_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_4_downstream_burstcount_last_time <= system_0_burst_4_downstream_burstcount;
    end


  //system_0_burst_4_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_4_downstream_burstcount != system_0_burst_4_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_4_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_4_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_4_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_4_downstream_byteenable_last_time <= system_0_burst_4_downstream_byteenable;
    end


  //system_0_burst_4_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_4_downstream_byteenable != system_0_burst_4_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_4_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_4_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_4_downstream_read_last_time <= 0;
      else 
        system_0_burst_4_downstream_read_last_time <= system_0_burst_4_downstream_read;
    end


  //system_0_burst_4_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_4_downstream_read != system_0_burst_4_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_4_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_4_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_4_downstream_write_last_time <= 0;
      else 
        system_0_burst_4_downstream_write_last_time <= system_0_burst_4_downstream_write;
    end


  //system_0_burst_4_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_4_downstream_write != system_0_burst_4_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_4_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_4_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_4_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_4_downstream_writedata_last_time <= system_0_burst_4_downstream_writedata;
    end


  //system_0_burst_4_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_4_downstream_writedata != system_0_burst_4_downstream_writedata_last_time) & system_0_burst_4_downstream_write)
        begin
          $write("%0d ns: system_0_burst_4_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_5_upstream_module (
                                                              // inputs:
                                                               clear_fifo,
                                                               clk,
                                                               data_in,
                                                               read,
                                                               reset_n,
                                                               sync_reset,
                                                               write,

                                                              // outputs:
                                                               data_out,
                                                               empty,
                                                               fifo_contains_ones_n,
                                                               full
                                                            )
;

  output  [  4: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  4: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  4: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  reg              full_2;
  reg              full_3;
  reg              full_4;
  reg              full_5;
  reg              full_6;
  reg              full_7;
  reg              full_8;
  wire             full_9;
  reg     [  4: 0] how_many_ones;
  wire    [  4: 0] one_count_minus_one;
  wire    [  4: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  4: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  4: 0] p1_stage_1;
  wire             p2_full_2;
  wire    [  4: 0] p2_stage_2;
  wire             p3_full_3;
  wire    [  4: 0] p3_stage_3;
  wire             p4_full_4;
  wire    [  4: 0] p4_stage_4;
  wire             p5_full_5;
  wire    [  4: 0] p5_stage_5;
  wire             p6_full_6;
  wire    [  4: 0] p6_stage_6;
  wire             p7_full_7;
  wire    [  4: 0] p7_stage_7;
  wire             p8_full_8;
  wire    [  4: 0] p8_stage_8;
  reg     [  4: 0] stage_0;
  reg     [  4: 0] stage_1;
  reg     [  4: 0] stage_2;
  reg     [  4: 0] stage_3;
  reg     [  4: 0] stage_4;
  reg     [  4: 0] stage_5;
  reg     [  4: 0] stage_6;
  reg     [  4: 0] stage_7;
  reg     [  4: 0] stage_8;
  wire    [  4: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_8;
  assign empty = !full_0;
  assign full_9 = 0;
  //data_8, which is an e_mux
  assign p8_stage_8 = ((full_9 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_8, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_8 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_8))
          if (sync_reset & full_8 & !((full_9 == 0) & read & write))
              stage_8 <= 0;
          else 
            stage_8 <= p8_stage_8;
    end


  //control_8, which is an e_mux
  assign p8_full_8 = ((read & !write) == 0)? full_7 :
    0;

  //control_reg_8, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_8 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_8 <= 0;
          else 
            full_8 <= p8_full_8;
    end


  //data_7, which is an e_mux
  assign p7_stage_7 = ((full_8 & ~clear_fifo) == 0)? data_in :
    stage_8;

  //data_reg_7, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_7 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_7))
          if (sync_reset & full_7 & !((full_8 == 0) & read & write))
              stage_7 <= 0;
          else 
            stage_7 <= p7_stage_7;
    end


  //control_7, which is an e_mux
  assign p7_full_7 = ((read & !write) == 0)? full_6 :
    full_8;

  //control_reg_7, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_7 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_7 <= 0;
          else 
            full_7 <= p7_full_7;
    end


  //data_6, which is an e_mux
  assign p6_stage_6 = ((full_7 & ~clear_fifo) == 0)? data_in :
    stage_7;

  //data_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_6 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_6))
          if (sync_reset & full_6 & !((full_7 == 0) & read & write))
              stage_6 <= 0;
          else 
            stage_6 <= p6_stage_6;
    end


  //control_6, which is an e_mux
  assign p6_full_6 = ((read & !write) == 0)? full_5 :
    full_7;

  //control_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_6 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_6 <= 0;
          else 
            full_6 <= p6_full_6;
    end


  //data_5, which is an e_mux
  assign p5_stage_5 = ((full_6 & ~clear_fifo) == 0)? data_in :
    stage_6;

  //data_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_5 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_5))
          if (sync_reset & full_5 & !((full_6 == 0) & read & write))
              stage_5 <= 0;
          else 
            stage_5 <= p5_stage_5;
    end


  //control_5, which is an e_mux
  assign p5_full_5 = ((read & !write) == 0)? full_4 :
    full_6;

  //control_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_5 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_5 <= 0;
          else 
            full_5 <= p5_full_5;
    end


  //data_4, which is an e_mux
  assign p4_stage_4 = ((full_5 & ~clear_fifo) == 0)? data_in :
    stage_5;

  //data_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_4 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_4))
          if (sync_reset & full_4 & !((full_5 == 0) & read & write))
              stage_4 <= 0;
          else 
            stage_4 <= p4_stage_4;
    end


  //control_4, which is an e_mux
  assign p4_full_4 = ((read & !write) == 0)? full_3 :
    full_5;

  //control_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_4 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_4 <= 0;
          else 
            full_4 <= p4_full_4;
    end


  //data_3, which is an e_mux
  assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
    stage_4;

  //data_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_3 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_3))
          if (sync_reset & full_3 & !((full_4 == 0) & read & write))
              stage_3 <= 0;
          else 
            stage_3 <= p3_stage_3;
    end


  //control_3, which is an e_mux
  assign p3_full_3 = ((read & !write) == 0)? full_2 :
    full_4;

  //control_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_5_upstream_module (
                                                                            // inputs:
                                                                             clear_fifo,
                                                                             clk,
                                                                             data_in,
                                                                             read,
                                                                             reset_n,
                                                                             sync_reset,
                                                                             write,

                                                                            // outputs:
                                                                             data_out,
                                                                             empty,
                                                                             fifo_contains_ones_n,
                                                                             full
                                                                          )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  reg              full_2;
  reg              full_3;
  reg              full_4;
  reg              full_5;
  reg              full_6;
  reg              full_7;
  reg              full_8;
  wire             full_9;
  reg     [  4: 0] how_many_ones;
  wire    [  4: 0] one_count_minus_one;
  wire    [  4: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  wire             p2_full_2;
  wire             p2_stage_2;
  wire             p3_full_3;
  wire             p3_stage_3;
  wire             p4_full_4;
  wire             p4_stage_4;
  wire             p5_full_5;
  wire             p5_stage_5;
  wire             p6_full_6;
  wire             p6_stage_6;
  wire             p7_full_7;
  wire             p7_stage_7;
  wire             p8_full_8;
  wire             p8_stage_8;
  reg              stage_0;
  reg              stage_1;
  reg              stage_2;
  reg              stage_3;
  reg              stage_4;
  reg              stage_5;
  reg              stage_6;
  reg              stage_7;
  reg              stage_8;
  wire    [  4: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_8;
  assign empty = !full_0;
  assign full_9 = 0;
  //data_8, which is an e_mux
  assign p8_stage_8 = ((full_9 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_8, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_8 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_8))
          if (sync_reset & full_8 & !((full_9 == 0) & read & write))
              stage_8 <= 0;
          else 
            stage_8 <= p8_stage_8;
    end


  //control_8, which is an e_mux
  assign p8_full_8 = ((read & !write) == 0)? full_7 :
    0;

  //control_reg_8, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_8 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_8 <= 0;
          else 
            full_8 <= p8_full_8;
    end


  //data_7, which is an e_mux
  assign p7_stage_7 = ((full_8 & ~clear_fifo) == 0)? data_in :
    stage_8;

  //data_reg_7, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_7 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_7))
          if (sync_reset & full_7 & !((full_8 == 0) & read & write))
              stage_7 <= 0;
          else 
            stage_7 <= p7_stage_7;
    end


  //control_7, which is an e_mux
  assign p7_full_7 = ((read & !write) == 0)? full_6 :
    full_8;

  //control_reg_7, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_7 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_7 <= 0;
          else 
            full_7 <= p7_full_7;
    end


  //data_6, which is an e_mux
  assign p6_stage_6 = ((full_7 & ~clear_fifo) == 0)? data_in :
    stage_7;

  //data_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_6 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_6))
          if (sync_reset & full_6 & !((full_7 == 0) & read & write))
              stage_6 <= 0;
          else 
            stage_6 <= p6_stage_6;
    end


  //control_6, which is an e_mux
  assign p6_full_6 = ((read & !write) == 0)? full_5 :
    full_7;

  //control_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_6 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_6 <= 0;
          else 
            full_6 <= p6_full_6;
    end


  //data_5, which is an e_mux
  assign p5_stage_5 = ((full_6 & ~clear_fifo) == 0)? data_in :
    stage_6;

  //data_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_5 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_5))
          if (sync_reset & full_5 & !((full_6 == 0) & read & write))
              stage_5 <= 0;
          else 
            stage_5 <= p5_stage_5;
    end


  //control_5, which is an e_mux
  assign p5_full_5 = ((read & !write) == 0)? full_4 :
    full_6;

  //control_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_5 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_5 <= 0;
          else 
            full_5 <= p5_full_5;
    end


  //data_4, which is an e_mux
  assign p4_stage_4 = ((full_5 & ~clear_fifo) == 0)? data_in :
    stage_5;

  //data_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_4 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_4))
          if (sync_reset & full_4 & !((full_5 == 0) & read & write))
              stage_4 <= 0;
          else 
            stage_4 <= p4_stage_4;
    end


  //control_4, which is an e_mux
  assign p4_full_4 = ((read & !write) == 0)? full_3 :
    full_5;

  //control_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_4 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_4 <= 0;
          else 
            full_4 <= p4_full_4;
    end


  //data_3, which is an e_mux
  assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
    stage_4;

  //data_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_3 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_3))
          if (sync_reset & full_3 & !((full_4 == 0) & read & write))
              stage_3 <= 0;
          else 
            stage_3 <= p3_stage_3;
    end


  //control_3, which is an e_mux
  assign p3_full_3 = ((read & !write) == 0)? full_2 :
    full_4;

  //control_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_5_upstream_arbitrator (
                                              // inputs:
                                               clk,
                                               cpu_0_data_master_address_to_slave,
                                               cpu_0_data_master_burstcount,
                                               cpu_0_data_master_byteenable,
                                               cpu_0_data_master_dbs_address,
                                               cpu_0_data_master_dbs_write_16,
                                               cpu_0_data_master_debugaccess,
                                               cpu_0_data_master_latency_counter,
                                               cpu_0_data_master_read,
                                               cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                               cpu_0_data_master_write,
                                               reset_n,
                                               system_0_burst_5_upstream_readdata,
                                               system_0_burst_5_upstream_readdatavalid,
                                               system_0_burst_5_upstream_waitrequest,

                                              // outputs:
                                               cpu_0_data_master_byteenable_system_0_burst_5_upstream,
                                               cpu_0_data_master_granted_system_0_burst_5_upstream,
                                               cpu_0_data_master_qualified_request_system_0_burst_5_upstream,
                                               cpu_0_data_master_read_data_valid_system_0_burst_5_upstream,
                                               cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                               cpu_0_data_master_requests_system_0_burst_5_upstream,
                                               d1_system_0_burst_5_upstream_end_xfer,
                                               system_0_burst_5_upstream_address,
                                               system_0_burst_5_upstream_burstcount,
                                               system_0_burst_5_upstream_byteaddress,
                                               system_0_burst_5_upstream_byteenable,
                                               system_0_burst_5_upstream_debugaccess,
                                               system_0_burst_5_upstream_read,
                                               system_0_burst_5_upstream_readdata_from_sa,
                                               system_0_burst_5_upstream_waitrequest_from_sa,
                                               system_0_burst_5_upstream_write,
                                               system_0_burst_5_upstream_writedata
                                            )
;

  output  [  1: 0] cpu_0_data_master_byteenable_system_0_burst_5_upstream;
  output           cpu_0_data_master_granted_system_0_burst_5_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_5_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_5_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_5_upstream;
  output           d1_system_0_burst_5_upstream_end_xfer;
  output  [ 22: 0] system_0_burst_5_upstream_address;
  output  [  3: 0] system_0_burst_5_upstream_burstcount;
  output  [ 23: 0] system_0_burst_5_upstream_byteaddress;
  output  [  1: 0] system_0_burst_5_upstream_byteenable;
  output           system_0_burst_5_upstream_debugaccess;
  output           system_0_burst_5_upstream_read;
  output  [ 15: 0] system_0_burst_5_upstream_readdata_from_sa;
  output           system_0_burst_5_upstream_waitrequest_from_sa;
  output           system_0_burst_5_upstream_write;
  output  [ 15: 0] system_0_burst_5_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input   [  1: 0] cpu_0_data_master_dbs_address;
  input   [ 15: 0] cpu_0_data_master_dbs_write_16;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input            reset_n;
  input   [ 15: 0] system_0_burst_5_upstream_readdata;
  input            system_0_burst_5_upstream_readdatavalid;
  input            system_0_burst_5_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire    [  1: 0] cpu_0_data_master_byteenable_system_0_burst_5_upstream;
  wire    [  1: 0] cpu_0_data_master_byteenable_system_0_burst_5_upstream_segment_0;
  wire    [  1: 0] cpu_0_data_master_byteenable_system_0_burst_5_upstream_segment_1;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_5_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_5_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_5_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_5_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_5_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_5_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_5_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_5_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_5_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_5_upstream_load_fifo;
  wire    [ 22: 0] system_0_burst_5_upstream_address;
  wire             system_0_burst_5_upstream_allgrants;
  wire             system_0_burst_5_upstream_allow_new_arb_cycle;
  wire             system_0_burst_5_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_5_upstream_any_continuerequest;
  wire             system_0_burst_5_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_5_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_5_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_5_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_5_upstream_bbt_burstcounter;
  wire             system_0_burst_5_upstream_beginbursttransfer_internal;
  wire             system_0_burst_5_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_5_upstream_burstcount;
  wire             system_0_burst_5_upstream_burstcount_fifo_empty;
  wire    [ 23: 0] system_0_burst_5_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_5_upstream_byteenable;
  reg     [  4: 0] system_0_burst_5_upstream_current_burst;
  wire    [  4: 0] system_0_burst_5_upstream_current_burst_minus_one;
  wire             system_0_burst_5_upstream_debugaccess;
  wire             system_0_burst_5_upstream_end_xfer;
  wire             system_0_burst_5_upstream_firsttransfer;
  wire             system_0_burst_5_upstream_grant_vector;
  wire             system_0_burst_5_upstream_in_a_read_cycle;
  wire             system_0_burst_5_upstream_in_a_write_cycle;
  reg              system_0_burst_5_upstream_load_fifo;
  wire             system_0_burst_5_upstream_master_qreq_vector;
  wire             system_0_burst_5_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_5_upstream_next_bbt_burstcount;
  wire    [  4: 0] system_0_burst_5_upstream_next_burst_count;
  wire             system_0_burst_5_upstream_non_bursting_master_requests;
  wire             system_0_burst_5_upstream_read;
  wire    [ 15: 0] system_0_burst_5_upstream_readdata_from_sa;
  wire             system_0_burst_5_upstream_readdatavalid_from_sa;
  reg              system_0_burst_5_upstream_reg_firsttransfer;
  wire    [  4: 0] system_0_burst_5_upstream_selected_burstcount;
  reg              system_0_burst_5_upstream_slavearbiterlockenable;
  wire             system_0_burst_5_upstream_slavearbiterlockenable2;
  wire             system_0_burst_5_upstream_this_cycle_is_the_last_burst;
  wire    [  4: 0] system_0_burst_5_upstream_transaction_burst_count;
  wire             system_0_burst_5_upstream_unreg_firsttransfer;
  wire             system_0_burst_5_upstream_waitrequest_from_sa;
  wire             system_0_burst_5_upstream_waits_for_read;
  wire             system_0_burst_5_upstream_waits_for_write;
  wire             system_0_burst_5_upstream_write;
  wire    [ 15: 0] system_0_burst_5_upstream_writedata;
  wire             wait_for_system_0_burst_5_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_5_upstream_end_xfer;
    end


  assign system_0_burst_5_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_5_upstream));
  //assign system_0_burst_5_upstream_readdatavalid_from_sa = system_0_burst_5_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_5_upstream_readdatavalid_from_sa = system_0_burst_5_upstream_readdatavalid;

  //assign system_0_burst_5_upstream_readdata_from_sa = system_0_burst_5_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_5_upstream_readdata_from_sa = system_0_burst_5_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_5_upstream = ({cpu_0_data_master_address_to_slave[24 : 23] , 23'b0} == 25'h800000) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_5_upstream_waitrequest_from_sa = system_0_burst_5_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_5_upstream_waitrequest_from_sa = system_0_burst_5_upstream_waitrequest;

  //system_0_burst_5_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_5_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_5_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount<< 1 : 1)) :
    1;

  //system_0_burst_5_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_5_upstream_non_bursting_master_requests = 0;

  //system_0_burst_5_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_5_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_5_upstream;

  //system_0_burst_5_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_5_upstream_arb_share_counter_next_value = system_0_burst_5_upstream_firsttransfer ? (system_0_burst_5_upstream_arb_share_set_values - 1) : |system_0_burst_5_upstream_arb_share_counter ? (system_0_burst_5_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_5_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_5_upstream_allgrants = |system_0_burst_5_upstream_grant_vector;

  //system_0_burst_5_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_5_upstream_end_xfer = ~(system_0_burst_5_upstream_waits_for_read | system_0_burst_5_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_5_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_5_upstream = system_0_burst_5_upstream_end_xfer & (~system_0_burst_5_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_5_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_5_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_5_upstream & system_0_burst_5_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_5_upstream & ~system_0_burst_5_upstream_non_bursting_master_requests);

  //system_0_burst_5_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_5_upstream_arb_share_counter <= 0;
      else if (system_0_burst_5_upstream_arb_counter_enable)
          system_0_burst_5_upstream_arb_share_counter <= system_0_burst_5_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_5_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_5_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_5_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_5_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_5_upstream & ~system_0_burst_5_upstream_non_bursting_master_requests))
          system_0_burst_5_upstream_slavearbiterlockenable <= |system_0_burst_5_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_5/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_5_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_5_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_5_upstream_slavearbiterlockenable2 = |system_0_burst_5_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_5/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_5_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_5_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_5_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_5_upstream = cpu_0_data_master_requests_system_0_burst_5_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_5_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_5_upstream_move_on_to_next_transaction = system_0_burst_5_upstream_this_cycle_is_the_last_burst & system_0_burst_5_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_5_upstream, which is an e_mux
  assign system_0_burst_5_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_5_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_5_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_5_upstream_module burstcount_fifo_for_system_0_burst_5_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_5_upstream_selected_burstcount),
      .data_out             (system_0_burst_5_upstream_transaction_burst_count),
      .empty                (system_0_burst_5_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_5_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_5_upstream_waits_for_read & system_0_burst_5_upstream_load_fifo & ~(system_0_burst_5_upstream_this_cycle_is_the_last_burst & system_0_burst_5_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_5_upstream current burst minus one, which is an e_assign
  assign system_0_burst_5_upstream_current_burst_minus_one = system_0_burst_5_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_5_upstream, which is an e_mux
  assign system_0_burst_5_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_5_upstream_waits_for_read) & ~system_0_burst_5_upstream_load_fifo))? {system_0_burst_5_upstream_selected_burstcount, 1'b0} :
    ((in_a_read_cycle & ~system_0_burst_5_upstream_waits_for_read & system_0_burst_5_upstream_this_cycle_is_the_last_burst & system_0_burst_5_upstream_burstcount_fifo_empty))? {system_0_burst_5_upstream_selected_burstcount, 1'b0} :
    (system_0_burst_5_upstream_this_cycle_is_the_last_burst)? {system_0_burst_5_upstream_transaction_burst_count,  1'b0} :
    system_0_burst_5_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_5_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_5_upstream_current_burst <= 0;
      else if (system_0_burst_5_upstream_readdatavalid_from_sa | (~system_0_burst_5_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_5_upstream_waits_for_read)))
          system_0_burst_5_upstream_current_burst <= system_0_burst_5_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_5_upstream_load_fifo = (~system_0_burst_5_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_5_upstream_waits_for_read) & system_0_burst_5_upstream_load_fifo))? 1 :
    ~system_0_burst_5_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_5_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_5_upstream_waits_for_read) & ~system_0_burst_5_upstream_load_fifo | system_0_burst_5_upstream_this_cycle_is_the_last_burst)
          system_0_burst_5_upstream_load_fifo <= p0_system_0_burst_5_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_5_upstream, which is an e_assign
  assign system_0_burst_5_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_5_upstream_current_burst_minus_one) & system_0_burst_5_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_5_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_5_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_5_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_5_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_5_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_5_upstream),
      .full                 (),
      .read                 (system_0_burst_5_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_5_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_5_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_5_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_5_upstream = system_0_burst_5_upstream_readdatavalid_from_sa;

  //system_0_burst_5_upstream_writedata mux, which is an e_mux
  assign system_0_burst_5_upstream_writedata = cpu_0_data_master_dbs_write_16;

  //byteaddress mux for system_0_burst_5/upstream, which is an e_mux
  assign system_0_burst_5_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_5_upstream = cpu_0_data_master_qualified_request_system_0_burst_5_upstream;

  //cpu_0/data_master saved-grant system_0_burst_5/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_5_upstream = cpu_0_data_master_requests_system_0_burst_5_upstream;

  //allow new arb cycle for system_0_burst_5/upstream, which is an e_assign
  assign system_0_burst_5_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_5_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_5_upstream_master_qreq_vector = 1;

  //system_0_burst_5_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_5_upstream_firsttransfer = system_0_burst_5_upstream_begins_xfer ? system_0_burst_5_upstream_unreg_firsttransfer : system_0_burst_5_upstream_reg_firsttransfer;

  //system_0_burst_5_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_5_upstream_unreg_firsttransfer = ~(system_0_burst_5_upstream_slavearbiterlockenable & system_0_burst_5_upstream_any_continuerequest);

  //system_0_burst_5_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_5_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_5_upstream_begins_xfer)
          system_0_burst_5_upstream_reg_firsttransfer <= system_0_burst_5_upstream_unreg_firsttransfer;
    end


  //system_0_burst_5_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_5_upstream_next_bbt_burstcount = ((((system_0_burst_5_upstream_write) && (system_0_burst_5_upstream_bbt_burstcounter == 0))))? (system_0_burst_5_upstream_burstcount - 1) :
    ((((system_0_burst_5_upstream_read) && (system_0_burst_5_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_5_upstream_bbt_burstcounter - 1);

  //system_0_burst_5_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_5_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_5_upstream_begins_xfer)
          system_0_burst_5_upstream_bbt_burstcounter <= system_0_burst_5_upstream_next_bbt_burstcount;
    end


  //system_0_burst_5_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_5_upstream_beginbursttransfer_internal = system_0_burst_5_upstream_begins_xfer & (system_0_burst_5_upstream_bbt_burstcounter == 0);

  //system_0_burst_5_upstream_read assignment, which is an e_mux
  assign system_0_burst_5_upstream_read = cpu_0_data_master_granted_system_0_burst_5_upstream & cpu_0_data_master_read;

  //system_0_burst_5_upstream_write assignment, which is an e_mux
  assign system_0_burst_5_upstream_write = cpu_0_data_master_granted_system_0_burst_5_upstream & cpu_0_data_master_write;

  //system_0_burst_5_upstream_address mux, which is an e_mux
  assign system_0_burst_5_upstream_address = {cpu_0_data_master_address_to_slave >> 2,
    cpu_0_data_master_dbs_address[1],
    {1 {1'b0}}};

  //d1_system_0_burst_5_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_5_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_5_upstream_end_xfer <= system_0_burst_5_upstream_end_xfer;
    end


  //system_0_burst_5_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_5_upstream_waits_for_read = system_0_burst_5_upstream_in_a_read_cycle & system_0_burst_5_upstream_waitrequest_from_sa;

  //system_0_burst_5_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_5_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_5_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_5_upstream_in_a_read_cycle;

  //system_0_burst_5_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_5_upstream_waits_for_write = system_0_burst_5_upstream_in_a_write_cycle & system_0_burst_5_upstream_waitrequest_from_sa;

  //system_0_burst_5_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_5_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_5_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_5_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_5_upstream_counter = 0;
  //system_0_burst_5_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_5_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_5_upstream)? cpu_0_data_master_byteenable_system_0_burst_5_upstream :
    -1;

  assign {cpu_0_data_master_byteenable_system_0_burst_5_upstream_segment_1,
cpu_0_data_master_byteenable_system_0_burst_5_upstream_segment_0} = cpu_0_data_master_byteenable;
  assign cpu_0_data_master_byteenable_system_0_burst_5_upstream = ((cpu_0_data_master_dbs_address[1] == 0))? cpu_0_data_master_byteenable_system_0_burst_5_upstream_segment_0 :
    cpu_0_data_master_byteenable_system_0_burst_5_upstream_segment_1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_5_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_5_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_5_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_5_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_5/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_5_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_5/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_5_downstream_arbitrator (
                                                // inputs:
                                                 clk,
                                                 d1_sdram_0_s1_end_xfer,
                                                 reset_n,
                                                 sdram_0_s1_readdata_from_sa,
                                                 sdram_0_s1_waitrequest_from_sa,
                                                 system_0_burst_5_downstream_address,
                                                 system_0_burst_5_downstream_burstcount,
                                                 system_0_burst_5_downstream_byteenable,
                                                 system_0_burst_5_downstream_granted_sdram_0_s1,
                                                 system_0_burst_5_downstream_qualified_request_sdram_0_s1,
                                                 system_0_burst_5_downstream_read,
                                                 system_0_burst_5_downstream_read_data_valid_sdram_0_s1,
                                                 system_0_burst_5_downstream_read_data_valid_sdram_0_s1_shift_register,
                                                 system_0_burst_5_downstream_requests_sdram_0_s1,
                                                 system_0_burst_5_downstream_write,
                                                 system_0_burst_5_downstream_writedata,

                                                // outputs:
                                                 system_0_burst_5_downstream_address_to_slave,
                                                 system_0_burst_5_downstream_latency_counter,
                                                 system_0_burst_5_downstream_readdata,
                                                 system_0_burst_5_downstream_readdatavalid,
                                                 system_0_burst_5_downstream_reset_n,
                                                 system_0_burst_5_downstream_waitrequest
                                              )
;

  output  [ 22: 0] system_0_burst_5_downstream_address_to_slave;
  output           system_0_burst_5_downstream_latency_counter;
  output  [ 15: 0] system_0_burst_5_downstream_readdata;
  output           system_0_burst_5_downstream_readdatavalid;
  output           system_0_burst_5_downstream_reset_n;
  output           system_0_burst_5_downstream_waitrequest;
  input            clk;
  input            d1_sdram_0_s1_end_xfer;
  input            reset_n;
  input   [ 15: 0] sdram_0_s1_readdata_from_sa;
  input            sdram_0_s1_waitrequest_from_sa;
  input   [ 22: 0] system_0_burst_5_downstream_address;
  input            system_0_burst_5_downstream_burstcount;
  input   [  1: 0] system_0_burst_5_downstream_byteenable;
  input            system_0_burst_5_downstream_granted_sdram_0_s1;
  input            system_0_burst_5_downstream_qualified_request_sdram_0_s1;
  input            system_0_burst_5_downstream_read;
  input            system_0_burst_5_downstream_read_data_valid_sdram_0_s1;
  input            system_0_burst_5_downstream_read_data_valid_sdram_0_s1_shift_register;
  input            system_0_burst_5_downstream_requests_sdram_0_s1;
  input            system_0_burst_5_downstream_write;
  input   [ 15: 0] system_0_burst_5_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             latency_load_value;
  wire             p1_system_0_burst_5_downstream_latency_counter;
  wire             pre_flush_system_0_burst_5_downstream_readdatavalid;
  wire             r_0;
  reg     [ 22: 0] system_0_burst_5_downstream_address_last_time;
  wire    [ 22: 0] system_0_burst_5_downstream_address_to_slave;
  reg              system_0_burst_5_downstream_burstcount_last_time;
  reg     [  1: 0] system_0_burst_5_downstream_byteenable_last_time;
  wire             system_0_burst_5_downstream_is_granted_some_slave;
  reg              system_0_burst_5_downstream_latency_counter;
  reg              system_0_burst_5_downstream_read_but_no_slave_selected;
  reg              system_0_burst_5_downstream_read_last_time;
  wire    [ 15: 0] system_0_burst_5_downstream_readdata;
  wire             system_0_burst_5_downstream_readdatavalid;
  wire             system_0_burst_5_downstream_reset_n;
  wire             system_0_burst_5_downstream_run;
  wire             system_0_burst_5_downstream_waitrequest;
  reg              system_0_burst_5_downstream_write_last_time;
  reg     [ 15: 0] system_0_burst_5_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_5_downstream_qualified_request_sdram_0_s1 | ~system_0_burst_5_downstream_requests_sdram_0_s1) & (system_0_burst_5_downstream_granted_sdram_0_s1 | ~system_0_burst_5_downstream_qualified_request_sdram_0_s1) & ((~system_0_burst_5_downstream_qualified_request_sdram_0_s1 | ~(system_0_burst_5_downstream_read | system_0_burst_5_downstream_write) | (1 & ~sdram_0_s1_waitrequest_from_sa & (system_0_burst_5_downstream_read | system_0_burst_5_downstream_write)))) & ((~system_0_burst_5_downstream_qualified_request_sdram_0_s1 | ~(system_0_burst_5_downstream_read | system_0_burst_5_downstream_write) | (1 & ~sdram_0_s1_waitrequest_from_sa & (system_0_burst_5_downstream_read | system_0_burst_5_downstream_write))));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_5_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_5_downstream_address_to_slave = system_0_burst_5_downstream_address;

  //system_0_burst_5_downstream_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_5_downstream_read_but_no_slave_selected <= 0;
      else 
        system_0_burst_5_downstream_read_but_no_slave_selected <= system_0_burst_5_downstream_read & system_0_burst_5_downstream_run & ~system_0_burst_5_downstream_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign system_0_burst_5_downstream_is_granted_some_slave = system_0_burst_5_downstream_granted_sdram_0_s1;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_5_downstream_readdatavalid = system_0_burst_5_downstream_read_data_valid_sdram_0_s1;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_5_downstream_readdatavalid = system_0_burst_5_downstream_read_but_no_slave_selected |
    pre_flush_system_0_burst_5_downstream_readdatavalid;

  //system_0_burst_5/downstream readdata mux, which is an e_mux
  assign system_0_burst_5_downstream_readdata = sdram_0_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_5_downstream_waitrequest = ~system_0_burst_5_downstream_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_5_downstream_latency_counter <= 0;
      else 
        system_0_burst_5_downstream_latency_counter <= p1_system_0_burst_5_downstream_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_system_0_burst_5_downstream_latency_counter = ((system_0_burst_5_downstream_run & system_0_burst_5_downstream_read))? latency_load_value :
    (system_0_burst_5_downstream_latency_counter)? system_0_burst_5_downstream_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = 0;

  //system_0_burst_5_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_5_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_5_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_5_downstream_address_last_time <= 0;
      else 
        system_0_burst_5_downstream_address_last_time <= system_0_burst_5_downstream_address;
    end


  //system_0_burst_5/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_5_downstream_waitrequest & (system_0_burst_5_downstream_read | system_0_burst_5_downstream_write);
    end


  //system_0_burst_5_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_5_downstream_address != system_0_burst_5_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_5_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_5_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_5_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_5_downstream_burstcount_last_time <= system_0_burst_5_downstream_burstcount;
    end


  //system_0_burst_5_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_5_downstream_burstcount != system_0_burst_5_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_5_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_5_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_5_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_5_downstream_byteenable_last_time <= system_0_burst_5_downstream_byteenable;
    end


  //system_0_burst_5_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_5_downstream_byteenable != system_0_burst_5_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_5_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_5_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_5_downstream_read_last_time <= 0;
      else 
        system_0_burst_5_downstream_read_last_time <= system_0_burst_5_downstream_read;
    end


  //system_0_burst_5_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_5_downstream_read != system_0_burst_5_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_5_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_5_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_5_downstream_write_last_time <= 0;
      else 
        system_0_burst_5_downstream_write_last_time <= system_0_burst_5_downstream_write;
    end


  //system_0_burst_5_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_5_downstream_write != system_0_burst_5_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_5_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_5_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_5_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_5_downstream_writedata_last_time <= system_0_burst_5_downstream_writedata;
    end


  //system_0_burst_5_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_5_downstream_writedata != system_0_burst_5_downstream_writedata_last_time) & system_0_burst_5_downstream_write)
        begin
          $write("%0d ns: system_0_burst_5_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_6_upstream_module (
                                                              // inputs:
                                                               clear_fifo,
                                                               clk,
                                                               data_in,
                                                               read,
                                                               reset_n,
                                                               sync_reset,
                                                               write,

                                                              // outputs:
                                                               data_out,
                                                               empty,
                                                               fifo_contains_ones_n,
                                                               full
                                                            )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_6_upstream_module (
                                                                                   // inputs:
                                                                                    clear_fifo,
                                                                                    clk,
                                                                                    data_in,
                                                                                    read,
                                                                                    reset_n,
                                                                                    sync_reset,
                                                                                    write,

                                                                                   // outputs:
                                                                                    data_out,
                                                                                    empty,
                                                                                    fifo_contains_ones_n,
                                                                                    full
                                                                                 )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_6_upstream_arbitrator (
                                              // inputs:
                                               clk,
                                               cpu_0_instruction_master_address_to_slave,
                                               cpu_0_instruction_master_burstcount,
                                               cpu_0_instruction_master_latency_counter,
                                               cpu_0_instruction_master_read,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register,
                                               reset_n,
                                               system_0_burst_6_upstream_readdata,
                                               system_0_burst_6_upstream_readdatavalid,
                                               system_0_burst_6_upstream_waitrequest,

                                              // outputs:
                                               cpu_0_instruction_master_granted_system_0_burst_6_upstream,
                                               cpu_0_instruction_master_qualified_request_system_0_burst_6_upstream,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream,
                                               cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register,
                                               cpu_0_instruction_master_requests_system_0_burst_6_upstream,
                                               d1_system_0_burst_6_upstream_end_xfer,
                                               system_0_burst_6_upstream_address,
                                               system_0_burst_6_upstream_byteaddress,
                                               system_0_burst_6_upstream_byteenable,
                                               system_0_burst_6_upstream_debugaccess,
                                               system_0_burst_6_upstream_read,
                                               system_0_burst_6_upstream_readdata_from_sa,
                                               system_0_burst_6_upstream_waitrequest_from_sa,
                                               system_0_burst_6_upstream_write
                                            )
;

  output           cpu_0_instruction_master_granted_system_0_burst_6_upstream;
  output           cpu_0_instruction_master_qualified_request_system_0_burst_6_upstream;
  output           cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream;
  output           cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register;
  output           cpu_0_instruction_master_requests_system_0_burst_6_upstream;
  output           d1_system_0_burst_6_upstream_end_xfer;
  output  [ 10: 0] system_0_burst_6_upstream_address;
  output  [ 12: 0] system_0_burst_6_upstream_byteaddress;
  output  [  3: 0] system_0_burst_6_upstream_byteenable;
  output           system_0_burst_6_upstream_debugaccess;
  output           system_0_burst_6_upstream_read;
  output  [ 31: 0] system_0_burst_6_upstream_readdata_from_sa;
  output           system_0_burst_6_upstream_waitrequest_from_sa;
  output           system_0_burst_6_upstream_write;
  input            clk;
  input   [ 24: 0] cpu_0_instruction_master_address_to_slave;
  input   [  3: 0] cpu_0_instruction_master_burstcount;
  input            cpu_0_instruction_master_latency_counter;
  input            cpu_0_instruction_master_read;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register;
  input            cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register;
  input            reset_n;
  input   [ 31: 0] system_0_burst_6_upstream_readdata;
  input            system_0_burst_6_upstream_readdatavalid;
  input            system_0_burst_6_upstream_waitrequest;

  wire             cpu_0_instruction_master_arbiterlock;
  wire             cpu_0_instruction_master_arbiterlock2;
  wire             cpu_0_instruction_master_continuerequest;
  wire             cpu_0_instruction_master_granted_system_0_burst_6_upstream;
  wire             cpu_0_instruction_master_qualified_request_system_0_burst_6_upstream;
  wire             cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_6_upstream;
  wire             cpu_0_instruction_master_rdv_fifo_output_from_system_0_burst_6_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register;
  wire             cpu_0_instruction_master_requests_system_0_burst_6_upstream;
  wire             cpu_0_instruction_master_saved_grant_system_0_burst_6_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_6_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_6_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_6_upstream_load_fifo;
  wire    [ 10: 0] system_0_burst_6_upstream_address;
  wire             system_0_burst_6_upstream_allgrants;
  wire             system_0_burst_6_upstream_allow_new_arb_cycle;
  wire             system_0_burst_6_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_6_upstream_any_continuerequest;
  wire             system_0_burst_6_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_6_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_6_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_6_upstream_arb_share_set_values;
  wire             system_0_burst_6_upstream_beginbursttransfer_internal;
  wire             system_0_burst_6_upstream_begins_xfer;
  wire             system_0_burst_6_upstream_burstcount_fifo_empty;
  wire    [ 12: 0] system_0_burst_6_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_6_upstream_byteenable;
  reg     [  3: 0] system_0_burst_6_upstream_current_burst;
  wire    [  3: 0] system_0_burst_6_upstream_current_burst_minus_one;
  wire             system_0_burst_6_upstream_debugaccess;
  wire             system_0_burst_6_upstream_end_xfer;
  wire             system_0_burst_6_upstream_firsttransfer;
  wire             system_0_burst_6_upstream_grant_vector;
  wire             system_0_burst_6_upstream_in_a_read_cycle;
  wire             system_0_burst_6_upstream_in_a_write_cycle;
  reg              system_0_burst_6_upstream_load_fifo;
  wire             system_0_burst_6_upstream_master_qreq_vector;
  wire             system_0_burst_6_upstream_move_on_to_next_transaction;
  wire    [  3: 0] system_0_burst_6_upstream_next_burst_count;
  wire             system_0_burst_6_upstream_non_bursting_master_requests;
  wire             system_0_burst_6_upstream_read;
  wire    [ 31: 0] system_0_burst_6_upstream_readdata_from_sa;
  wire             system_0_burst_6_upstream_readdatavalid_from_sa;
  reg              system_0_burst_6_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_6_upstream_selected_burstcount;
  reg              system_0_burst_6_upstream_slavearbiterlockenable;
  wire             system_0_burst_6_upstream_slavearbiterlockenable2;
  wire             system_0_burst_6_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_6_upstream_transaction_burst_count;
  wire             system_0_burst_6_upstream_unreg_firsttransfer;
  wire             system_0_burst_6_upstream_waitrequest_from_sa;
  wire             system_0_burst_6_upstream_waits_for_read;
  wire             system_0_burst_6_upstream_waits_for_write;
  wire             system_0_burst_6_upstream_write;
  wire             wait_for_system_0_burst_6_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_6_upstream_end_xfer;
    end


  assign system_0_burst_6_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_instruction_master_qualified_request_system_0_burst_6_upstream));
  //assign system_0_burst_6_upstream_readdatavalid_from_sa = system_0_burst_6_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_6_upstream_readdatavalid_from_sa = system_0_burst_6_upstream_readdatavalid;

  //assign system_0_burst_6_upstream_readdata_from_sa = system_0_burst_6_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_6_upstream_readdata_from_sa = system_0_burst_6_upstream_readdata;

  assign cpu_0_instruction_master_requests_system_0_burst_6_upstream = (({cpu_0_instruction_master_address_to_slave[24 : 11] , 11'b0} == 25'h1909800) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
  //assign system_0_burst_6_upstream_waitrequest_from_sa = system_0_burst_6_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_6_upstream_waitrequest_from_sa = system_0_burst_6_upstream_waitrequest;

  //system_0_burst_6_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_6_upstream_arb_share_set_values = 1;

  //system_0_burst_6_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_6_upstream_non_bursting_master_requests = 0;

  //system_0_burst_6_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_6_upstream_any_bursting_master_saved_grant = cpu_0_instruction_master_saved_grant_system_0_burst_6_upstream;

  //system_0_burst_6_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_6_upstream_arb_share_counter_next_value = system_0_burst_6_upstream_firsttransfer ? (system_0_burst_6_upstream_arb_share_set_values - 1) : |system_0_burst_6_upstream_arb_share_counter ? (system_0_burst_6_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_6_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_6_upstream_allgrants = |system_0_burst_6_upstream_grant_vector;

  //system_0_burst_6_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_6_upstream_end_xfer = ~(system_0_burst_6_upstream_waits_for_read | system_0_burst_6_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_6_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_6_upstream = system_0_burst_6_upstream_end_xfer & (~system_0_burst_6_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_6_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_6_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_6_upstream & system_0_burst_6_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_6_upstream & ~system_0_burst_6_upstream_non_bursting_master_requests);

  //system_0_burst_6_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_6_upstream_arb_share_counter <= 0;
      else if (system_0_burst_6_upstream_arb_counter_enable)
          system_0_burst_6_upstream_arb_share_counter <= system_0_burst_6_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_6_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_6_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_6_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_6_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_6_upstream & ~system_0_burst_6_upstream_non_bursting_master_requests))
          system_0_burst_6_upstream_slavearbiterlockenable <= |system_0_burst_6_upstream_arb_share_counter_next_value;
    end


  //cpu_0/instruction_master system_0_burst_6/upstream arbiterlock, which is an e_assign
  assign cpu_0_instruction_master_arbiterlock = system_0_burst_6_upstream_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;

  //system_0_burst_6_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_6_upstream_slavearbiterlockenable2 = |system_0_burst_6_upstream_arb_share_counter_next_value;

  //cpu_0/instruction_master system_0_burst_6/upstream arbiterlock2, which is an e_assign
  assign cpu_0_instruction_master_arbiterlock2 = system_0_burst_6_upstream_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;

  //system_0_burst_6_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_6_upstream_any_continuerequest = 1;

  //cpu_0_instruction_master_continuerequest continued request, which is an e_assign
  assign cpu_0_instruction_master_continuerequest = 1;

  assign cpu_0_instruction_master_qualified_request_system_0_burst_6_upstream = cpu_0_instruction_master_requests_system_0_burst_6_upstream & ~((cpu_0_instruction_master_read & ((cpu_0_instruction_master_latency_counter != 0) | (1 < cpu_0_instruction_master_latency_counter) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register) | (|cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register))));
  //unique name for system_0_burst_6_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_6_upstream_move_on_to_next_transaction = system_0_burst_6_upstream_this_cycle_is_the_last_burst & system_0_burst_6_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_6_upstream, which is an e_mux
  assign system_0_burst_6_upstream_selected_burstcount = (cpu_0_instruction_master_granted_system_0_burst_6_upstream)? cpu_0_instruction_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_6_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_6_upstream_module burstcount_fifo_for_system_0_burst_6_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_6_upstream_selected_burstcount),
      .data_out             (system_0_burst_6_upstream_transaction_burst_count),
      .empty                (system_0_burst_6_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_6_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_6_upstream_waits_for_read & system_0_burst_6_upstream_load_fifo & ~(system_0_burst_6_upstream_this_cycle_is_the_last_burst & system_0_burst_6_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_6_upstream current burst minus one, which is an e_assign
  assign system_0_burst_6_upstream_current_burst_minus_one = system_0_burst_6_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_6_upstream, which is an e_mux
  assign system_0_burst_6_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_6_upstream_waits_for_read) & ~system_0_burst_6_upstream_load_fifo))? system_0_burst_6_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_6_upstream_waits_for_read & system_0_burst_6_upstream_this_cycle_is_the_last_burst & system_0_burst_6_upstream_burstcount_fifo_empty))? system_0_burst_6_upstream_selected_burstcount :
    (system_0_burst_6_upstream_this_cycle_is_the_last_burst)? system_0_burst_6_upstream_transaction_burst_count :
    system_0_burst_6_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_6_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_6_upstream_current_burst <= 0;
      else if (system_0_burst_6_upstream_readdatavalid_from_sa | (~system_0_burst_6_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_6_upstream_waits_for_read)))
          system_0_burst_6_upstream_current_burst <= system_0_burst_6_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_6_upstream_load_fifo = (~system_0_burst_6_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_6_upstream_waits_for_read) & system_0_burst_6_upstream_load_fifo))? 1 :
    ~system_0_burst_6_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_6_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_6_upstream_waits_for_read) & ~system_0_burst_6_upstream_load_fifo | system_0_burst_6_upstream_this_cycle_is_the_last_burst)
          system_0_burst_6_upstream_load_fifo <= p0_system_0_burst_6_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_6_upstream, which is an e_assign
  assign system_0_burst_6_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_6_upstream_current_burst_minus_one) & system_0_burst_6_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_6_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_6_upstream_module rdv_fifo_for_cpu_0_instruction_master_to_system_0_burst_6_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_instruction_master_granted_system_0_burst_6_upstream),
      .data_out             (cpu_0_instruction_master_rdv_fifo_output_from_system_0_burst_6_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_6_upstream),
      .full                 (),
      .read                 (system_0_burst_6_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_6_upstream_waits_for_read)
    );

  assign cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register = ~cpu_0_instruction_master_rdv_fifo_empty_system_0_burst_6_upstream;
  //local readdatavalid cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream, which is an e_mux
  assign cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream = system_0_burst_6_upstream_readdatavalid_from_sa;

  //byteaddress mux for system_0_burst_6/upstream, which is an e_mux
  assign system_0_burst_6_upstream_byteaddress = cpu_0_instruction_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_instruction_master_granted_system_0_burst_6_upstream = cpu_0_instruction_master_qualified_request_system_0_burst_6_upstream;

  //cpu_0/instruction_master saved-grant system_0_burst_6/upstream, which is an e_assign
  assign cpu_0_instruction_master_saved_grant_system_0_burst_6_upstream = cpu_0_instruction_master_requests_system_0_burst_6_upstream;

  //allow new arb cycle for system_0_burst_6/upstream, which is an e_assign
  assign system_0_burst_6_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_6_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_6_upstream_master_qreq_vector = 1;

  //system_0_burst_6_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_6_upstream_firsttransfer = system_0_burst_6_upstream_begins_xfer ? system_0_burst_6_upstream_unreg_firsttransfer : system_0_burst_6_upstream_reg_firsttransfer;

  //system_0_burst_6_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_6_upstream_unreg_firsttransfer = ~(system_0_burst_6_upstream_slavearbiterlockenable & system_0_burst_6_upstream_any_continuerequest);

  //system_0_burst_6_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_6_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_6_upstream_begins_xfer)
          system_0_burst_6_upstream_reg_firsttransfer <= system_0_burst_6_upstream_unreg_firsttransfer;
    end


  //system_0_burst_6_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_6_upstream_beginbursttransfer_internal = system_0_burst_6_upstream_begins_xfer;

  //system_0_burst_6_upstream_read assignment, which is an e_mux
  assign system_0_burst_6_upstream_read = cpu_0_instruction_master_granted_system_0_burst_6_upstream & cpu_0_instruction_master_read;

  //system_0_burst_6_upstream_write assignment, which is an e_mux
  assign system_0_burst_6_upstream_write = 0;

  //system_0_burst_6_upstream_address mux, which is an e_mux
  assign system_0_burst_6_upstream_address = cpu_0_instruction_master_address_to_slave;

  //d1_system_0_burst_6_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_6_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_6_upstream_end_xfer <= system_0_burst_6_upstream_end_xfer;
    end


  //system_0_burst_6_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_6_upstream_waits_for_read = system_0_burst_6_upstream_in_a_read_cycle & system_0_burst_6_upstream_waitrequest_from_sa;

  //system_0_burst_6_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_6_upstream_in_a_read_cycle = cpu_0_instruction_master_granted_system_0_burst_6_upstream & cpu_0_instruction_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_6_upstream_in_a_read_cycle;

  //system_0_burst_6_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_6_upstream_waits_for_write = system_0_burst_6_upstream_in_a_write_cycle & system_0_burst_6_upstream_waitrequest_from_sa;

  //system_0_burst_6_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_6_upstream_in_a_write_cycle = 0;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_6_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_6_upstream_counter = 0;
  //system_0_burst_6_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_6_upstream_byteenable = -1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_6_upstream_debugaccess = 0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_6/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/instruction_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_instruction_master_requests_system_0_burst_6_upstream && (cpu_0_instruction_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/instruction_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_6/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_6_downstream_arbitrator (
                                                // inputs:
                                                 clk,
                                                 d1_epcs_controller_epcs_control_port_end_xfer,
                                                 epcs_controller_epcs_control_port_readdata_from_sa,
                                                 reset_n,
                                                 system_0_burst_6_downstream_address,
                                                 system_0_burst_6_downstream_burstcount,
                                                 system_0_burst_6_downstream_byteenable,
                                                 system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port,
                                                 system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port,
                                                 system_0_burst_6_downstream_read,
                                                 system_0_burst_6_downstream_read_data_valid_epcs_controller_epcs_control_port,
                                                 system_0_burst_6_downstream_requests_epcs_controller_epcs_control_port,
                                                 system_0_burst_6_downstream_write,
                                                 system_0_burst_6_downstream_writedata,

                                                // outputs:
                                                 system_0_burst_6_downstream_address_to_slave,
                                                 system_0_burst_6_downstream_latency_counter,
                                                 system_0_burst_6_downstream_readdata,
                                                 system_0_burst_6_downstream_readdatavalid,
                                                 system_0_burst_6_downstream_reset_n,
                                                 system_0_burst_6_downstream_waitrequest
                                              )
;

  output  [ 10: 0] system_0_burst_6_downstream_address_to_slave;
  output           system_0_burst_6_downstream_latency_counter;
  output  [ 31: 0] system_0_burst_6_downstream_readdata;
  output           system_0_burst_6_downstream_readdatavalid;
  output           system_0_burst_6_downstream_reset_n;
  output           system_0_burst_6_downstream_waitrequest;
  input            clk;
  input            d1_epcs_controller_epcs_control_port_end_xfer;
  input   [ 31: 0] epcs_controller_epcs_control_port_readdata_from_sa;
  input            reset_n;
  input   [ 10: 0] system_0_burst_6_downstream_address;
  input            system_0_burst_6_downstream_burstcount;
  input   [  3: 0] system_0_burst_6_downstream_byteenable;
  input            system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port;
  input            system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port;
  input            system_0_burst_6_downstream_read;
  input            system_0_burst_6_downstream_read_data_valid_epcs_controller_epcs_control_port;
  input            system_0_burst_6_downstream_requests_epcs_controller_epcs_control_port;
  input            system_0_burst_6_downstream_write;
  input   [ 31: 0] system_0_burst_6_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             latency_load_value;
  wire             p1_system_0_burst_6_downstream_latency_counter;
  wire             pre_flush_system_0_burst_6_downstream_readdatavalid;
  wire             r_0;
  reg     [ 10: 0] system_0_burst_6_downstream_address_last_time;
  wire    [ 10: 0] system_0_burst_6_downstream_address_to_slave;
  reg              system_0_burst_6_downstream_burstcount_last_time;
  reg     [  3: 0] system_0_burst_6_downstream_byteenable_last_time;
  wire             system_0_burst_6_downstream_is_granted_some_slave;
  reg              system_0_burst_6_downstream_latency_counter;
  reg              system_0_burst_6_downstream_read_but_no_slave_selected;
  reg              system_0_burst_6_downstream_read_last_time;
  wire    [ 31: 0] system_0_burst_6_downstream_readdata;
  wire             system_0_burst_6_downstream_readdatavalid;
  wire             system_0_burst_6_downstream_reset_n;
  wire             system_0_burst_6_downstream_run;
  wire             system_0_burst_6_downstream_waitrequest;
  reg              system_0_burst_6_downstream_write_last_time;
  reg     [ 31: 0] system_0_burst_6_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port | ~system_0_burst_6_downstream_requests_epcs_controller_epcs_control_port) & (system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port | ~system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port) & ((~system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port | ~(system_0_burst_6_downstream_read | system_0_burst_6_downstream_write) | (1 & ~d1_epcs_controller_epcs_control_port_end_xfer & (system_0_burst_6_downstream_read | system_0_burst_6_downstream_write)))) & ((~system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port | ~(system_0_burst_6_downstream_read | system_0_burst_6_downstream_write) | (1 & ~d1_epcs_controller_epcs_control_port_end_xfer & (system_0_burst_6_downstream_read | system_0_burst_6_downstream_write))));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_6_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_6_downstream_address_to_slave = system_0_burst_6_downstream_address;

  //system_0_burst_6_downstream_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_6_downstream_read_but_no_slave_selected <= 0;
      else 
        system_0_burst_6_downstream_read_but_no_slave_selected <= system_0_burst_6_downstream_read & system_0_burst_6_downstream_run & ~system_0_burst_6_downstream_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign system_0_burst_6_downstream_is_granted_some_slave = system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_6_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_6_downstream_readdatavalid = system_0_burst_6_downstream_read_but_no_slave_selected |
    pre_flush_system_0_burst_6_downstream_readdatavalid |
    system_0_burst_6_downstream_read_data_valid_epcs_controller_epcs_control_port;

  //system_0_burst_6/downstream readdata mux, which is an e_mux
  assign system_0_burst_6_downstream_readdata = epcs_controller_epcs_control_port_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_6_downstream_waitrequest = ~system_0_burst_6_downstream_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_6_downstream_latency_counter <= 0;
      else 
        system_0_burst_6_downstream_latency_counter <= p1_system_0_burst_6_downstream_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_system_0_burst_6_downstream_latency_counter = ((system_0_burst_6_downstream_run & system_0_burst_6_downstream_read))? latency_load_value :
    (system_0_burst_6_downstream_latency_counter)? system_0_burst_6_downstream_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = 0;

  //system_0_burst_6_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_6_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_6_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_6_downstream_address_last_time <= 0;
      else 
        system_0_burst_6_downstream_address_last_time <= system_0_burst_6_downstream_address;
    end


  //system_0_burst_6/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_6_downstream_waitrequest & (system_0_burst_6_downstream_read | system_0_burst_6_downstream_write);
    end


  //system_0_burst_6_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_6_downstream_address != system_0_burst_6_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_6_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_6_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_6_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_6_downstream_burstcount_last_time <= system_0_burst_6_downstream_burstcount;
    end


  //system_0_burst_6_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_6_downstream_burstcount != system_0_burst_6_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_6_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_6_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_6_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_6_downstream_byteenable_last_time <= system_0_burst_6_downstream_byteenable;
    end


  //system_0_burst_6_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_6_downstream_byteenable != system_0_burst_6_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_6_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_6_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_6_downstream_read_last_time <= 0;
      else 
        system_0_burst_6_downstream_read_last_time <= system_0_burst_6_downstream_read;
    end


  //system_0_burst_6_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_6_downstream_read != system_0_burst_6_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_6_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_6_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_6_downstream_write_last_time <= 0;
      else 
        system_0_burst_6_downstream_write_last_time <= system_0_burst_6_downstream_write;
    end


  //system_0_burst_6_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_6_downstream_write != system_0_burst_6_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_6_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_6_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_6_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_6_downstream_writedata_last_time <= system_0_burst_6_downstream_writedata;
    end


  //system_0_burst_6_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_6_downstream_writedata != system_0_burst_6_downstream_writedata_last_time) & system_0_burst_6_downstream_write)
        begin
          $write("%0d ns: system_0_burst_6_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_7_upstream_module (
                                                              // inputs:
                                                               clear_fifo,
                                                               clk,
                                                               data_in,
                                                               read,
                                                               reset_n,
                                                               sync_reset,
                                                               write,

                                                              // outputs:
                                                               data_out,
                                                               empty,
                                                               fifo_contains_ones_n,
                                                               full
                                                            )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_7_upstream_module (
                                                                            // inputs:
                                                                             clear_fifo,
                                                                             clk,
                                                                             data_in,
                                                                             read,
                                                                             reset_n,
                                                                             sync_reset,
                                                                             write,

                                                                            // outputs:
                                                                             data_out,
                                                                             empty,
                                                                             fifo_contains_ones_n,
                                                                             full
                                                                          )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_7_upstream_arbitrator (
                                              // inputs:
                                               clk,
                                               cpu_0_data_master_address_to_slave,
                                               cpu_0_data_master_burstcount,
                                               cpu_0_data_master_byteenable,
                                               cpu_0_data_master_debugaccess,
                                               cpu_0_data_master_latency_counter,
                                               cpu_0_data_master_read,
                                               cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                               cpu_0_data_master_write,
                                               cpu_0_data_master_writedata,
                                               reset_n,
                                               system_0_burst_7_upstream_readdata,
                                               system_0_burst_7_upstream_readdatavalid,
                                               system_0_burst_7_upstream_waitrequest,

                                              // outputs:
                                               cpu_0_data_master_granted_system_0_burst_7_upstream,
                                               cpu_0_data_master_qualified_request_system_0_burst_7_upstream,
                                               cpu_0_data_master_read_data_valid_system_0_burst_7_upstream,
                                               cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                               cpu_0_data_master_requests_system_0_burst_7_upstream,
                                               d1_system_0_burst_7_upstream_end_xfer,
                                               system_0_burst_7_upstream_address,
                                               system_0_burst_7_upstream_burstcount,
                                               system_0_burst_7_upstream_byteaddress,
                                               system_0_burst_7_upstream_byteenable,
                                               system_0_burst_7_upstream_debugaccess,
                                               system_0_burst_7_upstream_read,
                                               system_0_burst_7_upstream_readdata_from_sa,
                                               system_0_burst_7_upstream_waitrequest_from_sa,
                                               system_0_burst_7_upstream_write,
                                               system_0_burst_7_upstream_writedata
                                            )
;

  output           cpu_0_data_master_granted_system_0_burst_7_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_7_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_7_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_7_upstream;
  output           d1_system_0_burst_7_upstream_end_xfer;
  output  [ 10: 0] system_0_burst_7_upstream_address;
  output  [  3: 0] system_0_burst_7_upstream_burstcount;
  output  [ 12: 0] system_0_burst_7_upstream_byteaddress;
  output  [  3: 0] system_0_burst_7_upstream_byteenable;
  output           system_0_burst_7_upstream_debugaccess;
  output           system_0_burst_7_upstream_read;
  output  [ 31: 0] system_0_burst_7_upstream_readdata_from_sa;
  output           system_0_burst_7_upstream_waitrequest_from_sa;
  output           system_0_burst_7_upstream_write;
  output  [ 31: 0] system_0_burst_7_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [ 31: 0] system_0_burst_7_upstream_readdata;
  input            system_0_burst_7_upstream_readdatavalid;
  input            system_0_burst_7_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_7_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_7_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_7_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_7_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_7_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_7_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_7_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_7_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_7_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_7_upstream_load_fifo;
  wire    [ 10: 0] system_0_burst_7_upstream_address;
  wire             system_0_burst_7_upstream_allgrants;
  wire             system_0_burst_7_upstream_allow_new_arb_cycle;
  wire             system_0_burst_7_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_7_upstream_any_continuerequest;
  wire             system_0_burst_7_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_7_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_7_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_7_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_7_upstream_bbt_burstcounter;
  wire             system_0_burst_7_upstream_beginbursttransfer_internal;
  wire             system_0_burst_7_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_7_upstream_burstcount;
  wire             system_0_burst_7_upstream_burstcount_fifo_empty;
  wire    [ 12: 0] system_0_burst_7_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_7_upstream_byteenable;
  reg     [  3: 0] system_0_burst_7_upstream_current_burst;
  wire    [  3: 0] system_0_burst_7_upstream_current_burst_minus_one;
  wire             system_0_burst_7_upstream_debugaccess;
  wire             system_0_burst_7_upstream_end_xfer;
  wire             system_0_burst_7_upstream_firsttransfer;
  wire             system_0_burst_7_upstream_grant_vector;
  wire             system_0_burst_7_upstream_in_a_read_cycle;
  wire             system_0_burst_7_upstream_in_a_write_cycle;
  reg              system_0_burst_7_upstream_load_fifo;
  wire             system_0_burst_7_upstream_master_qreq_vector;
  wire             system_0_burst_7_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_7_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_7_upstream_next_burst_count;
  wire             system_0_burst_7_upstream_non_bursting_master_requests;
  wire             system_0_burst_7_upstream_read;
  wire    [ 31: 0] system_0_burst_7_upstream_readdata_from_sa;
  wire             system_0_burst_7_upstream_readdatavalid_from_sa;
  reg              system_0_burst_7_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_7_upstream_selected_burstcount;
  reg              system_0_burst_7_upstream_slavearbiterlockenable;
  wire             system_0_burst_7_upstream_slavearbiterlockenable2;
  wire             system_0_burst_7_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_7_upstream_transaction_burst_count;
  wire             system_0_burst_7_upstream_unreg_firsttransfer;
  wire             system_0_burst_7_upstream_waitrequest_from_sa;
  wire             system_0_burst_7_upstream_waits_for_read;
  wire             system_0_burst_7_upstream_waits_for_write;
  wire             system_0_burst_7_upstream_write;
  wire    [ 31: 0] system_0_burst_7_upstream_writedata;
  wire             wait_for_system_0_burst_7_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_7_upstream_end_xfer;
    end


  assign system_0_burst_7_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_7_upstream));
  //assign system_0_burst_7_upstream_readdatavalid_from_sa = system_0_burst_7_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_7_upstream_readdatavalid_from_sa = system_0_burst_7_upstream_readdatavalid;

  //assign system_0_burst_7_upstream_readdata_from_sa = system_0_burst_7_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_7_upstream_readdata_from_sa = system_0_burst_7_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_7_upstream = ({cpu_0_data_master_address_to_slave[24 : 11] , 11'b0} == 25'h1909800) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_7_upstream_waitrequest_from_sa = system_0_burst_7_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_7_upstream_waitrequest_from_sa = system_0_burst_7_upstream_waitrequest;

  //system_0_burst_7_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_7_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_7_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_7_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_7_upstream_non_bursting_master_requests = 0;

  //system_0_burst_7_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_7_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_7_upstream;

  //system_0_burst_7_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_7_upstream_arb_share_counter_next_value = system_0_burst_7_upstream_firsttransfer ? (system_0_burst_7_upstream_arb_share_set_values - 1) : |system_0_burst_7_upstream_arb_share_counter ? (system_0_burst_7_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_7_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_7_upstream_allgrants = |system_0_burst_7_upstream_grant_vector;

  //system_0_burst_7_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_7_upstream_end_xfer = ~(system_0_burst_7_upstream_waits_for_read | system_0_burst_7_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_7_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_7_upstream = system_0_burst_7_upstream_end_xfer & (~system_0_burst_7_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_7_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_7_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_7_upstream & system_0_burst_7_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_7_upstream & ~system_0_burst_7_upstream_non_bursting_master_requests);

  //system_0_burst_7_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_7_upstream_arb_share_counter <= 0;
      else if (system_0_burst_7_upstream_arb_counter_enable)
          system_0_burst_7_upstream_arb_share_counter <= system_0_burst_7_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_7_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_7_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_7_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_7_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_7_upstream & ~system_0_burst_7_upstream_non_bursting_master_requests))
          system_0_burst_7_upstream_slavearbiterlockenable <= |system_0_burst_7_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_7/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_7_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_7_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_7_upstream_slavearbiterlockenable2 = |system_0_burst_7_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_7/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_7_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_7_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_7_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_7_upstream = cpu_0_data_master_requests_system_0_burst_7_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_7_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_7_upstream_move_on_to_next_transaction = system_0_burst_7_upstream_this_cycle_is_the_last_burst & system_0_burst_7_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_7_upstream, which is an e_mux
  assign system_0_burst_7_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_7_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_7_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_7_upstream_module burstcount_fifo_for_system_0_burst_7_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_7_upstream_selected_burstcount),
      .data_out             (system_0_burst_7_upstream_transaction_burst_count),
      .empty                (system_0_burst_7_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_7_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_7_upstream_waits_for_read & system_0_burst_7_upstream_load_fifo & ~(system_0_burst_7_upstream_this_cycle_is_the_last_burst & system_0_burst_7_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_7_upstream current burst minus one, which is an e_assign
  assign system_0_burst_7_upstream_current_burst_minus_one = system_0_burst_7_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_7_upstream, which is an e_mux
  assign system_0_burst_7_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_7_upstream_waits_for_read) & ~system_0_burst_7_upstream_load_fifo))? system_0_burst_7_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_7_upstream_waits_for_read & system_0_burst_7_upstream_this_cycle_is_the_last_burst & system_0_burst_7_upstream_burstcount_fifo_empty))? system_0_burst_7_upstream_selected_burstcount :
    (system_0_burst_7_upstream_this_cycle_is_the_last_burst)? system_0_burst_7_upstream_transaction_burst_count :
    system_0_burst_7_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_7_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_7_upstream_current_burst <= 0;
      else if (system_0_burst_7_upstream_readdatavalid_from_sa | (~system_0_burst_7_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_7_upstream_waits_for_read)))
          system_0_burst_7_upstream_current_burst <= system_0_burst_7_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_7_upstream_load_fifo = (~system_0_burst_7_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_7_upstream_waits_for_read) & system_0_burst_7_upstream_load_fifo))? 1 :
    ~system_0_burst_7_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_7_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_7_upstream_waits_for_read) & ~system_0_burst_7_upstream_load_fifo | system_0_burst_7_upstream_this_cycle_is_the_last_burst)
          system_0_burst_7_upstream_load_fifo <= p0_system_0_burst_7_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_7_upstream, which is an e_assign
  assign system_0_burst_7_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_7_upstream_current_burst_minus_one) & system_0_burst_7_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_7_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_7_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_7_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_7_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_7_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_7_upstream),
      .full                 (),
      .read                 (system_0_burst_7_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_7_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_7_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_7_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_7_upstream = system_0_burst_7_upstream_readdatavalid_from_sa;

  //system_0_burst_7_upstream_writedata mux, which is an e_mux
  assign system_0_burst_7_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_7/upstream, which is an e_mux
  assign system_0_burst_7_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_7_upstream = cpu_0_data_master_qualified_request_system_0_burst_7_upstream;

  //cpu_0/data_master saved-grant system_0_burst_7/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_7_upstream = cpu_0_data_master_requests_system_0_burst_7_upstream;

  //allow new arb cycle for system_0_burst_7/upstream, which is an e_assign
  assign system_0_burst_7_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_7_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_7_upstream_master_qreq_vector = 1;

  //system_0_burst_7_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_7_upstream_firsttransfer = system_0_burst_7_upstream_begins_xfer ? system_0_burst_7_upstream_unreg_firsttransfer : system_0_burst_7_upstream_reg_firsttransfer;

  //system_0_burst_7_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_7_upstream_unreg_firsttransfer = ~(system_0_burst_7_upstream_slavearbiterlockenable & system_0_burst_7_upstream_any_continuerequest);

  //system_0_burst_7_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_7_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_7_upstream_begins_xfer)
          system_0_burst_7_upstream_reg_firsttransfer <= system_0_burst_7_upstream_unreg_firsttransfer;
    end


  //system_0_burst_7_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_7_upstream_next_bbt_burstcount = ((((system_0_burst_7_upstream_write) && (system_0_burst_7_upstream_bbt_burstcounter == 0))))? (system_0_burst_7_upstream_burstcount - 1) :
    ((((system_0_burst_7_upstream_read) && (system_0_burst_7_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_7_upstream_bbt_burstcounter - 1);

  //system_0_burst_7_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_7_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_7_upstream_begins_xfer)
          system_0_burst_7_upstream_bbt_burstcounter <= system_0_burst_7_upstream_next_bbt_burstcount;
    end


  //system_0_burst_7_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_7_upstream_beginbursttransfer_internal = system_0_burst_7_upstream_begins_xfer & (system_0_burst_7_upstream_bbt_burstcounter == 0);

  //system_0_burst_7_upstream_read assignment, which is an e_mux
  assign system_0_burst_7_upstream_read = cpu_0_data_master_granted_system_0_burst_7_upstream & cpu_0_data_master_read;

  //system_0_burst_7_upstream_write assignment, which is an e_mux
  assign system_0_burst_7_upstream_write = cpu_0_data_master_granted_system_0_burst_7_upstream & cpu_0_data_master_write;

  //system_0_burst_7_upstream_address mux, which is an e_mux
  assign system_0_burst_7_upstream_address = cpu_0_data_master_address_to_slave;

  //d1_system_0_burst_7_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_7_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_7_upstream_end_xfer <= system_0_burst_7_upstream_end_xfer;
    end


  //system_0_burst_7_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_7_upstream_waits_for_read = system_0_burst_7_upstream_in_a_read_cycle & system_0_burst_7_upstream_waitrequest_from_sa;

  //system_0_burst_7_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_7_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_7_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_7_upstream_in_a_read_cycle;

  //system_0_burst_7_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_7_upstream_waits_for_write = system_0_burst_7_upstream_in_a_write_cycle & system_0_burst_7_upstream_waitrequest_from_sa;

  //system_0_burst_7_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_7_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_7_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_7_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_7_upstream_counter = 0;
  //system_0_burst_7_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_7_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_7_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_7_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_7_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_7_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_7_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_7/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_7_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_7/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_7_downstream_arbitrator (
                                                // inputs:
                                                 clk,
                                                 d1_epcs_controller_epcs_control_port_end_xfer,
                                                 epcs_controller_epcs_control_port_readdata_from_sa,
                                                 reset_n,
                                                 system_0_burst_7_downstream_address,
                                                 system_0_burst_7_downstream_burstcount,
                                                 system_0_burst_7_downstream_byteenable,
                                                 system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port,
                                                 system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port,
                                                 system_0_burst_7_downstream_read,
                                                 system_0_burst_7_downstream_read_data_valid_epcs_controller_epcs_control_port,
                                                 system_0_burst_7_downstream_requests_epcs_controller_epcs_control_port,
                                                 system_0_burst_7_downstream_write,
                                                 system_0_burst_7_downstream_writedata,

                                                // outputs:
                                                 system_0_burst_7_downstream_address_to_slave,
                                                 system_0_burst_7_downstream_latency_counter,
                                                 system_0_burst_7_downstream_readdata,
                                                 system_0_burst_7_downstream_readdatavalid,
                                                 system_0_burst_7_downstream_reset_n,
                                                 system_0_burst_7_downstream_waitrequest
                                              )
;

  output  [ 10: 0] system_0_burst_7_downstream_address_to_slave;
  output           system_0_burst_7_downstream_latency_counter;
  output  [ 31: 0] system_0_burst_7_downstream_readdata;
  output           system_0_burst_7_downstream_readdatavalid;
  output           system_0_burst_7_downstream_reset_n;
  output           system_0_burst_7_downstream_waitrequest;
  input            clk;
  input            d1_epcs_controller_epcs_control_port_end_xfer;
  input   [ 31: 0] epcs_controller_epcs_control_port_readdata_from_sa;
  input            reset_n;
  input   [ 10: 0] system_0_burst_7_downstream_address;
  input            system_0_burst_7_downstream_burstcount;
  input   [  3: 0] system_0_burst_7_downstream_byteenable;
  input            system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port;
  input            system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port;
  input            system_0_burst_7_downstream_read;
  input            system_0_burst_7_downstream_read_data_valid_epcs_controller_epcs_control_port;
  input            system_0_burst_7_downstream_requests_epcs_controller_epcs_control_port;
  input            system_0_burst_7_downstream_write;
  input   [ 31: 0] system_0_burst_7_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             latency_load_value;
  wire             p1_system_0_burst_7_downstream_latency_counter;
  wire             pre_flush_system_0_burst_7_downstream_readdatavalid;
  wire             r_0;
  reg     [ 10: 0] system_0_burst_7_downstream_address_last_time;
  wire    [ 10: 0] system_0_burst_7_downstream_address_to_slave;
  reg              system_0_burst_7_downstream_burstcount_last_time;
  reg     [  3: 0] system_0_burst_7_downstream_byteenable_last_time;
  wire             system_0_burst_7_downstream_is_granted_some_slave;
  reg              system_0_burst_7_downstream_latency_counter;
  reg              system_0_burst_7_downstream_read_but_no_slave_selected;
  reg              system_0_burst_7_downstream_read_last_time;
  wire    [ 31: 0] system_0_burst_7_downstream_readdata;
  wire             system_0_burst_7_downstream_readdatavalid;
  wire             system_0_burst_7_downstream_reset_n;
  wire             system_0_burst_7_downstream_run;
  wire             system_0_burst_7_downstream_waitrequest;
  reg              system_0_burst_7_downstream_write_last_time;
  reg     [ 31: 0] system_0_burst_7_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port | ~system_0_burst_7_downstream_requests_epcs_controller_epcs_control_port) & (system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port | ~system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port) & ((~system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port | ~(system_0_burst_7_downstream_read | system_0_burst_7_downstream_write) | (1 & ~d1_epcs_controller_epcs_control_port_end_xfer & (system_0_burst_7_downstream_read | system_0_burst_7_downstream_write)))) & ((~system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port | ~(system_0_burst_7_downstream_read | system_0_burst_7_downstream_write) | (1 & ~d1_epcs_controller_epcs_control_port_end_xfer & (system_0_burst_7_downstream_read | system_0_burst_7_downstream_write))));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_7_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_7_downstream_address_to_slave = system_0_burst_7_downstream_address;

  //system_0_burst_7_downstream_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_7_downstream_read_but_no_slave_selected <= 0;
      else 
        system_0_burst_7_downstream_read_but_no_slave_selected <= system_0_burst_7_downstream_read & system_0_burst_7_downstream_run & ~system_0_burst_7_downstream_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign system_0_burst_7_downstream_is_granted_some_slave = system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_7_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_7_downstream_readdatavalid = system_0_burst_7_downstream_read_but_no_slave_selected |
    pre_flush_system_0_burst_7_downstream_readdatavalid |
    system_0_burst_7_downstream_read_data_valid_epcs_controller_epcs_control_port;

  //system_0_burst_7/downstream readdata mux, which is an e_mux
  assign system_0_burst_7_downstream_readdata = epcs_controller_epcs_control_port_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_7_downstream_waitrequest = ~system_0_burst_7_downstream_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_7_downstream_latency_counter <= 0;
      else 
        system_0_burst_7_downstream_latency_counter <= p1_system_0_burst_7_downstream_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_system_0_burst_7_downstream_latency_counter = ((system_0_burst_7_downstream_run & system_0_burst_7_downstream_read))? latency_load_value :
    (system_0_burst_7_downstream_latency_counter)? system_0_burst_7_downstream_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = 0;

  //system_0_burst_7_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_7_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_7_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_7_downstream_address_last_time <= 0;
      else 
        system_0_burst_7_downstream_address_last_time <= system_0_burst_7_downstream_address;
    end


  //system_0_burst_7/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_7_downstream_waitrequest & (system_0_burst_7_downstream_read | system_0_burst_7_downstream_write);
    end


  //system_0_burst_7_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_7_downstream_address != system_0_burst_7_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_7_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_7_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_7_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_7_downstream_burstcount_last_time <= system_0_burst_7_downstream_burstcount;
    end


  //system_0_burst_7_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_7_downstream_burstcount != system_0_burst_7_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_7_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_7_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_7_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_7_downstream_byteenable_last_time <= system_0_burst_7_downstream_byteenable;
    end


  //system_0_burst_7_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_7_downstream_byteenable != system_0_burst_7_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_7_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_7_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_7_downstream_read_last_time <= 0;
      else 
        system_0_burst_7_downstream_read_last_time <= system_0_burst_7_downstream_read;
    end


  //system_0_burst_7_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_7_downstream_read != system_0_burst_7_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_7_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_7_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_7_downstream_write_last_time <= 0;
      else 
        system_0_burst_7_downstream_write_last_time <= system_0_burst_7_downstream_write;
    end


  //system_0_burst_7_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_7_downstream_write != system_0_burst_7_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_7_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_7_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_7_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_7_downstream_writedata_last_time <= system_0_burst_7_downstream_writedata;
    end


  //system_0_burst_7_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_7_downstream_writedata != system_0_burst_7_downstream_writedata_last_time) & system_0_burst_7_downstream_write)
        begin
          $write("%0d ns: system_0_burst_7_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_8_upstream_module (
                                                              // inputs:
                                                               clear_fifo,
                                                               clk,
                                                               data_in,
                                                               read,
                                                               reset_n,
                                                               sync_reset,
                                                               write,

                                                              // outputs:
                                                               data_out,
                                                               empty,
                                                               fifo_contains_ones_n,
                                                               full
                                                            )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_8_upstream_module (
                                                                            // inputs:
                                                                             clear_fifo,
                                                                             clk,
                                                                             data_in,
                                                                             read,
                                                                             reset_n,
                                                                             sync_reset,
                                                                             write,

                                                                            // outputs:
                                                                             data_out,
                                                                             empty,
                                                                             fifo_contains_ones_n,
                                                                             full
                                                                          )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_8_upstream_arbitrator (
                                              // inputs:
                                               clk,
                                               cpu_0_data_master_address_to_slave,
                                               cpu_0_data_master_burstcount,
                                               cpu_0_data_master_byteenable,
                                               cpu_0_data_master_debugaccess,
                                               cpu_0_data_master_latency_counter,
                                               cpu_0_data_master_read,
                                               cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                               cpu_0_data_master_write,
                                               cpu_0_data_master_writedata,
                                               reset_n,
                                               system_0_burst_8_upstream_readdata,
                                               system_0_burst_8_upstream_readdatavalid,
                                               system_0_burst_8_upstream_waitrequest,

                                              // outputs:
                                               cpu_0_data_master_granted_system_0_burst_8_upstream,
                                               cpu_0_data_master_qualified_request_system_0_burst_8_upstream,
                                               cpu_0_data_master_read_data_valid_system_0_burst_8_upstream,
                                               cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                               cpu_0_data_master_requests_system_0_burst_8_upstream,
                                               d1_system_0_burst_8_upstream_end_xfer,
                                               system_0_burst_8_upstream_address,
                                               system_0_burst_8_upstream_burstcount,
                                               system_0_burst_8_upstream_byteaddress,
                                               system_0_burst_8_upstream_byteenable,
                                               system_0_burst_8_upstream_debugaccess,
                                               system_0_burst_8_upstream_read,
                                               system_0_burst_8_upstream_readdata_from_sa,
                                               system_0_burst_8_upstream_waitrequest_from_sa,
                                               system_0_burst_8_upstream_write,
                                               system_0_burst_8_upstream_writedata
                                            )
;

  output           cpu_0_data_master_granted_system_0_burst_8_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_8_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_8_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_8_upstream;
  output           d1_system_0_burst_8_upstream_end_xfer;
  output  [  2: 0] system_0_burst_8_upstream_address;
  output  [  3: 0] system_0_burst_8_upstream_burstcount;
  output  [  4: 0] system_0_burst_8_upstream_byteaddress;
  output  [  3: 0] system_0_burst_8_upstream_byteenable;
  output           system_0_burst_8_upstream_debugaccess;
  output           system_0_burst_8_upstream_read;
  output  [ 31: 0] system_0_burst_8_upstream_readdata_from_sa;
  output           system_0_burst_8_upstream_waitrequest_from_sa;
  output           system_0_burst_8_upstream_write;
  output  [ 31: 0] system_0_burst_8_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [ 31: 0] system_0_burst_8_upstream_readdata;
  input            system_0_burst_8_upstream_readdatavalid;
  input            system_0_burst_8_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_8_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_8_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_8_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_8_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_8_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_8_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_8_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_8_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_8_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_8_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_8_upstream_from_cpu_0_data_master;
  wire    [  2: 0] system_0_burst_8_upstream_address;
  wire             system_0_burst_8_upstream_allgrants;
  wire             system_0_burst_8_upstream_allow_new_arb_cycle;
  wire             system_0_burst_8_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_8_upstream_any_continuerequest;
  wire             system_0_burst_8_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_8_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_8_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_8_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_8_upstream_bbt_burstcounter;
  wire             system_0_burst_8_upstream_beginbursttransfer_internal;
  wire             system_0_burst_8_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_8_upstream_burstcount;
  wire             system_0_burst_8_upstream_burstcount_fifo_empty;
  wire    [  4: 0] system_0_burst_8_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_8_upstream_byteenable;
  reg     [  3: 0] system_0_burst_8_upstream_current_burst;
  wire    [  3: 0] system_0_burst_8_upstream_current_burst_minus_one;
  wire             system_0_burst_8_upstream_debugaccess;
  wire             system_0_burst_8_upstream_end_xfer;
  wire             system_0_burst_8_upstream_firsttransfer;
  wire             system_0_burst_8_upstream_grant_vector;
  wire             system_0_burst_8_upstream_in_a_read_cycle;
  wire             system_0_burst_8_upstream_in_a_write_cycle;
  reg              system_0_burst_8_upstream_load_fifo;
  wire             system_0_burst_8_upstream_master_qreq_vector;
  wire             system_0_burst_8_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_8_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_8_upstream_next_burst_count;
  wire             system_0_burst_8_upstream_non_bursting_master_requests;
  wire             system_0_burst_8_upstream_read;
  wire    [ 31: 0] system_0_burst_8_upstream_readdata_from_sa;
  wire             system_0_burst_8_upstream_readdatavalid_from_sa;
  reg              system_0_burst_8_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_8_upstream_selected_burstcount;
  reg              system_0_burst_8_upstream_slavearbiterlockenable;
  wire             system_0_burst_8_upstream_slavearbiterlockenable2;
  wire             system_0_burst_8_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_8_upstream_transaction_burst_count;
  wire             system_0_burst_8_upstream_unreg_firsttransfer;
  wire             system_0_burst_8_upstream_waitrequest_from_sa;
  wire             system_0_burst_8_upstream_waits_for_read;
  wire             system_0_burst_8_upstream_waits_for_write;
  wire             system_0_burst_8_upstream_write;
  wire    [ 31: 0] system_0_burst_8_upstream_writedata;
  wire             wait_for_system_0_burst_8_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_8_upstream_end_xfer;
    end


  assign system_0_burst_8_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_8_upstream));
  //assign system_0_burst_8_upstream_readdatavalid_from_sa = system_0_burst_8_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_8_upstream_readdatavalid_from_sa = system_0_burst_8_upstream_readdatavalid;

  //assign system_0_burst_8_upstream_readdata_from_sa = system_0_burst_8_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_8_upstream_readdata_from_sa = system_0_burst_8_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_8_upstream = ({cpu_0_data_master_address_to_slave[24 : 3] , 3'b0} == 25'h190a1d0) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_8_upstream_waitrequest_from_sa = system_0_burst_8_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_8_upstream_waitrequest_from_sa = system_0_burst_8_upstream_waitrequest;

  //system_0_burst_8_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_8_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_8_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_8_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_8_upstream_non_bursting_master_requests = 0;

  //system_0_burst_8_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_8_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_8_upstream;

  //system_0_burst_8_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_8_upstream_arb_share_counter_next_value = system_0_burst_8_upstream_firsttransfer ? (system_0_burst_8_upstream_arb_share_set_values - 1) : |system_0_burst_8_upstream_arb_share_counter ? (system_0_burst_8_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_8_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_8_upstream_allgrants = |system_0_burst_8_upstream_grant_vector;

  //system_0_burst_8_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_8_upstream_end_xfer = ~(system_0_burst_8_upstream_waits_for_read | system_0_burst_8_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_8_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_8_upstream = system_0_burst_8_upstream_end_xfer & (~system_0_burst_8_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_8_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_8_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_8_upstream & system_0_burst_8_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_8_upstream & ~system_0_burst_8_upstream_non_bursting_master_requests);

  //system_0_burst_8_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_8_upstream_arb_share_counter <= 0;
      else if (system_0_burst_8_upstream_arb_counter_enable)
          system_0_burst_8_upstream_arb_share_counter <= system_0_burst_8_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_8_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_8_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_8_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_8_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_8_upstream & ~system_0_burst_8_upstream_non_bursting_master_requests))
          system_0_burst_8_upstream_slavearbiterlockenable <= |system_0_burst_8_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_8/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_8_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_8_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_8_upstream_slavearbiterlockenable2 = |system_0_burst_8_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_8/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_8_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_8_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_8_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_8_upstream = cpu_0_data_master_requests_system_0_burst_8_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register))));
  //unique name for system_0_burst_8_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_8_upstream_move_on_to_next_transaction = system_0_burst_8_upstream_this_cycle_is_the_last_burst & system_0_burst_8_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_8_upstream, which is an e_mux
  assign system_0_burst_8_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_8_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_8_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_8_upstream_module burstcount_fifo_for_system_0_burst_8_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_8_upstream_selected_burstcount),
      .data_out             (system_0_burst_8_upstream_transaction_burst_count),
      .empty                (system_0_burst_8_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_8_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_8_upstream_waits_for_read & system_0_burst_8_upstream_load_fifo & ~(system_0_burst_8_upstream_this_cycle_is_the_last_burst & system_0_burst_8_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_8_upstream current burst minus one, which is an e_assign
  assign system_0_burst_8_upstream_current_burst_minus_one = system_0_burst_8_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_8_upstream, which is an e_mux
  assign system_0_burst_8_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_8_upstream_waits_for_read) & ~system_0_burst_8_upstream_load_fifo))? system_0_burst_8_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_8_upstream_waits_for_read & system_0_burst_8_upstream_this_cycle_is_the_last_burst & system_0_burst_8_upstream_burstcount_fifo_empty))? system_0_burst_8_upstream_selected_burstcount :
    (system_0_burst_8_upstream_this_cycle_is_the_last_burst)? system_0_burst_8_upstream_transaction_burst_count :
    system_0_burst_8_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_8_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_8_upstream_current_burst <= 0;
      else if (system_0_burst_8_upstream_readdatavalid_from_sa | (~system_0_burst_8_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_8_upstream_waits_for_read)))
          system_0_burst_8_upstream_current_burst <= system_0_burst_8_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_8_upstream_load_fifo = (~system_0_burst_8_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_8_upstream_waits_for_read) & system_0_burst_8_upstream_load_fifo))? 1 :
    ~system_0_burst_8_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_8_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_8_upstream_waits_for_read) & ~system_0_burst_8_upstream_load_fifo | system_0_burst_8_upstream_this_cycle_is_the_last_burst)
          system_0_burst_8_upstream_load_fifo <= p0_system_0_burst_8_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_8_upstream, which is an e_assign
  assign system_0_burst_8_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_8_upstream_current_burst_minus_one) & system_0_burst_8_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_8_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_8_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_8_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_8_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_8_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_8_upstream),
      .full                 (),
      .read                 (system_0_burst_8_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_8_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_8_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_8_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_8_upstream = system_0_burst_8_upstream_readdatavalid_from_sa;

  //system_0_burst_8_upstream_writedata mux, which is an e_mux
  assign system_0_burst_8_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_8/upstream, which is an e_mux
  assign system_0_burst_8_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_8_upstream = cpu_0_data_master_qualified_request_system_0_burst_8_upstream;

  //cpu_0/data_master saved-grant system_0_burst_8/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_8_upstream = cpu_0_data_master_requests_system_0_burst_8_upstream;

  //allow new arb cycle for system_0_burst_8/upstream, which is an e_assign
  assign system_0_burst_8_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_8_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_8_upstream_master_qreq_vector = 1;

  //system_0_burst_8_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_8_upstream_firsttransfer = system_0_burst_8_upstream_begins_xfer ? system_0_burst_8_upstream_unreg_firsttransfer : system_0_burst_8_upstream_reg_firsttransfer;

  //system_0_burst_8_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_8_upstream_unreg_firsttransfer = ~(system_0_burst_8_upstream_slavearbiterlockenable & system_0_burst_8_upstream_any_continuerequest);

  //system_0_burst_8_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_8_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_8_upstream_begins_xfer)
          system_0_burst_8_upstream_reg_firsttransfer <= system_0_burst_8_upstream_unreg_firsttransfer;
    end


  //system_0_burst_8_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_8_upstream_next_bbt_burstcount = ((((system_0_burst_8_upstream_write) && (system_0_burst_8_upstream_bbt_burstcounter == 0))))? (system_0_burst_8_upstream_burstcount - 1) :
    ((((system_0_burst_8_upstream_read) && (system_0_burst_8_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_8_upstream_bbt_burstcounter - 1);

  //system_0_burst_8_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_8_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_8_upstream_begins_xfer)
          system_0_burst_8_upstream_bbt_burstcounter <= system_0_burst_8_upstream_next_bbt_burstcount;
    end


  //system_0_burst_8_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_8_upstream_beginbursttransfer_internal = system_0_burst_8_upstream_begins_xfer & (system_0_burst_8_upstream_bbt_burstcounter == 0);

  //system_0_burst_8_upstream_read assignment, which is an e_mux
  assign system_0_burst_8_upstream_read = cpu_0_data_master_granted_system_0_burst_8_upstream & cpu_0_data_master_read;

  //system_0_burst_8_upstream_write assignment, which is an e_mux
  assign system_0_burst_8_upstream_write = cpu_0_data_master_granted_system_0_burst_8_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_8_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_8_upstream_address mux, which is an e_mux
  assign system_0_burst_8_upstream_address = shifted_address_to_system_0_burst_8_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_8_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_8_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_8_upstream_end_xfer <= system_0_burst_8_upstream_end_xfer;
    end


  //system_0_burst_8_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_8_upstream_waits_for_read = system_0_burst_8_upstream_in_a_read_cycle & system_0_burst_8_upstream_waitrequest_from_sa;

  //system_0_burst_8_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_8_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_8_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_8_upstream_in_a_read_cycle;

  //system_0_burst_8_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_8_upstream_waits_for_write = system_0_burst_8_upstream_in_a_write_cycle & system_0_burst_8_upstream_waitrequest_from_sa;

  //system_0_burst_8_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_8_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_8_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_8_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_8_upstream_counter = 0;
  //system_0_burst_8_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_8_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_8_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_8_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_8_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_8_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_8_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_8/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_8_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_8/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_8_downstream_arbitrator (
                                                // inputs:
                                                 clk,
                                                 d1_jtag_uart_0_avalon_jtag_slave_end_xfer,
                                                 jtag_uart_0_avalon_jtag_slave_readdata_from_sa,
                                                 jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa,
                                                 reset_n,
                                                 system_0_burst_8_downstream_address,
                                                 system_0_burst_8_downstream_burstcount,
                                                 system_0_burst_8_downstream_byteenable,
                                                 system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave,
                                                 system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave,
                                                 system_0_burst_8_downstream_read,
                                                 system_0_burst_8_downstream_read_data_valid_jtag_uart_0_avalon_jtag_slave,
                                                 system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave,
                                                 system_0_burst_8_downstream_write,
                                                 system_0_burst_8_downstream_writedata,

                                                // outputs:
                                                 system_0_burst_8_downstream_address_to_slave,
                                                 system_0_burst_8_downstream_latency_counter,
                                                 system_0_burst_8_downstream_readdata,
                                                 system_0_burst_8_downstream_readdatavalid,
                                                 system_0_burst_8_downstream_reset_n,
                                                 system_0_burst_8_downstream_waitrequest
                                              )
;

  output  [  2: 0] system_0_burst_8_downstream_address_to_slave;
  output           system_0_burst_8_downstream_latency_counter;
  output  [ 31: 0] system_0_burst_8_downstream_readdata;
  output           system_0_burst_8_downstream_readdatavalid;
  output           system_0_burst_8_downstream_reset_n;
  output           system_0_burst_8_downstream_waitrequest;
  input            clk;
  input            d1_jtag_uart_0_avalon_jtag_slave_end_xfer;
  input   [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
  input            jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
  input            reset_n;
  input   [  2: 0] system_0_burst_8_downstream_address;
  input            system_0_burst_8_downstream_burstcount;
  input   [  3: 0] system_0_burst_8_downstream_byteenable;
  input            system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave;
  input            system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave;
  input            system_0_burst_8_downstream_read;
  input            system_0_burst_8_downstream_read_data_valid_jtag_uart_0_avalon_jtag_slave;
  input            system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave;
  input            system_0_burst_8_downstream_write;
  input   [ 31: 0] system_0_burst_8_downstream_writedata;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_8_downstream_readdatavalid;
  wire             r_0;
  reg     [  2: 0] system_0_burst_8_downstream_address_last_time;
  wire    [  2: 0] system_0_burst_8_downstream_address_to_slave;
  reg              system_0_burst_8_downstream_burstcount_last_time;
  reg     [  3: 0] system_0_burst_8_downstream_byteenable_last_time;
  wire             system_0_burst_8_downstream_latency_counter;
  reg              system_0_burst_8_downstream_read_last_time;
  wire    [ 31: 0] system_0_burst_8_downstream_readdata;
  wire             system_0_burst_8_downstream_readdatavalid;
  wire             system_0_burst_8_downstream_reset_n;
  wire             system_0_burst_8_downstream_run;
  wire             system_0_burst_8_downstream_waitrequest;
  reg              system_0_burst_8_downstream_write_last_time;
  reg     [ 31: 0] system_0_burst_8_downstream_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave | ~system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave) & ((~system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave | ~(system_0_burst_8_downstream_read | system_0_burst_8_downstream_write) | (1 & ~jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa & (system_0_burst_8_downstream_read | system_0_burst_8_downstream_write)))) & ((~system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave | ~(system_0_burst_8_downstream_read | system_0_burst_8_downstream_write) | (1 & ~jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa & (system_0_burst_8_downstream_read | system_0_burst_8_downstream_write))));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_8_downstream_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_8_downstream_address_to_slave = system_0_burst_8_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_8_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_8_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_8_downstream_readdatavalid |
    system_0_burst_8_downstream_read_data_valid_jtag_uart_0_avalon_jtag_slave;

  //system_0_burst_8/downstream readdata mux, which is an e_mux
  assign system_0_burst_8_downstream_readdata = jtag_uart_0_avalon_jtag_slave_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_8_downstream_waitrequest = ~system_0_burst_8_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_8_downstream_latency_counter = 0;

  //system_0_burst_8_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_8_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_8_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_8_downstream_address_last_time <= 0;
      else 
        system_0_burst_8_downstream_address_last_time <= system_0_burst_8_downstream_address;
    end


  //system_0_burst_8/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_8_downstream_waitrequest & (system_0_burst_8_downstream_read | system_0_burst_8_downstream_write);
    end


  //system_0_burst_8_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_8_downstream_address != system_0_burst_8_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_8_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_8_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_8_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_8_downstream_burstcount_last_time <= system_0_burst_8_downstream_burstcount;
    end


  //system_0_burst_8_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_8_downstream_burstcount != system_0_burst_8_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_8_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_8_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_8_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_8_downstream_byteenable_last_time <= system_0_burst_8_downstream_byteenable;
    end


  //system_0_burst_8_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_8_downstream_byteenable != system_0_burst_8_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_8_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_8_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_8_downstream_read_last_time <= 0;
      else 
        system_0_burst_8_downstream_read_last_time <= system_0_burst_8_downstream_read;
    end


  //system_0_burst_8_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_8_downstream_read != system_0_burst_8_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_8_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_8_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_8_downstream_write_last_time <= 0;
      else 
        system_0_burst_8_downstream_write_last_time <= system_0_burst_8_downstream_write;
    end


  //system_0_burst_8_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_8_downstream_write != system_0_burst_8_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_8_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_8_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_8_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_8_downstream_writedata_last_time <= system_0_burst_8_downstream_writedata;
    end


  //system_0_burst_8_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_8_downstream_writedata != system_0_burst_8_downstream_writedata_last_time) & system_0_burst_8_downstream_write)
        begin
          $write("%0d ns: system_0_burst_8_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burstcount_fifo_for_system_0_burst_9_upstream_module (
                                                              // inputs:
                                                               clear_fifo,
                                                               clk,
                                                               data_in,
                                                               read,
                                                               reset_n,
                                                               sync_reset,
                                                               write,

                                                              // outputs:
                                                               data_out,
                                                               empty,
                                                               fifo_contains_ones_n,
                                                               full
                                                            )
;

  output  [  3: 0] data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input   [  3: 0] data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire    [  3: 0] data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire    [  3: 0] p0_stage_0;
  wire             p1_full_1;
  wire    [  3: 0] p1_stage_1;
  reg     [  3: 0] stage_0;
  reg     [  3: 0] stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_9_upstream_module (
                                                                            // inputs:
                                                                             clear_fifo,
                                                                             clk,
                                                                             data_in,
                                                                             read,
                                                                             reset_n,
                                                                             sync_reset,
                                                                             write,

                                                                            // outputs:
                                                                             data_out,
                                                                             empty,
                                                                             fifo_contains_ones_n,
                                                                             full
                                                                          )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  wire             full_2;
  reg     [  2: 0] how_many_ones;
  wire    [  2: 0] one_count_minus_one;
  wire    [  2: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  reg              stage_0;
  reg              stage_1;
  wire    [  2: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_1;
  assign empty = !full_0;
  assign full_2 = 0;
  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    0;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_9_upstream_arbitrator (
                                              // inputs:
                                               clk,
                                               cpu_0_data_master_address_to_slave,
                                               cpu_0_data_master_burstcount,
                                               cpu_0_data_master_byteenable,
                                               cpu_0_data_master_debugaccess,
                                               cpu_0_data_master_latency_counter,
                                               cpu_0_data_master_read,
                                               cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register,
                                               cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register,
                                               cpu_0_data_master_write,
                                               cpu_0_data_master_writedata,
                                               reset_n,
                                               system_0_burst_9_upstream_readdata,
                                               system_0_burst_9_upstream_readdatavalid,
                                               system_0_burst_9_upstream_waitrequest,

                                              // outputs:
                                               cpu_0_data_master_granted_system_0_burst_9_upstream,
                                               cpu_0_data_master_qualified_request_system_0_burst_9_upstream,
                                               cpu_0_data_master_read_data_valid_system_0_burst_9_upstream,
                                               cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register,
                                               cpu_0_data_master_requests_system_0_burst_9_upstream,
                                               d1_system_0_burst_9_upstream_end_xfer,
                                               system_0_burst_9_upstream_address,
                                               system_0_burst_9_upstream_burstcount,
                                               system_0_burst_9_upstream_byteaddress,
                                               system_0_burst_9_upstream_byteenable,
                                               system_0_burst_9_upstream_debugaccess,
                                               system_0_burst_9_upstream_read,
                                               system_0_burst_9_upstream_readdata_from_sa,
                                               system_0_burst_9_upstream_waitrequest_from_sa,
                                               system_0_burst_9_upstream_write,
                                               system_0_burst_9_upstream_writedata
                                            )
;

  output           cpu_0_data_master_granted_system_0_burst_9_upstream;
  output           cpu_0_data_master_qualified_request_system_0_burst_9_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_9_upstream;
  output           cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  output           cpu_0_data_master_requests_system_0_burst_9_upstream;
  output           d1_system_0_burst_9_upstream_end_xfer;
  output  [  3: 0] system_0_burst_9_upstream_address;
  output  [  3: 0] system_0_burst_9_upstream_burstcount;
  output  [  4: 0] system_0_burst_9_upstream_byteaddress;
  output  [  1: 0] system_0_burst_9_upstream_byteenable;
  output           system_0_burst_9_upstream_debugaccess;
  output           system_0_burst_9_upstream_read;
  output  [ 15: 0] system_0_burst_9_upstream_readdata_from_sa;
  output           system_0_burst_9_upstream_waitrequest_from_sa;
  output           system_0_burst_9_upstream_write;
  output  [ 15: 0] system_0_burst_9_upstream_writedata;
  input            clk;
  input   [ 24: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_burstcount;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_latency_counter;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  input            cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;
  input   [ 15: 0] system_0_burst_9_upstream_readdata;
  input            system_0_burst_9_upstream_readdatavalid;
  input            system_0_burst_9_upstream_waitrequest;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_system_0_burst_9_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_9_upstream;
  wire             cpu_0_data_master_rdv_fifo_empty_system_0_burst_9_upstream;
  wire             cpu_0_data_master_rdv_fifo_output_from_system_0_burst_9_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_9_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  wire             cpu_0_data_master_requests_system_0_burst_9_upstream;
  wire             cpu_0_data_master_saved_grant_system_0_burst_9_upstream;
  reg              d1_reasons_to_wait;
  reg              d1_system_0_burst_9_upstream_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_burst_9_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_system_0_burst_9_upstream_load_fifo;
  wire    [ 24: 0] shifted_address_to_system_0_burst_9_upstream_from_cpu_0_data_master;
  wire    [  3: 0] system_0_burst_9_upstream_address;
  wire             system_0_burst_9_upstream_allgrants;
  wire             system_0_burst_9_upstream_allow_new_arb_cycle;
  wire             system_0_burst_9_upstream_any_bursting_master_saved_grant;
  wire             system_0_burst_9_upstream_any_continuerequest;
  wire             system_0_burst_9_upstream_arb_counter_enable;
  reg     [  7: 0] system_0_burst_9_upstream_arb_share_counter;
  wire    [  7: 0] system_0_burst_9_upstream_arb_share_counter_next_value;
  wire    [  7: 0] system_0_burst_9_upstream_arb_share_set_values;
  reg     [  2: 0] system_0_burst_9_upstream_bbt_burstcounter;
  wire             system_0_burst_9_upstream_beginbursttransfer_internal;
  wire             system_0_burst_9_upstream_begins_xfer;
  wire    [  3: 0] system_0_burst_9_upstream_burstcount;
  wire             system_0_burst_9_upstream_burstcount_fifo_empty;
  wire    [  4: 0] system_0_burst_9_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_9_upstream_byteenable;
  reg     [  3: 0] system_0_burst_9_upstream_current_burst;
  wire    [  3: 0] system_0_burst_9_upstream_current_burst_minus_one;
  wire             system_0_burst_9_upstream_debugaccess;
  wire             system_0_burst_9_upstream_end_xfer;
  wire             system_0_burst_9_upstream_firsttransfer;
  wire             system_0_burst_9_upstream_grant_vector;
  wire             system_0_burst_9_upstream_in_a_read_cycle;
  wire             system_0_burst_9_upstream_in_a_write_cycle;
  reg              system_0_burst_9_upstream_load_fifo;
  wire             system_0_burst_9_upstream_master_qreq_vector;
  wire             system_0_burst_9_upstream_move_on_to_next_transaction;
  wire    [  2: 0] system_0_burst_9_upstream_next_bbt_burstcount;
  wire    [  3: 0] system_0_burst_9_upstream_next_burst_count;
  wire             system_0_burst_9_upstream_non_bursting_master_requests;
  wire             system_0_burst_9_upstream_read;
  wire    [ 15: 0] system_0_burst_9_upstream_readdata_from_sa;
  wire             system_0_burst_9_upstream_readdatavalid_from_sa;
  reg              system_0_burst_9_upstream_reg_firsttransfer;
  wire    [  3: 0] system_0_burst_9_upstream_selected_burstcount;
  reg              system_0_burst_9_upstream_slavearbiterlockenable;
  wire             system_0_burst_9_upstream_slavearbiterlockenable2;
  wire             system_0_burst_9_upstream_this_cycle_is_the_last_burst;
  wire    [  3: 0] system_0_burst_9_upstream_transaction_burst_count;
  wire             system_0_burst_9_upstream_unreg_firsttransfer;
  wire             system_0_burst_9_upstream_waitrequest_from_sa;
  wire             system_0_burst_9_upstream_waits_for_read;
  wire             system_0_burst_9_upstream_waits_for_write;
  wire             system_0_burst_9_upstream_write;
  wire    [ 15: 0] system_0_burst_9_upstream_writedata;
  wire             wait_for_system_0_burst_9_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_burst_9_upstream_end_xfer;
    end


  assign system_0_burst_9_upstream_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_system_0_burst_9_upstream));
  //assign system_0_burst_9_upstream_readdatavalid_from_sa = system_0_burst_9_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_9_upstream_readdatavalid_from_sa = system_0_burst_9_upstream_readdatavalid;

  //assign system_0_burst_9_upstream_readdata_from_sa = system_0_burst_9_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_9_upstream_readdata_from_sa = system_0_burst_9_upstream_readdata;

  assign cpu_0_data_master_requests_system_0_burst_9_upstream = ({cpu_0_data_master_address_to_slave[24 : 5] , 5'b0} == 25'h190a020) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign system_0_burst_9_upstream_waitrequest_from_sa = system_0_burst_9_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_burst_9_upstream_waitrequest_from_sa = system_0_burst_9_upstream_waitrequest;

  //system_0_burst_9_upstream_arb_share_counter set values, which is an e_mux
  assign system_0_burst_9_upstream_arb_share_set_values = (cpu_0_data_master_granted_system_0_burst_9_upstream)? (((cpu_0_data_master_write) ? cpu_0_data_master_burstcount : 1)) :
    1;

  //system_0_burst_9_upstream_non_bursting_master_requests mux, which is an e_mux
  assign system_0_burst_9_upstream_non_bursting_master_requests = 0;

  //system_0_burst_9_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_burst_9_upstream_any_bursting_master_saved_grant = cpu_0_data_master_saved_grant_system_0_burst_9_upstream;

  //system_0_burst_9_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_burst_9_upstream_arb_share_counter_next_value = system_0_burst_9_upstream_firsttransfer ? (system_0_burst_9_upstream_arb_share_set_values - 1) : |system_0_burst_9_upstream_arb_share_counter ? (system_0_burst_9_upstream_arb_share_counter - 1) : 0;

  //system_0_burst_9_upstream_allgrants all slave grants, which is an e_mux
  assign system_0_burst_9_upstream_allgrants = |system_0_burst_9_upstream_grant_vector;

  //system_0_burst_9_upstream_end_xfer assignment, which is an e_assign
  assign system_0_burst_9_upstream_end_xfer = ~(system_0_burst_9_upstream_waits_for_read | system_0_burst_9_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_burst_9_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_burst_9_upstream = system_0_burst_9_upstream_end_xfer & (~system_0_burst_9_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_burst_9_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_burst_9_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_burst_9_upstream & system_0_burst_9_upstream_allgrants) | (end_xfer_arb_share_counter_term_system_0_burst_9_upstream & ~system_0_burst_9_upstream_non_bursting_master_requests);

  //system_0_burst_9_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_9_upstream_arb_share_counter <= 0;
      else if (system_0_burst_9_upstream_arb_counter_enable)
          system_0_burst_9_upstream_arb_share_counter <= system_0_burst_9_upstream_arb_share_counter_next_value;
    end


  //system_0_burst_9_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_9_upstream_slavearbiterlockenable <= 0;
      else if ((|system_0_burst_9_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_burst_9_upstream) | (end_xfer_arb_share_counter_term_system_0_burst_9_upstream & ~system_0_burst_9_upstream_non_bursting_master_requests))
          system_0_burst_9_upstream_slavearbiterlockenable <= |system_0_burst_9_upstream_arb_share_counter_next_value;
    end


  //cpu_0/data_master system_0_burst_9/upstream arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = system_0_burst_9_upstream_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //system_0_burst_9_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_burst_9_upstream_slavearbiterlockenable2 = |system_0_burst_9_upstream_arb_share_counter_next_value;

  //cpu_0/data_master system_0_burst_9/upstream arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = system_0_burst_9_upstream_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //system_0_burst_9_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_burst_9_upstream_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_system_0_burst_9_upstream = cpu_0_data_master_requests_system_0_burst_9_upstream & ~((cpu_0_data_master_read & ((cpu_0_data_master_latency_counter != 0) | (1 < cpu_0_data_master_latency_counter) | (|cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register) | (|cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register))));
  //unique name for system_0_burst_9_upstream_move_on_to_next_transaction, which is an e_assign
  assign system_0_burst_9_upstream_move_on_to_next_transaction = system_0_burst_9_upstream_this_cycle_is_the_last_burst & system_0_burst_9_upstream_load_fifo;

  //the currently selected burstcount for system_0_burst_9_upstream, which is an e_mux
  assign system_0_burst_9_upstream_selected_burstcount = (cpu_0_data_master_granted_system_0_burst_9_upstream)? cpu_0_data_master_burstcount :
    1;

  //burstcount_fifo_for_system_0_burst_9_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_system_0_burst_9_upstream_module burstcount_fifo_for_system_0_burst_9_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (system_0_burst_9_upstream_selected_burstcount),
      .data_out             (system_0_burst_9_upstream_transaction_burst_count),
      .empty                (system_0_burst_9_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (system_0_burst_9_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_9_upstream_waits_for_read & system_0_burst_9_upstream_load_fifo & ~(system_0_burst_9_upstream_this_cycle_is_the_last_burst & system_0_burst_9_upstream_burstcount_fifo_empty))
    );

  //system_0_burst_9_upstream current burst minus one, which is an e_assign
  assign system_0_burst_9_upstream_current_burst_minus_one = system_0_burst_9_upstream_current_burst - 1;

  //what to load in current_burst, for system_0_burst_9_upstream, which is an e_mux
  assign system_0_burst_9_upstream_next_burst_count = (((in_a_read_cycle & ~system_0_burst_9_upstream_waits_for_read) & ~system_0_burst_9_upstream_load_fifo))? system_0_burst_9_upstream_selected_burstcount :
    ((in_a_read_cycle & ~system_0_burst_9_upstream_waits_for_read & system_0_burst_9_upstream_this_cycle_is_the_last_burst & system_0_burst_9_upstream_burstcount_fifo_empty))? system_0_burst_9_upstream_selected_burstcount :
    (system_0_burst_9_upstream_this_cycle_is_the_last_burst)? system_0_burst_9_upstream_transaction_burst_count :
    system_0_burst_9_upstream_current_burst_minus_one;

  //the current burst count for system_0_burst_9_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_9_upstream_current_burst <= 0;
      else if (system_0_burst_9_upstream_readdatavalid_from_sa | (~system_0_burst_9_upstream_load_fifo & (in_a_read_cycle & ~system_0_burst_9_upstream_waits_for_read)))
          system_0_burst_9_upstream_current_burst <= system_0_burst_9_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_system_0_burst_9_upstream_load_fifo = (~system_0_burst_9_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~system_0_burst_9_upstream_waits_for_read) & system_0_burst_9_upstream_load_fifo))? 1 :
    ~system_0_burst_9_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_9_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~system_0_burst_9_upstream_waits_for_read) & ~system_0_burst_9_upstream_load_fifo | system_0_burst_9_upstream_this_cycle_is_the_last_burst)
          system_0_burst_9_upstream_load_fifo <= p0_system_0_burst_9_upstream_load_fifo;
    end


  //the last cycle in the burst for system_0_burst_9_upstream, which is an e_assign
  assign system_0_burst_9_upstream_this_cycle_is_the_last_burst = ~(|system_0_burst_9_upstream_current_burst_minus_one) & system_0_burst_9_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_0_data_master_to_system_0_burst_9_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_0_data_master_to_system_0_burst_9_upstream_module rdv_fifo_for_cpu_0_data_master_to_system_0_burst_9_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_0_data_master_granted_system_0_burst_9_upstream),
      .data_out             (cpu_0_data_master_rdv_fifo_output_from_system_0_burst_9_upstream),
      .empty                (),
      .fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_system_0_burst_9_upstream),
      .full                 (),
      .read                 (system_0_burst_9_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~system_0_burst_9_upstream_waits_for_read)
    );

  assign cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register = ~cpu_0_data_master_rdv_fifo_empty_system_0_burst_9_upstream;
  //local readdatavalid cpu_0_data_master_read_data_valid_system_0_burst_9_upstream, which is an e_mux
  assign cpu_0_data_master_read_data_valid_system_0_burst_9_upstream = system_0_burst_9_upstream_readdatavalid_from_sa;

  //system_0_burst_9_upstream_writedata mux, which is an e_mux
  assign system_0_burst_9_upstream_writedata = cpu_0_data_master_writedata;

  //byteaddress mux for system_0_burst_9/upstream, which is an e_mux
  assign system_0_burst_9_upstream_byteaddress = cpu_0_data_master_address_to_slave;

  //master is always granted when requested
  assign cpu_0_data_master_granted_system_0_burst_9_upstream = cpu_0_data_master_qualified_request_system_0_burst_9_upstream;

  //cpu_0/data_master saved-grant system_0_burst_9/upstream, which is an e_assign
  assign cpu_0_data_master_saved_grant_system_0_burst_9_upstream = cpu_0_data_master_requests_system_0_burst_9_upstream;

  //allow new arb cycle for system_0_burst_9/upstream, which is an e_assign
  assign system_0_burst_9_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_burst_9_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_burst_9_upstream_master_qreq_vector = 1;

  //system_0_burst_9_upstream_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_9_upstream_firsttransfer = system_0_burst_9_upstream_begins_xfer ? system_0_burst_9_upstream_unreg_firsttransfer : system_0_burst_9_upstream_reg_firsttransfer;

  //system_0_burst_9_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_burst_9_upstream_unreg_firsttransfer = ~(system_0_burst_9_upstream_slavearbiterlockenable & system_0_burst_9_upstream_any_continuerequest);

  //system_0_burst_9_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_9_upstream_reg_firsttransfer <= 1'b1;
      else if (system_0_burst_9_upstream_begins_xfer)
          system_0_burst_9_upstream_reg_firsttransfer <= system_0_burst_9_upstream_unreg_firsttransfer;
    end


  //system_0_burst_9_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign system_0_burst_9_upstream_next_bbt_burstcount = ((((system_0_burst_9_upstream_write) && (system_0_burst_9_upstream_bbt_burstcounter == 0))))? (system_0_burst_9_upstream_burstcount - 1) :
    ((((system_0_burst_9_upstream_read) && (system_0_burst_9_upstream_bbt_burstcounter == 0))))? 0 :
    (system_0_burst_9_upstream_bbt_burstcounter - 1);

  //system_0_burst_9_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_9_upstream_bbt_burstcounter <= 0;
      else if (system_0_burst_9_upstream_begins_xfer)
          system_0_burst_9_upstream_bbt_burstcounter <= system_0_burst_9_upstream_next_bbt_burstcount;
    end


  //system_0_burst_9_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_burst_9_upstream_beginbursttransfer_internal = system_0_burst_9_upstream_begins_xfer & (system_0_burst_9_upstream_bbt_burstcounter == 0);

  //system_0_burst_9_upstream_read assignment, which is an e_mux
  assign system_0_burst_9_upstream_read = cpu_0_data_master_granted_system_0_burst_9_upstream & cpu_0_data_master_read;

  //system_0_burst_9_upstream_write assignment, which is an e_mux
  assign system_0_burst_9_upstream_write = cpu_0_data_master_granted_system_0_burst_9_upstream & cpu_0_data_master_write;

  assign shifted_address_to_system_0_burst_9_upstream_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //system_0_burst_9_upstream_address mux, which is an e_mux
  assign system_0_burst_9_upstream_address = shifted_address_to_system_0_burst_9_upstream_from_cpu_0_data_master >> 2;

  //d1_system_0_burst_9_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_burst_9_upstream_end_xfer <= 1;
      else 
        d1_system_0_burst_9_upstream_end_xfer <= system_0_burst_9_upstream_end_xfer;
    end


  //system_0_burst_9_upstream_waits_for_read in a cycle, which is an e_mux
  assign system_0_burst_9_upstream_waits_for_read = system_0_burst_9_upstream_in_a_read_cycle & system_0_burst_9_upstream_waitrequest_from_sa;

  //system_0_burst_9_upstream_in_a_read_cycle assignment, which is an e_assign
  assign system_0_burst_9_upstream_in_a_read_cycle = cpu_0_data_master_granted_system_0_burst_9_upstream & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_burst_9_upstream_in_a_read_cycle;

  //system_0_burst_9_upstream_waits_for_write in a cycle, which is an e_mux
  assign system_0_burst_9_upstream_waits_for_write = system_0_burst_9_upstream_in_a_write_cycle & system_0_burst_9_upstream_waitrequest_from_sa;

  //system_0_burst_9_upstream_in_a_write_cycle assignment, which is an e_assign
  assign system_0_burst_9_upstream_in_a_write_cycle = cpu_0_data_master_granted_system_0_burst_9_upstream & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_burst_9_upstream_in_a_write_cycle;

  assign wait_for_system_0_burst_9_upstream_counter = 0;
  //system_0_burst_9_upstream_byteenable byte enable port mux, which is an e_mux
  assign system_0_burst_9_upstream_byteenable = (cpu_0_data_master_granted_system_0_burst_9_upstream)? cpu_0_data_master_byteenable :
    -1;

  //burstcount mux, which is an e_mux
  assign system_0_burst_9_upstream_burstcount = (cpu_0_data_master_granted_system_0_burst_9_upstream)? cpu_0_data_master_burstcount :
    1;

  //debugaccess mux, which is an e_mux
  assign system_0_burst_9_upstream_debugaccess = (cpu_0_data_master_granted_system_0_burst_9_upstream)? cpu_0_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_9/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //cpu_0/data_master non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_requests_system_0_burst_9_upstream && (cpu_0_data_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: cpu_0/data_master drove 0 on its 'burstcount' port while accessing slave system_0_burst_9/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_burst_9_downstream_arbitrator (
                                                // inputs:
                                                 clk,
                                                 d1_uart_0_s1_end_xfer,
                                                 reset_n,
                                                 system_0_burst_9_downstream_address,
                                                 system_0_burst_9_downstream_burstcount,
                                                 system_0_burst_9_downstream_byteenable,
                                                 system_0_burst_9_downstream_granted_uart_0_s1,
                                                 system_0_burst_9_downstream_qualified_request_uart_0_s1,
                                                 system_0_burst_9_downstream_read,
                                                 system_0_burst_9_downstream_read_data_valid_uart_0_s1,
                                                 system_0_burst_9_downstream_requests_uart_0_s1,
                                                 system_0_burst_9_downstream_write,
                                                 system_0_burst_9_downstream_writedata,
                                                 uart_0_s1_readdata_from_sa,

                                                // outputs:
                                                 system_0_burst_9_downstream_address_to_slave,
                                                 system_0_burst_9_downstream_latency_counter,
                                                 system_0_burst_9_downstream_readdata,
                                                 system_0_burst_9_downstream_readdatavalid,
                                                 system_0_burst_9_downstream_reset_n,
                                                 system_0_burst_9_downstream_waitrequest
                                              )
;

  output  [  3: 0] system_0_burst_9_downstream_address_to_slave;
  output           system_0_burst_9_downstream_latency_counter;
  output  [ 15: 0] system_0_burst_9_downstream_readdata;
  output           system_0_burst_9_downstream_readdatavalid;
  output           system_0_burst_9_downstream_reset_n;
  output           system_0_burst_9_downstream_waitrequest;
  input            clk;
  input            d1_uart_0_s1_end_xfer;
  input            reset_n;
  input   [  3: 0] system_0_burst_9_downstream_address;
  input            system_0_burst_9_downstream_burstcount;
  input   [  1: 0] system_0_burst_9_downstream_byteenable;
  input            system_0_burst_9_downstream_granted_uart_0_s1;
  input            system_0_burst_9_downstream_qualified_request_uart_0_s1;
  input            system_0_burst_9_downstream_read;
  input            system_0_burst_9_downstream_read_data_valid_uart_0_s1;
  input            system_0_burst_9_downstream_requests_uart_0_s1;
  input            system_0_burst_9_downstream_write;
  input   [ 15: 0] system_0_burst_9_downstream_writedata;
  input   [ 15: 0] uart_0_s1_readdata_from_sa;

  reg              active_and_waiting_last_time;
  wire             pre_flush_system_0_burst_9_downstream_readdatavalid;
  wire             r_6;
  reg     [  3: 0] system_0_burst_9_downstream_address_last_time;
  wire    [  3: 0] system_0_burst_9_downstream_address_to_slave;
  reg              system_0_burst_9_downstream_burstcount_last_time;
  reg     [  1: 0] system_0_burst_9_downstream_byteenable_last_time;
  wire             system_0_burst_9_downstream_latency_counter;
  reg              system_0_burst_9_downstream_read_last_time;
  wire    [ 15: 0] system_0_burst_9_downstream_readdata;
  wire             system_0_burst_9_downstream_readdatavalid;
  wire             system_0_burst_9_downstream_reset_n;
  wire             system_0_burst_9_downstream_run;
  wire             system_0_burst_9_downstream_waitrequest;
  reg              system_0_burst_9_downstream_write_last_time;
  reg     [ 15: 0] system_0_burst_9_downstream_writedata_last_time;
  //r_6 master_run cascaded wait assignment, which is an e_assign
  assign r_6 = 1 & (system_0_burst_9_downstream_qualified_request_uart_0_s1 | ~system_0_burst_9_downstream_requests_uart_0_s1) & ((~system_0_burst_9_downstream_qualified_request_uart_0_s1 | ~(system_0_burst_9_downstream_read | system_0_burst_9_downstream_write) | (1 & ~d1_uart_0_s1_end_xfer & (system_0_burst_9_downstream_read | system_0_burst_9_downstream_write)))) & ((~system_0_burst_9_downstream_qualified_request_uart_0_s1 | ~(system_0_burst_9_downstream_read | system_0_burst_9_downstream_write) | (1 & ~d1_uart_0_s1_end_xfer & (system_0_burst_9_downstream_read | system_0_burst_9_downstream_write))));

  //cascaded wait assignment, which is an e_assign
  assign system_0_burst_9_downstream_run = r_6;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_burst_9_downstream_address_to_slave = system_0_burst_9_downstream_address;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_system_0_burst_9_downstream_readdatavalid = 0;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign system_0_burst_9_downstream_readdatavalid = 0 |
    pre_flush_system_0_burst_9_downstream_readdatavalid |
    system_0_burst_9_downstream_read_data_valid_uart_0_s1;

  //system_0_burst_9/downstream readdata mux, which is an e_mux
  assign system_0_burst_9_downstream_readdata = uart_0_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_burst_9_downstream_waitrequest = ~system_0_burst_9_downstream_run;

  //latent max counter, which is an e_assign
  assign system_0_burst_9_downstream_latency_counter = 0;

  //system_0_burst_9_downstream_reset_n assignment, which is an e_assign
  assign system_0_burst_9_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_burst_9_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_9_downstream_address_last_time <= 0;
      else 
        system_0_burst_9_downstream_address_last_time <= system_0_burst_9_downstream_address;
    end


  //system_0_burst_9/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_burst_9_downstream_waitrequest & (system_0_burst_9_downstream_read | system_0_burst_9_downstream_write);
    end


  //system_0_burst_9_downstream_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_9_downstream_address != system_0_burst_9_downstream_address_last_time))
        begin
          $write("%0d ns: system_0_burst_9_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_9_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_9_downstream_burstcount_last_time <= 0;
      else 
        system_0_burst_9_downstream_burstcount_last_time <= system_0_burst_9_downstream_burstcount;
    end


  //system_0_burst_9_downstream_burstcount matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_9_downstream_burstcount != system_0_burst_9_downstream_burstcount_last_time))
        begin
          $write("%0d ns: system_0_burst_9_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_9_downstream_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_9_downstream_byteenable_last_time <= 0;
      else 
        system_0_burst_9_downstream_byteenable_last_time <= system_0_burst_9_downstream_byteenable;
    end


  //system_0_burst_9_downstream_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_9_downstream_byteenable != system_0_burst_9_downstream_byteenable_last_time))
        begin
          $write("%0d ns: system_0_burst_9_downstream_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_9_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_9_downstream_read_last_time <= 0;
      else 
        system_0_burst_9_downstream_read_last_time <= system_0_burst_9_downstream_read;
    end


  //system_0_burst_9_downstream_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_9_downstream_read != system_0_burst_9_downstream_read_last_time))
        begin
          $write("%0d ns: system_0_burst_9_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_9_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_9_downstream_write_last_time <= 0;
      else 
        system_0_burst_9_downstream_write_last_time <= system_0_burst_9_downstream_write;
    end


  //system_0_burst_9_downstream_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_9_downstream_write != system_0_burst_9_downstream_write_last_time))
        begin
          $write("%0d ns: system_0_burst_9_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_burst_9_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_9_downstream_writedata_last_time <= 0;
      else 
        system_0_burst_9_downstream_writedata_last_time <= system_0_burst_9_downstream_writedata;
    end


  //system_0_burst_9_downstream_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_burst_9_downstream_writedata != system_0_burst_9_downstream_writedata_last_time) & system_0_burst_9_downstream_write)
        begin
          $write("%0d ns: system_0_burst_9_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_clock_0_in_arbitrator (
                                        // inputs:
                                         clk,
                                         reset_n,
                                         system_0_burst_35_downstream_address_to_slave,
                                         system_0_burst_35_downstream_arbitrationshare,
                                         system_0_burst_35_downstream_burstcount,
                                         system_0_burst_35_downstream_byteenable,
                                         system_0_burst_35_downstream_latency_counter,
                                         system_0_burst_35_downstream_nativeaddress,
                                         system_0_burst_35_downstream_read,
                                         system_0_burst_35_downstream_write,
                                         system_0_burst_35_downstream_writedata,
                                         system_0_clock_0_in_endofpacket,
                                         system_0_clock_0_in_readdata,
                                         system_0_clock_0_in_waitrequest,

                                        // outputs:
                                         d1_system_0_clock_0_in_end_xfer,
                                         system_0_burst_35_downstream_granted_system_0_clock_0_in,
                                         system_0_burst_35_downstream_qualified_request_system_0_clock_0_in,
                                         system_0_burst_35_downstream_read_data_valid_system_0_clock_0_in,
                                         system_0_burst_35_downstream_requests_system_0_clock_0_in,
                                         system_0_clock_0_in_address,
                                         system_0_clock_0_in_byteenable,
                                         system_0_clock_0_in_endofpacket_from_sa,
                                         system_0_clock_0_in_nativeaddress,
                                         system_0_clock_0_in_read,
                                         system_0_clock_0_in_readdata_from_sa,
                                         system_0_clock_0_in_reset_n,
                                         system_0_clock_0_in_waitrequest_from_sa,
                                         system_0_clock_0_in_write,
                                         system_0_clock_0_in_writedata
                                      )
;

  output           d1_system_0_clock_0_in_end_xfer;
  output           system_0_burst_35_downstream_granted_system_0_clock_0_in;
  output           system_0_burst_35_downstream_qualified_request_system_0_clock_0_in;
  output           system_0_burst_35_downstream_read_data_valid_system_0_clock_0_in;
  output           system_0_burst_35_downstream_requests_system_0_clock_0_in;
  output  [  3: 0] system_0_clock_0_in_address;
  output  [  3: 0] system_0_clock_0_in_byteenable;
  output           system_0_clock_0_in_endofpacket_from_sa;
  output  [  1: 0] system_0_clock_0_in_nativeaddress;
  output           system_0_clock_0_in_read;
  output  [ 31: 0] system_0_clock_0_in_readdata_from_sa;
  output           system_0_clock_0_in_reset_n;
  output           system_0_clock_0_in_waitrequest_from_sa;
  output           system_0_clock_0_in_write;
  output  [ 31: 0] system_0_clock_0_in_writedata;
  input            clk;
  input            reset_n;
  input   [  3: 0] system_0_burst_35_downstream_address_to_slave;
  input   [  3: 0] system_0_burst_35_downstream_arbitrationshare;
  input            system_0_burst_35_downstream_burstcount;
  input   [  3: 0] system_0_burst_35_downstream_byteenable;
  input            system_0_burst_35_downstream_latency_counter;
  input   [  3: 0] system_0_burst_35_downstream_nativeaddress;
  input            system_0_burst_35_downstream_read;
  input            system_0_burst_35_downstream_write;
  input   [ 31: 0] system_0_burst_35_downstream_writedata;
  input            system_0_clock_0_in_endofpacket;
  input   [ 31: 0] system_0_clock_0_in_readdata;
  input            system_0_clock_0_in_waitrequest;

  reg              d1_reasons_to_wait;
  reg              d1_system_0_clock_0_in_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_system_0_clock_0_in;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             system_0_burst_35_downstream_arbiterlock;
  wire             system_0_burst_35_downstream_arbiterlock2;
  wire             system_0_burst_35_downstream_continuerequest;
  wire             system_0_burst_35_downstream_granted_system_0_clock_0_in;
  wire             system_0_burst_35_downstream_qualified_request_system_0_clock_0_in;
  wire             system_0_burst_35_downstream_read_data_valid_system_0_clock_0_in;
  wire             system_0_burst_35_downstream_requests_system_0_clock_0_in;
  wire             system_0_burst_35_downstream_saved_grant_system_0_clock_0_in;
  wire    [  3: 0] system_0_clock_0_in_address;
  wire             system_0_clock_0_in_allgrants;
  wire             system_0_clock_0_in_allow_new_arb_cycle;
  wire             system_0_clock_0_in_any_bursting_master_saved_grant;
  wire             system_0_clock_0_in_any_continuerequest;
  wire             system_0_clock_0_in_arb_counter_enable;
  reg     [  3: 0] system_0_clock_0_in_arb_share_counter;
  wire    [  3: 0] system_0_clock_0_in_arb_share_counter_next_value;
  wire    [  3: 0] system_0_clock_0_in_arb_share_set_values;
  wire             system_0_clock_0_in_beginbursttransfer_internal;
  wire             system_0_clock_0_in_begins_xfer;
  wire    [  3: 0] system_0_clock_0_in_byteenable;
  wire             system_0_clock_0_in_end_xfer;
  wire             system_0_clock_0_in_endofpacket_from_sa;
  wire             system_0_clock_0_in_firsttransfer;
  wire             system_0_clock_0_in_grant_vector;
  wire             system_0_clock_0_in_in_a_read_cycle;
  wire             system_0_clock_0_in_in_a_write_cycle;
  wire             system_0_clock_0_in_master_qreq_vector;
  wire    [  1: 0] system_0_clock_0_in_nativeaddress;
  wire             system_0_clock_0_in_non_bursting_master_requests;
  wire             system_0_clock_0_in_read;
  wire    [ 31: 0] system_0_clock_0_in_readdata_from_sa;
  reg              system_0_clock_0_in_reg_firsttransfer;
  wire             system_0_clock_0_in_reset_n;
  reg              system_0_clock_0_in_slavearbiterlockenable;
  wire             system_0_clock_0_in_slavearbiterlockenable2;
  wire             system_0_clock_0_in_unreg_firsttransfer;
  wire             system_0_clock_0_in_waitrequest_from_sa;
  wire             system_0_clock_0_in_waits_for_read;
  wire             system_0_clock_0_in_waits_for_write;
  wire             system_0_clock_0_in_write;
  wire    [ 31: 0] system_0_clock_0_in_writedata;
  wire             wait_for_system_0_clock_0_in_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~system_0_clock_0_in_end_xfer;
    end


  assign system_0_clock_0_in_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_35_downstream_qualified_request_system_0_clock_0_in));
  //assign system_0_clock_0_in_readdata_from_sa = system_0_clock_0_in_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_clock_0_in_readdata_from_sa = system_0_clock_0_in_readdata;

  assign system_0_burst_35_downstream_requests_system_0_clock_0_in = (1) & (system_0_burst_35_downstream_read | system_0_burst_35_downstream_write);
  //assign system_0_clock_0_in_waitrequest_from_sa = system_0_clock_0_in_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_clock_0_in_waitrequest_from_sa = system_0_clock_0_in_waitrequest;

  //system_0_clock_0_in_arb_share_counter set values, which is an e_mux
  assign system_0_clock_0_in_arb_share_set_values = (system_0_burst_35_downstream_granted_system_0_clock_0_in)? system_0_burst_35_downstream_arbitrationshare :
    1;

  //system_0_clock_0_in_non_bursting_master_requests mux, which is an e_mux
  assign system_0_clock_0_in_non_bursting_master_requests = 0;

  //system_0_clock_0_in_any_bursting_master_saved_grant mux, which is an e_mux
  assign system_0_clock_0_in_any_bursting_master_saved_grant = system_0_burst_35_downstream_saved_grant_system_0_clock_0_in;

  //system_0_clock_0_in_arb_share_counter_next_value assignment, which is an e_assign
  assign system_0_clock_0_in_arb_share_counter_next_value = system_0_clock_0_in_firsttransfer ? (system_0_clock_0_in_arb_share_set_values - 1) : |system_0_clock_0_in_arb_share_counter ? (system_0_clock_0_in_arb_share_counter - 1) : 0;

  //system_0_clock_0_in_allgrants all slave grants, which is an e_mux
  assign system_0_clock_0_in_allgrants = |system_0_clock_0_in_grant_vector;

  //system_0_clock_0_in_end_xfer assignment, which is an e_assign
  assign system_0_clock_0_in_end_xfer = ~(system_0_clock_0_in_waits_for_read | system_0_clock_0_in_waits_for_write);

  //end_xfer_arb_share_counter_term_system_0_clock_0_in arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_system_0_clock_0_in = system_0_clock_0_in_end_xfer & (~system_0_clock_0_in_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //system_0_clock_0_in_arb_share_counter arbitration counter enable, which is an e_assign
  assign system_0_clock_0_in_arb_counter_enable = (end_xfer_arb_share_counter_term_system_0_clock_0_in & system_0_clock_0_in_allgrants) | (end_xfer_arb_share_counter_term_system_0_clock_0_in & ~system_0_clock_0_in_non_bursting_master_requests);

  //system_0_clock_0_in_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_clock_0_in_arb_share_counter <= 0;
      else if (system_0_clock_0_in_arb_counter_enable)
          system_0_clock_0_in_arb_share_counter <= system_0_clock_0_in_arb_share_counter_next_value;
    end


  //system_0_clock_0_in_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_clock_0_in_slavearbiterlockenable <= 0;
      else if ((|system_0_clock_0_in_master_qreq_vector & end_xfer_arb_share_counter_term_system_0_clock_0_in) | (end_xfer_arb_share_counter_term_system_0_clock_0_in & ~system_0_clock_0_in_non_bursting_master_requests))
          system_0_clock_0_in_slavearbiterlockenable <= |system_0_clock_0_in_arb_share_counter_next_value;
    end


  //system_0_burst_35/downstream system_0_clock_0/in arbiterlock, which is an e_assign
  assign system_0_burst_35_downstream_arbiterlock = system_0_clock_0_in_slavearbiterlockenable & system_0_burst_35_downstream_continuerequest;

  //system_0_clock_0_in_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign system_0_clock_0_in_slavearbiterlockenable2 = |system_0_clock_0_in_arb_share_counter_next_value;

  //system_0_burst_35/downstream system_0_clock_0/in arbiterlock2, which is an e_assign
  assign system_0_burst_35_downstream_arbiterlock2 = system_0_clock_0_in_slavearbiterlockenable2 & system_0_burst_35_downstream_continuerequest;

  //system_0_clock_0_in_any_continuerequest at least one master continues requesting, which is an e_assign
  assign system_0_clock_0_in_any_continuerequest = 1;

  //system_0_burst_35_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_35_downstream_continuerequest = 1;

  assign system_0_burst_35_downstream_qualified_request_system_0_clock_0_in = system_0_burst_35_downstream_requests_system_0_clock_0_in & ~((system_0_burst_35_downstream_read & ((system_0_burst_35_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_35_downstream_read_data_valid_system_0_clock_0_in, which is an e_mux
  assign system_0_burst_35_downstream_read_data_valid_system_0_clock_0_in = system_0_burst_35_downstream_granted_system_0_clock_0_in & system_0_burst_35_downstream_read & ~system_0_clock_0_in_waits_for_read;

  //system_0_clock_0_in_writedata mux, which is an e_mux
  assign system_0_clock_0_in_writedata = system_0_burst_35_downstream_writedata;

  //assign system_0_clock_0_in_endofpacket_from_sa = system_0_clock_0_in_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign system_0_clock_0_in_endofpacket_from_sa = system_0_clock_0_in_endofpacket;

  //master is always granted when requested
  assign system_0_burst_35_downstream_granted_system_0_clock_0_in = system_0_burst_35_downstream_qualified_request_system_0_clock_0_in;

  //system_0_burst_35/downstream saved-grant system_0_clock_0/in, which is an e_assign
  assign system_0_burst_35_downstream_saved_grant_system_0_clock_0_in = system_0_burst_35_downstream_requests_system_0_clock_0_in;

  //allow new arb cycle for system_0_clock_0/in, which is an e_assign
  assign system_0_clock_0_in_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign system_0_clock_0_in_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign system_0_clock_0_in_master_qreq_vector = 1;

  //system_0_clock_0_in_reset_n assignment, which is an e_assign
  assign system_0_clock_0_in_reset_n = reset_n;

  //system_0_clock_0_in_firsttransfer first transaction, which is an e_assign
  assign system_0_clock_0_in_firsttransfer = system_0_clock_0_in_begins_xfer ? system_0_clock_0_in_unreg_firsttransfer : system_0_clock_0_in_reg_firsttransfer;

  //system_0_clock_0_in_unreg_firsttransfer first transaction, which is an e_assign
  assign system_0_clock_0_in_unreg_firsttransfer = ~(system_0_clock_0_in_slavearbiterlockenable & system_0_clock_0_in_any_continuerequest);

  //system_0_clock_0_in_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_clock_0_in_reg_firsttransfer <= 1'b1;
      else if (system_0_clock_0_in_begins_xfer)
          system_0_clock_0_in_reg_firsttransfer <= system_0_clock_0_in_unreg_firsttransfer;
    end


  //system_0_clock_0_in_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign system_0_clock_0_in_beginbursttransfer_internal = system_0_clock_0_in_begins_xfer;

  //system_0_clock_0_in_read assignment, which is an e_mux
  assign system_0_clock_0_in_read = system_0_burst_35_downstream_granted_system_0_clock_0_in & system_0_burst_35_downstream_read;

  //system_0_clock_0_in_write assignment, which is an e_mux
  assign system_0_clock_0_in_write = system_0_burst_35_downstream_granted_system_0_clock_0_in & system_0_burst_35_downstream_write;

  //system_0_clock_0_in_address mux, which is an e_mux
  assign system_0_clock_0_in_address = system_0_burst_35_downstream_address_to_slave;

  //slaveid system_0_clock_0_in_nativeaddress nativeaddress mux, which is an e_mux
  assign system_0_clock_0_in_nativeaddress = system_0_burst_35_downstream_nativeaddress;

  //d1_system_0_clock_0_in_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_system_0_clock_0_in_end_xfer <= 1;
      else 
        d1_system_0_clock_0_in_end_xfer <= system_0_clock_0_in_end_xfer;
    end


  //system_0_clock_0_in_waits_for_read in a cycle, which is an e_mux
  assign system_0_clock_0_in_waits_for_read = system_0_clock_0_in_in_a_read_cycle & system_0_clock_0_in_waitrequest_from_sa;

  //system_0_clock_0_in_in_a_read_cycle assignment, which is an e_assign
  assign system_0_clock_0_in_in_a_read_cycle = system_0_burst_35_downstream_granted_system_0_clock_0_in & system_0_burst_35_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = system_0_clock_0_in_in_a_read_cycle;

  //system_0_clock_0_in_waits_for_write in a cycle, which is an e_mux
  assign system_0_clock_0_in_waits_for_write = system_0_clock_0_in_in_a_write_cycle & system_0_clock_0_in_waitrequest_from_sa;

  //system_0_clock_0_in_in_a_write_cycle assignment, which is an e_assign
  assign system_0_clock_0_in_in_a_write_cycle = system_0_burst_35_downstream_granted_system_0_clock_0_in & system_0_burst_35_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = system_0_clock_0_in_in_a_write_cycle;

  assign wait_for_system_0_clock_0_in_counter = 0;
  //system_0_clock_0_in_byteenable byte enable port mux, which is an e_mux
  assign system_0_clock_0_in_byteenable = (system_0_burst_35_downstream_granted_system_0_clock_0_in)? system_0_burst_35_downstream_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_clock_0/in enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_35/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_35_downstream_requests_system_0_clock_0_in && (system_0_burst_35_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_35/downstream drove 0 on its 'arbitrationshare' port while accessing slave system_0_clock_0/in", $time);
          $stop;
        end
    end


  //system_0_burst_35/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_35_downstream_requests_system_0_clock_0_in && (system_0_burst_35_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_35/downstream drove 0 on its 'burstcount' port while accessing slave system_0_clock_0/in", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_clock_0_out_arbitrator (
                                         // inputs:
                                          altpll_0_pll_slave_readdata_from_sa,
                                          clk,
                                          d1_altpll_0_pll_slave_end_xfer,
                                          reset_n,
                                          system_0_clock_0_out_address,
                                          system_0_clock_0_out_byteenable,
                                          system_0_clock_0_out_granted_altpll_0_pll_slave,
                                          system_0_clock_0_out_qualified_request_altpll_0_pll_slave,
                                          system_0_clock_0_out_read,
                                          system_0_clock_0_out_read_data_valid_altpll_0_pll_slave,
                                          system_0_clock_0_out_requests_altpll_0_pll_slave,
                                          system_0_clock_0_out_write,
                                          system_0_clock_0_out_writedata,

                                         // outputs:
                                          system_0_clock_0_out_address_to_slave,
                                          system_0_clock_0_out_readdata,
                                          system_0_clock_0_out_reset_n,
                                          system_0_clock_0_out_waitrequest
                                       )
;

  output  [  3: 0] system_0_clock_0_out_address_to_slave;
  output  [ 31: 0] system_0_clock_0_out_readdata;
  output           system_0_clock_0_out_reset_n;
  output           system_0_clock_0_out_waitrequest;
  input   [ 31: 0] altpll_0_pll_slave_readdata_from_sa;
  input            clk;
  input            d1_altpll_0_pll_slave_end_xfer;
  input            reset_n;
  input   [  3: 0] system_0_clock_0_out_address;
  input   [  3: 0] system_0_clock_0_out_byteenable;
  input            system_0_clock_0_out_granted_altpll_0_pll_slave;
  input            system_0_clock_0_out_qualified_request_altpll_0_pll_slave;
  input            system_0_clock_0_out_read;
  input            system_0_clock_0_out_read_data_valid_altpll_0_pll_slave;
  input            system_0_clock_0_out_requests_altpll_0_pll_slave;
  input            system_0_clock_0_out_write;
  input   [ 31: 0] system_0_clock_0_out_writedata;

  reg              active_and_waiting_last_time;
  wire             r_0;
  reg     [  3: 0] system_0_clock_0_out_address_last_time;
  wire    [  3: 0] system_0_clock_0_out_address_to_slave;
  reg     [  3: 0] system_0_clock_0_out_byteenable_last_time;
  reg              system_0_clock_0_out_read_last_time;
  wire    [ 31: 0] system_0_clock_0_out_readdata;
  wire             system_0_clock_0_out_reset_n;
  wire             system_0_clock_0_out_run;
  wire             system_0_clock_0_out_waitrequest;
  reg              system_0_clock_0_out_write_last_time;
  reg     [ 31: 0] system_0_clock_0_out_writedata_last_time;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & ((~system_0_clock_0_out_qualified_request_altpll_0_pll_slave | ~(system_0_clock_0_out_read | system_0_clock_0_out_write) | (1 & (system_0_clock_0_out_read | system_0_clock_0_out_write)))) & ((~system_0_clock_0_out_qualified_request_altpll_0_pll_slave | ~(system_0_clock_0_out_read | system_0_clock_0_out_write) | (1 & (system_0_clock_0_out_read | system_0_clock_0_out_write))));

  //cascaded wait assignment, which is an e_assign
  assign system_0_clock_0_out_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign system_0_clock_0_out_address_to_slave = system_0_clock_0_out_address;

  //system_0_clock_0/out readdata mux, which is an e_mux
  assign system_0_clock_0_out_readdata = altpll_0_pll_slave_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign system_0_clock_0_out_waitrequest = ~system_0_clock_0_out_run;

  //system_0_clock_0_out_reset_n assignment, which is an e_assign
  assign system_0_clock_0_out_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //system_0_clock_0_out_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_clock_0_out_address_last_time <= 0;
      else 
        system_0_clock_0_out_address_last_time <= system_0_clock_0_out_address;
    end


  //system_0_clock_0/out waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= system_0_clock_0_out_waitrequest & (system_0_clock_0_out_read | system_0_clock_0_out_write);
    end


  //system_0_clock_0_out_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_clock_0_out_address != system_0_clock_0_out_address_last_time))
        begin
          $write("%0d ns: system_0_clock_0_out_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_clock_0_out_byteenable check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_clock_0_out_byteenable_last_time <= 0;
      else 
        system_0_clock_0_out_byteenable_last_time <= system_0_clock_0_out_byteenable;
    end


  //system_0_clock_0_out_byteenable matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_clock_0_out_byteenable != system_0_clock_0_out_byteenable_last_time))
        begin
          $write("%0d ns: system_0_clock_0_out_byteenable did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_clock_0_out_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_clock_0_out_read_last_time <= 0;
      else 
        system_0_clock_0_out_read_last_time <= system_0_clock_0_out_read;
    end


  //system_0_clock_0_out_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_clock_0_out_read != system_0_clock_0_out_read_last_time))
        begin
          $write("%0d ns: system_0_clock_0_out_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_clock_0_out_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_clock_0_out_write_last_time <= 0;
      else 
        system_0_clock_0_out_write_last_time <= system_0_clock_0_out_write;
    end


  //system_0_clock_0_out_write matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_clock_0_out_write != system_0_clock_0_out_write_last_time))
        begin
          $write("%0d ns: system_0_clock_0_out_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //system_0_clock_0_out_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_clock_0_out_writedata_last_time <= 0;
      else 
        system_0_clock_0_out_writedata_last_time <= system_0_clock_0_out_writedata;
    end


  //system_0_clock_0_out_writedata matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (system_0_clock_0_out_writedata != system_0_clock_0_out_writedata_last_time) & system_0_clock_0_out_write)
        begin
          $write("%0d ns: system_0_clock_0_out_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module timer_0_s1_arbitrator (
                               // inputs:
                                clk,
                                reset_n,
                                system_0_burst_10_downstream_address_to_slave,
                                system_0_burst_10_downstream_arbitrationshare,
                                system_0_burst_10_downstream_burstcount,
                                system_0_burst_10_downstream_latency_counter,
                                system_0_burst_10_downstream_nativeaddress,
                                system_0_burst_10_downstream_read,
                                system_0_burst_10_downstream_write,
                                system_0_burst_10_downstream_writedata,
                                timer_0_s1_irq,
                                timer_0_s1_readdata,

                               // outputs:
                                d1_timer_0_s1_end_xfer,
                                system_0_burst_10_downstream_granted_timer_0_s1,
                                system_0_burst_10_downstream_qualified_request_timer_0_s1,
                                system_0_burst_10_downstream_read_data_valid_timer_0_s1,
                                system_0_burst_10_downstream_requests_timer_0_s1,
                                timer_0_s1_address,
                                timer_0_s1_chipselect,
                                timer_0_s1_irq_from_sa,
                                timer_0_s1_readdata_from_sa,
                                timer_0_s1_reset_n,
                                timer_0_s1_write_n,
                                timer_0_s1_writedata
                             )
;

  output           d1_timer_0_s1_end_xfer;
  output           system_0_burst_10_downstream_granted_timer_0_s1;
  output           system_0_burst_10_downstream_qualified_request_timer_0_s1;
  output           system_0_burst_10_downstream_read_data_valid_timer_0_s1;
  output           system_0_burst_10_downstream_requests_timer_0_s1;
  output  [  2: 0] timer_0_s1_address;
  output           timer_0_s1_chipselect;
  output           timer_0_s1_irq_from_sa;
  output  [ 15: 0] timer_0_s1_readdata_from_sa;
  output           timer_0_s1_reset_n;
  output           timer_0_s1_write_n;
  output  [ 15: 0] timer_0_s1_writedata;
  input            clk;
  input            reset_n;
  input   [  3: 0] system_0_burst_10_downstream_address_to_slave;
  input   [  4: 0] system_0_burst_10_downstream_arbitrationshare;
  input            system_0_burst_10_downstream_burstcount;
  input            system_0_burst_10_downstream_latency_counter;
  input   [  3: 0] system_0_burst_10_downstream_nativeaddress;
  input            system_0_burst_10_downstream_read;
  input            system_0_burst_10_downstream_write;
  input   [ 15: 0] system_0_burst_10_downstream_writedata;
  input            timer_0_s1_irq;
  input   [ 15: 0] timer_0_s1_readdata;

  reg              d1_reasons_to_wait;
  reg              d1_timer_0_s1_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_timer_0_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             system_0_burst_10_downstream_arbiterlock;
  wire             system_0_burst_10_downstream_arbiterlock2;
  wire             system_0_burst_10_downstream_continuerequest;
  wire             system_0_burst_10_downstream_granted_timer_0_s1;
  wire             system_0_burst_10_downstream_qualified_request_timer_0_s1;
  wire             system_0_burst_10_downstream_read_data_valid_timer_0_s1;
  wire             system_0_burst_10_downstream_requests_timer_0_s1;
  wire             system_0_burst_10_downstream_saved_grant_timer_0_s1;
  wire    [  2: 0] timer_0_s1_address;
  wire             timer_0_s1_allgrants;
  wire             timer_0_s1_allow_new_arb_cycle;
  wire             timer_0_s1_any_bursting_master_saved_grant;
  wire             timer_0_s1_any_continuerequest;
  wire             timer_0_s1_arb_counter_enable;
  reg     [  4: 0] timer_0_s1_arb_share_counter;
  wire    [  4: 0] timer_0_s1_arb_share_counter_next_value;
  wire    [  4: 0] timer_0_s1_arb_share_set_values;
  wire             timer_0_s1_beginbursttransfer_internal;
  wire             timer_0_s1_begins_xfer;
  wire             timer_0_s1_chipselect;
  wire             timer_0_s1_end_xfer;
  wire             timer_0_s1_firsttransfer;
  wire             timer_0_s1_grant_vector;
  wire             timer_0_s1_in_a_read_cycle;
  wire             timer_0_s1_in_a_write_cycle;
  wire             timer_0_s1_irq_from_sa;
  wire             timer_0_s1_master_qreq_vector;
  wire             timer_0_s1_non_bursting_master_requests;
  wire    [ 15: 0] timer_0_s1_readdata_from_sa;
  reg              timer_0_s1_reg_firsttransfer;
  wire             timer_0_s1_reset_n;
  reg              timer_0_s1_slavearbiterlockenable;
  wire             timer_0_s1_slavearbiterlockenable2;
  wire             timer_0_s1_unreg_firsttransfer;
  wire             timer_0_s1_waits_for_read;
  wire             timer_0_s1_waits_for_write;
  wire             timer_0_s1_write_n;
  wire    [ 15: 0] timer_0_s1_writedata;
  wire             wait_for_timer_0_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~timer_0_s1_end_xfer;
    end


  assign timer_0_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_10_downstream_qualified_request_timer_0_s1));
  //assign timer_0_s1_readdata_from_sa = timer_0_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign timer_0_s1_readdata_from_sa = timer_0_s1_readdata;

  assign system_0_burst_10_downstream_requests_timer_0_s1 = (1) & (system_0_burst_10_downstream_read | system_0_burst_10_downstream_write);
  //timer_0_s1_arb_share_counter set values, which is an e_mux
  assign timer_0_s1_arb_share_set_values = (system_0_burst_10_downstream_granted_timer_0_s1)? system_0_burst_10_downstream_arbitrationshare :
    1;

  //timer_0_s1_non_bursting_master_requests mux, which is an e_mux
  assign timer_0_s1_non_bursting_master_requests = 0;

  //timer_0_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign timer_0_s1_any_bursting_master_saved_grant = system_0_burst_10_downstream_saved_grant_timer_0_s1;

  //timer_0_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign timer_0_s1_arb_share_counter_next_value = timer_0_s1_firsttransfer ? (timer_0_s1_arb_share_set_values - 1) : |timer_0_s1_arb_share_counter ? (timer_0_s1_arb_share_counter - 1) : 0;

  //timer_0_s1_allgrants all slave grants, which is an e_mux
  assign timer_0_s1_allgrants = |timer_0_s1_grant_vector;

  //timer_0_s1_end_xfer assignment, which is an e_assign
  assign timer_0_s1_end_xfer = ~(timer_0_s1_waits_for_read | timer_0_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_timer_0_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_timer_0_s1 = timer_0_s1_end_xfer & (~timer_0_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //timer_0_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign timer_0_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_timer_0_s1 & timer_0_s1_allgrants) | (end_xfer_arb_share_counter_term_timer_0_s1 & ~timer_0_s1_non_bursting_master_requests);

  //timer_0_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          timer_0_s1_arb_share_counter <= 0;
      else if (timer_0_s1_arb_counter_enable)
          timer_0_s1_arb_share_counter <= timer_0_s1_arb_share_counter_next_value;
    end


  //timer_0_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          timer_0_s1_slavearbiterlockenable <= 0;
      else if ((|timer_0_s1_master_qreq_vector & end_xfer_arb_share_counter_term_timer_0_s1) | (end_xfer_arb_share_counter_term_timer_0_s1 & ~timer_0_s1_non_bursting_master_requests))
          timer_0_s1_slavearbiterlockenable <= |timer_0_s1_arb_share_counter_next_value;
    end


  //system_0_burst_10/downstream timer_0/s1 arbiterlock, which is an e_assign
  assign system_0_burst_10_downstream_arbiterlock = timer_0_s1_slavearbiterlockenable & system_0_burst_10_downstream_continuerequest;

  //timer_0_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign timer_0_s1_slavearbiterlockenable2 = |timer_0_s1_arb_share_counter_next_value;

  //system_0_burst_10/downstream timer_0/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_10_downstream_arbiterlock2 = timer_0_s1_slavearbiterlockenable2 & system_0_burst_10_downstream_continuerequest;

  //timer_0_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign timer_0_s1_any_continuerequest = 1;

  //system_0_burst_10_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_10_downstream_continuerequest = 1;

  assign system_0_burst_10_downstream_qualified_request_timer_0_s1 = system_0_burst_10_downstream_requests_timer_0_s1 & ~((system_0_burst_10_downstream_read & ((system_0_burst_10_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_10_downstream_read_data_valid_timer_0_s1, which is an e_mux
  assign system_0_burst_10_downstream_read_data_valid_timer_0_s1 = system_0_burst_10_downstream_granted_timer_0_s1 & system_0_burst_10_downstream_read & ~timer_0_s1_waits_for_read;

  //timer_0_s1_writedata mux, which is an e_mux
  assign timer_0_s1_writedata = system_0_burst_10_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_10_downstream_granted_timer_0_s1 = system_0_burst_10_downstream_qualified_request_timer_0_s1;

  //system_0_burst_10/downstream saved-grant timer_0/s1, which is an e_assign
  assign system_0_burst_10_downstream_saved_grant_timer_0_s1 = system_0_burst_10_downstream_requests_timer_0_s1;

  //allow new arb cycle for timer_0/s1, which is an e_assign
  assign timer_0_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign timer_0_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign timer_0_s1_master_qreq_vector = 1;

  //timer_0_s1_reset_n assignment, which is an e_assign
  assign timer_0_s1_reset_n = reset_n;

  assign timer_0_s1_chipselect = system_0_burst_10_downstream_granted_timer_0_s1;
  //timer_0_s1_firsttransfer first transaction, which is an e_assign
  assign timer_0_s1_firsttransfer = timer_0_s1_begins_xfer ? timer_0_s1_unreg_firsttransfer : timer_0_s1_reg_firsttransfer;

  //timer_0_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign timer_0_s1_unreg_firsttransfer = ~(timer_0_s1_slavearbiterlockenable & timer_0_s1_any_continuerequest);

  //timer_0_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          timer_0_s1_reg_firsttransfer <= 1'b1;
      else if (timer_0_s1_begins_xfer)
          timer_0_s1_reg_firsttransfer <= timer_0_s1_unreg_firsttransfer;
    end


  //timer_0_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign timer_0_s1_beginbursttransfer_internal = timer_0_s1_begins_xfer;

  //~timer_0_s1_write_n assignment, which is an e_mux
  assign timer_0_s1_write_n = ~(system_0_burst_10_downstream_granted_timer_0_s1 & system_0_burst_10_downstream_write);

  //timer_0_s1_address mux, which is an e_mux
  assign timer_0_s1_address = system_0_burst_10_downstream_nativeaddress;

  //d1_timer_0_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_timer_0_s1_end_xfer <= 1;
      else 
        d1_timer_0_s1_end_xfer <= timer_0_s1_end_xfer;
    end


  //timer_0_s1_waits_for_read in a cycle, which is an e_mux
  assign timer_0_s1_waits_for_read = timer_0_s1_in_a_read_cycle & timer_0_s1_begins_xfer;

  //timer_0_s1_in_a_read_cycle assignment, which is an e_assign
  assign timer_0_s1_in_a_read_cycle = system_0_burst_10_downstream_granted_timer_0_s1 & system_0_burst_10_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = timer_0_s1_in_a_read_cycle;

  //timer_0_s1_waits_for_write in a cycle, which is an e_mux
  assign timer_0_s1_waits_for_write = timer_0_s1_in_a_write_cycle & 0;

  //timer_0_s1_in_a_write_cycle assignment, which is an e_assign
  assign timer_0_s1_in_a_write_cycle = system_0_burst_10_downstream_granted_timer_0_s1 & system_0_burst_10_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = timer_0_s1_in_a_write_cycle;

  assign wait_for_timer_0_s1_counter = 0;
  //assign timer_0_s1_irq_from_sa = timer_0_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign timer_0_s1_irq_from_sa = timer_0_s1_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //timer_0/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_10/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_10_downstream_requests_timer_0_s1 && (system_0_burst_10_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_10/downstream drove 0 on its 'arbitrationshare' port while accessing slave timer_0/s1", $time);
          $stop;
        end
    end


  //system_0_burst_10/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_10_downstream_requests_timer_0_s1 && (system_0_burst_10_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_10/downstream drove 0 on its 'burstcount' port while accessing slave timer_0/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module timer_1_s1_arbitrator (
                               // inputs:
                                clk,
                                reset_n,
                                system_0_burst_11_downstream_address_to_slave,
                                system_0_burst_11_downstream_arbitrationshare,
                                system_0_burst_11_downstream_burstcount,
                                system_0_burst_11_downstream_latency_counter,
                                system_0_burst_11_downstream_nativeaddress,
                                system_0_burst_11_downstream_read,
                                system_0_burst_11_downstream_write,
                                system_0_burst_11_downstream_writedata,
                                timer_1_s1_irq,
                                timer_1_s1_readdata,

                               // outputs:
                                d1_timer_1_s1_end_xfer,
                                system_0_burst_11_downstream_granted_timer_1_s1,
                                system_0_burst_11_downstream_qualified_request_timer_1_s1,
                                system_0_burst_11_downstream_read_data_valid_timer_1_s1,
                                system_0_burst_11_downstream_requests_timer_1_s1,
                                timer_1_s1_address,
                                timer_1_s1_chipselect,
                                timer_1_s1_irq_from_sa,
                                timer_1_s1_readdata_from_sa,
                                timer_1_s1_reset_n,
                                timer_1_s1_write_n,
                                timer_1_s1_writedata
                             )
;

  output           d1_timer_1_s1_end_xfer;
  output           system_0_burst_11_downstream_granted_timer_1_s1;
  output           system_0_burst_11_downstream_qualified_request_timer_1_s1;
  output           system_0_burst_11_downstream_read_data_valid_timer_1_s1;
  output           system_0_burst_11_downstream_requests_timer_1_s1;
  output  [  2: 0] timer_1_s1_address;
  output           timer_1_s1_chipselect;
  output           timer_1_s1_irq_from_sa;
  output  [ 15: 0] timer_1_s1_readdata_from_sa;
  output           timer_1_s1_reset_n;
  output           timer_1_s1_write_n;
  output  [ 15: 0] timer_1_s1_writedata;
  input            clk;
  input            reset_n;
  input   [  3: 0] system_0_burst_11_downstream_address_to_slave;
  input   [  4: 0] system_0_burst_11_downstream_arbitrationshare;
  input            system_0_burst_11_downstream_burstcount;
  input            system_0_burst_11_downstream_latency_counter;
  input   [  3: 0] system_0_burst_11_downstream_nativeaddress;
  input            system_0_burst_11_downstream_read;
  input            system_0_burst_11_downstream_write;
  input   [ 15: 0] system_0_burst_11_downstream_writedata;
  input            timer_1_s1_irq;
  input   [ 15: 0] timer_1_s1_readdata;

  reg              d1_reasons_to_wait;
  reg              d1_timer_1_s1_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_timer_1_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             system_0_burst_11_downstream_arbiterlock;
  wire             system_0_burst_11_downstream_arbiterlock2;
  wire             system_0_burst_11_downstream_continuerequest;
  wire             system_0_burst_11_downstream_granted_timer_1_s1;
  wire             system_0_burst_11_downstream_qualified_request_timer_1_s1;
  wire             system_0_burst_11_downstream_read_data_valid_timer_1_s1;
  wire             system_0_burst_11_downstream_requests_timer_1_s1;
  wire             system_0_burst_11_downstream_saved_grant_timer_1_s1;
  wire    [  2: 0] timer_1_s1_address;
  wire             timer_1_s1_allgrants;
  wire             timer_1_s1_allow_new_arb_cycle;
  wire             timer_1_s1_any_bursting_master_saved_grant;
  wire             timer_1_s1_any_continuerequest;
  wire             timer_1_s1_arb_counter_enable;
  reg     [  4: 0] timer_1_s1_arb_share_counter;
  wire    [  4: 0] timer_1_s1_arb_share_counter_next_value;
  wire    [  4: 0] timer_1_s1_arb_share_set_values;
  wire             timer_1_s1_beginbursttransfer_internal;
  wire             timer_1_s1_begins_xfer;
  wire             timer_1_s1_chipselect;
  wire             timer_1_s1_end_xfer;
  wire             timer_1_s1_firsttransfer;
  wire             timer_1_s1_grant_vector;
  wire             timer_1_s1_in_a_read_cycle;
  wire             timer_1_s1_in_a_write_cycle;
  wire             timer_1_s1_irq_from_sa;
  wire             timer_1_s1_master_qreq_vector;
  wire             timer_1_s1_non_bursting_master_requests;
  wire    [ 15: 0] timer_1_s1_readdata_from_sa;
  reg              timer_1_s1_reg_firsttransfer;
  wire             timer_1_s1_reset_n;
  reg              timer_1_s1_slavearbiterlockenable;
  wire             timer_1_s1_slavearbiterlockenable2;
  wire             timer_1_s1_unreg_firsttransfer;
  wire             timer_1_s1_waits_for_read;
  wire             timer_1_s1_waits_for_write;
  wire             timer_1_s1_write_n;
  wire    [ 15: 0] timer_1_s1_writedata;
  wire             wait_for_timer_1_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~timer_1_s1_end_xfer;
    end


  assign timer_1_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_11_downstream_qualified_request_timer_1_s1));
  //assign timer_1_s1_readdata_from_sa = timer_1_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign timer_1_s1_readdata_from_sa = timer_1_s1_readdata;

  assign system_0_burst_11_downstream_requests_timer_1_s1 = (1) & (system_0_burst_11_downstream_read | system_0_burst_11_downstream_write);
  //timer_1_s1_arb_share_counter set values, which is an e_mux
  assign timer_1_s1_arb_share_set_values = (system_0_burst_11_downstream_granted_timer_1_s1)? system_0_burst_11_downstream_arbitrationshare :
    1;

  //timer_1_s1_non_bursting_master_requests mux, which is an e_mux
  assign timer_1_s1_non_bursting_master_requests = 0;

  //timer_1_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign timer_1_s1_any_bursting_master_saved_grant = system_0_burst_11_downstream_saved_grant_timer_1_s1;

  //timer_1_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign timer_1_s1_arb_share_counter_next_value = timer_1_s1_firsttransfer ? (timer_1_s1_arb_share_set_values - 1) : |timer_1_s1_arb_share_counter ? (timer_1_s1_arb_share_counter - 1) : 0;

  //timer_1_s1_allgrants all slave grants, which is an e_mux
  assign timer_1_s1_allgrants = |timer_1_s1_grant_vector;

  //timer_1_s1_end_xfer assignment, which is an e_assign
  assign timer_1_s1_end_xfer = ~(timer_1_s1_waits_for_read | timer_1_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_timer_1_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_timer_1_s1 = timer_1_s1_end_xfer & (~timer_1_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //timer_1_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign timer_1_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_timer_1_s1 & timer_1_s1_allgrants) | (end_xfer_arb_share_counter_term_timer_1_s1 & ~timer_1_s1_non_bursting_master_requests);

  //timer_1_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          timer_1_s1_arb_share_counter <= 0;
      else if (timer_1_s1_arb_counter_enable)
          timer_1_s1_arb_share_counter <= timer_1_s1_arb_share_counter_next_value;
    end


  //timer_1_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          timer_1_s1_slavearbiterlockenable <= 0;
      else if ((|timer_1_s1_master_qreq_vector & end_xfer_arb_share_counter_term_timer_1_s1) | (end_xfer_arb_share_counter_term_timer_1_s1 & ~timer_1_s1_non_bursting_master_requests))
          timer_1_s1_slavearbiterlockenable <= |timer_1_s1_arb_share_counter_next_value;
    end


  //system_0_burst_11/downstream timer_1/s1 arbiterlock, which is an e_assign
  assign system_0_burst_11_downstream_arbiterlock = timer_1_s1_slavearbiterlockenable & system_0_burst_11_downstream_continuerequest;

  //timer_1_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign timer_1_s1_slavearbiterlockenable2 = |timer_1_s1_arb_share_counter_next_value;

  //system_0_burst_11/downstream timer_1/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_11_downstream_arbiterlock2 = timer_1_s1_slavearbiterlockenable2 & system_0_burst_11_downstream_continuerequest;

  //timer_1_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign timer_1_s1_any_continuerequest = 1;

  //system_0_burst_11_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_11_downstream_continuerequest = 1;

  assign system_0_burst_11_downstream_qualified_request_timer_1_s1 = system_0_burst_11_downstream_requests_timer_1_s1 & ~((system_0_burst_11_downstream_read & ((system_0_burst_11_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_11_downstream_read_data_valid_timer_1_s1, which is an e_mux
  assign system_0_burst_11_downstream_read_data_valid_timer_1_s1 = system_0_burst_11_downstream_granted_timer_1_s1 & system_0_burst_11_downstream_read & ~timer_1_s1_waits_for_read;

  //timer_1_s1_writedata mux, which is an e_mux
  assign timer_1_s1_writedata = system_0_burst_11_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_11_downstream_granted_timer_1_s1 = system_0_burst_11_downstream_qualified_request_timer_1_s1;

  //system_0_burst_11/downstream saved-grant timer_1/s1, which is an e_assign
  assign system_0_burst_11_downstream_saved_grant_timer_1_s1 = system_0_burst_11_downstream_requests_timer_1_s1;

  //allow new arb cycle for timer_1/s1, which is an e_assign
  assign timer_1_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign timer_1_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign timer_1_s1_master_qreq_vector = 1;

  //timer_1_s1_reset_n assignment, which is an e_assign
  assign timer_1_s1_reset_n = reset_n;

  assign timer_1_s1_chipselect = system_0_burst_11_downstream_granted_timer_1_s1;
  //timer_1_s1_firsttransfer first transaction, which is an e_assign
  assign timer_1_s1_firsttransfer = timer_1_s1_begins_xfer ? timer_1_s1_unreg_firsttransfer : timer_1_s1_reg_firsttransfer;

  //timer_1_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign timer_1_s1_unreg_firsttransfer = ~(timer_1_s1_slavearbiterlockenable & timer_1_s1_any_continuerequest);

  //timer_1_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          timer_1_s1_reg_firsttransfer <= 1'b1;
      else if (timer_1_s1_begins_xfer)
          timer_1_s1_reg_firsttransfer <= timer_1_s1_unreg_firsttransfer;
    end


  //timer_1_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign timer_1_s1_beginbursttransfer_internal = timer_1_s1_begins_xfer;

  //~timer_1_s1_write_n assignment, which is an e_mux
  assign timer_1_s1_write_n = ~(system_0_burst_11_downstream_granted_timer_1_s1 & system_0_burst_11_downstream_write);

  //timer_1_s1_address mux, which is an e_mux
  assign timer_1_s1_address = system_0_burst_11_downstream_nativeaddress;

  //d1_timer_1_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_timer_1_s1_end_xfer <= 1;
      else 
        d1_timer_1_s1_end_xfer <= timer_1_s1_end_xfer;
    end


  //timer_1_s1_waits_for_read in a cycle, which is an e_mux
  assign timer_1_s1_waits_for_read = timer_1_s1_in_a_read_cycle & timer_1_s1_begins_xfer;

  //timer_1_s1_in_a_read_cycle assignment, which is an e_assign
  assign timer_1_s1_in_a_read_cycle = system_0_burst_11_downstream_granted_timer_1_s1 & system_0_burst_11_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = timer_1_s1_in_a_read_cycle;

  //timer_1_s1_waits_for_write in a cycle, which is an e_mux
  assign timer_1_s1_waits_for_write = timer_1_s1_in_a_write_cycle & 0;

  //timer_1_s1_in_a_write_cycle assignment, which is an e_assign
  assign timer_1_s1_in_a_write_cycle = system_0_burst_11_downstream_granted_timer_1_s1 & system_0_burst_11_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = timer_1_s1_in_a_write_cycle;

  assign wait_for_timer_1_s1_counter = 0;
  //assign timer_1_s1_irq_from_sa = timer_1_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign timer_1_s1_irq_from_sa = timer_1_s1_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //timer_1/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_11/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_11_downstream_requests_timer_1_s1 && (system_0_burst_11_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_11/downstream drove 0 on its 'arbitrationshare' port while accessing slave timer_1/s1", $time);
          $stop;
        end
    end


  //system_0_burst_11/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_11_downstream_requests_timer_1_s1 && (system_0_burst_11_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_11/downstream drove 0 on its 'burstcount' port while accessing slave timer_1/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module tri_state_bridge_0_avalon_slave_arbitrator (
                                                    // inputs:
                                                     clk,
                                                     reset_n,
                                                     system_0_burst_2_downstream_address_to_slave,
                                                     system_0_burst_2_downstream_arbitrationshare,
                                                     system_0_burst_2_downstream_burstcount,
                                                     system_0_burst_2_downstream_byteenable,
                                                     system_0_burst_2_downstream_latency_counter,
                                                     system_0_burst_2_downstream_read,
                                                     system_0_burst_2_downstream_write,
                                                     system_0_burst_2_downstream_writedata,
                                                     system_0_burst_3_downstream_address_to_slave,
                                                     system_0_burst_3_downstream_arbitrationshare,
                                                     system_0_burst_3_downstream_burstcount,
                                                     system_0_burst_3_downstream_byteenable,
                                                     system_0_burst_3_downstream_latency_counter,
                                                     system_0_burst_3_downstream_read,
                                                     system_0_burst_3_downstream_write,
                                                     system_0_burst_3_downstream_writedata,

                                                    // outputs:
                                                     cfi_flash_0_s1_wait_counter_eq_0,
                                                     d1_tri_state_bridge_0_avalon_slave_end_xfer,
                                                     incoming_tri_state_bridge_0_data_with_Xs_converted_to_0,
                                                     select_n_to_the_cfi_flash_0,
                                                     system_0_burst_2_downstream_granted_cfi_flash_0_s1,
                                                     system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1,
                                                     system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1,
                                                     system_0_burst_2_downstream_requests_cfi_flash_0_s1,
                                                     system_0_burst_3_downstream_granted_cfi_flash_0_s1,
                                                     system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1,
                                                     system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1,
                                                     system_0_burst_3_downstream_requests_cfi_flash_0_s1,
                                                     tri_state_bridge_0_address,
                                                     tri_state_bridge_0_data,
                                                     tri_state_bridge_0_readn,
                                                     write_n_to_the_cfi_flash_0
                                                  )
;

  output           cfi_flash_0_s1_wait_counter_eq_0;
  output           d1_tri_state_bridge_0_avalon_slave_end_xfer;
  output  [  7: 0] incoming_tri_state_bridge_0_data_with_Xs_converted_to_0;
  output           select_n_to_the_cfi_flash_0;
  output           system_0_burst_2_downstream_granted_cfi_flash_0_s1;
  output           system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1;
  output           system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1;
  output           system_0_burst_2_downstream_requests_cfi_flash_0_s1;
  output           system_0_burst_3_downstream_granted_cfi_flash_0_s1;
  output           system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1;
  output           system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1;
  output           system_0_burst_3_downstream_requests_cfi_flash_0_s1;
  output  [ 21: 0] tri_state_bridge_0_address;
  inout   [  7: 0] tri_state_bridge_0_data;
  output           tri_state_bridge_0_readn;
  output           write_n_to_the_cfi_flash_0;
  input            clk;
  input            reset_n;
  input   [ 21: 0] system_0_burst_2_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_2_downstream_arbitrationshare;
  input            system_0_burst_2_downstream_burstcount;
  input            system_0_burst_2_downstream_byteenable;
  input   [  1: 0] system_0_burst_2_downstream_latency_counter;
  input            system_0_burst_2_downstream_read;
  input            system_0_burst_2_downstream_write;
  input   [  7: 0] system_0_burst_2_downstream_writedata;
  input   [ 21: 0] system_0_burst_3_downstream_address_to_slave;
  input   [  5: 0] system_0_burst_3_downstream_arbitrationshare;
  input            system_0_burst_3_downstream_burstcount;
  input            system_0_burst_3_downstream_byteenable;
  input   [  1: 0] system_0_burst_3_downstream_latency_counter;
  input            system_0_burst_3_downstream_read;
  input            system_0_burst_3_downstream_write;
  input   [  7: 0] system_0_burst_3_downstream_writedata;

  wire    [  4: 0] cfi_flash_0_s1_counter_load_value;
  wire             cfi_flash_0_s1_in_a_read_cycle;
  wire             cfi_flash_0_s1_in_a_write_cycle;
  wire             cfi_flash_0_s1_pretend_byte_enable;
  reg     [  4: 0] cfi_flash_0_s1_wait_counter;
  wire             cfi_flash_0_s1_wait_counter_eq_0;
  wire             cfi_flash_0_s1_waits_for_read;
  wire             cfi_flash_0_s1_waits_for_write;
  wire             cfi_flash_0_s1_with_write_latency;
  reg              d1_in_a_write_cycle /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON"  */;
  reg     [  7: 0] d1_outgoing_tri_state_bridge_0_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON"  */;
  reg              d1_reasons_to_wait;
  reg              d1_tri_state_bridge_0_avalon_slave_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_tri_state_bridge_0_avalon_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg     [  7: 0] incoming_tri_state_bridge_0_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON"  */;
  wire             incoming_tri_state_bridge_0_data_bit_0_is_x;
  wire             incoming_tri_state_bridge_0_data_bit_1_is_x;
  wire             incoming_tri_state_bridge_0_data_bit_2_is_x;
  wire             incoming_tri_state_bridge_0_data_bit_3_is_x;
  wire             incoming_tri_state_bridge_0_data_bit_4_is_x;
  wire             incoming_tri_state_bridge_0_data_bit_5_is_x;
  wire             incoming_tri_state_bridge_0_data_bit_6_is_x;
  wire             incoming_tri_state_bridge_0_data_bit_7_is_x;
  wire    [  7: 0] incoming_tri_state_bridge_0_data_with_Xs_converted_to_0;
  reg              last_cycle_system_0_burst_2_downstream_granted_slave_cfi_flash_0_s1;
  reg              last_cycle_system_0_burst_3_downstream_granted_slave_cfi_flash_0_s1;
  wire    [  7: 0] outgoing_tri_state_bridge_0_data;
  wire             p1_select_n_to_the_cfi_flash_0;
  wire    [  1: 0] p1_system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1_shift_register;
  wire    [  1: 0] p1_system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1_shift_register;
  wire    [ 21: 0] p1_tri_state_bridge_0_address;
  wire             p1_tri_state_bridge_0_readn;
  wire             p1_write_n_to_the_cfi_flash_0;
  reg              select_n_to_the_cfi_flash_0 /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON"  */;
  wire             system_0_burst_2_downstream_arbiterlock;
  wire             system_0_burst_2_downstream_arbiterlock2;
  wire             system_0_burst_2_downstream_continuerequest;
  wire             system_0_burst_2_downstream_granted_cfi_flash_0_s1;
  wire             system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1;
  wire             system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1;
  reg     [  1: 0] system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1_shift_register;
  wire             system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1_shift_register_in;
  wire             system_0_burst_2_downstream_requests_cfi_flash_0_s1;
  wire             system_0_burst_2_downstream_saved_grant_cfi_flash_0_s1;
  wire             system_0_burst_3_downstream_arbiterlock;
  wire             system_0_burst_3_downstream_arbiterlock2;
  wire             system_0_burst_3_downstream_continuerequest;
  wire             system_0_burst_3_downstream_granted_cfi_flash_0_s1;
  wire             system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1;
  wire             system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1;
  reg     [  1: 0] system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1_shift_register;
  wire             system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1_shift_register_in;
  wire             system_0_burst_3_downstream_requests_cfi_flash_0_s1;
  wire             system_0_burst_3_downstream_saved_grant_cfi_flash_0_s1;
  wire             time_to_write;
  reg     [ 21: 0] tri_state_bridge_0_address /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON"  */;
  wire             tri_state_bridge_0_avalon_slave_allgrants;
  wire             tri_state_bridge_0_avalon_slave_allow_new_arb_cycle;
  wire             tri_state_bridge_0_avalon_slave_any_bursting_master_saved_grant;
  wire             tri_state_bridge_0_avalon_slave_any_continuerequest;
  reg     [  1: 0] tri_state_bridge_0_avalon_slave_arb_addend;
  wire             tri_state_bridge_0_avalon_slave_arb_counter_enable;
  reg     [  5: 0] tri_state_bridge_0_avalon_slave_arb_share_counter;
  wire    [  5: 0] tri_state_bridge_0_avalon_slave_arb_share_counter_next_value;
  wire    [  5: 0] tri_state_bridge_0_avalon_slave_arb_share_set_values;
  wire    [  1: 0] tri_state_bridge_0_avalon_slave_arb_winner;
  wire             tri_state_bridge_0_avalon_slave_arbitration_holdoff_internal;
  wire             tri_state_bridge_0_avalon_slave_beginbursttransfer_internal;
  wire             tri_state_bridge_0_avalon_slave_begins_xfer;
  wire    [  3: 0] tri_state_bridge_0_avalon_slave_chosen_master_double_vector;
  wire    [  1: 0] tri_state_bridge_0_avalon_slave_chosen_master_rot_left;
  wire             tri_state_bridge_0_avalon_slave_end_xfer;
  wire             tri_state_bridge_0_avalon_slave_firsttransfer;
  wire    [  1: 0] tri_state_bridge_0_avalon_slave_grant_vector;
  wire    [  1: 0] tri_state_bridge_0_avalon_slave_master_qreq_vector;
  wire             tri_state_bridge_0_avalon_slave_non_bursting_master_requests;
  wire             tri_state_bridge_0_avalon_slave_read_pending;
  reg              tri_state_bridge_0_avalon_slave_reg_firsttransfer;
  reg     [  1: 0] tri_state_bridge_0_avalon_slave_saved_chosen_master_vector;
  reg              tri_state_bridge_0_avalon_slave_slavearbiterlockenable;
  wire             tri_state_bridge_0_avalon_slave_slavearbiterlockenable2;
  wire             tri_state_bridge_0_avalon_slave_unreg_firsttransfer;
  wire             tri_state_bridge_0_avalon_slave_write_pending;
  wire    [  7: 0] tri_state_bridge_0_data;
  reg              tri_state_bridge_0_readn /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON"  */;
  wire             wait_for_cfi_flash_0_s1_counter;
  reg              write_n_to_the_cfi_flash_0 /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON"  */;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~tri_state_bridge_0_avalon_slave_end_xfer;
    end


  assign tri_state_bridge_0_avalon_slave_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1 | system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1));
  assign system_0_burst_2_downstream_requests_cfi_flash_0_s1 = (1) & (system_0_burst_2_downstream_read | system_0_burst_2_downstream_write);
  //~select_n_to_the_cfi_flash_0 of type chipselect to ~p1_select_n_to_the_cfi_flash_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          select_n_to_the_cfi_flash_0 <= ~0;
      else 
        select_n_to_the_cfi_flash_0 <= p1_select_n_to_the_cfi_flash_0;
    end


  assign tri_state_bridge_0_avalon_slave_write_pending = 0;
  //tri_state_bridge_0/avalon_slave read pending calc, which is an e_assign
  assign tri_state_bridge_0_avalon_slave_read_pending = 0;

  //tri_state_bridge_0_avalon_slave_arb_share_counter set values, which is an e_mux
  assign tri_state_bridge_0_avalon_slave_arb_share_set_values = (system_0_burst_2_downstream_granted_cfi_flash_0_s1)? system_0_burst_2_downstream_arbitrationshare :
    (system_0_burst_3_downstream_granted_cfi_flash_0_s1)? system_0_burst_3_downstream_arbitrationshare :
    (system_0_burst_2_downstream_granted_cfi_flash_0_s1)? system_0_burst_2_downstream_arbitrationshare :
    (system_0_burst_3_downstream_granted_cfi_flash_0_s1)? system_0_burst_3_downstream_arbitrationshare :
    1;

  //tri_state_bridge_0_avalon_slave_non_bursting_master_requests mux, which is an e_mux
  assign tri_state_bridge_0_avalon_slave_non_bursting_master_requests = 0;

  //tri_state_bridge_0_avalon_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign tri_state_bridge_0_avalon_slave_any_bursting_master_saved_grant = system_0_burst_2_downstream_saved_grant_cfi_flash_0_s1 |
    system_0_burst_3_downstream_saved_grant_cfi_flash_0_s1 |
    system_0_burst_2_downstream_saved_grant_cfi_flash_0_s1 |
    system_0_burst_3_downstream_saved_grant_cfi_flash_0_s1;

  //tri_state_bridge_0_avalon_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign tri_state_bridge_0_avalon_slave_arb_share_counter_next_value = tri_state_bridge_0_avalon_slave_firsttransfer ? (tri_state_bridge_0_avalon_slave_arb_share_set_values - 1) : |tri_state_bridge_0_avalon_slave_arb_share_counter ? (tri_state_bridge_0_avalon_slave_arb_share_counter - 1) : 0;

  //tri_state_bridge_0_avalon_slave_allgrants all slave grants, which is an e_mux
  assign tri_state_bridge_0_avalon_slave_allgrants = (|tri_state_bridge_0_avalon_slave_grant_vector) |
    (|tri_state_bridge_0_avalon_slave_grant_vector) |
    (|tri_state_bridge_0_avalon_slave_grant_vector) |
    (|tri_state_bridge_0_avalon_slave_grant_vector);

  //tri_state_bridge_0_avalon_slave_end_xfer assignment, which is an e_assign
  assign tri_state_bridge_0_avalon_slave_end_xfer = ~(cfi_flash_0_s1_waits_for_read | cfi_flash_0_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_tri_state_bridge_0_avalon_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_tri_state_bridge_0_avalon_slave = tri_state_bridge_0_avalon_slave_end_xfer & (~tri_state_bridge_0_avalon_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //tri_state_bridge_0_avalon_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign tri_state_bridge_0_avalon_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_tri_state_bridge_0_avalon_slave & tri_state_bridge_0_avalon_slave_allgrants) | (end_xfer_arb_share_counter_term_tri_state_bridge_0_avalon_slave & ~tri_state_bridge_0_avalon_slave_non_bursting_master_requests);

  //tri_state_bridge_0_avalon_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          tri_state_bridge_0_avalon_slave_arb_share_counter <= 0;
      else if (tri_state_bridge_0_avalon_slave_arb_counter_enable)
          tri_state_bridge_0_avalon_slave_arb_share_counter <= tri_state_bridge_0_avalon_slave_arb_share_counter_next_value;
    end


  //tri_state_bridge_0_avalon_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          tri_state_bridge_0_avalon_slave_slavearbiterlockenable <= 0;
      else if ((|tri_state_bridge_0_avalon_slave_master_qreq_vector & end_xfer_arb_share_counter_term_tri_state_bridge_0_avalon_slave) | (end_xfer_arb_share_counter_term_tri_state_bridge_0_avalon_slave & ~tri_state_bridge_0_avalon_slave_non_bursting_master_requests))
          tri_state_bridge_0_avalon_slave_slavearbiterlockenable <= |tri_state_bridge_0_avalon_slave_arb_share_counter_next_value;
    end


  //system_0_burst_2/downstream tri_state_bridge_0/avalon_slave arbiterlock, which is an e_assign
  assign system_0_burst_2_downstream_arbiterlock = tri_state_bridge_0_avalon_slave_slavearbiterlockenable & system_0_burst_2_downstream_continuerequest;

  //tri_state_bridge_0_avalon_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign tri_state_bridge_0_avalon_slave_slavearbiterlockenable2 = |tri_state_bridge_0_avalon_slave_arb_share_counter_next_value;

  //system_0_burst_2/downstream tri_state_bridge_0/avalon_slave arbiterlock2, which is an e_assign
  assign system_0_burst_2_downstream_arbiterlock2 = tri_state_bridge_0_avalon_slave_slavearbiterlockenable2 & system_0_burst_2_downstream_continuerequest;

  //system_0_burst_3/downstream tri_state_bridge_0/avalon_slave arbiterlock, which is an e_assign
  assign system_0_burst_3_downstream_arbiterlock = tri_state_bridge_0_avalon_slave_slavearbiterlockenable & system_0_burst_3_downstream_continuerequest;

  //system_0_burst_3/downstream tri_state_bridge_0/avalon_slave arbiterlock2, which is an e_assign
  assign system_0_burst_3_downstream_arbiterlock2 = tri_state_bridge_0_avalon_slave_slavearbiterlockenable2 & system_0_burst_3_downstream_continuerequest;

  //system_0_burst_3/downstream granted cfi_flash_0/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_system_0_burst_3_downstream_granted_slave_cfi_flash_0_s1 <= 0;
      else 
        last_cycle_system_0_burst_3_downstream_granted_slave_cfi_flash_0_s1 <= system_0_burst_3_downstream_saved_grant_cfi_flash_0_s1 ? 1 : (tri_state_bridge_0_avalon_slave_arbitration_holdoff_internal | 0) ? 0 : last_cycle_system_0_burst_3_downstream_granted_slave_cfi_flash_0_s1;
    end


  //system_0_burst_3_downstream_continuerequest continued request, which is an e_mux
  assign system_0_burst_3_downstream_continuerequest = last_cycle_system_0_burst_3_downstream_granted_slave_cfi_flash_0_s1 & 1;

  //tri_state_bridge_0_avalon_slave_any_continuerequest at least one master continues requesting, which is an e_mux
  assign tri_state_bridge_0_avalon_slave_any_continuerequest = system_0_burst_3_downstream_continuerequest |
    system_0_burst_2_downstream_continuerequest;

  assign system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1 = system_0_burst_2_downstream_requests_cfi_flash_0_s1 & ~((system_0_burst_2_downstream_read & (tri_state_bridge_0_avalon_slave_write_pending | (tri_state_bridge_0_avalon_slave_read_pending))) | ((tri_state_bridge_0_avalon_slave_read_pending) & system_0_burst_2_downstream_write) | system_0_burst_3_downstream_arbiterlock);
  //system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  assign system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1_shift_register_in = system_0_burst_2_downstream_granted_cfi_flash_0_s1 & system_0_burst_2_downstream_read & ~cfi_flash_0_s1_waits_for_read;

  //shift register p1 system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1_shift_register = {system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1_shift_register, system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1_shift_register_in};

  //system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1_shift_register <= 0;
      else 
        system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1_shift_register <= p1_system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1_shift_register;
    end


  //local readdatavalid system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1, which is an e_mux
  assign system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1 = system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1_shift_register[1];

  //tri_state_bridge_0_data register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          incoming_tri_state_bridge_0_data <= 0;
      else 
        incoming_tri_state_bridge_0_data <= tri_state_bridge_0_data;
    end


  //cfi_flash_0_s1_with_write_latency assignment, which is an e_assign
  assign cfi_flash_0_s1_with_write_latency = in_a_write_cycle & (system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1 | system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1);

  //time to write the data, which is an e_mux
  assign time_to_write = (cfi_flash_0_s1_with_write_latency)? 1 :
    (cfi_flash_0_s1_with_write_latency)? 1 :
    0;

  //d1_outgoing_tri_state_bridge_0_data register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_outgoing_tri_state_bridge_0_data <= 0;
      else 
        d1_outgoing_tri_state_bridge_0_data <= outgoing_tri_state_bridge_0_data;
    end


  //write cycle delayed by 1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_in_a_write_cycle <= 0;
      else 
        d1_in_a_write_cycle <= time_to_write;
    end


  //d1_outgoing_tri_state_bridge_0_data tristate driver, which is an e_assign
  assign tri_state_bridge_0_data = (d1_in_a_write_cycle)? d1_outgoing_tri_state_bridge_0_data:{8{1'bz}};

  //outgoing_tri_state_bridge_0_data mux, which is an e_mux
  assign outgoing_tri_state_bridge_0_data = (system_0_burst_2_downstream_granted_cfi_flash_0_s1)? system_0_burst_2_downstream_writedata :
    system_0_burst_3_downstream_writedata;

  assign system_0_burst_3_downstream_requests_cfi_flash_0_s1 = (1) & (system_0_burst_3_downstream_read | system_0_burst_3_downstream_write);
  //system_0_burst_2/downstream granted cfi_flash_0/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_system_0_burst_2_downstream_granted_slave_cfi_flash_0_s1 <= 0;
      else 
        last_cycle_system_0_burst_2_downstream_granted_slave_cfi_flash_0_s1 <= system_0_burst_2_downstream_saved_grant_cfi_flash_0_s1 ? 1 : (tri_state_bridge_0_avalon_slave_arbitration_holdoff_internal | 0) ? 0 : last_cycle_system_0_burst_2_downstream_granted_slave_cfi_flash_0_s1;
    end


  //system_0_burst_2_downstream_continuerequest continued request, which is an e_mux
  assign system_0_burst_2_downstream_continuerequest = last_cycle_system_0_burst_2_downstream_granted_slave_cfi_flash_0_s1 & 1;

  assign system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1 = system_0_burst_3_downstream_requests_cfi_flash_0_s1 & ~((system_0_burst_3_downstream_read & (tri_state_bridge_0_avalon_slave_write_pending | (tri_state_bridge_0_avalon_slave_read_pending))) | ((tri_state_bridge_0_avalon_slave_read_pending) & system_0_burst_3_downstream_write) | system_0_burst_2_downstream_arbiterlock);
  //system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  assign system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1_shift_register_in = system_0_burst_3_downstream_granted_cfi_flash_0_s1 & system_0_burst_3_downstream_read & ~cfi_flash_0_s1_waits_for_read;

  //shift register p1 system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1_shift_register = {system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1_shift_register, system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1_shift_register_in};

  //system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1_shift_register <= 0;
      else 
        system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1_shift_register <= p1_system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1_shift_register;
    end


  //local readdatavalid system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1, which is an e_mux
  assign system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1 = system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1_shift_register[1];

  //allow new arb cycle for tri_state_bridge_0/avalon_slave, which is an e_assign
  assign tri_state_bridge_0_avalon_slave_allow_new_arb_cycle = ~system_0_burst_2_downstream_arbiterlock & ~system_0_burst_3_downstream_arbiterlock;

  //system_0_burst_3/downstream assignment into master qualified-requests vector for cfi_flash_0/s1, which is an e_assign
  assign tri_state_bridge_0_avalon_slave_master_qreq_vector[0] = system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1;

  //system_0_burst_3/downstream grant cfi_flash_0/s1, which is an e_assign
  assign system_0_burst_3_downstream_granted_cfi_flash_0_s1 = tri_state_bridge_0_avalon_slave_grant_vector[0];

  //system_0_burst_3/downstream saved-grant cfi_flash_0/s1, which is an e_assign
  assign system_0_burst_3_downstream_saved_grant_cfi_flash_0_s1 = tri_state_bridge_0_avalon_slave_arb_winner[0];

  //system_0_burst_2/downstream assignment into master qualified-requests vector for cfi_flash_0/s1, which is an e_assign
  assign tri_state_bridge_0_avalon_slave_master_qreq_vector[1] = system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1;

  //system_0_burst_2/downstream grant cfi_flash_0/s1, which is an e_assign
  assign system_0_burst_2_downstream_granted_cfi_flash_0_s1 = tri_state_bridge_0_avalon_slave_grant_vector[1];

  //system_0_burst_2/downstream saved-grant cfi_flash_0/s1, which is an e_assign
  assign system_0_burst_2_downstream_saved_grant_cfi_flash_0_s1 = tri_state_bridge_0_avalon_slave_arb_winner[1];

  //tri_state_bridge_0/avalon_slave chosen-master double-vector, which is an e_assign
  assign tri_state_bridge_0_avalon_slave_chosen_master_double_vector = {tri_state_bridge_0_avalon_slave_master_qreq_vector, tri_state_bridge_0_avalon_slave_master_qreq_vector} & ({~tri_state_bridge_0_avalon_slave_master_qreq_vector, ~tri_state_bridge_0_avalon_slave_master_qreq_vector} + tri_state_bridge_0_avalon_slave_arb_addend);

  //stable onehot encoding of arb winner
  assign tri_state_bridge_0_avalon_slave_arb_winner = (tri_state_bridge_0_avalon_slave_allow_new_arb_cycle & | tri_state_bridge_0_avalon_slave_grant_vector) ? tri_state_bridge_0_avalon_slave_grant_vector : tri_state_bridge_0_avalon_slave_saved_chosen_master_vector;

  //saved tri_state_bridge_0_avalon_slave_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          tri_state_bridge_0_avalon_slave_saved_chosen_master_vector <= 0;
      else if (tri_state_bridge_0_avalon_slave_allow_new_arb_cycle)
          tri_state_bridge_0_avalon_slave_saved_chosen_master_vector <= |tri_state_bridge_0_avalon_slave_grant_vector ? tri_state_bridge_0_avalon_slave_grant_vector : tri_state_bridge_0_avalon_slave_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign tri_state_bridge_0_avalon_slave_grant_vector = {(tri_state_bridge_0_avalon_slave_chosen_master_double_vector[1] | tri_state_bridge_0_avalon_slave_chosen_master_double_vector[3]),
    (tri_state_bridge_0_avalon_slave_chosen_master_double_vector[0] | tri_state_bridge_0_avalon_slave_chosen_master_double_vector[2])};

  //tri_state_bridge_0/avalon_slave chosen master rotated left, which is an e_assign
  assign tri_state_bridge_0_avalon_slave_chosen_master_rot_left = (tri_state_bridge_0_avalon_slave_arb_winner << 1) ? (tri_state_bridge_0_avalon_slave_arb_winner << 1) : 1;

  //tri_state_bridge_0/avalon_slave's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          tri_state_bridge_0_avalon_slave_arb_addend <= 1;
      else if (|tri_state_bridge_0_avalon_slave_grant_vector)
          tri_state_bridge_0_avalon_slave_arb_addend <= tri_state_bridge_0_avalon_slave_end_xfer? tri_state_bridge_0_avalon_slave_chosen_master_rot_left : tri_state_bridge_0_avalon_slave_grant_vector;
    end


  assign p1_select_n_to_the_cfi_flash_0 = ~(system_0_burst_2_downstream_granted_cfi_flash_0_s1 | system_0_burst_3_downstream_granted_cfi_flash_0_s1);
  //tri_state_bridge_0_avalon_slave_firsttransfer first transaction, which is an e_assign
  assign tri_state_bridge_0_avalon_slave_firsttransfer = tri_state_bridge_0_avalon_slave_begins_xfer ? tri_state_bridge_0_avalon_slave_unreg_firsttransfer : tri_state_bridge_0_avalon_slave_reg_firsttransfer;

  //tri_state_bridge_0_avalon_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign tri_state_bridge_0_avalon_slave_unreg_firsttransfer = ~(tri_state_bridge_0_avalon_slave_slavearbiterlockenable & tri_state_bridge_0_avalon_slave_any_continuerequest);

  //tri_state_bridge_0_avalon_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          tri_state_bridge_0_avalon_slave_reg_firsttransfer <= 1'b1;
      else if (tri_state_bridge_0_avalon_slave_begins_xfer)
          tri_state_bridge_0_avalon_slave_reg_firsttransfer <= tri_state_bridge_0_avalon_slave_unreg_firsttransfer;
    end


  //tri_state_bridge_0_avalon_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign tri_state_bridge_0_avalon_slave_beginbursttransfer_internal = tri_state_bridge_0_avalon_slave_begins_xfer;

  //tri_state_bridge_0_avalon_slave_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign tri_state_bridge_0_avalon_slave_arbitration_holdoff_internal = tri_state_bridge_0_avalon_slave_begins_xfer & tri_state_bridge_0_avalon_slave_firsttransfer;

  //~tri_state_bridge_0_readn of type read to ~p1_tri_state_bridge_0_readn, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          tri_state_bridge_0_readn <= ~0;
      else 
        tri_state_bridge_0_readn <= p1_tri_state_bridge_0_readn;
    end


  //~p1_tri_state_bridge_0_readn assignment, which is an e_mux
  assign p1_tri_state_bridge_0_readn = ~(((system_0_burst_2_downstream_granted_cfi_flash_0_s1 & system_0_burst_2_downstream_read) | (system_0_burst_3_downstream_granted_cfi_flash_0_s1 & system_0_burst_3_downstream_read))& ~tri_state_bridge_0_avalon_slave_begins_xfer & (cfi_flash_0_s1_wait_counter < 16));

  //~write_n_to_the_cfi_flash_0 of type write to ~p1_write_n_to_the_cfi_flash_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          write_n_to_the_cfi_flash_0 <= ~0;
      else 
        write_n_to_the_cfi_flash_0 <= p1_write_n_to_the_cfi_flash_0;
    end


  //~p1_write_n_to_the_cfi_flash_0 assignment, which is an e_mux
  assign p1_write_n_to_the_cfi_flash_0 = ~(((system_0_burst_2_downstream_granted_cfi_flash_0_s1 & system_0_burst_2_downstream_write) | (system_0_burst_3_downstream_granted_cfi_flash_0_s1 & system_0_burst_3_downstream_write)) & ~tri_state_bridge_0_avalon_slave_begins_xfer & (cfi_flash_0_s1_wait_counter >= 4) & (cfi_flash_0_s1_wait_counter < 20) & cfi_flash_0_s1_pretend_byte_enable);

  //tri_state_bridge_0_address of type address to p1_tri_state_bridge_0_address, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          tri_state_bridge_0_address <= 0;
      else 
        tri_state_bridge_0_address <= p1_tri_state_bridge_0_address;
    end


  //p1_tri_state_bridge_0_address mux, which is an e_mux
  assign p1_tri_state_bridge_0_address = (system_0_burst_2_downstream_granted_cfi_flash_0_s1)? system_0_burst_2_downstream_address_to_slave :
    system_0_burst_3_downstream_address_to_slave;

  //d1_tri_state_bridge_0_avalon_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_tri_state_bridge_0_avalon_slave_end_xfer <= 1;
      else 
        d1_tri_state_bridge_0_avalon_slave_end_xfer <= tri_state_bridge_0_avalon_slave_end_xfer;
    end


  //cfi_flash_0_s1_waits_for_read in a cycle, which is an e_mux
  assign cfi_flash_0_s1_waits_for_read = cfi_flash_0_s1_in_a_read_cycle & wait_for_cfi_flash_0_s1_counter;

  //cfi_flash_0_s1_in_a_read_cycle assignment, which is an e_assign
  assign cfi_flash_0_s1_in_a_read_cycle = (system_0_burst_2_downstream_granted_cfi_flash_0_s1 & system_0_burst_2_downstream_read) | (system_0_burst_3_downstream_granted_cfi_flash_0_s1 & system_0_burst_3_downstream_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = cfi_flash_0_s1_in_a_read_cycle;

  //cfi_flash_0_s1_waits_for_write in a cycle, which is an e_mux
  assign cfi_flash_0_s1_waits_for_write = cfi_flash_0_s1_in_a_write_cycle & wait_for_cfi_flash_0_s1_counter;

  //cfi_flash_0_s1_in_a_write_cycle assignment, which is an e_assign
  assign cfi_flash_0_s1_in_a_write_cycle = (system_0_burst_2_downstream_granted_cfi_flash_0_s1 & system_0_burst_2_downstream_write) | (system_0_burst_3_downstream_granted_cfi_flash_0_s1 & system_0_burst_3_downstream_write);

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = cfi_flash_0_s1_in_a_write_cycle;

  assign cfi_flash_0_s1_wait_counter_eq_0 = cfi_flash_0_s1_wait_counter == 0;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cfi_flash_0_s1_wait_counter <= 0;
      else 
        cfi_flash_0_s1_wait_counter <= cfi_flash_0_s1_counter_load_value;
    end


  assign cfi_flash_0_s1_counter_load_value = ((cfi_flash_0_s1_in_a_write_cycle & tri_state_bridge_0_avalon_slave_begins_xfer))? 22 :
    ((cfi_flash_0_s1_in_a_read_cycle & tri_state_bridge_0_avalon_slave_begins_xfer))? 18 :
    (~cfi_flash_0_s1_wait_counter_eq_0)? cfi_flash_0_s1_wait_counter - 1 :
    0;

  assign wait_for_cfi_flash_0_s1_counter = tri_state_bridge_0_avalon_slave_begins_xfer | ~cfi_flash_0_s1_wait_counter_eq_0;
  //cfi_flash_0_s1_pretend_byte_enable byte enable port mux, which is an e_mux
  assign cfi_flash_0_s1_pretend_byte_enable = (system_0_burst_2_downstream_granted_cfi_flash_0_s1)? system_0_burst_2_downstream_byteenable :
    (system_0_burst_3_downstream_granted_cfi_flash_0_s1)? system_0_burst_3_downstream_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //incoming_tri_state_bridge_0_data_bit_0_is_x x check, which is an e_assign_is_x
  assign incoming_tri_state_bridge_0_data_bit_0_is_x = ^(incoming_tri_state_bridge_0_data[0]) === 1'bx;

  //Crush incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[0] Xs to 0, which is an e_assign
  assign incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[0] = incoming_tri_state_bridge_0_data_bit_0_is_x ? 1'b0 : incoming_tri_state_bridge_0_data[0];

  //incoming_tri_state_bridge_0_data_bit_1_is_x x check, which is an e_assign_is_x
  assign incoming_tri_state_bridge_0_data_bit_1_is_x = ^(incoming_tri_state_bridge_0_data[1]) === 1'bx;

  //Crush incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[1] Xs to 0, which is an e_assign
  assign incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[1] = incoming_tri_state_bridge_0_data_bit_1_is_x ? 1'b0 : incoming_tri_state_bridge_0_data[1];

  //incoming_tri_state_bridge_0_data_bit_2_is_x x check, which is an e_assign_is_x
  assign incoming_tri_state_bridge_0_data_bit_2_is_x = ^(incoming_tri_state_bridge_0_data[2]) === 1'bx;

  //Crush incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[2] Xs to 0, which is an e_assign
  assign incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[2] = incoming_tri_state_bridge_0_data_bit_2_is_x ? 1'b0 : incoming_tri_state_bridge_0_data[2];

  //incoming_tri_state_bridge_0_data_bit_3_is_x x check, which is an e_assign_is_x
  assign incoming_tri_state_bridge_0_data_bit_3_is_x = ^(incoming_tri_state_bridge_0_data[3]) === 1'bx;

  //Crush incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[3] Xs to 0, which is an e_assign
  assign incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[3] = incoming_tri_state_bridge_0_data_bit_3_is_x ? 1'b0 : incoming_tri_state_bridge_0_data[3];

  //incoming_tri_state_bridge_0_data_bit_4_is_x x check, which is an e_assign_is_x
  assign incoming_tri_state_bridge_0_data_bit_4_is_x = ^(incoming_tri_state_bridge_0_data[4]) === 1'bx;

  //Crush incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[4] Xs to 0, which is an e_assign
  assign incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[4] = incoming_tri_state_bridge_0_data_bit_4_is_x ? 1'b0 : incoming_tri_state_bridge_0_data[4];

  //incoming_tri_state_bridge_0_data_bit_5_is_x x check, which is an e_assign_is_x
  assign incoming_tri_state_bridge_0_data_bit_5_is_x = ^(incoming_tri_state_bridge_0_data[5]) === 1'bx;

  //Crush incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[5] Xs to 0, which is an e_assign
  assign incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[5] = incoming_tri_state_bridge_0_data_bit_5_is_x ? 1'b0 : incoming_tri_state_bridge_0_data[5];

  //incoming_tri_state_bridge_0_data_bit_6_is_x x check, which is an e_assign_is_x
  assign incoming_tri_state_bridge_0_data_bit_6_is_x = ^(incoming_tri_state_bridge_0_data[6]) === 1'bx;

  //Crush incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[6] Xs to 0, which is an e_assign
  assign incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[6] = incoming_tri_state_bridge_0_data_bit_6_is_x ? 1'b0 : incoming_tri_state_bridge_0_data[6];

  //incoming_tri_state_bridge_0_data_bit_7_is_x x check, which is an e_assign_is_x
  assign incoming_tri_state_bridge_0_data_bit_7_is_x = ^(incoming_tri_state_bridge_0_data[7]) === 1'bx;

  //Crush incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[7] Xs to 0, which is an e_assign
  assign incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[7] = incoming_tri_state_bridge_0_data_bit_7_is_x ? 1'b0 : incoming_tri_state_bridge_0_data[7];

  //cfi_flash_0/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_2/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_2_downstream_requests_cfi_flash_0_s1 && (system_0_burst_2_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_2/downstream drove 0 on its 'arbitrationshare' port while accessing slave cfi_flash_0/s1", $time);
          $stop;
        end
    end


  //system_0_burst_2/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_2_downstream_requests_cfi_flash_0_s1 && (system_0_burst_2_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_2/downstream drove 0 on its 'burstcount' port while accessing slave cfi_flash_0/s1", $time);
          $stop;
        end
    end


  //system_0_burst_3/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_3_downstream_requests_cfi_flash_0_s1 && (system_0_burst_3_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_3/downstream drove 0 on its 'arbitrationshare' port while accessing slave cfi_flash_0/s1", $time);
          $stop;
        end
    end


  //system_0_burst_3/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_3_downstream_requests_cfi_flash_0_s1 && (system_0_burst_3_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_3/downstream drove 0 on its 'burstcount' port while accessing slave cfi_flash_0/s1", $time);
          $stop;
        end
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_2_downstream_granted_cfi_flash_0_s1 + system_0_burst_3_downstream_granted_cfi_flash_0_s1 > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_2_downstream_saved_grant_cfi_flash_0_s1 + system_0_burst_3_downstream_saved_grant_cfi_flash_0_s1 > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  
//  assign incoming_tri_state_bridge_0_data_with_Xs_converted_to_0 = incoming_tri_state_bridge_0_data;
//
//synthesis read_comments_as_HDL off

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module tri_state_bridge_0_bridge_arbitrator 
;



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module uart_0_s1_arbitrator (
                              // inputs:
                               clk,
                               reset_n,
                               system_0_burst_9_downstream_address_to_slave,
                               system_0_burst_9_downstream_arbitrationshare,
                               system_0_burst_9_downstream_burstcount,
                               system_0_burst_9_downstream_latency_counter,
                               system_0_burst_9_downstream_nativeaddress,
                               system_0_burst_9_downstream_read,
                               system_0_burst_9_downstream_write,
                               system_0_burst_9_downstream_writedata,
                               uart_0_s1_dataavailable,
                               uart_0_s1_irq,
                               uart_0_s1_readdata,
                               uart_0_s1_readyfordata,

                              // outputs:
                               d1_uart_0_s1_end_xfer,
                               system_0_burst_9_downstream_granted_uart_0_s1,
                               system_0_burst_9_downstream_qualified_request_uart_0_s1,
                               system_0_burst_9_downstream_read_data_valid_uart_0_s1,
                               system_0_burst_9_downstream_requests_uart_0_s1,
                               uart_0_s1_address,
                               uart_0_s1_begintransfer,
                               uart_0_s1_chipselect,
                               uart_0_s1_dataavailable_from_sa,
                               uart_0_s1_irq_from_sa,
                               uart_0_s1_read_n,
                               uart_0_s1_readdata_from_sa,
                               uart_0_s1_readyfordata_from_sa,
                               uart_0_s1_reset_n,
                               uart_0_s1_write_n,
                               uart_0_s1_writedata
                            )
;

  output           d1_uart_0_s1_end_xfer;
  output           system_0_burst_9_downstream_granted_uart_0_s1;
  output           system_0_burst_9_downstream_qualified_request_uart_0_s1;
  output           system_0_burst_9_downstream_read_data_valid_uart_0_s1;
  output           system_0_burst_9_downstream_requests_uart_0_s1;
  output  [  2: 0] uart_0_s1_address;
  output           uart_0_s1_begintransfer;
  output           uart_0_s1_chipselect;
  output           uart_0_s1_dataavailable_from_sa;
  output           uart_0_s1_irq_from_sa;
  output           uart_0_s1_read_n;
  output  [ 15: 0] uart_0_s1_readdata_from_sa;
  output           uart_0_s1_readyfordata_from_sa;
  output           uart_0_s1_reset_n;
  output           uart_0_s1_write_n;
  output  [ 15: 0] uart_0_s1_writedata;
  input            clk;
  input            reset_n;
  input   [  3: 0] system_0_burst_9_downstream_address_to_slave;
  input   [  4: 0] system_0_burst_9_downstream_arbitrationshare;
  input            system_0_burst_9_downstream_burstcount;
  input            system_0_burst_9_downstream_latency_counter;
  input   [  3: 0] system_0_burst_9_downstream_nativeaddress;
  input            system_0_burst_9_downstream_read;
  input            system_0_burst_9_downstream_write;
  input   [ 15: 0] system_0_burst_9_downstream_writedata;
  input            uart_0_s1_dataavailable;
  input            uart_0_s1_irq;
  input   [ 15: 0] uart_0_s1_readdata;
  input            uart_0_s1_readyfordata;

  reg              d1_reasons_to_wait;
  reg              d1_uart_0_s1_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_uart_0_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             system_0_burst_9_downstream_arbiterlock;
  wire             system_0_burst_9_downstream_arbiterlock2;
  wire             system_0_burst_9_downstream_continuerequest;
  wire             system_0_burst_9_downstream_granted_uart_0_s1;
  wire             system_0_burst_9_downstream_qualified_request_uart_0_s1;
  wire             system_0_burst_9_downstream_read_data_valid_uart_0_s1;
  wire             system_0_burst_9_downstream_requests_uart_0_s1;
  wire             system_0_burst_9_downstream_saved_grant_uart_0_s1;
  wire    [  2: 0] uart_0_s1_address;
  wire             uart_0_s1_allgrants;
  wire             uart_0_s1_allow_new_arb_cycle;
  wire             uart_0_s1_any_bursting_master_saved_grant;
  wire             uart_0_s1_any_continuerequest;
  wire             uart_0_s1_arb_counter_enable;
  reg     [  4: 0] uart_0_s1_arb_share_counter;
  wire    [  4: 0] uart_0_s1_arb_share_counter_next_value;
  wire    [  4: 0] uart_0_s1_arb_share_set_values;
  wire             uart_0_s1_beginbursttransfer_internal;
  wire             uart_0_s1_begins_xfer;
  wire             uart_0_s1_begintransfer;
  wire             uart_0_s1_chipselect;
  wire             uart_0_s1_dataavailable_from_sa;
  wire             uart_0_s1_end_xfer;
  wire             uart_0_s1_firsttransfer;
  wire             uart_0_s1_grant_vector;
  wire             uart_0_s1_in_a_read_cycle;
  wire             uart_0_s1_in_a_write_cycle;
  wire             uart_0_s1_irq_from_sa;
  wire             uart_0_s1_master_qreq_vector;
  wire             uart_0_s1_non_bursting_master_requests;
  wire             uart_0_s1_read_n;
  wire    [ 15: 0] uart_0_s1_readdata_from_sa;
  wire             uart_0_s1_readyfordata_from_sa;
  reg              uart_0_s1_reg_firsttransfer;
  wire             uart_0_s1_reset_n;
  reg              uart_0_s1_slavearbiterlockenable;
  wire             uart_0_s1_slavearbiterlockenable2;
  wire             uart_0_s1_unreg_firsttransfer;
  wire             uart_0_s1_waits_for_read;
  wire             uart_0_s1_waits_for_write;
  wire             uart_0_s1_write_n;
  wire    [ 15: 0] uart_0_s1_writedata;
  wire             wait_for_uart_0_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~uart_0_s1_end_xfer;
    end


  assign uart_0_s1_begins_xfer = ~d1_reasons_to_wait & ((system_0_burst_9_downstream_qualified_request_uart_0_s1));
  //assign uart_0_s1_readdata_from_sa = uart_0_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign uart_0_s1_readdata_from_sa = uart_0_s1_readdata;

  assign system_0_burst_9_downstream_requests_uart_0_s1 = (1) & (system_0_burst_9_downstream_read | system_0_burst_9_downstream_write);
  //assign uart_0_s1_dataavailable_from_sa = uart_0_s1_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign uart_0_s1_dataavailable_from_sa = uart_0_s1_dataavailable;

  //assign uart_0_s1_readyfordata_from_sa = uart_0_s1_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign uart_0_s1_readyfordata_from_sa = uart_0_s1_readyfordata;

  //uart_0_s1_arb_share_counter set values, which is an e_mux
  assign uart_0_s1_arb_share_set_values = (system_0_burst_9_downstream_granted_uart_0_s1)? system_0_burst_9_downstream_arbitrationshare :
    1;

  //uart_0_s1_non_bursting_master_requests mux, which is an e_mux
  assign uart_0_s1_non_bursting_master_requests = 0;

  //uart_0_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign uart_0_s1_any_bursting_master_saved_grant = system_0_burst_9_downstream_saved_grant_uart_0_s1;

  //uart_0_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign uart_0_s1_arb_share_counter_next_value = uart_0_s1_firsttransfer ? (uart_0_s1_arb_share_set_values - 1) : |uart_0_s1_arb_share_counter ? (uart_0_s1_arb_share_counter - 1) : 0;

  //uart_0_s1_allgrants all slave grants, which is an e_mux
  assign uart_0_s1_allgrants = |uart_0_s1_grant_vector;

  //uart_0_s1_end_xfer assignment, which is an e_assign
  assign uart_0_s1_end_xfer = ~(uart_0_s1_waits_for_read | uart_0_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_uart_0_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_uart_0_s1 = uart_0_s1_end_xfer & (~uart_0_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //uart_0_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign uart_0_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_uart_0_s1 & uart_0_s1_allgrants) | (end_xfer_arb_share_counter_term_uart_0_s1 & ~uart_0_s1_non_bursting_master_requests);

  //uart_0_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          uart_0_s1_arb_share_counter <= 0;
      else if (uart_0_s1_arb_counter_enable)
          uart_0_s1_arb_share_counter <= uart_0_s1_arb_share_counter_next_value;
    end


  //uart_0_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          uart_0_s1_slavearbiterlockenable <= 0;
      else if ((|uart_0_s1_master_qreq_vector & end_xfer_arb_share_counter_term_uart_0_s1) | (end_xfer_arb_share_counter_term_uart_0_s1 & ~uart_0_s1_non_bursting_master_requests))
          uart_0_s1_slavearbiterlockenable <= |uart_0_s1_arb_share_counter_next_value;
    end


  //system_0_burst_9/downstream uart_0/s1 arbiterlock, which is an e_assign
  assign system_0_burst_9_downstream_arbiterlock = uart_0_s1_slavearbiterlockenable & system_0_burst_9_downstream_continuerequest;

  //uart_0_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign uart_0_s1_slavearbiterlockenable2 = |uart_0_s1_arb_share_counter_next_value;

  //system_0_burst_9/downstream uart_0/s1 arbiterlock2, which is an e_assign
  assign system_0_burst_9_downstream_arbiterlock2 = uart_0_s1_slavearbiterlockenable2 & system_0_burst_9_downstream_continuerequest;

  //uart_0_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign uart_0_s1_any_continuerequest = 1;

  //system_0_burst_9_downstream_continuerequest continued request, which is an e_assign
  assign system_0_burst_9_downstream_continuerequest = 1;

  assign system_0_burst_9_downstream_qualified_request_uart_0_s1 = system_0_burst_9_downstream_requests_uart_0_s1 & ~((system_0_burst_9_downstream_read & ((system_0_burst_9_downstream_latency_counter != 0))));
  //local readdatavalid system_0_burst_9_downstream_read_data_valid_uart_0_s1, which is an e_mux
  assign system_0_burst_9_downstream_read_data_valid_uart_0_s1 = system_0_burst_9_downstream_granted_uart_0_s1 & system_0_burst_9_downstream_read & ~uart_0_s1_waits_for_read;

  //uart_0_s1_writedata mux, which is an e_mux
  assign uart_0_s1_writedata = system_0_burst_9_downstream_writedata;

  //master is always granted when requested
  assign system_0_burst_9_downstream_granted_uart_0_s1 = system_0_burst_9_downstream_qualified_request_uart_0_s1;

  //system_0_burst_9/downstream saved-grant uart_0/s1, which is an e_assign
  assign system_0_burst_9_downstream_saved_grant_uart_0_s1 = system_0_burst_9_downstream_requests_uart_0_s1;

  //allow new arb cycle for uart_0/s1, which is an e_assign
  assign uart_0_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign uart_0_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign uart_0_s1_master_qreq_vector = 1;

  assign uart_0_s1_begintransfer = uart_0_s1_begins_xfer;
  //uart_0_s1_reset_n assignment, which is an e_assign
  assign uart_0_s1_reset_n = reset_n;

  assign uart_0_s1_chipselect = system_0_burst_9_downstream_granted_uart_0_s1;
  //uart_0_s1_firsttransfer first transaction, which is an e_assign
  assign uart_0_s1_firsttransfer = uart_0_s1_begins_xfer ? uart_0_s1_unreg_firsttransfer : uart_0_s1_reg_firsttransfer;

  //uart_0_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign uart_0_s1_unreg_firsttransfer = ~(uart_0_s1_slavearbiterlockenable & uart_0_s1_any_continuerequest);

  //uart_0_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          uart_0_s1_reg_firsttransfer <= 1'b1;
      else if (uart_0_s1_begins_xfer)
          uart_0_s1_reg_firsttransfer <= uart_0_s1_unreg_firsttransfer;
    end


  //uart_0_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign uart_0_s1_beginbursttransfer_internal = uart_0_s1_begins_xfer;

  //~uart_0_s1_read_n assignment, which is an e_mux
  assign uart_0_s1_read_n = ~(system_0_burst_9_downstream_granted_uart_0_s1 & system_0_burst_9_downstream_read);

  //~uart_0_s1_write_n assignment, which is an e_mux
  assign uart_0_s1_write_n = ~(system_0_burst_9_downstream_granted_uart_0_s1 & system_0_burst_9_downstream_write);

  //uart_0_s1_address mux, which is an e_mux
  assign uart_0_s1_address = system_0_burst_9_downstream_nativeaddress;

  //d1_uart_0_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_uart_0_s1_end_xfer <= 1;
      else 
        d1_uart_0_s1_end_xfer <= uart_0_s1_end_xfer;
    end


  //uart_0_s1_waits_for_read in a cycle, which is an e_mux
  assign uart_0_s1_waits_for_read = uart_0_s1_in_a_read_cycle & uart_0_s1_begins_xfer;

  //uart_0_s1_in_a_read_cycle assignment, which is an e_assign
  assign uart_0_s1_in_a_read_cycle = system_0_burst_9_downstream_granted_uart_0_s1 & system_0_burst_9_downstream_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = uart_0_s1_in_a_read_cycle;

  //uart_0_s1_waits_for_write in a cycle, which is an e_mux
  assign uart_0_s1_waits_for_write = uart_0_s1_in_a_write_cycle & uart_0_s1_begins_xfer;

  //uart_0_s1_in_a_write_cycle assignment, which is an e_assign
  assign uart_0_s1_in_a_write_cycle = system_0_burst_9_downstream_granted_uart_0_s1 & system_0_burst_9_downstream_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = uart_0_s1_in_a_write_cycle;

  assign wait_for_uart_0_s1_counter = 0;
  //assign uart_0_s1_irq_from_sa = uart_0_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign uart_0_s1_irq_from_sa = uart_0_s1_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //uart_0/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //system_0_burst_9/downstream non-zero arbitrationshare assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_9_downstream_requests_uart_0_s1 && (system_0_burst_9_downstream_arbitrationshare == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_9/downstream drove 0 on its 'arbitrationshare' port while accessing slave uart_0/s1", $time);
          $stop;
        end
    end


  //system_0_burst_9/downstream non-zero burstcount assertion, which is an e_process
  always @(posedge clk)
    begin
      if (system_0_burst_9_downstream_requests_uart_0_s1 && (system_0_burst_9_downstream_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: system_0_burst_9/downstream drove 0 on its 'burstcount' port while accessing slave uart_0/s1", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_reset_altpll_0_c1_out_domain_synch_module (
                                                            // inputs:
                                                             clk,
                                                             data_in,
                                                             reset_n,

                                                            // outputs:
                                                             data_out
                                                          )
;

  output           data_out;
  input            clk;
  input            data_in;
  input            reset_n;

  reg              data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  reg              data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_in_d1 <= 0;
      else 
        data_in_d1 <= data_in;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_out <= 0;
      else 
        data_out <= data_in_d1;
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0_reset_clk_domain_synch_module (
                                                // inputs:
                                                 clk,
                                                 data_in,
                                                 reset_n,

                                                // outputs:
                                                 data_out
                                              )
;

  output           data_out;
  input            clk;
  input            data_in;
  input            reset_n;

  reg              data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  reg              data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_in_d1 <= 0;
      else 
        data_in_d1 <= data_in;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_out <= 0;
      else 
        data_out <= data_in_d1;
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module system_0 (
                  // 1) global signals:
                   altpll_0_c0_out,
                   altpll_0_c1_out,
                   clk,
                   reset_n,

                  // the_Accel_Control
                   interrupt2_to_the_Accel_Control,
                   scl_i2c_to_accel_from_the_Accel_Control,
                   scl_i2c_to_bus_to_the_Accel_Control,
                   sda_i2c_to_accel_to_and_from_the_Accel_Control,
                   sda_i2c_to_bus_to_and_from_the_Accel_Control,
                   sda_padoen_o_to_the_Accel_Control,

                  // the_Audio_0
                   iCLK_18_4_to_the_Audio_0,
                   oAUD_BCK_from_the_Audio_0,
                   oAUD_DATA_from_the_Audio_0,
                   oAUD_LRCK_from_the_Audio_0,
                   oAUD_XCK_from_the_Audio_0,

                  // the_MS
                   in_port_to_the_MS,

                  // the_Oct_DOWN
                   in_port_to_the_Oct_DOWN,

                  // the_Oct_UP
                   in_port_to_the_Oct_UP,

                  // the_RST
                   in_port_to_the_RST,

                  // the_SD_CLK
                   out_port_from_the_SD_CLK,

                  // the_SD_CMD
                   bidir_port_to_and_from_the_SD_CMD,

                  // the_SD_DAT
                   bidir_port_to_and_from_the_SD_DAT,

                  // the_SEG7_Display
                   oSEG0_from_the_SEG7_Display,
                   oSEG1_from_the_SEG7_Display,
                   oSEG2_from_the_SEG7_Display,
                   oSEG3_from_the_SEG7_Display,
                   oSEG4_from_the_SEG7_Display,
                   oSEG5_from_the_SEG7_Display,
                   oSEG6_from_the_SEG7_Display,
                   oSEG7_from_the_SEG7_Display,

                  // the_altpll_0
                   locked_from_the_altpll_0,
                   phasedone_from_the_altpll_0,

                  // the_dist_sensor
                   in_port_to_the_dist_sensor,

                  // the_i2c_master
                   scl_pad_io_from_the_i2c_master,
                   sda_pad_io_to_and_from_the_i2c_master,
                   sda_padoen_out_from_the_i2c_master,
                   wb_err_o_from_the_i2c_master,

                  // the_lcd_16207_0
                   LCD_E_from_the_lcd_16207_0,
                   LCD_RS_from_the_lcd_16207_0,
                   LCD_RW_from_the_lcd_16207_0,
                   LCD_data_to_and_from_the_lcd_16207_0,

                  // the_noteA
                   in_port_to_the_noteA,

                  // the_noteB
                   in_port_to_the_noteB,

                  // the_noteC
                   in_port_to_the_noteC,

                  // the_noteD
                   in_port_to_the_noteD,

                  // the_noteE
                   in_port_to_the_noteE,

                  // the_noteF
                   in_port_to_the_noteF,

                  // the_noteG
                   in_port_to_the_noteG,

                  // the_sdram_0
                   zs_addr_from_the_sdram_0,
                   zs_ba_from_the_sdram_0,
                   zs_cas_n_from_the_sdram_0,
                   zs_cke_from_the_sdram_0,
                   zs_cs_n_from_the_sdram_0,
                   zs_dq_to_and_from_the_sdram_0,
                   zs_dqm_from_the_sdram_0,
                   zs_ras_n_from_the_sdram_0,
                   zs_we_n_from_the_sdram_0,

                  // the_sram_0
                   SRAM_ADDR_from_the_sram_0,
                   SRAM_CE_N_from_the_sram_0,
                   SRAM_DQ_to_and_from_the_sram_0,
                   SRAM_LB_N_from_the_sram_0,
                   SRAM_OE_N_from_the_sram_0,
                   SRAM_UB_N_from_the_sram_0,
                   SRAM_WE_N_from_the_sram_0,

                  // the_tri_state_bridge_0_avalon_slave
                   select_n_to_the_cfi_flash_0,
                   tri_state_bridge_0_address,
                   tri_state_bridge_0_data,
                   tri_state_bridge_0_readn,
                   write_n_to_the_cfi_flash_0,

                  // the_uart_0
                   rxd_to_the_uart_0,
                   txd_from_the_uart_0
                )
;

  output           LCD_E_from_the_lcd_16207_0;
  output           LCD_RS_from_the_lcd_16207_0;
  output           LCD_RW_from_the_lcd_16207_0;
  inout   [  7: 0] LCD_data_to_and_from_the_lcd_16207_0;
  output  [ 17: 0] SRAM_ADDR_from_the_sram_0;
  output           SRAM_CE_N_from_the_sram_0;
  inout   [ 15: 0] SRAM_DQ_to_and_from_the_sram_0;
  output           SRAM_LB_N_from_the_sram_0;
  output           SRAM_OE_N_from_the_sram_0;
  output           SRAM_UB_N_from_the_sram_0;
  output           SRAM_WE_N_from_the_sram_0;
  output           altpll_0_c0_out;
  output           altpll_0_c1_out;
  inout            bidir_port_to_and_from_the_SD_CMD;
  inout            bidir_port_to_and_from_the_SD_DAT;
  output           locked_from_the_altpll_0;
  output           oAUD_BCK_from_the_Audio_0;
  output           oAUD_DATA_from_the_Audio_0;
  output           oAUD_LRCK_from_the_Audio_0;
  output           oAUD_XCK_from_the_Audio_0;
  output  [  6: 0] oSEG0_from_the_SEG7_Display;
  output  [  6: 0] oSEG1_from_the_SEG7_Display;
  output  [  6: 0] oSEG2_from_the_SEG7_Display;
  output  [  6: 0] oSEG3_from_the_SEG7_Display;
  output  [  6: 0] oSEG4_from_the_SEG7_Display;
  output  [  6: 0] oSEG5_from_the_SEG7_Display;
  output  [  6: 0] oSEG6_from_the_SEG7_Display;
  output  [  6: 0] oSEG7_from_the_SEG7_Display;
  output           out_port_from_the_SD_CLK;
  output           phasedone_from_the_altpll_0;
  output           scl_i2c_to_accel_from_the_Accel_Control;
  output           scl_pad_io_from_the_i2c_master;
  inout            sda_i2c_to_accel_to_and_from_the_Accel_Control;
  inout            sda_i2c_to_bus_to_and_from_the_Accel_Control;
  inout            sda_pad_io_to_and_from_the_i2c_master;
  output           sda_padoen_out_from_the_i2c_master;
  output           select_n_to_the_cfi_flash_0;
  output  [ 21: 0] tri_state_bridge_0_address;
  inout   [  7: 0] tri_state_bridge_0_data;
  output           tri_state_bridge_0_readn;
  output           txd_from_the_uart_0;
  output           wb_err_o_from_the_i2c_master;
  output           write_n_to_the_cfi_flash_0;
  output  [ 11: 0] zs_addr_from_the_sdram_0;
  output  [  1: 0] zs_ba_from_the_sdram_0;
  output           zs_cas_n_from_the_sdram_0;
  output           zs_cke_from_the_sdram_0;
  output           zs_cs_n_from_the_sdram_0;
  inout   [ 15: 0] zs_dq_to_and_from_the_sdram_0;
  output  [  1: 0] zs_dqm_from_the_sdram_0;
  output           zs_ras_n_from_the_sdram_0;
  output           zs_we_n_from_the_sdram_0;
  input            clk;
  input            iCLK_18_4_to_the_Audio_0;
  input            in_port_to_the_MS;
  input            in_port_to_the_Oct_DOWN;
  input            in_port_to_the_Oct_UP;
  input            in_port_to_the_RST;
  input            in_port_to_the_dist_sensor;
  input            in_port_to_the_noteA;
  input            in_port_to_the_noteB;
  input            in_port_to_the_noteC;
  input            in_port_to_the_noteD;
  input            in_port_to_the_noteE;
  input            in_port_to_the_noteF;
  input            in_port_to_the_noteG;
  input            interrupt2_to_the_Accel_Control;
  input            reset_n;
  input            rxd_to_the_uart_0;
  input            scl_i2c_to_bus_to_the_Accel_Control;
  input            sda_padoen_o_to_the_Accel_Control;

  wire    [  2: 0] Accel_Control_avalon_slave_address;
  wire    [  3: 0] Accel_Control_avalon_slave_byteenable;
  wire             Accel_Control_avalon_slave_chipselect;
  wire             Accel_Control_avalon_slave_read;
  wire    [ 31: 0] Accel_Control_avalon_slave_readdata;
  wire    [ 31: 0] Accel_Control_avalon_slave_readdata_from_sa;
  wire             Accel_Control_avalon_slave_reset_n;
  wire             Accel_Control_avalon_slave_write_n;
  wire    [ 31: 0] Accel_Control_avalon_slave_writedata;
  wire    [ 15: 0] Audio_0_avalon_slave_0_readdata;
  wire    [ 15: 0] Audio_0_avalon_slave_0_readdata_from_sa;
  wire             Audio_0_avalon_slave_0_reset_n;
  wire             Audio_0_avalon_slave_0_write;
  wire    [ 15: 0] Audio_0_avalon_slave_0_writedata;
  wire             LCD_E_from_the_lcd_16207_0;
  wire             LCD_RS_from_the_lcd_16207_0;
  wire             LCD_RW_from_the_lcd_16207_0;
  wire    [  7: 0] LCD_data_to_and_from_the_lcd_16207_0;
  wire    [  1: 0] MS_s1_address;
  wire             MS_s1_chipselect;
  wire             MS_s1_irq;
  wire             MS_s1_irq_from_sa;
  wire             MS_s1_readdata;
  wire             MS_s1_readdata_from_sa;
  wire             MS_s1_reset_n;
  wire             MS_s1_write_n;
  wire             MS_s1_writedata;
  wire    [  1: 0] Oct_DOWN_s1_address;
  wire             Oct_DOWN_s1_chipselect;
  wire             Oct_DOWN_s1_irq;
  wire             Oct_DOWN_s1_irq_from_sa;
  wire             Oct_DOWN_s1_readdata;
  wire             Oct_DOWN_s1_readdata_from_sa;
  wire             Oct_DOWN_s1_reset_n;
  wire             Oct_DOWN_s1_write_n;
  wire             Oct_DOWN_s1_writedata;
  wire    [  1: 0] Oct_UP_s1_address;
  wire             Oct_UP_s1_chipselect;
  wire             Oct_UP_s1_irq;
  wire             Oct_UP_s1_irq_from_sa;
  wire             Oct_UP_s1_readdata;
  wire             Oct_UP_s1_readdata_from_sa;
  wire             Oct_UP_s1_reset_n;
  wire             Oct_UP_s1_write_n;
  wire             Oct_UP_s1_writedata;
  wire    [  1: 0] RST_s1_address;
  wire             RST_s1_chipselect;
  wire             RST_s1_irq;
  wire             RST_s1_irq_from_sa;
  wire             RST_s1_readdata;
  wire             RST_s1_readdata_from_sa;
  wire             RST_s1_reset_n;
  wire             RST_s1_write_n;
  wire             RST_s1_writedata;
  wire    [  1: 0] SD_CLK_s1_address;
  wire             SD_CLK_s1_chipselect;
  wire             SD_CLK_s1_readdata;
  wire             SD_CLK_s1_readdata_from_sa;
  wire             SD_CLK_s1_reset_n;
  wire             SD_CLK_s1_write_n;
  wire             SD_CLK_s1_writedata;
  wire    [  1: 0] SD_CMD_s1_address;
  wire             SD_CMD_s1_chipselect;
  wire             SD_CMD_s1_readdata;
  wire             SD_CMD_s1_readdata_from_sa;
  wire             SD_CMD_s1_reset_n;
  wire             SD_CMD_s1_write_n;
  wire             SD_CMD_s1_writedata;
  wire    [  1: 0] SD_DAT_s1_address;
  wire             SD_DAT_s1_chipselect;
  wire             SD_DAT_s1_readdata;
  wire             SD_DAT_s1_readdata_from_sa;
  wire             SD_DAT_s1_reset_n;
  wire             SD_DAT_s1_write_n;
  wire             SD_DAT_s1_writedata;
  wire             SEG7_Display_avalon_slave_0_reset_n;
  wire             SEG7_Display_avalon_slave_0_write;
  wire    [ 31: 0] SEG7_Display_avalon_slave_0_writedata;
  wire    [ 17: 0] SRAM_ADDR_from_the_sram_0;
  wire             SRAM_CE_N_from_the_sram_0;
  wire    [ 15: 0] SRAM_DQ_to_and_from_the_sram_0;
  wire             SRAM_LB_N_from_the_sram_0;
  wire             SRAM_OE_N_from_the_sram_0;
  wire             SRAM_UB_N_from_the_sram_0;
  wire             SRAM_WE_N_from_the_sram_0;
  wire             altpll_0_c0_out;
  wire             altpll_0_c1_out;
  wire             altpll_0_c1_out_reset_n;
  wire    [  1: 0] altpll_0_pll_slave_address;
  wire             altpll_0_pll_slave_read;
  wire    [ 31: 0] altpll_0_pll_slave_readdata;
  wire    [ 31: 0] altpll_0_pll_slave_readdata_from_sa;
  wire             altpll_0_pll_slave_reset;
  wire             altpll_0_pll_slave_write;
  wire    [ 31: 0] altpll_0_pll_slave_writedata;
  wire             bidir_port_to_and_from_the_SD_CMD;
  wire             bidir_port_to_and_from_the_SD_DAT;
  wire             cfi_flash_0_s1_wait_counter_eq_0;
  wire             clk_reset_n;
  wire    [ 24: 0] cpu_0_data_master_address;
  wire    [ 24: 0] cpu_0_data_master_address_to_slave;
  wire    [  3: 0] cpu_0_data_master_burstcount;
  wire    [  3: 0] cpu_0_data_master_byteenable;
  wire    [  1: 0] cpu_0_data_master_byteenable_system_0_burst_15_upstream;
  wire             cpu_0_data_master_byteenable_system_0_burst_3_upstream;
  wire    [  1: 0] cpu_0_data_master_byteenable_system_0_burst_5_upstream;
  wire    [  1: 0] cpu_0_data_master_dbs_address;
  wire    [ 15: 0] cpu_0_data_master_dbs_write_16;
  wire    [  7: 0] cpu_0_data_master_dbs_write_8;
  wire             cpu_0_data_master_debugaccess;
  wire             cpu_0_data_master_granted_system_0_burst_10_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_11_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_12_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_13_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_15_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_16_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_17_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_18_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_19_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_1_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_20_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_21_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_22_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_23_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_24_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_25_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_26_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_27_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_28_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_29_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_30_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_31_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_32_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_34_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_35_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_3_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_5_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_7_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_8_upstream;
  wire             cpu_0_data_master_granted_system_0_burst_9_upstream;
  wire    [ 31: 0] cpu_0_data_master_irq;
  wire             cpu_0_data_master_latency_counter;
  wire             cpu_0_data_master_qualified_request_system_0_burst_10_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_11_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_12_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_13_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_15_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_16_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_17_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_18_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_19_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_1_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_20_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_21_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_22_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_23_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_24_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_25_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_26_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_27_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_28_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_29_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_30_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_31_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_32_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_34_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_35_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_3_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_5_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_7_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_8_upstream;
  wire             cpu_0_data_master_qualified_request_system_0_burst_9_upstream;
  wire             cpu_0_data_master_read;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_10_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_11_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_12_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_13_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_15_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_16_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_17_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_18_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_19_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_1_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_20_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_21_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_22_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_23_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_24_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_25_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_26_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_27_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_28_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_29_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_30_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_31_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_32_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_34_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_35_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_3_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_5_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_7_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_8_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_9_upstream;
  wire             cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register;
  wire    [ 31: 0] cpu_0_data_master_readdata;
  wire             cpu_0_data_master_readdatavalid;
  wire             cpu_0_data_master_requests_system_0_burst_10_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_11_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_12_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_13_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_15_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_16_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_17_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_18_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_19_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_1_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_20_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_21_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_22_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_23_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_24_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_25_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_26_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_27_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_28_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_29_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_30_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_31_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_32_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_34_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_35_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_3_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_5_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_7_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_8_upstream;
  wire             cpu_0_data_master_requests_system_0_burst_9_upstream;
  wire             cpu_0_data_master_waitrequest;
  wire             cpu_0_data_master_write;
  wire    [ 31: 0] cpu_0_data_master_writedata;
  wire    [ 24: 0] cpu_0_instruction_master_address;
  wire    [ 24: 0] cpu_0_instruction_master_address_to_slave;
  wire    [  3: 0] cpu_0_instruction_master_burstcount;
  wire    [  1: 0] cpu_0_instruction_master_dbs_address;
  wire             cpu_0_instruction_master_granted_system_0_burst_0_upstream;
  wire             cpu_0_instruction_master_granted_system_0_burst_14_upstream;
  wire             cpu_0_instruction_master_granted_system_0_burst_2_upstream;
  wire             cpu_0_instruction_master_granted_system_0_burst_33_upstream;
  wire             cpu_0_instruction_master_granted_system_0_burst_4_upstream;
  wire             cpu_0_instruction_master_granted_system_0_burst_6_upstream;
  wire             cpu_0_instruction_master_latency_counter;
  wire             cpu_0_instruction_master_qualified_request_system_0_burst_0_upstream;
  wire             cpu_0_instruction_master_qualified_request_system_0_burst_14_upstream;
  wire             cpu_0_instruction_master_qualified_request_system_0_burst_2_upstream;
  wire             cpu_0_instruction_master_qualified_request_system_0_burst_33_upstream;
  wire             cpu_0_instruction_master_qualified_request_system_0_burst_4_upstream;
  wire             cpu_0_instruction_master_qualified_request_system_0_burst_6_upstream;
  wire             cpu_0_instruction_master_read;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream;
  wire             cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register;
  wire    [ 31: 0] cpu_0_instruction_master_readdata;
  wire             cpu_0_instruction_master_readdatavalid;
  wire             cpu_0_instruction_master_requests_system_0_burst_0_upstream;
  wire             cpu_0_instruction_master_requests_system_0_burst_14_upstream;
  wire             cpu_0_instruction_master_requests_system_0_burst_2_upstream;
  wire             cpu_0_instruction_master_requests_system_0_burst_33_upstream;
  wire             cpu_0_instruction_master_requests_system_0_burst_4_upstream;
  wire             cpu_0_instruction_master_requests_system_0_burst_6_upstream;
  wire             cpu_0_instruction_master_waitrequest;
  wire    [  8: 0] cpu_0_jtag_debug_module_address;
  wire             cpu_0_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu_0_jtag_debug_module_byteenable;
  wire             cpu_0_jtag_debug_module_chipselect;
  wire             cpu_0_jtag_debug_module_debugaccess;
  wire    [ 31: 0] cpu_0_jtag_debug_module_readdata;
  wire    [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
  wire             cpu_0_jtag_debug_module_reset_n;
  wire             cpu_0_jtag_debug_module_resetrequest;
  wire             cpu_0_jtag_debug_module_resetrequest_from_sa;
  wire             cpu_0_jtag_debug_module_write;
  wire    [ 31: 0] cpu_0_jtag_debug_module_writedata;
  wire             d1_Accel_Control_avalon_slave_end_xfer;
  wire             d1_Audio_0_avalon_slave_0_end_xfer;
  wire             d1_MS_s1_end_xfer;
  wire             d1_Oct_DOWN_s1_end_xfer;
  wire             d1_Oct_UP_s1_end_xfer;
  wire             d1_RST_s1_end_xfer;
  wire             d1_SD_CLK_s1_end_xfer;
  wire             d1_SD_CMD_s1_end_xfer;
  wire             d1_SD_DAT_s1_end_xfer;
  wire             d1_SEG7_Display_avalon_slave_0_end_xfer;
  wire             d1_altpll_0_pll_slave_end_xfer;
  wire             d1_cpu_0_jtag_debug_module_end_xfer;
  wire             d1_dist_sensor_s1_end_xfer;
  wire             d1_epcs_controller_epcs_control_port_end_xfer;
  wire             d1_i2c_master_avalon_slave_0_end_xfer;
  wire             d1_jtag_uart_0_avalon_jtag_slave_end_xfer;
  wire             d1_lcd_16207_0_control_slave_end_xfer;
  wire             d1_noteA_s1_end_xfer;
  wire             d1_noteB_s1_end_xfer;
  wire             d1_noteC_s1_end_xfer;
  wire             d1_noteD_s1_end_xfer;
  wire             d1_noteE_s1_end_xfer;
  wire             d1_noteF_s1_end_xfer;
  wire             d1_noteG_s1_end_xfer;
  wire             d1_sdram_0_s1_end_xfer;
  wire             d1_sram_0_avalon_slave_0_end_xfer;
  wire             d1_system_0_burst_0_upstream_end_xfer;
  wire             d1_system_0_burst_10_upstream_end_xfer;
  wire             d1_system_0_burst_11_upstream_end_xfer;
  wire             d1_system_0_burst_12_upstream_end_xfer;
  wire             d1_system_0_burst_13_upstream_end_xfer;
  wire             d1_system_0_burst_14_upstream_end_xfer;
  wire             d1_system_0_burst_15_upstream_end_xfer;
  wire             d1_system_0_burst_16_upstream_end_xfer;
  wire             d1_system_0_burst_17_upstream_end_xfer;
  wire             d1_system_0_burst_18_upstream_end_xfer;
  wire             d1_system_0_burst_19_upstream_end_xfer;
  wire             d1_system_0_burst_1_upstream_end_xfer;
  wire             d1_system_0_burst_20_upstream_end_xfer;
  wire             d1_system_0_burst_21_upstream_end_xfer;
  wire             d1_system_0_burst_22_upstream_end_xfer;
  wire             d1_system_0_burst_23_upstream_end_xfer;
  wire             d1_system_0_burst_24_upstream_end_xfer;
  wire             d1_system_0_burst_25_upstream_end_xfer;
  wire             d1_system_0_burst_26_upstream_end_xfer;
  wire             d1_system_0_burst_27_upstream_end_xfer;
  wire             d1_system_0_burst_28_upstream_end_xfer;
  wire             d1_system_0_burst_29_upstream_end_xfer;
  wire             d1_system_0_burst_2_upstream_end_xfer;
  wire             d1_system_0_burst_30_upstream_end_xfer;
  wire             d1_system_0_burst_31_upstream_end_xfer;
  wire             d1_system_0_burst_32_upstream_end_xfer;
  wire             d1_system_0_burst_33_upstream_end_xfer;
  wire             d1_system_0_burst_34_upstream_end_xfer;
  wire             d1_system_0_burst_35_upstream_end_xfer;
  wire             d1_system_0_burst_3_upstream_end_xfer;
  wire             d1_system_0_burst_4_upstream_end_xfer;
  wire             d1_system_0_burst_5_upstream_end_xfer;
  wire             d1_system_0_burst_6_upstream_end_xfer;
  wire             d1_system_0_burst_7_upstream_end_xfer;
  wire             d1_system_0_burst_8_upstream_end_xfer;
  wire             d1_system_0_burst_9_upstream_end_xfer;
  wire             d1_system_0_clock_0_in_end_xfer;
  wire             d1_timer_0_s1_end_xfer;
  wire             d1_timer_1_s1_end_xfer;
  wire             d1_tri_state_bridge_0_avalon_slave_end_xfer;
  wire             d1_uart_0_s1_end_xfer;
  wire    [  1: 0] dist_sensor_s1_address;
  wire             dist_sensor_s1_chipselect;
  wire             dist_sensor_s1_irq;
  wire             dist_sensor_s1_irq_from_sa;
  wire             dist_sensor_s1_readdata;
  wire             dist_sensor_s1_readdata_from_sa;
  wire             dist_sensor_s1_reset_n;
  wire             dist_sensor_s1_write_n;
  wire             dist_sensor_s1_writedata;
  wire    [  8: 0] epcs_controller_epcs_control_port_address;
  wire             epcs_controller_epcs_control_port_chipselect;
  wire             epcs_controller_epcs_control_port_dataavailable;
  wire             epcs_controller_epcs_control_port_dataavailable_from_sa;
  wire             epcs_controller_epcs_control_port_endofpacket;
  wire             epcs_controller_epcs_control_port_endofpacket_from_sa;
  wire             epcs_controller_epcs_control_port_irq;
  wire             epcs_controller_epcs_control_port_irq_from_sa;
  wire             epcs_controller_epcs_control_port_read_n;
  wire    [ 31: 0] epcs_controller_epcs_control_port_readdata;
  wire    [ 31: 0] epcs_controller_epcs_control_port_readdata_from_sa;
  wire             epcs_controller_epcs_control_port_readyfordata;
  wire             epcs_controller_epcs_control_port_readyfordata_from_sa;
  wire             epcs_controller_epcs_control_port_reset_n;
  wire             epcs_controller_epcs_control_port_write_n;
  wire    [ 31: 0] epcs_controller_epcs_control_port_writedata;
  wire    [  2: 0] i2c_master_avalon_slave_0_address;
  wire             i2c_master_avalon_slave_0_chipselect;
  wire             i2c_master_avalon_slave_0_irq;
  wire             i2c_master_avalon_slave_0_irq_from_sa;
  wire    [ 31: 0] i2c_master_avalon_slave_0_readdata;
  wire    [ 31: 0] i2c_master_avalon_slave_0_readdata_from_sa;
  wire             i2c_master_avalon_slave_0_reset;
  wire             i2c_master_avalon_slave_0_waitrequest_n;
  wire             i2c_master_avalon_slave_0_waitrequest_n_from_sa;
  wire             i2c_master_avalon_slave_0_write;
  wire    [ 31: 0] i2c_master_avalon_slave_0_writedata;
  wire    [  7: 0] incoming_tri_state_bridge_0_data_with_Xs_converted_to_0;
  wire             jtag_uart_0_avalon_jtag_slave_address;
  wire             jtag_uart_0_avalon_jtag_slave_chipselect;
  wire             jtag_uart_0_avalon_jtag_slave_dataavailable;
  wire             jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_0_avalon_jtag_slave_irq;
  wire             jtag_uart_0_avalon_jtag_slave_irq_from_sa;
  wire             jtag_uart_0_avalon_jtag_slave_read_n;
  wire    [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata;
  wire    [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
  wire             jtag_uart_0_avalon_jtag_slave_readyfordata;
  wire             jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa;
  wire             jtag_uart_0_avalon_jtag_slave_reset_n;
  wire             jtag_uart_0_avalon_jtag_slave_waitrequest;
  wire             jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
  wire             jtag_uart_0_avalon_jtag_slave_write_n;
  wire    [ 31: 0] jtag_uart_0_avalon_jtag_slave_writedata;
  wire    [  1: 0] lcd_16207_0_control_slave_address;
  wire             lcd_16207_0_control_slave_begintransfer;
  wire             lcd_16207_0_control_slave_read;
  wire    [  7: 0] lcd_16207_0_control_slave_readdata;
  wire    [  7: 0] lcd_16207_0_control_slave_readdata_from_sa;
  wire             lcd_16207_0_control_slave_wait_counter_eq_0;
  wire             lcd_16207_0_control_slave_write;
  wire    [  7: 0] lcd_16207_0_control_slave_writedata;
  wire             locked_from_the_altpll_0;
  wire    [  1: 0] noteA_s1_address;
  wire             noteA_s1_readdata;
  wire             noteA_s1_readdata_from_sa;
  wire             noteA_s1_reset_n;
  wire    [  1: 0] noteB_s1_address;
  wire             noteB_s1_readdata;
  wire             noteB_s1_readdata_from_sa;
  wire             noteB_s1_reset_n;
  wire    [  1: 0] noteC_s1_address;
  wire             noteC_s1_readdata;
  wire             noteC_s1_readdata_from_sa;
  wire             noteC_s1_reset_n;
  wire    [  1: 0] noteD_s1_address;
  wire             noteD_s1_readdata;
  wire             noteD_s1_readdata_from_sa;
  wire             noteD_s1_reset_n;
  wire    [  1: 0] noteE_s1_address;
  wire             noteE_s1_readdata;
  wire             noteE_s1_readdata_from_sa;
  wire             noteE_s1_reset_n;
  wire    [  1: 0] noteF_s1_address;
  wire             noteF_s1_readdata;
  wire             noteF_s1_readdata_from_sa;
  wire             noteF_s1_reset_n;
  wire    [  1: 0] noteG_s1_address;
  wire             noteG_s1_readdata;
  wire             noteG_s1_readdata_from_sa;
  wire             noteG_s1_reset_n;
  wire             oAUD_BCK_from_the_Audio_0;
  wire             oAUD_DATA_from_the_Audio_0;
  wire             oAUD_LRCK_from_the_Audio_0;
  wire             oAUD_XCK_from_the_Audio_0;
  wire    [  6: 0] oSEG0_from_the_SEG7_Display;
  wire    [  6: 0] oSEG1_from_the_SEG7_Display;
  wire    [  6: 0] oSEG2_from_the_SEG7_Display;
  wire    [  6: 0] oSEG3_from_the_SEG7_Display;
  wire    [  6: 0] oSEG4_from_the_SEG7_Display;
  wire    [  6: 0] oSEG5_from_the_SEG7_Display;
  wire    [  6: 0] oSEG6_from_the_SEG7_Display;
  wire    [  6: 0] oSEG7_from_the_SEG7_Display;
  wire             out_clk_altpll_0_c0;
  wire             out_clk_altpll_0_c1;
  wire             out_port_from_the_SD_CLK;
  wire             phasedone_from_the_altpll_0;
  wire             reset_n_sources;
  wire             scl_i2c_to_accel_from_the_Accel_Control;
  wire             scl_pad_io_from_the_i2c_master;
  wire             sda_i2c_to_accel_to_and_from_the_Accel_Control;
  wire             sda_i2c_to_bus_to_and_from_the_Accel_Control;
  wire             sda_pad_io_to_and_from_the_i2c_master;
  wire             sda_padoen_out_from_the_i2c_master;
  wire    [ 21: 0] sdram_0_s1_address;
  wire    [  1: 0] sdram_0_s1_byteenable_n;
  wire             sdram_0_s1_chipselect;
  wire             sdram_0_s1_read_n;
  wire    [ 15: 0] sdram_0_s1_readdata;
  wire    [ 15: 0] sdram_0_s1_readdata_from_sa;
  wire             sdram_0_s1_readdatavalid;
  wire             sdram_0_s1_reset_n;
  wire             sdram_0_s1_waitrequest;
  wire             sdram_0_s1_waitrequest_from_sa;
  wire             sdram_0_s1_write_n;
  wire    [ 15: 0] sdram_0_s1_writedata;
  wire             select_n_to_the_cfi_flash_0;
  wire    [ 17: 0] sram_0_avalon_slave_0_address;
  wire    [  1: 0] sram_0_avalon_slave_0_byteenable_n;
  wire             sram_0_avalon_slave_0_chipselect_n;
  wire             sram_0_avalon_slave_0_read_n;
  wire    [ 15: 0] sram_0_avalon_slave_0_readdata;
  wire    [ 15: 0] sram_0_avalon_slave_0_readdata_from_sa;
  wire             sram_0_avalon_slave_0_wait_counter_eq_0;
  wire             sram_0_avalon_slave_0_write_n;
  wire    [ 15: 0] sram_0_avalon_slave_0_writedata;
  wire    [ 10: 0] system_0_burst_0_downstream_address;
  wire    [ 10: 0] system_0_burst_0_downstream_address_to_slave;
  wire    [  3: 0] system_0_burst_0_downstream_arbitrationshare;
  wire             system_0_burst_0_downstream_burstcount;
  wire    [  3: 0] system_0_burst_0_downstream_byteenable;
  wire             system_0_burst_0_downstream_debugaccess;
  wire             system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module;
  wire             system_0_burst_0_downstream_latency_counter;
  wire    [ 10: 0] system_0_burst_0_downstream_nativeaddress;
  wire             system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module;
  wire             system_0_burst_0_downstream_read;
  wire             system_0_burst_0_downstream_read_data_valid_cpu_0_jtag_debug_module;
  wire    [ 31: 0] system_0_burst_0_downstream_readdata;
  wire             system_0_burst_0_downstream_readdatavalid;
  wire             system_0_burst_0_downstream_requests_cpu_0_jtag_debug_module;
  wire             system_0_burst_0_downstream_reset_n;
  wire             system_0_burst_0_downstream_waitrequest;
  wire             system_0_burst_0_downstream_write;
  wire    [ 31: 0] system_0_burst_0_downstream_writedata;
  wire    [ 10: 0] system_0_burst_0_upstream_address;
  wire    [ 12: 0] system_0_burst_0_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_0_upstream_byteenable;
  wire             system_0_burst_0_upstream_debugaccess;
  wire             system_0_burst_0_upstream_read;
  wire    [ 31: 0] system_0_burst_0_upstream_readdata;
  wire    [ 31: 0] system_0_burst_0_upstream_readdata_from_sa;
  wire             system_0_burst_0_upstream_readdatavalid;
  wire             system_0_burst_0_upstream_waitrequest;
  wire             system_0_burst_0_upstream_waitrequest_from_sa;
  wire             system_0_burst_0_upstream_write;
  wire    [ 31: 0] system_0_burst_0_upstream_writedata;
  wire    [  3: 0] system_0_burst_10_downstream_address;
  wire    [  3: 0] system_0_burst_10_downstream_address_to_slave;
  wire    [  4: 0] system_0_burst_10_downstream_arbitrationshare;
  wire             system_0_burst_10_downstream_burstcount;
  wire    [  1: 0] system_0_burst_10_downstream_byteenable;
  wire             system_0_burst_10_downstream_debugaccess;
  wire             system_0_burst_10_downstream_granted_timer_0_s1;
  wire             system_0_burst_10_downstream_latency_counter;
  wire    [  3: 0] system_0_burst_10_downstream_nativeaddress;
  wire             system_0_burst_10_downstream_qualified_request_timer_0_s1;
  wire             system_0_burst_10_downstream_read;
  wire             system_0_burst_10_downstream_read_data_valid_timer_0_s1;
  wire    [ 15: 0] system_0_burst_10_downstream_readdata;
  wire             system_0_burst_10_downstream_readdatavalid;
  wire             system_0_burst_10_downstream_requests_timer_0_s1;
  wire             system_0_burst_10_downstream_reset_n;
  wire             system_0_burst_10_downstream_waitrequest;
  wire             system_0_burst_10_downstream_write;
  wire    [ 15: 0] system_0_burst_10_downstream_writedata;
  wire    [  3: 0] system_0_burst_10_upstream_address;
  wire    [  3: 0] system_0_burst_10_upstream_burstcount;
  wire    [  4: 0] system_0_burst_10_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_10_upstream_byteenable;
  wire             system_0_burst_10_upstream_debugaccess;
  wire             system_0_burst_10_upstream_read;
  wire    [ 15: 0] system_0_burst_10_upstream_readdata;
  wire    [ 15: 0] system_0_burst_10_upstream_readdata_from_sa;
  wire             system_0_burst_10_upstream_readdatavalid;
  wire             system_0_burst_10_upstream_waitrequest;
  wire             system_0_burst_10_upstream_waitrequest_from_sa;
  wire             system_0_burst_10_upstream_write;
  wire    [ 15: 0] system_0_burst_10_upstream_writedata;
  wire    [  3: 0] system_0_burst_11_downstream_address;
  wire    [  3: 0] system_0_burst_11_downstream_address_to_slave;
  wire    [  4: 0] system_0_burst_11_downstream_arbitrationshare;
  wire             system_0_burst_11_downstream_burstcount;
  wire    [  1: 0] system_0_burst_11_downstream_byteenable;
  wire             system_0_burst_11_downstream_debugaccess;
  wire             system_0_burst_11_downstream_granted_timer_1_s1;
  wire             system_0_burst_11_downstream_latency_counter;
  wire    [  3: 0] system_0_burst_11_downstream_nativeaddress;
  wire             system_0_burst_11_downstream_qualified_request_timer_1_s1;
  wire             system_0_burst_11_downstream_read;
  wire             system_0_burst_11_downstream_read_data_valid_timer_1_s1;
  wire    [ 15: 0] system_0_burst_11_downstream_readdata;
  wire             system_0_burst_11_downstream_readdatavalid;
  wire             system_0_burst_11_downstream_requests_timer_1_s1;
  wire             system_0_burst_11_downstream_reset_n;
  wire             system_0_burst_11_downstream_waitrequest;
  wire             system_0_burst_11_downstream_write;
  wire    [ 15: 0] system_0_burst_11_downstream_writedata;
  wire    [  3: 0] system_0_burst_11_upstream_address;
  wire    [  3: 0] system_0_burst_11_upstream_burstcount;
  wire    [  4: 0] system_0_burst_11_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_11_upstream_byteenable;
  wire             system_0_burst_11_upstream_debugaccess;
  wire             system_0_burst_11_upstream_read;
  wire    [ 15: 0] system_0_burst_11_upstream_readdata;
  wire    [ 15: 0] system_0_burst_11_upstream_readdata_from_sa;
  wire             system_0_burst_11_upstream_readdatavalid;
  wire             system_0_burst_11_upstream_waitrequest;
  wire             system_0_burst_11_upstream_waitrequest_from_sa;
  wire             system_0_burst_11_upstream_write;
  wire    [ 15: 0] system_0_burst_11_upstream_writedata;
  wire    [  1: 0] system_0_burst_12_downstream_address;
  wire    [  1: 0] system_0_burst_12_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_12_downstream_arbitrationshare;
  wire             system_0_burst_12_downstream_burstcount;
  wire             system_0_burst_12_downstream_byteenable;
  wire             system_0_burst_12_downstream_debugaccess;
  wire             system_0_burst_12_downstream_granted_lcd_16207_0_control_slave;
  wire             system_0_burst_12_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_12_downstream_nativeaddress;
  wire             system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave;
  wire             system_0_burst_12_downstream_read;
  wire             system_0_burst_12_downstream_read_data_valid_lcd_16207_0_control_slave;
  wire    [  7: 0] system_0_burst_12_downstream_readdata;
  wire             system_0_burst_12_downstream_readdatavalid;
  wire             system_0_burst_12_downstream_requests_lcd_16207_0_control_slave;
  wire             system_0_burst_12_downstream_reset_n;
  wire             system_0_burst_12_downstream_waitrequest;
  wire             system_0_burst_12_downstream_write;
  wire    [  7: 0] system_0_burst_12_downstream_writedata;
  wire    [  1: 0] system_0_burst_12_upstream_address;
  wire    [  3: 0] system_0_burst_12_upstream_burstcount;
  wire    [  1: 0] system_0_burst_12_upstream_byteaddress;
  wire             system_0_burst_12_upstream_byteenable;
  wire             system_0_burst_12_upstream_debugaccess;
  wire             system_0_burst_12_upstream_read;
  wire    [  7: 0] system_0_burst_12_upstream_readdata;
  wire    [  7: 0] system_0_burst_12_upstream_readdata_from_sa;
  wire             system_0_burst_12_upstream_readdatavalid;
  wire             system_0_burst_12_upstream_waitrequest;
  wire             system_0_burst_12_upstream_waitrequest_from_sa;
  wire             system_0_burst_12_upstream_write;
  wire    [  7: 0] system_0_burst_12_upstream_writedata;
  wire    [  1: 0] system_0_burst_13_downstream_address;
  wire    [  1: 0] system_0_burst_13_downstream_address_to_slave;
  wire    [  3: 0] system_0_burst_13_downstream_arbitrationshare;
  wire             system_0_burst_13_downstream_burstcount;
  wire    [  3: 0] system_0_burst_13_downstream_byteenable;
  wire             system_0_burst_13_downstream_debugaccess;
  wire             system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0;
  wire             system_0_burst_13_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_13_downstream_nativeaddress;
  wire             system_0_burst_13_downstream_qualified_request_SEG7_Display_avalon_slave_0;
  wire             system_0_burst_13_downstream_read;
  wire             system_0_burst_13_downstream_read_data_valid_SEG7_Display_avalon_slave_0;
  wire    [ 31: 0] system_0_burst_13_downstream_readdata;
  wire             system_0_burst_13_downstream_readdatavalid;
  wire             system_0_burst_13_downstream_requests_SEG7_Display_avalon_slave_0;
  wire             system_0_burst_13_downstream_reset_n;
  wire             system_0_burst_13_downstream_waitrequest;
  wire             system_0_burst_13_downstream_write;
  wire    [ 31: 0] system_0_burst_13_downstream_writedata;
  wire    [  1: 0] system_0_burst_13_upstream_address;
  wire    [  3: 0] system_0_burst_13_upstream_burstcount;
  wire    [  3: 0] system_0_burst_13_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_13_upstream_byteenable;
  wire             system_0_burst_13_upstream_debugaccess;
  wire             system_0_burst_13_upstream_read;
  wire    [ 31: 0] system_0_burst_13_upstream_readdata;
  wire    [ 31: 0] system_0_burst_13_upstream_readdata_from_sa;
  wire             system_0_burst_13_upstream_readdatavalid;
  wire             system_0_burst_13_upstream_waitrequest;
  wire             system_0_burst_13_upstream_waitrequest_from_sa;
  wire             system_0_burst_13_upstream_write;
  wire    [ 31: 0] system_0_burst_13_upstream_writedata;
  wire    [ 18: 0] system_0_burst_14_downstream_address;
  wire    [ 18: 0] system_0_burst_14_downstream_address_to_slave;
  wire    [  4: 0] system_0_burst_14_downstream_arbitrationshare;
  wire             system_0_burst_14_downstream_burstcount;
  wire    [  1: 0] system_0_burst_14_downstream_byteenable;
  wire             system_0_burst_14_downstream_debugaccess;
  wire             system_0_burst_14_downstream_granted_sram_0_avalon_slave_0;
  wire             system_0_burst_14_downstream_latency_counter;
  wire    [ 18: 0] system_0_burst_14_downstream_nativeaddress;
  wire             system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0;
  wire             system_0_burst_14_downstream_read;
  wire             system_0_burst_14_downstream_read_data_valid_sram_0_avalon_slave_0;
  wire    [ 15: 0] system_0_burst_14_downstream_readdata;
  wire             system_0_burst_14_downstream_readdatavalid;
  wire             system_0_burst_14_downstream_requests_sram_0_avalon_slave_0;
  wire             system_0_burst_14_downstream_reset_n;
  wire             system_0_burst_14_downstream_waitrequest;
  wire             system_0_burst_14_downstream_write;
  wire    [ 15: 0] system_0_burst_14_downstream_writedata;
  wire    [ 18: 0] system_0_burst_14_upstream_address;
  wire    [ 19: 0] system_0_burst_14_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_14_upstream_byteenable;
  wire             system_0_burst_14_upstream_debugaccess;
  wire             system_0_burst_14_upstream_read;
  wire    [ 15: 0] system_0_burst_14_upstream_readdata;
  wire    [ 15: 0] system_0_burst_14_upstream_readdata_from_sa;
  wire             system_0_burst_14_upstream_readdatavalid;
  wire             system_0_burst_14_upstream_waitrequest;
  wire             system_0_burst_14_upstream_waitrequest_from_sa;
  wire             system_0_burst_14_upstream_write;
  wire    [ 15: 0] system_0_burst_14_upstream_writedata;
  wire    [ 18: 0] system_0_burst_15_downstream_address;
  wire    [ 18: 0] system_0_burst_15_downstream_address_to_slave;
  wire    [  4: 0] system_0_burst_15_downstream_arbitrationshare;
  wire             system_0_burst_15_downstream_burstcount;
  wire    [  1: 0] system_0_burst_15_downstream_byteenable;
  wire             system_0_burst_15_downstream_debugaccess;
  wire             system_0_burst_15_downstream_granted_sram_0_avalon_slave_0;
  wire             system_0_burst_15_downstream_latency_counter;
  wire    [ 18: 0] system_0_burst_15_downstream_nativeaddress;
  wire             system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0;
  wire             system_0_burst_15_downstream_read;
  wire             system_0_burst_15_downstream_read_data_valid_sram_0_avalon_slave_0;
  wire    [ 15: 0] system_0_burst_15_downstream_readdata;
  wire             system_0_burst_15_downstream_readdatavalid;
  wire             system_0_burst_15_downstream_requests_sram_0_avalon_slave_0;
  wire             system_0_burst_15_downstream_reset_n;
  wire             system_0_burst_15_downstream_waitrequest;
  wire             system_0_burst_15_downstream_write;
  wire    [ 15: 0] system_0_burst_15_downstream_writedata;
  wire    [ 18: 0] system_0_burst_15_upstream_address;
  wire    [  3: 0] system_0_burst_15_upstream_burstcount;
  wire    [ 19: 0] system_0_burst_15_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_15_upstream_byteenable;
  wire             system_0_burst_15_upstream_debugaccess;
  wire             system_0_burst_15_upstream_read;
  wire    [ 15: 0] system_0_burst_15_upstream_readdata;
  wire    [ 15: 0] system_0_burst_15_upstream_readdata_from_sa;
  wire             system_0_burst_15_upstream_readdatavalid;
  wire             system_0_burst_15_upstream_waitrequest;
  wire             system_0_burst_15_upstream_waitrequest_from_sa;
  wire             system_0_burst_15_upstream_write;
  wire    [ 15: 0] system_0_burst_15_upstream_writedata;
  wire             system_0_burst_16_downstream_address;
  wire             system_0_burst_16_downstream_address_to_slave;
  wire    [  4: 0] system_0_burst_16_downstream_arbitrationshare;
  wire             system_0_burst_16_downstream_burstcount;
  wire    [  1: 0] system_0_burst_16_downstream_byteenable;
  wire             system_0_burst_16_downstream_debugaccess;
  wire             system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0;
  wire             system_0_burst_16_downstream_latency_counter;
  wire             system_0_burst_16_downstream_nativeaddress;
  wire             system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0;
  wire             system_0_burst_16_downstream_read;
  wire             system_0_burst_16_downstream_read_data_valid_Audio_0_avalon_slave_0;
  wire    [ 15: 0] system_0_burst_16_downstream_readdata;
  wire             system_0_burst_16_downstream_readdatavalid;
  wire             system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0;
  wire             system_0_burst_16_downstream_reset_n;
  wire             system_0_burst_16_downstream_waitrequest;
  wire             system_0_burst_16_downstream_write;
  wire    [ 15: 0] system_0_burst_16_downstream_writedata;
  wire             system_0_burst_16_upstream_address;
  wire    [  3: 0] system_0_burst_16_upstream_burstcount;
  wire    [  1: 0] system_0_burst_16_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_16_upstream_byteenable;
  wire             system_0_burst_16_upstream_debugaccess;
  wire             system_0_burst_16_upstream_read;
  wire    [ 15: 0] system_0_burst_16_upstream_readdata;
  wire    [ 15: 0] system_0_burst_16_upstream_readdata_from_sa;
  wire             system_0_burst_16_upstream_readdatavalid;
  wire             system_0_burst_16_upstream_waitrequest;
  wire             system_0_burst_16_upstream_waitrequest_from_sa;
  wire             system_0_burst_16_upstream_write;
  wire    [ 15: 0] system_0_burst_16_upstream_writedata;
  wire    [  1: 0] system_0_burst_17_downstream_address;
  wire    [  1: 0] system_0_burst_17_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_17_downstream_arbitrationshare;
  wire             system_0_burst_17_downstream_burstcount;
  wire             system_0_burst_17_downstream_byteenable;
  wire             system_0_burst_17_downstream_debugaccess;
  wire             system_0_burst_17_downstream_granted_SD_DAT_s1;
  wire             system_0_burst_17_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_17_downstream_nativeaddress;
  wire             system_0_burst_17_downstream_qualified_request_SD_DAT_s1;
  wire             system_0_burst_17_downstream_read;
  wire             system_0_burst_17_downstream_read_data_valid_SD_DAT_s1;
  wire    [  7: 0] system_0_burst_17_downstream_readdata;
  wire             system_0_burst_17_downstream_readdatavalid;
  wire             system_0_burst_17_downstream_requests_SD_DAT_s1;
  wire             system_0_burst_17_downstream_reset_n;
  wire             system_0_burst_17_downstream_waitrequest;
  wire             system_0_burst_17_downstream_write;
  wire    [  7: 0] system_0_burst_17_downstream_writedata;
  wire    [  1: 0] system_0_burst_17_upstream_address;
  wire    [  3: 0] system_0_burst_17_upstream_burstcount;
  wire    [  1: 0] system_0_burst_17_upstream_byteaddress;
  wire             system_0_burst_17_upstream_byteenable;
  wire             system_0_burst_17_upstream_debugaccess;
  wire             system_0_burst_17_upstream_read;
  wire    [  7: 0] system_0_burst_17_upstream_readdata;
  wire    [  7: 0] system_0_burst_17_upstream_readdata_from_sa;
  wire             system_0_burst_17_upstream_readdatavalid;
  wire             system_0_burst_17_upstream_waitrequest;
  wire             system_0_burst_17_upstream_waitrequest_from_sa;
  wire             system_0_burst_17_upstream_write;
  wire    [  7: 0] system_0_burst_17_upstream_writedata;
  wire    [  1: 0] system_0_burst_18_downstream_address;
  wire    [  1: 0] system_0_burst_18_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_18_downstream_arbitrationshare;
  wire             system_0_burst_18_downstream_burstcount;
  wire             system_0_burst_18_downstream_byteenable;
  wire             system_0_burst_18_downstream_debugaccess;
  wire             system_0_burst_18_downstream_granted_SD_CMD_s1;
  wire             system_0_burst_18_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_18_downstream_nativeaddress;
  wire             system_0_burst_18_downstream_qualified_request_SD_CMD_s1;
  wire             system_0_burst_18_downstream_read;
  wire             system_0_burst_18_downstream_read_data_valid_SD_CMD_s1;
  wire    [  7: 0] system_0_burst_18_downstream_readdata;
  wire             system_0_burst_18_downstream_readdatavalid;
  wire             system_0_burst_18_downstream_requests_SD_CMD_s1;
  wire             system_0_burst_18_downstream_reset_n;
  wire             system_0_burst_18_downstream_waitrequest;
  wire             system_0_burst_18_downstream_write;
  wire    [  7: 0] system_0_burst_18_downstream_writedata;
  wire    [  1: 0] system_0_burst_18_upstream_address;
  wire    [  3: 0] system_0_burst_18_upstream_burstcount;
  wire    [  1: 0] system_0_burst_18_upstream_byteaddress;
  wire             system_0_burst_18_upstream_byteenable;
  wire             system_0_burst_18_upstream_debugaccess;
  wire             system_0_burst_18_upstream_read;
  wire    [  7: 0] system_0_burst_18_upstream_readdata;
  wire    [  7: 0] system_0_burst_18_upstream_readdata_from_sa;
  wire             system_0_burst_18_upstream_readdatavalid;
  wire             system_0_burst_18_upstream_waitrequest;
  wire             system_0_burst_18_upstream_waitrequest_from_sa;
  wire             system_0_burst_18_upstream_write;
  wire    [  7: 0] system_0_burst_18_upstream_writedata;
  wire    [  1: 0] system_0_burst_19_downstream_address;
  wire    [  1: 0] system_0_burst_19_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_19_downstream_arbitrationshare;
  wire             system_0_burst_19_downstream_burstcount;
  wire             system_0_burst_19_downstream_byteenable;
  wire             system_0_burst_19_downstream_debugaccess;
  wire             system_0_burst_19_downstream_granted_SD_CLK_s1;
  wire             system_0_burst_19_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_19_downstream_nativeaddress;
  wire             system_0_burst_19_downstream_qualified_request_SD_CLK_s1;
  wire             system_0_burst_19_downstream_read;
  wire             system_0_burst_19_downstream_read_data_valid_SD_CLK_s1;
  wire    [  7: 0] system_0_burst_19_downstream_readdata;
  wire             system_0_burst_19_downstream_readdatavalid;
  wire             system_0_burst_19_downstream_requests_SD_CLK_s1;
  wire             system_0_burst_19_downstream_reset_n;
  wire             system_0_burst_19_downstream_waitrequest;
  wire             system_0_burst_19_downstream_write;
  wire    [  7: 0] system_0_burst_19_downstream_writedata;
  wire    [  1: 0] system_0_burst_19_upstream_address;
  wire    [  3: 0] system_0_burst_19_upstream_burstcount;
  wire    [  1: 0] system_0_burst_19_upstream_byteaddress;
  wire             system_0_burst_19_upstream_byteenable;
  wire             system_0_burst_19_upstream_debugaccess;
  wire             system_0_burst_19_upstream_read;
  wire    [  7: 0] system_0_burst_19_upstream_readdata;
  wire    [  7: 0] system_0_burst_19_upstream_readdata_from_sa;
  wire             system_0_burst_19_upstream_readdatavalid;
  wire             system_0_burst_19_upstream_waitrequest;
  wire             system_0_burst_19_upstream_waitrequest_from_sa;
  wire             system_0_burst_19_upstream_write;
  wire    [  7: 0] system_0_burst_19_upstream_writedata;
  wire    [ 10: 0] system_0_burst_1_downstream_address;
  wire    [ 10: 0] system_0_burst_1_downstream_address_to_slave;
  wire    [  3: 0] system_0_burst_1_downstream_arbitrationshare;
  wire             system_0_burst_1_downstream_burstcount;
  wire    [  3: 0] system_0_burst_1_downstream_byteenable;
  wire             system_0_burst_1_downstream_debugaccess;
  wire             system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module;
  wire             system_0_burst_1_downstream_latency_counter;
  wire    [ 10: 0] system_0_burst_1_downstream_nativeaddress;
  wire             system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module;
  wire             system_0_burst_1_downstream_read;
  wire             system_0_burst_1_downstream_read_data_valid_cpu_0_jtag_debug_module;
  wire    [ 31: 0] system_0_burst_1_downstream_readdata;
  wire             system_0_burst_1_downstream_readdatavalid;
  wire             system_0_burst_1_downstream_requests_cpu_0_jtag_debug_module;
  wire             system_0_burst_1_downstream_reset_n;
  wire             system_0_burst_1_downstream_waitrequest;
  wire             system_0_burst_1_downstream_write;
  wire    [ 31: 0] system_0_burst_1_downstream_writedata;
  wire    [ 10: 0] system_0_burst_1_upstream_address;
  wire    [  3: 0] system_0_burst_1_upstream_burstcount;
  wire    [ 12: 0] system_0_burst_1_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_1_upstream_byteenable;
  wire             system_0_burst_1_upstream_debugaccess;
  wire             system_0_burst_1_upstream_read;
  wire    [ 31: 0] system_0_burst_1_upstream_readdata;
  wire    [ 31: 0] system_0_burst_1_upstream_readdata_from_sa;
  wire             system_0_burst_1_upstream_readdatavalid;
  wire             system_0_burst_1_upstream_waitrequest;
  wire             system_0_burst_1_upstream_waitrequest_from_sa;
  wire             system_0_burst_1_upstream_write;
  wire    [ 31: 0] system_0_burst_1_upstream_writedata;
  wire    [  1: 0] system_0_burst_20_downstream_address;
  wire    [  1: 0] system_0_burst_20_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_20_downstream_arbitrationshare;
  wire             system_0_burst_20_downstream_burstcount;
  wire             system_0_burst_20_downstream_byteenable;
  wire             system_0_burst_20_downstream_debugaccess;
  wire             system_0_burst_20_downstream_granted_noteA_s1;
  wire             system_0_burst_20_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_20_downstream_nativeaddress;
  wire             system_0_burst_20_downstream_qualified_request_noteA_s1;
  wire             system_0_burst_20_downstream_read;
  wire             system_0_burst_20_downstream_read_data_valid_noteA_s1;
  wire    [  7: 0] system_0_burst_20_downstream_readdata;
  wire             system_0_burst_20_downstream_readdatavalid;
  wire             system_0_burst_20_downstream_requests_noteA_s1;
  wire             system_0_burst_20_downstream_reset_n;
  wire             system_0_burst_20_downstream_waitrequest;
  wire             system_0_burst_20_downstream_write;
  wire    [  7: 0] system_0_burst_20_downstream_writedata;
  wire    [  1: 0] system_0_burst_20_upstream_address;
  wire    [  3: 0] system_0_burst_20_upstream_burstcount;
  wire    [  1: 0] system_0_burst_20_upstream_byteaddress;
  wire             system_0_burst_20_upstream_byteenable;
  wire             system_0_burst_20_upstream_debugaccess;
  wire             system_0_burst_20_upstream_read;
  wire    [  7: 0] system_0_burst_20_upstream_readdata;
  wire    [  7: 0] system_0_burst_20_upstream_readdata_from_sa;
  wire             system_0_burst_20_upstream_readdatavalid;
  wire             system_0_burst_20_upstream_waitrequest;
  wire             system_0_burst_20_upstream_waitrequest_from_sa;
  wire             system_0_burst_20_upstream_write;
  wire    [  7: 0] system_0_burst_20_upstream_writedata;
  wire    [  1: 0] system_0_burst_21_downstream_address;
  wire    [  1: 0] system_0_burst_21_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_21_downstream_arbitrationshare;
  wire             system_0_burst_21_downstream_burstcount;
  wire             system_0_burst_21_downstream_byteenable;
  wire             system_0_burst_21_downstream_debugaccess;
  wire             system_0_burst_21_downstream_granted_noteB_s1;
  wire             system_0_burst_21_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_21_downstream_nativeaddress;
  wire             system_0_burst_21_downstream_qualified_request_noteB_s1;
  wire             system_0_burst_21_downstream_read;
  wire             system_0_burst_21_downstream_read_data_valid_noteB_s1;
  wire    [  7: 0] system_0_burst_21_downstream_readdata;
  wire             system_0_burst_21_downstream_readdatavalid;
  wire             system_0_burst_21_downstream_requests_noteB_s1;
  wire             system_0_burst_21_downstream_reset_n;
  wire             system_0_burst_21_downstream_waitrequest;
  wire             system_0_burst_21_downstream_write;
  wire    [  7: 0] system_0_burst_21_downstream_writedata;
  wire    [  1: 0] system_0_burst_21_upstream_address;
  wire    [  3: 0] system_0_burst_21_upstream_burstcount;
  wire    [  1: 0] system_0_burst_21_upstream_byteaddress;
  wire             system_0_burst_21_upstream_byteenable;
  wire             system_0_burst_21_upstream_debugaccess;
  wire             system_0_burst_21_upstream_read;
  wire    [  7: 0] system_0_burst_21_upstream_readdata;
  wire    [  7: 0] system_0_burst_21_upstream_readdata_from_sa;
  wire             system_0_burst_21_upstream_readdatavalid;
  wire             system_0_burst_21_upstream_waitrequest;
  wire             system_0_burst_21_upstream_waitrequest_from_sa;
  wire             system_0_burst_21_upstream_write;
  wire    [  7: 0] system_0_burst_21_upstream_writedata;
  wire    [  1: 0] system_0_burst_22_downstream_address;
  wire    [  1: 0] system_0_burst_22_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_22_downstream_arbitrationshare;
  wire             system_0_burst_22_downstream_burstcount;
  wire             system_0_burst_22_downstream_byteenable;
  wire             system_0_burst_22_downstream_debugaccess;
  wire             system_0_burst_22_downstream_granted_noteC_s1;
  wire             system_0_burst_22_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_22_downstream_nativeaddress;
  wire             system_0_burst_22_downstream_qualified_request_noteC_s1;
  wire             system_0_burst_22_downstream_read;
  wire             system_0_burst_22_downstream_read_data_valid_noteC_s1;
  wire    [  7: 0] system_0_burst_22_downstream_readdata;
  wire             system_0_burst_22_downstream_readdatavalid;
  wire             system_0_burst_22_downstream_requests_noteC_s1;
  wire             system_0_burst_22_downstream_reset_n;
  wire             system_0_burst_22_downstream_waitrequest;
  wire             system_0_burst_22_downstream_write;
  wire    [  7: 0] system_0_burst_22_downstream_writedata;
  wire    [  1: 0] system_0_burst_22_upstream_address;
  wire    [  3: 0] system_0_burst_22_upstream_burstcount;
  wire    [  1: 0] system_0_burst_22_upstream_byteaddress;
  wire             system_0_burst_22_upstream_byteenable;
  wire             system_0_burst_22_upstream_debugaccess;
  wire             system_0_burst_22_upstream_read;
  wire    [  7: 0] system_0_burst_22_upstream_readdata;
  wire    [  7: 0] system_0_burst_22_upstream_readdata_from_sa;
  wire             system_0_burst_22_upstream_readdatavalid;
  wire             system_0_burst_22_upstream_waitrequest;
  wire             system_0_burst_22_upstream_waitrequest_from_sa;
  wire             system_0_burst_22_upstream_write;
  wire    [  7: 0] system_0_burst_22_upstream_writedata;
  wire    [  1: 0] system_0_burst_23_downstream_address;
  wire    [  1: 0] system_0_burst_23_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_23_downstream_arbitrationshare;
  wire             system_0_burst_23_downstream_burstcount;
  wire             system_0_burst_23_downstream_byteenable;
  wire             system_0_burst_23_downstream_debugaccess;
  wire             system_0_burst_23_downstream_granted_noteD_s1;
  wire             system_0_burst_23_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_23_downstream_nativeaddress;
  wire             system_0_burst_23_downstream_qualified_request_noteD_s1;
  wire             system_0_burst_23_downstream_read;
  wire             system_0_burst_23_downstream_read_data_valid_noteD_s1;
  wire    [  7: 0] system_0_burst_23_downstream_readdata;
  wire             system_0_burst_23_downstream_readdatavalid;
  wire             system_0_burst_23_downstream_requests_noteD_s1;
  wire             system_0_burst_23_downstream_reset_n;
  wire             system_0_burst_23_downstream_waitrequest;
  wire             system_0_burst_23_downstream_write;
  wire    [  7: 0] system_0_burst_23_downstream_writedata;
  wire    [  1: 0] system_0_burst_23_upstream_address;
  wire    [  3: 0] system_0_burst_23_upstream_burstcount;
  wire    [  1: 0] system_0_burst_23_upstream_byteaddress;
  wire             system_0_burst_23_upstream_byteenable;
  wire             system_0_burst_23_upstream_debugaccess;
  wire             system_0_burst_23_upstream_read;
  wire    [  7: 0] system_0_burst_23_upstream_readdata;
  wire    [  7: 0] system_0_burst_23_upstream_readdata_from_sa;
  wire             system_0_burst_23_upstream_readdatavalid;
  wire             system_0_burst_23_upstream_waitrequest;
  wire             system_0_burst_23_upstream_waitrequest_from_sa;
  wire             system_0_burst_23_upstream_write;
  wire    [  7: 0] system_0_burst_23_upstream_writedata;
  wire    [  1: 0] system_0_burst_24_downstream_address;
  wire    [  1: 0] system_0_burst_24_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_24_downstream_arbitrationshare;
  wire             system_0_burst_24_downstream_burstcount;
  wire             system_0_burst_24_downstream_byteenable;
  wire             system_0_burst_24_downstream_debugaccess;
  wire             system_0_burst_24_downstream_granted_noteE_s1;
  wire             system_0_burst_24_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_24_downstream_nativeaddress;
  wire             system_0_burst_24_downstream_qualified_request_noteE_s1;
  wire             system_0_burst_24_downstream_read;
  wire             system_0_burst_24_downstream_read_data_valid_noteE_s1;
  wire    [  7: 0] system_0_burst_24_downstream_readdata;
  wire             system_0_burst_24_downstream_readdatavalid;
  wire             system_0_burst_24_downstream_requests_noteE_s1;
  wire             system_0_burst_24_downstream_reset_n;
  wire             system_0_burst_24_downstream_waitrequest;
  wire             system_0_burst_24_downstream_write;
  wire    [  7: 0] system_0_burst_24_downstream_writedata;
  wire    [  1: 0] system_0_burst_24_upstream_address;
  wire    [  3: 0] system_0_burst_24_upstream_burstcount;
  wire    [  1: 0] system_0_burst_24_upstream_byteaddress;
  wire             system_0_burst_24_upstream_byteenable;
  wire             system_0_burst_24_upstream_debugaccess;
  wire             system_0_burst_24_upstream_read;
  wire    [  7: 0] system_0_burst_24_upstream_readdata;
  wire    [  7: 0] system_0_burst_24_upstream_readdata_from_sa;
  wire             system_0_burst_24_upstream_readdatavalid;
  wire             system_0_burst_24_upstream_waitrequest;
  wire             system_0_burst_24_upstream_waitrequest_from_sa;
  wire             system_0_burst_24_upstream_write;
  wire    [  7: 0] system_0_burst_24_upstream_writedata;
  wire    [  1: 0] system_0_burst_25_downstream_address;
  wire    [  1: 0] system_0_burst_25_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_25_downstream_arbitrationshare;
  wire             system_0_burst_25_downstream_burstcount;
  wire             system_0_burst_25_downstream_byteenable;
  wire             system_0_burst_25_downstream_debugaccess;
  wire             system_0_burst_25_downstream_granted_noteF_s1;
  wire             system_0_burst_25_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_25_downstream_nativeaddress;
  wire             system_0_burst_25_downstream_qualified_request_noteF_s1;
  wire             system_0_burst_25_downstream_read;
  wire             system_0_burst_25_downstream_read_data_valid_noteF_s1;
  wire    [  7: 0] system_0_burst_25_downstream_readdata;
  wire             system_0_burst_25_downstream_readdatavalid;
  wire             system_0_burst_25_downstream_requests_noteF_s1;
  wire             system_0_burst_25_downstream_reset_n;
  wire             system_0_burst_25_downstream_waitrequest;
  wire             system_0_burst_25_downstream_write;
  wire    [  7: 0] system_0_burst_25_downstream_writedata;
  wire    [  1: 0] system_0_burst_25_upstream_address;
  wire    [  3: 0] system_0_burst_25_upstream_burstcount;
  wire    [  1: 0] system_0_burst_25_upstream_byteaddress;
  wire             system_0_burst_25_upstream_byteenable;
  wire             system_0_burst_25_upstream_debugaccess;
  wire             system_0_burst_25_upstream_read;
  wire    [  7: 0] system_0_burst_25_upstream_readdata;
  wire    [  7: 0] system_0_burst_25_upstream_readdata_from_sa;
  wire             system_0_burst_25_upstream_readdatavalid;
  wire             system_0_burst_25_upstream_waitrequest;
  wire             system_0_burst_25_upstream_waitrequest_from_sa;
  wire             system_0_burst_25_upstream_write;
  wire    [  7: 0] system_0_burst_25_upstream_writedata;
  wire    [  1: 0] system_0_burst_26_downstream_address;
  wire    [  1: 0] system_0_burst_26_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_26_downstream_arbitrationshare;
  wire             system_0_burst_26_downstream_burstcount;
  wire             system_0_burst_26_downstream_byteenable;
  wire             system_0_burst_26_downstream_debugaccess;
  wire             system_0_burst_26_downstream_granted_noteG_s1;
  wire             system_0_burst_26_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_26_downstream_nativeaddress;
  wire             system_0_burst_26_downstream_qualified_request_noteG_s1;
  wire             system_0_burst_26_downstream_read;
  wire             system_0_burst_26_downstream_read_data_valid_noteG_s1;
  wire    [  7: 0] system_0_burst_26_downstream_readdata;
  wire             system_0_burst_26_downstream_readdatavalid;
  wire             system_0_burst_26_downstream_requests_noteG_s1;
  wire             system_0_burst_26_downstream_reset_n;
  wire             system_0_burst_26_downstream_waitrequest;
  wire             system_0_burst_26_downstream_write;
  wire    [  7: 0] system_0_burst_26_downstream_writedata;
  wire    [  1: 0] system_0_burst_26_upstream_address;
  wire    [  3: 0] system_0_burst_26_upstream_burstcount;
  wire    [  1: 0] system_0_burst_26_upstream_byteaddress;
  wire             system_0_burst_26_upstream_byteenable;
  wire             system_0_burst_26_upstream_debugaccess;
  wire             system_0_burst_26_upstream_read;
  wire    [  7: 0] system_0_burst_26_upstream_readdata;
  wire    [  7: 0] system_0_burst_26_upstream_readdata_from_sa;
  wire             system_0_burst_26_upstream_readdatavalid;
  wire             system_0_burst_26_upstream_waitrequest;
  wire             system_0_burst_26_upstream_waitrequest_from_sa;
  wire             system_0_burst_26_upstream_write;
  wire    [  7: 0] system_0_burst_26_upstream_writedata;
  wire    [  1: 0] system_0_burst_27_downstream_address;
  wire    [  1: 0] system_0_burst_27_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_27_downstream_arbitrationshare;
  wire             system_0_burst_27_downstream_burstcount;
  wire             system_0_burst_27_downstream_byteenable;
  wire             system_0_burst_27_downstream_debugaccess;
  wire             system_0_burst_27_downstream_granted_MS_s1;
  wire             system_0_burst_27_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_27_downstream_nativeaddress;
  wire             system_0_burst_27_downstream_qualified_request_MS_s1;
  wire             system_0_burst_27_downstream_read;
  wire             system_0_burst_27_downstream_read_data_valid_MS_s1;
  wire    [  7: 0] system_0_burst_27_downstream_readdata;
  wire             system_0_burst_27_downstream_readdatavalid;
  wire             system_0_burst_27_downstream_requests_MS_s1;
  wire             system_0_burst_27_downstream_reset_n;
  wire             system_0_burst_27_downstream_waitrequest;
  wire             system_0_burst_27_downstream_write;
  wire    [  7: 0] system_0_burst_27_downstream_writedata;
  wire    [  1: 0] system_0_burst_27_upstream_address;
  wire    [  3: 0] system_0_burst_27_upstream_burstcount;
  wire    [  1: 0] system_0_burst_27_upstream_byteaddress;
  wire             system_0_burst_27_upstream_byteenable;
  wire             system_0_burst_27_upstream_debugaccess;
  wire             system_0_burst_27_upstream_read;
  wire    [  7: 0] system_0_burst_27_upstream_readdata;
  wire    [  7: 0] system_0_burst_27_upstream_readdata_from_sa;
  wire             system_0_burst_27_upstream_readdatavalid;
  wire             system_0_burst_27_upstream_waitrequest;
  wire             system_0_burst_27_upstream_waitrequest_from_sa;
  wire             system_0_burst_27_upstream_write;
  wire    [  7: 0] system_0_burst_27_upstream_writedata;
  wire    [  1: 0] system_0_burst_28_downstream_address;
  wire    [  1: 0] system_0_burst_28_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_28_downstream_arbitrationshare;
  wire             system_0_burst_28_downstream_burstcount;
  wire             system_0_burst_28_downstream_byteenable;
  wire             system_0_burst_28_downstream_debugaccess;
  wire             system_0_burst_28_downstream_granted_dist_sensor_s1;
  wire             system_0_burst_28_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_28_downstream_nativeaddress;
  wire             system_0_burst_28_downstream_qualified_request_dist_sensor_s1;
  wire             system_0_burst_28_downstream_read;
  wire             system_0_burst_28_downstream_read_data_valid_dist_sensor_s1;
  wire    [  7: 0] system_0_burst_28_downstream_readdata;
  wire             system_0_burst_28_downstream_readdatavalid;
  wire             system_0_burst_28_downstream_requests_dist_sensor_s1;
  wire             system_0_burst_28_downstream_reset_n;
  wire             system_0_burst_28_downstream_waitrequest;
  wire             system_0_burst_28_downstream_write;
  wire    [  7: 0] system_0_burst_28_downstream_writedata;
  wire    [  1: 0] system_0_burst_28_upstream_address;
  wire    [  3: 0] system_0_burst_28_upstream_burstcount;
  wire    [  1: 0] system_0_burst_28_upstream_byteaddress;
  wire             system_0_burst_28_upstream_byteenable;
  wire             system_0_burst_28_upstream_debugaccess;
  wire             system_0_burst_28_upstream_read;
  wire    [  7: 0] system_0_burst_28_upstream_readdata;
  wire    [  7: 0] system_0_burst_28_upstream_readdata_from_sa;
  wire             system_0_burst_28_upstream_readdatavalid;
  wire             system_0_burst_28_upstream_waitrequest;
  wire             system_0_burst_28_upstream_waitrequest_from_sa;
  wire             system_0_burst_28_upstream_write;
  wire    [  7: 0] system_0_burst_28_upstream_writedata;
  wire    [  1: 0] system_0_burst_29_downstream_address;
  wire    [  1: 0] system_0_burst_29_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_29_downstream_arbitrationshare;
  wire             system_0_burst_29_downstream_burstcount;
  wire             system_0_burst_29_downstream_byteenable;
  wire             system_0_burst_29_downstream_debugaccess;
  wire             system_0_burst_29_downstream_granted_RST_s1;
  wire             system_0_burst_29_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_29_downstream_nativeaddress;
  wire             system_0_burst_29_downstream_qualified_request_RST_s1;
  wire             system_0_burst_29_downstream_read;
  wire             system_0_burst_29_downstream_read_data_valid_RST_s1;
  wire    [  7: 0] system_0_burst_29_downstream_readdata;
  wire             system_0_burst_29_downstream_readdatavalid;
  wire             system_0_burst_29_downstream_requests_RST_s1;
  wire             system_0_burst_29_downstream_reset_n;
  wire             system_0_burst_29_downstream_waitrequest;
  wire             system_0_burst_29_downstream_write;
  wire    [  7: 0] system_0_burst_29_downstream_writedata;
  wire    [  1: 0] system_0_burst_29_upstream_address;
  wire    [  3: 0] system_0_burst_29_upstream_burstcount;
  wire    [  1: 0] system_0_burst_29_upstream_byteaddress;
  wire             system_0_burst_29_upstream_byteenable;
  wire             system_0_burst_29_upstream_debugaccess;
  wire             system_0_burst_29_upstream_read;
  wire    [  7: 0] system_0_burst_29_upstream_readdata;
  wire    [  7: 0] system_0_burst_29_upstream_readdata_from_sa;
  wire             system_0_burst_29_upstream_readdatavalid;
  wire             system_0_burst_29_upstream_waitrequest;
  wire             system_0_burst_29_upstream_waitrequest_from_sa;
  wire             system_0_burst_29_upstream_write;
  wire    [  7: 0] system_0_burst_29_upstream_writedata;
  wire    [ 21: 0] system_0_burst_2_downstream_address;
  wire    [ 21: 0] system_0_burst_2_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_2_downstream_arbitrationshare;
  wire             system_0_burst_2_downstream_burstcount;
  wire             system_0_burst_2_downstream_byteenable;
  wire             system_0_burst_2_downstream_debugaccess;
  wire             system_0_burst_2_downstream_granted_cfi_flash_0_s1;
  wire    [  1: 0] system_0_burst_2_downstream_latency_counter;
  wire    [ 21: 0] system_0_burst_2_downstream_nativeaddress;
  wire             system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1;
  wire             system_0_burst_2_downstream_read;
  wire             system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1;
  wire    [  7: 0] system_0_burst_2_downstream_readdata;
  wire             system_0_burst_2_downstream_readdatavalid;
  wire             system_0_burst_2_downstream_requests_cfi_flash_0_s1;
  wire             system_0_burst_2_downstream_reset_n;
  wire             system_0_burst_2_downstream_waitrequest;
  wire             system_0_burst_2_downstream_write;
  wire    [  7: 0] system_0_burst_2_downstream_writedata;
  wire    [ 21: 0] system_0_burst_2_upstream_address;
  wire    [ 21: 0] system_0_burst_2_upstream_byteaddress;
  wire             system_0_burst_2_upstream_byteenable;
  wire             system_0_burst_2_upstream_debugaccess;
  wire             system_0_burst_2_upstream_read;
  wire    [  7: 0] system_0_burst_2_upstream_readdata;
  wire    [  7: 0] system_0_burst_2_upstream_readdata_from_sa;
  wire             system_0_burst_2_upstream_readdatavalid;
  wire             system_0_burst_2_upstream_waitrequest;
  wire             system_0_burst_2_upstream_waitrequest_from_sa;
  wire             system_0_burst_2_upstream_write;
  wire    [  7: 0] system_0_burst_2_upstream_writedata;
  wire    [  1: 0] system_0_burst_30_downstream_address;
  wire    [  1: 0] system_0_burst_30_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_30_downstream_arbitrationshare;
  wire             system_0_burst_30_downstream_burstcount;
  wire             system_0_burst_30_downstream_byteenable;
  wire             system_0_burst_30_downstream_debugaccess;
  wire             system_0_burst_30_downstream_granted_Oct_UP_s1;
  wire             system_0_burst_30_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_30_downstream_nativeaddress;
  wire             system_0_burst_30_downstream_qualified_request_Oct_UP_s1;
  wire             system_0_burst_30_downstream_read;
  wire             system_0_burst_30_downstream_read_data_valid_Oct_UP_s1;
  wire    [  7: 0] system_0_burst_30_downstream_readdata;
  wire             system_0_burst_30_downstream_readdatavalid;
  wire             system_0_burst_30_downstream_requests_Oct_UP_s1;
  wire             system_0_burst_30_downstream_reset_n;
  wire             system_0_burst_30_downstream_waitrequest;
  wire             system_0_burst_30_downstream_write;
  wire    [  7: 0] system_0_burst_30_downstream_writedata;
  wire    [  1: 0] system_0_burst_30_upstream_address;
  wire    [  3: 0] system_0_burst_30_upstream_burstcount;
  wire    [  1: 0] system_0_burst_30_upstream_byteaddress;
  wire             system_0_burst_30_upstream_byteenable;
  wire             system_0_burst_30_upstream_debugaccess;
  wire             system_0_burst_30_upstream_read;
  wire    [  7: 0] system_0_burst_30_upstream_readdata;
  wire    [  7: 0] system_0_burst_30_upstream_readdata_from_sa;
  wire             system_0_burst_30_upstream_readdatavalid;
  wire             system_0_burst_30_upstream_waitrequest;
  wire             system_0_burst_30_upstream_waitrequest_from_sa;
  wire             system_0_burst_30_upstream_write;
  wire    [  7: 0] system_0_burst_30_upstream_writedata;
  wire    [  1: 0] system_0_burst_31_downstream_address;
  wire    [  1: 0] system_0_burst_31_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_31_downstream_arbitrationshare;
  wire             system_0_burst_31_downstream_burstcount;
  wire             system_0_burst_31_downstream_byteenable;
  wire             system_0_burst_31_downstream_debugaccess;
  wire             system_0_burst_31_downstream_granted_Oct_DOWN_s1;
  wire             system_0_burst_31_downstream_latency_counter;
  wire    [  1: 0] system_0_burst_31_downstream_nativeaddress;
  wire             system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1;
  wire             system_0_burst_31_downstream_read;
  wire             system_0_burst_31_downstream_read_data_valid_Oct_DOWN_s1;
  wire    [  7: 0] system_0_burst_31_downstream_readdata;
  wire             system_0_burst_31_downstream_readdatavalid;
  wire             system_0_burst_31_downstream_requests_Oct_DOWN_s1;
  wire             system_0_burst_31_downstream_reset_n;
  wire             system_0_burst_31_downstream_waitrequest;
  wire             system_0_burst_31_downstream_write;
  wire    [  7: 0] system_0_burst_31_downstream_writedata;
  wire    [  1: 0] system_0_burst_31_upstream_address;
  wire    [  3: 0] system_0_burst_31_upstream_burstcount;
  wire    [  1: 0] system_0_burst_31_upstream_byteaddress;
  wire             system_0_burst_31_upstream_byteenable;
  wire             system_0_burst_31_upstream_debugaccess;
  wire             system_0_burst_31_upstream_read;
  wire    [  7: 0] system_0_burst_31_upstream_readdata;
  wire    [  7: 0] system_0_burst_31_upstream_readdata_from_sa;
  wire             system_0_burst_31_upstream_readdatavalid;
  wire             system_0_burst_31_upstream_waitrequest;
  wire             system_0_burst_31_upstream_waitrequest_from_sa;
  wire             system_0_burst_31_upstream_write;
  wire    [  7: 0] system_0_burst_31_upstream_writedata;
  wire    [  4: 0] system_0_burst_32_downstream_address;
  wire    [  4: 0] system_0_burst_32_downstream_address_to_slave;
  wire    [  3: 0] system_0_burst_32_downstream_arbitrationshare;
  wire             system_0_burst_32_downstream_burstcount;
  wire    [  3: 0] system_0_burst_32_downstream_byteenable;
  wire             system_0_burst_32_downstream_debugaccess;
  wire             system_0_burst_32_downstream_granted_Accel_Control_avalon_slave;
  wire             system_0_burst_32_downstream_latency_counter;
  wire    [  4: 0] system_0_burst_32_downstream_nativeaddress;
  wire             system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave;
  wire             system_0_burst_32_downstream_read;
  wire             system_0_burst_32_downstream_read_data_valid_Accel_Control_avalon_slave;
  wire    [ 31: 0] system_0_burst_32_downstream_readdata;
  wire             system_0_burst_32_downstream_readdatavalid;
  wire             system_0_burst_32_downstream_requests_Accel_Control_avalon_slave;
  wire             system_0_burst_32_downstream_reset_n;
  wire             system_0_burst_32_downstream_waitrequest;
  wire             system_0_burst_32_downstream_write;
  wire    [ 31: 0] system_0_burst_32_downstream_writedata;
  wire    [  4: 0] system_0_burst_32_upstream_address;
  wire    [  3: 0] system_0_burst_32_upstream_burstcount;
  wire    [  6: 0] system_0_burst_32_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_32_upstream_byteenable;
  wire             system_0_burst_32_upstream_debugaccess;
  wire             system_0_burst_32_upstream_read;
  wire    [ 31: 0] system_0_burst_32_upstream_readdata;
  wire    [ 31: 0] system_0_burst_32_upstream_readdata_from_sa;
  wire             system_0_burst_32_upstream_readdatavalid;
  wire             system_0_burst_32_upstream_waitrequest;
  wire             system_0_burst_32_upstream_waitrequest_from_sa;
  wire             system_0_burst_32_upstream_write;
  wire    [ 31: 0] system_0_burst_32_upstream_writedata;
  wire    [  4: 0] system_0_burst_33_downstream_address;
  wire    [  4: 0] system_0_burst_33_downstream_address_to_slave;
  wire    [  3: 0] system_0_burst_33_downstream_arbitrationshare;
  wire             system_0_burst_33_downstream_burstcount;
  wire    [  3: 0] system_0_burst_33_downstream_byteenable;
  wire             system_0_burst_33_downstream_debugaccess;
  wire             system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0;
  wire             system_0_burst_33_downstream_latency_counter;
  wire    [  4: 0] system_0_burst_33_downstream_nativeaddress;
  wire             system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0;
  wire             system_0_burst_33_downstream_read;
  wire             system_0_burst_33_downstream_read_data_valid_i2c_master_avalon_slave_0;
  wire    [ 31: 0] system_0_burst_33_downstream_readdata;
  wire             system_0_burst_33_downstream_readdatavalid;
  wire             system_0_burst_33_downstream_requests_i2c_master_avalon_slave_0;
  wire             system_0_burst_33_downstream_reset_n;
  wire             system_0_burst_33_downstream_waitrequest;
  wire             system_0_burst_33_downstream_write;
  wire    [ 31: 0] system_0_burst_33_downstream_writedata;
  wire    [  4: 0] system_0_burst_33_upstream_address;
  wire    [  6: 0] system_0_burst_33_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_33_upstream_byteenable;
  wire             system_0_burst_33_upstream_debugaccess;
  wire             system_0_burst_33_upstream_read;
  wire    [ 31: 0] system_0_burst_33_upstream_readdata;
  wire    [ 31: 0] system_0_burst_33_upstream_readdata_from_sa;
  wire             system_0_burst_33_upstream_readdatavalid;
  wire             system_0_burst_33_upstream_waitrequest;
  wire             system_0_burst_33_upstream_waitrequest_from_sa;
  wire             system_0_burst_33_upstream_write;
  wire    [ 31: 0] system_0_burst_33_upstream_writedata;
  wire    [  4: 0] system_0_burst_34_downstream_address;
  wire    [  4: 0] system_0_burst_34_downstream_address_to_slave;
  wire    [  3: 0] system_0_burst_34_downstream_arbitrationshare;
  wire             system_0_burst_34_downstream_burstcount;
  wire    [  3: 0] system_0_burst_34_downstream_byteenable;
  wire             system_0_burst_34_downstream_debugaccess;
  wire             system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0;
  wire             system_0_burst_34_downstream_latency_counter;
  wire    [  4: 0] system_0_burst_34_downstream_nativeaddress;
  wire             system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0;
  wire             system_0_burst_34_downstream_read;
  wire             system_0_burst_34_downstream_read_data_valid_i2c_master_avalon_slave_0;
  wire    [ 31: 0] system_0_burst_34_downstream_readdata;
  wire             system_0_burst_34_downstream_readdatavalid;
  wire             system_0_burst_34_downstream_requests_i2c_master_avalon_slave_0;
  wire             system_0_burst_34_downstream_reset_n;
  wire             system_0_burst_34_downstream_waitrequest;
  wire             system_0_burst_34_downstream_write;
  wire    [ 31: 0] system_0_burst_34_downstream_writedata;
  wire    [  4: 0] system_0_burst_34_upstream_address;
  wire    [  3: 0] system_0_burst_34_upstream_burstcount;
  wire    [  6: 0] system_0_burst_34_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_34_upstream_byteenable;
  wire             system_0_burst_34_upstream_debugaccess;
  wire             system_0_burst_34_upstream_read;
  wire    [ 31: 0] system_0_burst_34_upstream_readdata;
  wire    [ 31: 0] system_0_burst_34_upstream_readdata_from_sa;
  wire             system_0_burst_34_upstream_readdatavalid;
  wire             system_0_burst_34_upstream_waitrequest;
  wire             system_0_burst_34_upstream_waitrequest_from_sa;
  wire             system_0_burst_34_upstream_write;
  wire    [ 31: 0] system_0_burst_34_upstream_writedata;
  wire    [  3: 0] system_0_burst_35_downstream_address;
  wire    [  3: 0] system_0_burst_35_downstream_address_to_slave;
  wire    [  3: 0] system_0_burst_35_downstream_arbitrationshare;
  wire             system_0_burst_35_downstream_burstcount;
  wire    [  3: 0] system_0_burst_35_downstream_byteenable;
  wire             system_0_burst_35_downstream_debugaccess;
  wire             system_0_burst_35_downstream_granted_system_0_clock_0_in;
  wire             system_0_burst_35_downstream_latency_counter;
  wire    [  3: 0] system_0_burst_35_downstream_nativeaddress;
  wire             system_0_burst_35_downstream_qualified_request_system_0_clock_0_in;
  wire             system_0_burst_35_downstream_read;
  wire             system_0_burst_35_downstream_read_data_valid_system_0_clock_0_in;
  wire    [ 31: 0] system_0_burst_35_downstream_readdata;
  wire             system_0_burst_35_downstream_readdatavalid;
  wire             system_0_burst_35_downstream_requests_system_0_clock_0_in;
  wire             system_0_burst_35_downstream_reset_n;
  wire             system_0_burst_35_downstream_waitrequest;
  wire             system_0_burst_35_downstream_write;
  wire    [ 31: 0] system_0_burst_35_downstream_writedata;
  wire    [  3: 0] system_0_burst_35_upstream_address;
  wire    [  3: 0] system_0_burst_35_upstream_burstcount;
  wire    [  5: 0] system_0_burst_35_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_35_upstream_byteenable;
  wire             system_0_burst_35_upstream_debugaccess;
  wire             system_0_burst_35_upstream_read;
  wire    [ 31: 0] system_0_burst_35_upstream_readdata;
  wire    [ 31: 0] system_0_burst_35_upstream_readdata_from_sa;
  wire             system_0_burst_35_upstream_readdatavalid;
  wire             system_0_burst_35_upstream_waitrequest;
  wire             system_0_burst_35_upstream_waitrequest_from_sa;
  wire             system_0_burst_35_upstream_write;
  wire    [ 31: 0] system_0_burst_35_upstream_writedata;
  wire    [ 21: 0] system_0_burst_3_downstream_address;
  wire    [ 21: 0] system_0_burst_3_downstream_address_to_slave;
  wire    [  5: 0] system_0_burst_3_downstream_arbitrationshare;
  wire             system_0_burst_3_downstream_burstcount;
  wire             system_0_burst_3_downstream_byteenable;
  wire             system_0_burst_3_downstream_debugaccess;
  wire             system_0_burst_3_downstream_granted_cfi_flash_0_s1;
  wire    [  1: 0] system_0_burst_3_downstream_latency_counter;
  wire    [ 21: 0] system_0_burst_3_downstream_nativeaddress;
  wire             system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1;
  wire             system_0_burst_3_downstream_read;
  wire             system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1;
  wire    [  7: 0] system_0_burst_3_downstream_readdata;
  wire             system_0_burst_3_downstream_readdatavalid;
  wire             system_0_burst_3_downstream_requests_cfi_flash_0_s1;
  wire             system_0_burst_3_downstream_reset_n;
  wire             system_0_burst_3_downstream_waitrequest;
  wire             system_0_burst_3_downstream_write;
  wire    [  7: 0] system_0_burst_3_downstream_writedata;
  wire    [ 21: 0] system_0_burst_3_upstream_address;
  wire    [  3: 0] system_0_burst_3_upstream_burstcount;
  wire    [ 21: 0] system_0_burst_3_upstream_byteaddress;
  wire             system_0_burst_3_upstream_byteenable;
  wire             system_0_burst_3_upstream_debugaccess;
  wire             system_0_burst_3_upstream_read;
  wire    [  7: 0] system_0_burst_3_upstream_readdata;
  wire    [  7: 0] system_0_burst_3_upstream_readdata_from_sa;
  wire             system_0_burst_3_upstream_readdatavalid;
  wire             system_0_burst_3_upstream_waitrequest;
  wire             system_0_burst_3_upstream_waitrequest_from_sa;
  wire             system_0_burst_3_upstream_write;
  wire    [  7: 0] system_0_burst_3_upstream_writedata;
  wire    [ 22: 0] system_0_burst_4_downstream_address;
  wire    [ 22: 0] system_0_burst_4_downstream_address_to_slave;
  wire    [  4: 0] system_0_burst_4_downstream_arbitrationshare;
  wire             system_0_burst_4_downstream_burstcount;
  wire    [  1: 0] system_0_burst_4_downstream_byteenable;
  wire             system_0_burst_4_downstream_debugaccess;
  wire             system_0_burst_4_downstream_granted_sdram_0_s1;
  wire             system_0_burst_4_downstream_latency_counter;
  wire    [ 22: 0] system_0_burst_4_downstream_nativeaddress;
  wire             system_0_burst_4_downstream_qualified_request_sdram_0_s1;
  wire             system_0_burst_4_downstream_read;
  wire             system_0_burst_4_downstream_read_data_valid_sdram_0_s1;
  wire             system_0_burst_4_downstream_read_data_valid_sdram_0_s1_shift_register;
  wire    [ 15: 0] system_0_burst_4_downstream_readdata;
  wire             system_0_burst_4_downstream_readdatavalid;
  wire             system_0_burst_4_downstream_requests_sdram_0_s1;
  wire             system_0_burst_4_downstream_reset_n;
  wire             system_0_burst_4_downstream_waitrequest;
  wire             system_0_burst_4_downstream_write;
  wire    [ 15: 0] system_0_burst_4_downstream_writedata;
  wire    [ 22: 0] system_0_burst_4_upstream_address;
  wire    [ 23: 0] system_0_burst_4_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_4_upstream_byteenable;
  wire             system_0_burst_4_upstream_debugaccess;
  wire             system_0_burst_4_upstream_read;
  wire    [ 15: 0] system_0_burst_4_upstream_readdata;
  wire    [ 15: 0] system_0_burst_4_upstream_readdata_from_sa;
  wire             system_0_burst_4_upstream_readdatavalid;
  wire             system_0_burst_4_upstream_waitrequest;
  wire             system_0_burst_4_upstream_waitrequest_from_sa;
  wire             system_0_burst_4_upstream_write;
  wire    [ 15: 0] system_0_burst_4_upstream_writedata;
  wire    [ 22: 0] system_0_burst_5_downstream_address;
  wire    [ 22: 0] system_0_burst_5_downstream_address_to_slave;
  wire    [  4: 0] system_0_burst_5_downstream_arbitrationshare;
  wire             system_0_burst_5_downstream_burstcount;
  wire    [  1: 0] system_0_burst_5_downstream_byteenable;
  wire             system_0_burst_5_downstream_debugaccess;
  wire             system_0_burst_5_downstream_granted_sdram_0_s1;
  wire             system_0_burst_5_downstream_latency_counter;
  wire    [ 22: 0] system_0_burst_5_downstream_nativeaddress;
  wire             system_0_burst_5_downstream_qualified_request_sdram_0_s1;
  wire             system_0_burst_5_downstream_read;
  wire             system_0_burst_5_downstream_read_data_valid_sdram_0_s1;
  wire             system_0_burst_5_downstream_read_data_valid_sdram_0_s1_shift_register;
  wire    [ 15: 0] system_0_burst_5_downstream_readdata;
  wire             system_0_burst_5_downstream_readdatavalid;
  wire             system_0_burst_5_downstream_requests_sdram_0_s1;
  wire             system_0_burst_5_downstream_reset_n;
  wire             system_0_burst_5_downstream_waitrequest;
  wire             system_0_burst_5_downstream_write;
  wire    [ 15: 0] system_0_burst_5_downstream_writedata;
  wire    [ 22: 0] system_0_burst_5_upstream_address;
  wire    [  3: 0] system_0_burst_5_upstream_burstcount;
  wire    [ 23: 0] system_0_burst_5_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_5_upstream_byteenable;
  wire             system_0_burst_5_upstream_debugaccess;
  wire             system_0_burst_5_upstream_read;
  wire    [ 15: 0] system_0_burst_5_upstream_readdata;
  wire    [ 15: 0] system_0_burst_5_upstream_readdata_from_sa;
  wire             system_0_burst_5_upstream_readdatavalid;
  wire             system_0_burst_5_upstream_waitrequest;
  wire             system_0_burst_5_upstream_waitrequest_from_sa;
  wire             system_0_burst_5_upstream_write;
  wire    [ 15: 0] system_0_burst_5_upstream_writedata;
  wire    [ 10: 0] system_0_burst_6_downstream_address;
  wire    [ 10: 0] system_0_burst_6_downstream_address_to_slave;
  wire    [  3: 0] system_0_burst_6_downstream_arbitrationshare;
  wire             system_0_burst_6_downstream_burstcount;
  wire    [  3: 0] system_0_burst_6_downstream_byteenable;
  wire             system_0_burst_6_downstream_debugaccess;
  wire             system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port;
  wire             system_0_burst_6_downstream_latency_counter;
  wire    [ 10: 0] system_0_burst_6_downstream_nativeaddress;
  wire             system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port;
  wire             system_0_burst_6_downstream_read;
  wire             system_0_burst_6_downstream_read_data_valid_epcs_controller_epcs_control_port;
  wire    [ 31: 0] system_0_burst_6_downstream_readdata;
  wire             system_0_burst_6_downstream_readdatavalid;
  wire             system_0_burst_6_downstream_requests_epcs_controller_epcs_control_port;
  wire             system_0_burst_6_downstream_reset_n;
  wire             system_0_burst_6_downstream_waitrequest;
  wire             system_0_burst_6_downstream_write;
  wire    [ 31: 0] system_0_burst_6_downstream_writedata;
  wire    [ 10: 0] system_0_burst_6_upstream_address;
  wire    [ 12: 0] system_0_burst_6_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_6_upstream_byteenable;
  wire             system_0_burst_6_upstream_debugaccess;
  wire             system_0_burst_6_upstream_read;
  wire    [ 31: 0] system_0_burst_6_upstream_readdata;
  wire    [ 31: 0] system_0_burst_6_upstream_readdata_from_sa;
  wire             system_0_burst_6_upstream_readdatavalid;
  wire             system_0_burst_6_upstream_waitrequest;
  wire             system_0_burst_6_upstream_waitrequest_from_sa;
  wire             system_0_burst_6_upstream_write;
  wire    [ 31: 0] system_0_burst_6_upstream_writedata;
  wire    [ 10: 0] system_0_burst_7_downstream_address;
  wire    [ 10: 0] system_0_burst_7_downstream_address_to_slave;
  wire    [  3: 0] system_0_burst_7_downstream_arbitrationshare;
  wire             system_0_burst_7_downstream_burstcount;
  wire    [  3: 0] system_0_burst_7_downstream_byteenable;
  wire             system_0_burst_7_downstream_debugaccess;
  wire             system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port;
  wire             system_0_burst_7_downstream_latency_counter;
  wire    [ 10: 0] system_0_burst_7_downstream_nativeaddress;
  wire             system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port;
  wire             system_0_burst_7_downstream_read;
  wire             system_0_burst_7_downstream_read_data_valid_epcs_controller_epcs_control_port;
  wire    [ 31: 0] system_0_burst_7_downstream_readdata;
  wire             system_0_burst_7_downstream_readdatavalid;
  wire             system_0_burst_7_downstream_requests_epcs_controller_epcs_control_port;
  wire             system_0_burst_7_downstream_reset_n;
  wire             system_0_burst_7_downstream_waitrequest;
  wire             system_0_burst_7_downstream_write;
  wire    [ 31: 0] system_0_burst_7_downstream_writedata;
  wire    [ 10: 0] system_0_burst_7_upstream_address;
  wire    [  3: 0] system_0_burst_7_upstream_burstcount;
  wire    [ 12: 0] system_0_burst_7_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_7_upstream_byteenable;
  wire             system_0_burst_7_upstream_debugaccess;
  wire             system_0_burst_7_upstream_read;
  wire    [ 31: 0] system_0_burst_7_upstream_readdata;
  wire    [ 31: 0] system_0_burst_7_upstream_readdata_from_sa;
  wire             system_0_burst_7_upstream_readdatavalid;
  wire             system_0_burst_7_upstream_waitrequest;
  wire             system_0_burst_7_upstream_waitrequest_from_sa;
  wire             system_0_burst_7_upstream_write;
  wire    [ 31: 0] system_0_burst_7_upstream_writedata;
  wire    [  2: 0] system_0_burst_8_downstream_address;
  wire    [  2: 0] system_0_burst_8_downstream_address_to_slave;
  wire    [  3: 0] system_0_burst_8_downstream_arbitrationshare;
  wire             system_0_burst_8_downstream_burstcount;
  wire    [  3: 0] system_0_burst_8_downstream_byteenable;
  wire             system_0_burst_8_downstream_debugaccess;
  wire             system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave;
  wire             system_0_burst_8_downstream_latency_counter;
  wire    [  2: 0] system_0_burst_8_downstream_nativeaddress;
  wire             system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave;
  wire             system_0_burst_8_downstream_read;
  wire             system_0_burst_8_downstream_read_data_valid_jtag_uart_0_avalon_jtag_slave;
  wire    [ 31: 0] system_0_burst_8_downstream_readdata;
  wire             system_0_burst_8_downstream_readdatavalid;
  wire             system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave;
  wire             system_0_burst_8_downstream_reset_n;
  wire             system_0_burst_8_downstream_waitrequest;
  wire             system_0_burst_8_downstream_write;
  wire    [ 31: 0] system_0_burst_8_downstream_writedata;
  wire    [  2: 0] system_0_burst_8_upstream_address;
  wire    [  3: 0] system_0_burst_8_upstream_burstcount;
  wire    [  4: 0] system_0_burst_8_upstream_byteaddress;
  wire    [  3: 0] system_0_burst_8_upstream_byteenable;
  wire             system_0_burst_8_upstream_debugaccess;
  wire             system_0_burst_8_upstream_read;
  wire    [ 31: 0] system_0_burst_8_upstream_readdata;
  wire    [ 31: 0] system_0_burst_8_upstream_readdata_from_sa;
  wire             system_0_burst_8_upstream_readdatavalid;
  wire             system_0_burst_8_upstream_waitrequest;
  wire             system_0_burst_8_upstream_waitrequest_from_sa;
  wire             system_0_burst_8_upstream_write;
  wire    [ 31: 0] system_0_burst_8_upstream_writedata;
  wire    [  3: 0] system_0_burst_9_downstream_address;
  wire    [  3: 0] system_0_burst_9_downstream_address_to_slave;
  wire    [  4: 0] system_0_burst_9_downstream_arbitrationshare;
  wire             system_0_burst_9_downstream_burstcount;
  wire    [  1: 0] system_0_burst_9_downstream_byteenable;
  wire             system_0_burst_9_downstream_debugaccess;
  wire             system_0_burst_9_downstream_granted_uart_0_s1;
  wire             system_0_burst_9_downstream_latency_counter;
  wire    [  3: 0] system_0_burst_9_downstream_nativeaddress;
  wire             system_0_burst_9_downstream_qualified_request_uart_0_s1;
  wire             system_0_burst_9_downstream_read;
  wire             system_0_burst_9_downstream_read_data_valid_uart_0_s1;
  wire    [ 15: 0] system_0_burst_9_downstream_readdata;
  wire             system_0_burst_9_downstream_readdatavalid;
  wire             system_0_burst_9_downstream_requests_uart_0_s1;
  wire             system_0_burst_9_downstream_reset_n;
  wire             system_0_burst_9_downstream_waitrequest;
  wire             system_0_burst_9_downstream_write;
  wire    [ 15: 0] system_0_burst_9_downstream_writedata;
  wire    [  3: 0] system_0_burst_9_upstream_address;
  wire    [  3: 0] system_0_burst_9_upstream_burstcount;
  wire    [  4: 0] system_0_burst_9_upstream_byteaddress;
  wire    [  1: 0] system_0_burst_9_upstream_byteenable;
  wire             system_0_burst_9_upstream_debugaccess;
  wire             system_0_burst_9_upstream_read;
  wire    [ 15: 0] system_0_burst_9_upstream_readdata;
  wire    [ 15: 0] system_0_burst_9_upstream_readdata_from_sa;
  wire             system_0_burst_9_upstream_readdatavalid;
  wire             system_0_burst_9_upstream_waitrequest;
  wire             system_0_burst_9_upstream_waitrequest_from_sa;
  wire             system_0_burst_9_upstream_write;
  wire    [ 15: 0] system_0_burst_9_upstream_writedata;
  wire    [  3: 0] system_0_clock_0_in_address;
  wire    [  3: 0] system_0_clock_0_in_byteenable;
  wire             system_0_clock_0_in_endofpacket;
  wire             system_0_clock_0_in_endofpacket_from_sa;
  wire    [  1: 0] system_0_clock_0_in_nativeaddress;
  wire             system_0_clock_0_in_read;
  wire    [ 31: 0] system_0_clock_0_in_readdata;
  wire    [ 31: 0] system_0_clock_0_in_readdata_from_sa;
  wire             system_0_clock_0_in_reset_n;
  wire             system_0_clock_0_in_waitrequest;
  wire             system_0_clock_0_in_waitrequest_from_sa;
  wire             system_0_clock_0_in_write;
  wire    [ 31: 0] system_0_clock_0_in_writedata;
  wire    [  3: 0] system_0_clock_0_out_address;
  wire    [  3: 0] system_0_clock_0_out_address_to_slave;
  wire    [  3: 0] system_0_clock_0_out_byteenable;
  wire             system_0_clock_0_out_endofpacket;
  wire             system_0_clock_0_out_granted_altpll_0_pll_slave;
  wire    [  1: 0] system_0_clock_0_out_nativeaddress;
  wire             system_0_clock_0_out_qualified_request_altpll_0_pll_slave;
  wire             system_0_clock_0_out_read;
  wire             system_0_clock_0_out_read_data_valid_altpll_0_pll_slave;
  wire    [ 31: 0] system_0_clock_0_out_readdata;
  wire             system_0_clock_0_out_requests_altpll_0_pll_slave;
  wire             system_0_clock_0_out_reset_n;
  wire             system_0_clock_0_out_waitrequest;
  wire             system_0_clock_0_out_write;
  wire    [ 31: 0] system_0_clock_0_out_writedata;
  wire    [  2: 0] timer_0_s1_address;
  wire             timer_0_s1_chipselect;
  wire             timer_0_s1_irq;
  wire             timer_0_s1_irq_from_sa;
  wire    [ 15: 0] timer_0_s1_readdata;
  wire    [ 15: 0] timer_0_s1_readdata_from_sa;
  wire             timer_0_s1_reset_n;
  wire             timer_0_s1_write_n;
  wire    [ 15: 0] timer_0_s1_writedata;
  wire    [  2: 0] timer_1_s1_address;
  wire             timer_1_s1_chipselect;
  wire             timer_1_s1_irq;
  wire             timer_1_s1_irq_from_sa;
  wire    [ 15: 0] timer_1_s1_readdata;
  wire    [ 15: 0] timer_1_s1_readdata_from_sa;
  wire             timer_1_s1_reset_n;
  wire             timer_1_s1_write_n;
  wire    [ 15: 0] timer_1_s1_writedata;
  wire    [ 21: 0] tri_state_bridge_0_address;
  wire    [  7: 0] tri_state_bridge_0_data;
  wire             tri_state_bridge_0_readn;
  wire             txd_from_the_uart_0;
  wire    [  2: 0] uart_0_s1_address;
  wire             uart_0_s1_begintransfer;
  wire             uart_0_s1_chipselect;
  wire             uart_0_s1_dataavailable;
  wire             uart_0_s1_dataavailable_from_sa;
  wire             uart_0_s1_irq;
  wire             uart_0_s1_irq_from_sa;
  wire             uart_0_s1_read_n;
  wire    [ 15: 0] uart_0_s1_readdata;
  wire    [ 15: 0] uart_0_s1_readdata_from_sa;
  wire             uart_0_s1_readyfordata;
  wire             uart_0_s1_readyfordata_from_sa;
  wire             uart_0_s1_reset_n;
  wire             uart_0_s1_write_n;
  wire    [ 15: 0] uart_0_s1_writedata;
  wire             wb_err_o_from_the_i2c_master;
  wire             write_n_to_the_cfi_flash_0;
  wire    [ 11: 0] zs_addr_from_the_sdram_0;
  wire    [  1: 0] zs_ba_from_the_sdram_0;
  wire             zs_cas_n_from_the_sdram_0;
  wire             zs_cke_from_the_sdram_0;
  wire             zs_cs_n_from_the_sdram_0;
  wire    [ 15: 0] zs_dq_to_and_from_the_sdram_0;
  wire    [  1: 0] zs_dqm_from_the_sdram_0;
  wire             zs_ras_n_from_the_sdram_0;
  wire             zs_we_n_from_the_sdram_0;
  Accel_Control_avalon_slave_arbitrator the_Accel_Control_avalon_slave
    (
      .Accel_Control_avalon_slave_address                                        (Accel_Control_avalon_slave_address),
      .Accel_Control_avalon_slave_byteenable                                     (Accel_Control_avalon_slave_byteenable),
      .Accel_Control_avalon_slave_chipselect                                     (Accel_Control_avalon_slave_chipselect),
      .Accel_Control_avalon_slave_read                                           (Accel_Control_avalon_slave_read),
      .Accel_Control_avalon_slave_readdata                                       (Accel_Control_avalon_slave_readdata),
      .Accel_Control_avalon_slave_readdata_from_sa                               (Accel_Control_avalon_slave_readdata_from_sa),
      .Accel_Control_avalon_slave_reset_n                                        (Accel_Control_avalon_slave_reset_n),
      .Accel_Control_avalon_slave_write_n                                        (Accel_Control_avalon_slave_write_n),
      .Accel_Control_avalon_slave_writedata                                      (Accel_Control_avalon_slave_writedata),
      .clk                                                                       (altpll_0_c1_out),
      .d1_Accel_Control_avalon_slave_end_xfer                                    (d1_Accel_Control_avalon_slave_end_xfer),
      .reset_n                                                                   (altpll_0_c1_out_reset_n),
      .system_0_burst_32_downstream_address_to_slave                             (system_0_burst_32_downstream_address_to_slave),
      .system_0_burst_32_downstream_arbitrationshare                             (system_0_burst_32_downstream_arbitrationshare),
      .system_0_burst_32_downstream_burstcount                                   (system_0_burst_32_downstream_burstcount),
      .system_0_burst_32_downstream_byteenable                                   (system_0_burst_32_downstream_byteenable),
      .system_0_burst_32_downstream_granted_Accel_Control_avalon_slave           (system_0_burst_32_downstream_granted_Accel_Control_avalon_slave),
      .system_0_burst_32_downstream_latency_counter                              (system_0_burst_32_downstream_latency_counter),
      .system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave (system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave),
      .system_0_burst_32_downstream_read                                         (system_0_burst_32_downstream_read),
      .system_0_burst_32_downstream_read_data_valid_Accel_Control_avalon_slave   (system_0_burst_32_downstream_read_data_valid_Accel_Control_avalon_slave),
      .system_0_burst_32_downstream_requests_Accel_Control_avalon_slave          (system_0_burst_32_downstream_requests_Accel_Control_avalon_slave),
      .system_0_burst_32_downstream_write                                        (system_0_burst_32_downstream_write),
      .system_0_burst_32_downstream_writedata                                    (system_0_burst_32_downstream_writedata)
    );

  Accel_Control the_Accel_Control
    (
      .avalon_slave_address    (Accel_Control_avalon_slave_address),
      .avalon_slave_byteenable (Accel_Control_avalon_slave_byteenable),
      .avalon_slave_chipselect (Accel_Control_avalon_slave_chipselect),
      .avalon_slave_read       (Accel_Control_avalon_slave_read),
      .avalon_slave_readdata   (Accel_Control_avalon_slave_readdata),
      .avalon_slave_write_n    (Accel_Control_avalon_slave_write_n),
      .avalon_slave_writedata  (Accel_Control_avalon_slave_writedata),
      .clk                     (altpll_0_c1_out),
      .interrupt2              (interrupt2_to_the_Accel_Control),
      .reset_n                 (Accel_Control_avalon_slave_reset_n),
      .scl_i2c_to_accel        (scl_i2c_to_accel_from_the_Accel_Control),
      .scl_i2c_to_bus          (scl_i2c_to_bus_to_the_Accel_Control),
      .sda_i2c_to_accel        (sda_i2c_to_accel_to_and_from_the_Accel_Control),
      .sda_i2c_to_bus          (sda_i2c_to_bus_to_and_from_the_Accel_Control),
      .sda_padoen_o            (sda_padoen_o_to_the_Accel_Control)
    );

  Audio_0_avalon_slave_0_arbitrator the_Audio_0_avalon_slave_0
    (
      .Audio_0_avalon_slave_0_readdata                                       (Audio_0_avalon_slave_0_readdata),
      .Audio_0_avalon_slave_0_readdata_from_sa                               (Audio_0_avalon_slave_0_readdata_from_sa),
      .Audio_0_avalon_slave_0_reset_n                                        (Audio_0_avalon_slave_0_reset_n),
      .Audio_0_avalon_slave_0_write                                          (Audio_0_avalon_slave_0_write),
      .Audio_0_avalon_slave_0_writedata                                      (Audio_0_avalon_slave_0_writedata),
      .clk                                                                   (altpll_0_c1_out),
      .d1_Audio_0_avalon_slave_0_end_xfer                                    (d1_Audio_0_avalon_slave_0_end_xfer),
      .reset_n                                                               (altpll_0_c1_out_reset_n),
      .system_0_burst_16_downstream_address_to_slave                         (system_0_burst_16_downstream_address_to_slave),
      .system_0_burst_16_downstream_arbitrationshare                         (system_0_burst_16_downstream_arbitrationshare),
      .system_0_burst_16_downstream_burstcount                               (system_0_burst_16_downstream_burstcount),
      .system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0           (system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0),
      .system_0_burst_16_downstream_latency_counter                          (system_0_burst_16_downstream_latency_counter),
      .system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0 (system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0),
      .system_0_burst_16_downstream_read                                     (system_0_burst_16_downstream_read),
      .system_0_burst_16_downstream_read_data_valid_Audio_0_avalon_slave_0   (system_0_burst_16_downstream_read_data_valid_Audio_0_avalon_slave_0),
      .system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0          (system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0),
      .system_0_burst_16_downstream_write                                    (system_0_burst_16_downstream_write),
      .system_0_burst_16_downstream_writedata                                (system_0_burst_16_downstream_writedata)
    );

  Audio_0 the_Audio_0
    (
      .iCLK_18_4 (iCLK_18_4_to_the_Audio_0),
      .iDATA     (Audio_0_avalon_slave_0_writedata),
      .iRST_N    (Audio_0_avalon_slave_0_reset_n),
      .iWR       (Audio_0_avalon_slave_0_write),
      .iWR_CLK   (altpll_0_c1_out),
      .oAUD_BCK  (oAUD_BCK_from_the_Audio_0),
      .oAUD_DATA (oAUD_DATA_from_the_Audio_0),
      .oAUD_LRCK (oAUD_LRCK_from_the_Audio_0),
      .oAUD_XCK  (oAUD_XCK_from_the_Audio_0),
      .oDATA     (Audio_0_avalon_slave_0_readdata)
    );

  MS_s1_arbitrator the_MS_s1
    (
      .MS_s1_address                                        (MS_s1_address),
      .MS_s1_chipselect                                     (MS_s1_chipselect),
      .MS_s1_irq                                            (MS_s1_irq),
      .MS_s1_irq_from_sa                                    (MS_s1_irq_from_sa),
      .MS_s1_readdata                                       (MS_s1_readdata),
      .MS_s1_readdata_from_sa                               (MS_s1_readdata_from_sa),
      .MS_s1_reset_n                                        (MS_s1_reset_n),
      .MS_s1_write_n                                        (MS_s1_write_n),
      .MS_s1_writedata                                      (MS_s1_writedata),
      .clk                                                  (altpll_0_c1_out),
      .d1_MS_s1_end_xfer                                    (d1_MS_s1_end_xfer),
      .reset_n                                              (altpll_0_c1_out_reset_n),
      .system_0_burst_27_downstream_address_to_slave        (system_0_burst_27_downstream_address_to_slave),
      .system_0_burst_27_downstream_arbitrationshare        (system_0_burst_27_downstream_arbitrationshare),
      .system_0_burst_27_downstream_burstcount              (system_0_burst_27_downstream_burstcount),
      .system_0_burst_27_downstream_granted_MS_s1           (system_0_burst_27_downstream_granted_MS_s1),
      .system_0_burst_27_downstream_latency_counter         (system_0_burst_27_downstream_latency_counter),
      .system_0_burst_27_downstream_nativeaddress           (system_0_burst_27_downstream_nativeaddress),
      .system_0_burst_27_downstream_qualified_request_MS_s1 (system_0_burst_27_downstream_qualified_request_MS_s1),
      .system_0_burst_27_downstream_read                    (system_0_burst_27_downstream_read),
      .system_0_burst_27_downstream_read_data_valid_MS_s1   (system_0_burst_27_downstream_read_data_valid_MS_s1),
      .system_0_burst_27_downstream_requests_MS_s1          (system_0_burst_27_downstream_requests_MS_s1),
      .system_0_burst_27_downstream_write                   (system_0_burst_27_downstream_write),
      .system_0_burst_27_downstream_writedata               (system_0_burst_27_downstream_writedata)
    );

  MS the_MS
    (
      .address    (MS_s1_address),
      .chipselect (MS_s1_chipselect),
      .clk        (altpll_0_c1_out),
      .in_port    (in_port_to_the_MS),
      .irq        (MS_s1_irq),
      .readdata   (MS_s1_readdata),
      .reset_n    (MS_s1_reset_n),
      .write_n    (MS_s1_write_n),
      .writedata  (MS_s1_writedata)
    );

  Oct_DOWN_s1_arbitrator the_Oct_DOWN_s1
    (
      .Oct_DOWN_s1_address                                        (Oct_DOWN_s1_address),
      .Oct_DOWN_s1_chipselect                                     (Oct_DOWN_s1_chipselect),
      .Oct_DOWN_s1_irq                                            (Oct_DOWN_s1_irq),
      .Oct_DOWN_s1_irq_from_sa                                    (Oct_DOWN_s1_irq_from_sa),
      .Oct_DOWN_s1_readdata                                       (Oct_DOWN_s1_readdata),
      .Oct_DOWN_s1_readdata_from_sa                               (Oct_DOWN_s1_readdata_from_sa),
      .Oct_DOWN_s1_reset_n                                        (Oct_DOWN_s1_reset_n),
      .Oct_DOWN_s1_write_n                                        (Oct_DOWN_s1_write_n),
      .Oct_DOWN_s1_writedata                                      (Oct_DOWN_s1_writedata),
      .clk                                                        (altpll_0_c1_out),
      .d1_Oct_DOWN_s1_end_xfer                                    (d1_Oct_DOWN_s1_end_xfer),
      .reset_n                                                    (altpll_0_c1_out_reset_n),
      .system_0_burst_31_downstream_address_to_slave              (system_0_burst_31_downstream_address_to_slave),
      .system_0_burst_31_downstream_arbitrationshare              (system_0_burst_31_downstream_arbitrationshare),
      .system_0_burst_31_downstream_burstcount                    (system_0_burst_31_downstream_burstcount),
      .system_0_burst_31_downstream_granted_Oct_DOWN_s1           (system_0_burst_31_downstream_granted_Oct_DOWN_s1),
      .system_0_burst_31_downstream_latency_counter               (system_0_burst_31_downstream_latency_counter),
      .system_0_burst_31_downstream_nativeaddress                 (system_0_burst_31_downstream_nativeaddress),
      .system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1 (system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1),
      .system_0_burst_31_downstream_read                          (system_0_burst_31_downstream_read),
      .system_0_burst_31_downstream_read_data_valid_Oct_DOWN_s1   (system_0_burst_31_downstream_read_data_valid_Oct_DOWN_s1),
      .system_0_burst_31_downstream_requests_Oct_DOWN_s1          (system_0_burst_31_downstream_requests_Oct_DOWN_s1),
      .system_0_burst_31_downstream_write                         (system_0_burst_31_downstream_write),
      .system_0_burst_31_downstream_writedata                     (system_0_burst_31_downstream_writedata)
    );

  Oct_DOWN the_Oct_DOWN
    (
      .address    (Oct_DOWN_s1_address),
      .chipselect (Oct_DOWN_s1_chipselect),
      .clk        (altpll_0_c1_out),
      .in_port    (in_port_to_the_Oct_DOWN),
      .irq        (Oct_DOWN_s1_irq),
      .readdata   (Oct_DOWN_s1_readdata),
      .reset_n    (Oct_DOWN_s1_reset_n),
      .write_n    (Oct_DOWN_s1_write_n),
      .writedata  (Oct_DOWN_s1_writedata)
    );

  Oct_UP_s1_arbitrator the_Oct_UP_s1
    (
      .Oct_UP_s1_address                                        (Oct_UP_s1_address),
      .Oct_UP_s1_chipselect                                     (Oct_UP_s1_chipselect),
      .Oct_UP_s1_irq                                            (Oct_UP_s1_irq),
      .Oct_UP_s1_irq_from_sa                                    (Oct_UP_s1_irq_from_sa),
      .Oct_UP_s1_readdata                                       (Oct_UP_s1_readdata),
      .Oct_UP_s1_readdata_from_sa                               (Oct_UP_s1_readdata_from_sa),
      .Oct_UP_s1_reset_n                                        (Oct_UP_s1_reset_n),
      .Oct_UP_s1_write_n                                        (Oct_UP_s1_write_n),
      .Oct_UP_s1_writedata                                      (Oct_UP_s1_writedata),
      .clk                                                      (altpll_0_c1_out),
      .d1_Oct_UP_s1_end_xfer                                    (d1_Oct_UP_s1_end_xfer),
      .reset_n                                                  (altpll_0_c1_out_reset_n),
      .system_0_burst_30_downstream_address_to_slave            (system_0_burst_30_downstream_address_to_slave),
      .system_0_burst_30_downstream_arbitrationshare            (system_0_burst_30_downstream_arbitrationshare),
      .system_0_burst_30_downstream_burstcount                  (system_0_burst_30_downstream_burstcount),
      .system_0_burst_30_downstream_granted_Oct_UP_s1           (system_0_burst_30_downstream_granted_Oct_UP_s1),
      .system_0_burst_30_downstream_latency_counter             (system_0_burst_30_downstream_latency_counter),
      .system_0_burst_30_downstream_nativeaddress               (system_0_burst_30_downstream_nativeaddress),
      .system_0_burst_30_downstream_qualified_request_Oct_UP_s1 (system_0_burst_30_downstream_qualified_request_Oct_UP_s1),
      .system_0_burst_30_downstream_read                        (system_0_burst_30_downstream_read),
      .system_0_burst_30_downstream_read_data_valid_Oct_UP_s1   (system_0_burst_30_downstream_read_data_valid_Oct_UP_s1),
      .system_0_burst_30_downstream_requests_Oct_UP_s1          (system_0_burst_30_downstream_requests_Oct_UP_s1),
      .system_0_burst_30_downstream_write                       (system_0_burst_30_downstream_write),
      .system_0_burst_30_downstream_writedata                   (system_0_burst_30_downstream_writedata)
    );

  Oct_UP the_Oct_UP
    (
      .address    (Oct_UP_s1_address),
      .chipselect (Oct_UP_s1_chipselect),
      .clk        (altpll_0_c1_out),
      .in_port    (in_port_to_the_Oct_UP),
      .irq        (Oct_UP_s1_irq),
      .readdata   (Oct_UP_s1_readdata),
      .reset_n    (Oct_UP_s1_reset_n),
      .write_n    (Oct_UP_s1_write_n),
      .writedata  (Oct_UP_s1_writedata)
    );

  RST_s1_arbitrator the_RST_s1
    (
      .RST_s1_address                                        (RST_s1_address),
      .RST_s1_chipselect                                     (RST_s1_chipselect),
      .RST_s1_irq                                            (RST_s1_irq),
      .RST_s1_irq_from_sa                                    (RST_s1_irq_from_sa),
      .RST_s1_readdata                                       (RST_s1_readdata),
      .RST_s1_readdata_from_sa                               (RST_s1_readdata_from_sa),
      .RST_s1_reset_n                                        (RST_s1_reset_n),
      .RST_s1_write_n                                        (RST_s1_write_n),
      .RST_s1_writedata                                      (RST_s1_writedata),
      .clk                                                   (altpll_0_c1_out),
      .d1_RST_s1_end_xfer                                    (d1_RST_s1_end_xfer),
      .reset_n                                               (altpll_0_c1_out_reset_n),
      .system_0_burst_29_downstream_address_to_slave         (system_0_burst_29_downstream_address_to_slave),
      .system_0_burst_29_downstream_arbitrationshare         (system_0_burst_29_downstream_arbitrationshare),
      .system_0_burst_29_downstream_burstcount               (system_0_burst_29_downstream_burstcount),
      .system_0_burst_29_downstream_granted_RST_s1           (system_0_burst_29_downstream_granted_RST_s1),
      .system_0_burst_29_downstream_latency_counter          (system_0_burst_29_downstream_latency_counter),
      .system_0_burst_29_downstream_nativeaddress            (system_0_burst_29_downstream_nativeaddress),
      .system_0_burst_29_downstream_qualified_request_RST_s1 (system_0_burst_29_downstream_qualified_request_RST_s1),
      .system_0_burst_29_downstream_read                     (system_0_burst_29_downstream_read),
      .system_0_burst_29_downstream_read_data_valid_RST_s1   (system_0_burst_29_downstream_read_data_valid_RST_s1),
      .system_0_burst_29_downstream_requests_RST_s1          (system_0_burst_29_downstream_requests_RST_s1),
      .system_0_burst_29_downstream_write                    (system_0_burst_29_downstream_write),
      .system_0_burst_29_downstream_writedata                (system_0_burst_29_downstream_writedata)
    );

  RST the_RST
    (
      .address    (RST_s1_address),
      .chipselect (RST_s1_chipselect),
      .clk        (altpll_0_c1_out),
      .in_port    (in_port_to_the_RST),
      .irq        (RST_s1_irq),
      .readdata   (RST_s1_readdata),
      .reset_n    (RST_s1_reset_n),
      .write_n    (RST_s1_write_n),
      .writedata  (RST_s1_writedata)
    );

  SD_CLK_s1_arbitrator the_SD_CLK_s1
    (
      .SD_CLK_s1_address                                        (SD_CLK_s1_address),
      .SD_CLK_s1_chipselect                                     (SD_CLK_s1_chipselect),
      .SD_CLK_s1_readdata                                       (SD_CLK_s1_readdata),
      .SD_CLK_s1_readdata_from_sa                               (SD_CLK_s1_readdata_from_sa),
      .SD_CLK_s1_reset_n                                        (SD_CLK_s1_reset_n),
      .SD_CLK_s1_write_n                                        (SD_CLK_s1_write_n),
      .SD_CLK_s1_writedata                                      (SD_CLK_s1_writedata),
      .clk                                                      (altpll_0_c1_out),
      .d1_SD_CLK_s1_end_xfer                                    (d1_SD_CLK_s1_end_xfer),
      .reset_n                                                  (altpll_0_c1_out_reset_n),
      .system_0_burst_19_downstream_address_to_slave            (system_0_burst_19_downstream_address_to_slave),
      .system_0_burst_19_downstream_arbitrationshare            (system_0_burst_19_downstream_arbitrationshare),
      .system_0_burst_19_downstream_burstcount                  (system_0_burst_19_downstream_burstcount),
      .system_0_burst_19_downstream_granted_SD_CLK_s1           (system_0_burst_19_downstream_granted_SD_CLK_s1),
      .system_0_burst_19_downstream_latency_counter             (system_0_burst_19_downstream_latency_counter),
      .system_0_burst_19_downstream_nativeaddress               (system_0_burst_19_downstream_nativeaddress),
      .system_0_burst_19_downstream_qualified_request_SD_CLK_s1 (system_0_burst_19_downstream_qualified_request_SD_CLK_s1),
      .system_0_burst_19_downstream_read                        (system_0_burst_19_downstream_read),
      .system_0_burst_19_downstream_read_data_valid_SD_CLK_s1   (system_0_burst_19_downstream_read_data_valid_SD_CLK_s1),
      .system_0_burst_19_downstream_requests_SD_CLK_s1          (system_0_burst_19_downstream_requests_SD_CLK_s1),
      .system_0_burst_19_downstream_write                       (system_0_burst_19_downstream_write),
      .system_0_burst_19_downstream_writedata                   (system_0_burst_19_downstream_writedata)
    );

  SD_CLK the_SD_CLK
    (
      .address    (SD_CLK_s1_address),
      .chipselect (SD_CLK_s1_chipselect),
      .clk        (altpll_0_c1_out),
      .out_port   (out_port_from_the_SD_CLK),
      .readdata   (SD_CLK_s1_readdata),
      .reset_n    (SD_CLK_s1_reset_n),
      .write_n    (SD_CLK_s1_write_n),
      .writedata  (SD_CLK_s1_writedata)
    );

  SD_CMD_s1_arbitrator the_SD_CMD_s1
    (
      .SD_CMD_s1_address                                        (SD_CMD_s1_address),
      .SD_CMD_s1_chipselect                                     (SD_CMD_s1_chipselect),
      .SD_CMD_s1_readdata                                       (SD_CMD_s1_readdata),
      .SD_CMD_s1_readdata_from_sa                               (SD_CMD_s1_readdata_from_sa),
      .SD_CMD_s1_reset_n                                        (SD_CMD_s1_reset_n),
      .SD_CMD_s1_write_n                                        (SD_CMD_s1_write_n),
      .SD_CMD_s1_writedata                                      (SD_CMD_s1_writedata),
      .clk                                                      (altpll_0_c1_out),
      .d1_SD_CMD_s1_end_xfer                                    (d1_SD_CMD_s1_end_xfer),
      .reset_n                                                  (altpll_0_c1_out_reset_n),
      .system_0_burst_18_downstream_address_to_slave            (system_0_burst_18_downstream_address_to_slave),
      .system_0_burst_18_downstream_arbitrationshare            (system_0_burst_18_downstream_arbitrationshare),
      .system_0_burst_18_downstream_burstcount                  (system_0_burst_18_downstream_burstcount),
      .system_0_burst_18_downstream_granted_SD_CMD_s1           (system_0_burst_18_downstream_granted_SD_CMD_s1),
      .system_0_burst_18_downstream_latency_counter             (system_0_burst_18_downstream_latency_counter),
      .system_0_burst_18_downstream_nativeaddress               (system_0_burst_18_downstream_nativeaddress),
      .system_0_burst_18_downstream_qualified_request_SD_CMD_s1 (system_0_burst_18_downstream_qualified_request_SD_CMD_s1),
      .system_0_burst_18_downstream_read                        (system_0_burst_18_downstream_read),
      .system_0_burst_18_downstream_read_data_valid_SD_CMD_s1   (system_0_burst_18_downstream_read_data_valid_SD_CMD_s1),
      .system_0_burst_18_downstream_requests_SD_CMD_s1          (system_0_burst_18_downstream_requests_SD_CMD_s1),
      .system_0_burst_18_downstream_write                       (system_0_burst_18_downstream_write),
      .system_0_burst_18_downstream_writedata                   (system_0_burst_18_downstream_writedata)
    );

  SD_CMD the_SD_CMD
    (
      .address    (SD_CMD_s1_address),
      .bidir_port (bidir_port_to_and_from_the_SD_CMD),
      .chipselect (SD_CMD_s1_chipselect),
      .clk        (altpll_0_c1_out),
      .readdata   (SD_CMD_s1_readdata),
      .reset_n    (SD_CMD_s1_reset_n),
      .write_n    (SD_CMD_s1_write_n),
      .writedata  (SD_CMD_s1_writedata)
    );

  SD_DAT_s1_arbitrator the_SD_DAT_s1
    (
      .SD_DAT_s1_address                                        (SD_DAT_s1_address),
      .SD_DAT_s1_chipselect                                     (SD_DAT_s1_chipselect),
      .SD_DAT_s1_readdata                                       (SD_DAT_s1_readdata),
      .SD_DAT_s1_readdata_from_sa                               (SD_DAT_s1_readdata_from_sa),
      .SD_DAT_s1_reset_n                                        (SD_DAT_s1_reset_n),
      .SD_DAT_s1_write_n                                        (SD_DAT_s1_write_n),
      .SD_DAT_s1_writedata                                      (SD_DAT_s1_writedata),
      .clk                                                      (altpll_0_c1_out),
      .d1_SD_DAT_s1_end_xfer                                    (d1_SD_DAT_s1_end_xfer),
      .reset_n                                                  (altpll_0_c1_out_reset_n),
      .system_0_burst_17_downstream_address_to_slave            (system_0_burst_17_downstream_address_to_slave),
      .system_0_burst_17_downstream_arbitrationshare            (system_0_burst_17_downstream_arbitrationshare),
      .system_0_burst_17_downstream_burstcount                  (system_0_burst_17_downstream_burstcount),
      .system_0_burst_17_downstream_granted_SD_DAT_s1           (system_0_burst_17_downstream_granted_SD_DAT_s1),
      .system_0_burst_17_downstream_latency_counter             (system_0_burst_17_downstream_latency_counter),
      .system_0_burst_17_downstream_nativeaddress               (system_0_burst_17_downstream_nativeaddress),
      .system_0_burst_17_downstream_qualified_request_SD_DAT_s1 (system_0_burst_17_downstream_qualified_request_SD_DAT_s1),
      .system_0_burst_17_downstream_read                        (system_0_burst_17_downstream_read),
      .system_0_burst_17_downstream_read_data_valid_SD_DAT_s1   (system_0_burst_17_downstream_read_data_valid_SD_DAT_s1),
      .system_0_burst_17_downstream_requests_SD_DAT_s1          (system_0_burst_17_downstream_requests_SD_DAT_s1),
      .system_0_burst_17_downstream_write                       (system_0_burst_17_downstream_write),
      .system_0_burst_17_downstream_writedata                   (system_0_burst_17_downstream_writedata)
    );

  SD_DAT the_SD_DAT
    (
      .address    (SD_DAT_s1_address),
      .bidir_port (bidir_port_to_and_from_the_SD_DAT),
      .chipselect (SD_DAT_s1_chipselect),
      .clk        (altpll_0_c1_out),
      .readdata   (SD_DAT_s1_readdata),
      .reset_n    (SD_DAT_s1_reset_n),
      .write_n    (SD_DAT_s1_write_n),
      .writedata  (SD_DAT_s1_writedata)
    );

  SEG7_Display_avalon_slave_0_arbitrator the_SEG7_Display_avalon_slave_0
    (
      .SEG7_Display_avalon_slave_0_reset_n                                        (SEG7_Display_avalon_slave_0_reset_n),
      .SEG7_Display_avalon_slave_0_write                                          (SEG7_Display_avalon_slave_0_write),
      .SEG7_Display_avalon_slave_0_writedata                                      (SEG7_Display_avalon_slave_0_writedata),
      .clk                                                                        (altpll_0_c1_out),
      .d1_SEG7_Display_avalon_slave_0_end_xfer                                    (d1_SEG7_Display_avalon_slave_0_end_xfer),
      .reset_n                                                                    (altpll_0_c1_out_reset_n),
      .system_0_burst_13_downstream_address_to_slave                              (system_0_burst_13_downstream_address_to_slave),
      .system_0_burst_13_downstream_arbitrationshare                              (system_0_burst_13_downstream_arbitrationshare),
      .system_0_burst_13_downstream_burstcount                                    (system_0_burst_13_downstream_burstcount),
      .system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0           (system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0),
      .system_0_burst_13_downstream_latency_counter                               (system_0_burst_13_downstream_latency_counter),
      .system_0_burst_13_downstream_qualified_request_SEG7_Display_avalon_slave_0 (system_0_burst_13_downstream_qualified_request_SEG7_Display_avalon_slave_0),
      .system_0_burst_13_downstream_read                                          (system_0_burst_13_downstream_read),
      .system_0_burst_13_downstream_read_data_valid_SEG7_Display_avalon_slave_0   (system_0_burst_13_downstream_read_data_valid_SEG7_Display_avalon_slave_0),
      .system_0_burst_13_downstream_requests_SEG7_Display_avalon_slave_0          (system_0_burst_13_downstream_requests_SEG7_Display_avalon_slave_0),
      .system_0_burst_13_downstream_write                                         (system_0_burst_13_downstream_write),
      .system_0_burst_13_downstream_writedata                                     (system_0_burst_13_downstream_writedata)
    );

  SEG7_Display the_SEG7_Display
    (
      .iCLK   (altpll_0_c1_out),
      .iDIG   (SEG7_Display_avalon_slave_0_writedata),
      .iRST_N (SEG7_Display_avalon_slave_0_reset_n),
      .iWR    (SEG7_Display_avalon_slave_0_write),
      .oSEG0  (oSEG0_from_the_SEG7_Display),
      .oSEG1  (oSEG1_from_the_SEG7_Display),
      .oSEG2  (oSEG2_from_the_SEG7_Display),
      .oSEG3  (oSEG3_from_the_SEG7_Display),
      .oSEG4  (oSEG4_from_the_SEG7_Display),
      .oSEG5  (oSEG5_from_the_SEG7_Display),
      .oSEG6  (oSEG6_from_the_SEG7_Display),
      .oSEG7  (oSEG7_from_the_SEG7_Display)
    );

  altpll_0_pll_slave_arbitrator the_altpll_0_pll_slave
    (
      .altpll_0_pll_slave_address                                (altpll_0_pll_slave_address),
      .altpll_0_pll_slave_read                                   (altpll_0_pll_slave_read),
      .altpll_0_pll_slave_readdata                               (altpll_0_pll_slave_readdata),
      .altpll_0_pll_slave_readdata_from_sa                       (altpll_0_pll_slave_readdata_from_sa),
      .altpll_0_pll_slave_reset                                  (altpll_0_pll_slave_reset),
      .altpll_0_pll_slave_write                                  (altpll_0_pll_slave_write),
      .altpll_0_pll_slave_writedata                              (altpll_0_pll_slave_writedata),
      .clk                                                       (clk),
      .d1_altpll_0_pll_slave_end_xfer                            (d1_altpll_0_pll_slave_end_xfer),
      .reset_n                                                   (clk_reset_n),
      .system_0_clock_0_out_address_to_slave                     (system_0_clock_0_out_address_to_slave),
      .system_0_clock_0_out_granted_altpll_0_pll_slave           (system_0_clock_0_out_granted_altpll_0_pll_slave),
      .system_0_clock_0_out_qualified_request_altpll_0_pll_slave (system_0_clock_0_out_qualified_request_altpll_0_pll_slave),
      .system_0_clock_0_out_read                                 (system_0_clock_0_out_read),
      .system_0_clock_0_out_read_data_valid_altpll_0_pll_slave   (system_0_clock_0_out_read_data_valid_altpll_0_pll_slave),
      .system_0_clock_0_out_requests_altpll_0_pll_slave          (system_0_clock_0_out_requests_altpll_0_pll_slave),
      .system_0_clock_0_out_write                                (system_0_clock_0_out_write),
      .system_0_clock_0_out_writedata                            (system_0_clock_0_out_writedata)
    );

  //altpll_0_c0_out out_clk assignment, which is an e_assign
  assign altpll_0_c0_out = out_clk_altpll_0_c0;

  //altpll_0_c1_out out_clk assignment, which is an e_assign
  assign altpll_0_c1_out = out_clk_altpll_0_c1;

  altpll_0 the_altpll_0
    (
      .address   (altpll_0_pll_slave_address),
      .c0        (out_clk_altpll_0_c0),
      .c1        (out_clk_altpll_0_c1),
      .clk       (clk),
      .locked    (locked_from_the_altpll_0),
      .phasedone (phasedone_from_the_altpll_0),
      .read      (altpll_0_pll_slave_read),
      .readdata  (altpll_0_pll_slave_readdata),
      .reset     (altpll_0_pll_slave_reset),
      .write     (altpll_0_pll_slave_write),
      .writedata (altpll_0_pll_slave_writedata)
    );

  cpu_0_jtag_debug_module_arbitrator the_cpu_0_jtag_debug_module
    (
      .clk                                                                   (altpll_0_c1_out),
      .cpu_0_jtag_debug_module_address                                       (cpu_0_jtag_debug_module_address),
      .cpu_0_jtag_debug_module_begintransfer                                 (cpu_0_jtag_debug_module_begintransfer),
      .cpu_0_jtag_debug_module_byteenable                                    (cpu_0_jtag_debug_module_byteenable),
      .cpu_0_jtag_debug_module_chipselect                                    (cpu_0_jtag_debug_module_chipselect),
      .cpu_0_jtag_debug_module_debugaccess                                   (cpu_0_jtag_debug_module_debugaccess),
      .cpu_0_jtag_debug_module_readdata                                      (cpu_0_jtag_debug_module_readdata),
      .cpu_0_jtag_debug_module_readdata_from_sa                              (cpu_0_jtag_debug_module_readdata_from_sa),
      .cpu_0_jtag_debug_module_reset_n                                       (cpu_0_jtag_debug_module_reset_n),
      .cpu_0_jtag_debug_module_resetrequest                                  (cpu_0_jtag_debug_module_resetrequest),
      .cpu_0_jtag_debug_module_resetrequest_from_sa                          (cpu_0_jtag_debug_module_resetrequest_from_sa),
      .cpu_0_jtag_debug_module_write                                         (cpu_0_jtag_debug_module_write),
      .cpu_0_jtag_debug_module_writedata                                     (cpu_0_jtag_debug_module_writedata),
      .d1_cpu_0_jtag_debug_module_end_xfer                                   (d1_cpu_0_jtag_debug_module_end_xfer),
      .reset_n                                                               (altpll_0_c1_out_reset_n),
      .system_0_burst_0_downstream_address_to_slave                          (system_0_burst_0_downstream_address_to_slave),
      .system_0_burst_0_downstream_arbitrationshare                          (system_0_burst_0_downstream_arbitrationshare),
      .system_0_burst_0_downstream_burstcount                                (system_0_burst_0_downstream_burstcount),
      .system_0_burst_0_downstream_byteenable                                (system_0_burst_0_downstream_byteenable),
      .system_0_burst_0_downstream_debugaccess                               (system_0_burst_0_downstream_debugaccess),
      .system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module           (system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module),
      .system_0_burst_0_downstream_latency_counter                           (system_0_burst_0_downstream_latency_counter),
      .system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module (system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module),
      .system_0_burst_0_downstream_read                                      (system_0_burst_0_downstream_read),
      .system_0_burst_0_downstream_read_data_valid_cpu_0_jtag_debug_module   (system_0_burst_0_downstream_read_data_valid_cpu_0_jtag_debug_module),
      .system_0_burst_0_downstream_requests_cpu_0_jtag_debug_module          (system_0_burst_0_downstream_requests_cpu_0_jtag_debug_module),
      .system_0_burst_0_downstream_write                                     (system_0_burst_0_downstream_write),
      .system_0_burst_0_downstream_writedata                                 (system_0_burst_0_downstream_writedata),
      .system_0_burst_1_downstream_address_to_slave                          (system_0_burst_1_downstream_address_to_slave),
      .system_0_burst_1_downstream_arbitrationshare                          (system_0_burst_1_downstream_arbitrationshare),
      .system_0_burst_1_downstream_burstcount                                (system_0_burst_1_downstream_burstcount),
      .system_0_burst_1_downstream_byteenable                                (system_0_burst_1_downstream_byteenable),
      .system_0_burst_1_downstream_debugaccess                               (system_0_burst_1_downstream_debugaccess),
      .system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module           (system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module),
      .system_0_burst_1_downstream_latency_counter                           (system_0_burst_1_downstream_latency_counter),
      .system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module (system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module),
      .system_0_burst_1_downstream_read                                      (system_0_burst_1_downstream_read),
      .system_0_burst_1_downstream_read_data_valid_cpu_0_jtag_debug_module   (system_0_burst_1_downstream_read_data_valid_cpu_0_jtag_debug_module),
      .system_0_burst_1_downstream_requests_cpu_0_jtag_debug_module          (system_0_burst_1_downstream_requests_cpu_0_jtag_debug_module),
      .system_0_burst_1_downstream_write                                     (system_0_burst_1_downstream_write),
      .system_0_burst_1_downstream_writedata                                 (system_0_burst_1_downstream_writedata)
    );

  cpu_0_data_master_arbitrator the_cpu_0_data_master
    (
      .MS_s1_irq_from_sa                                                           (MS_s1_irq_from_sa),
      .Oct_DOWN_s1_irq_from_sa                                                     (Oct_DOWN_s1_irq_from_sa),
      .Oct_UP_s1_irq_from_sa                                                       (Oct_UP_s1_irq_from_sa),
      .RST_s1_irq_from_sa                                                          (RST_s1_irq_from_sa),
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address                                                   (cpu_0_data_master_address),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_byteenable_system_0_burst_15_upstream                     (cpu_0_data_master_byteenable_system_0_burst_15_upstream),
      .cpu_0_data_master_byteenable_system_0_burst_3_upstream                      (cpu_0_data_master_byteenable_system_0_burst_3_upstream),
      .cpu_0_data_master_byteenable_system_0_burst_5_upstream                      (cpu_0_data_master_byteenable_system_0_burst_5_upstream),
      .cpu_0_data_master_dbs_address                                               (cpu_0_data_master_dbs_address),
      .cpu_0_data_master_dbs_write_16                                              (cpu_0_data_master_dbs_write_16),
      .cpu_0_data_master_dbs_write_8                                               (cpu_0_data_master_dbs_write_8),
      .cpu_0_data_master_granted_system_0_burst_10_upstream                        (cpu_0_data_master_granted_system_0_burst_10_upstream),
      .cpu_0_data_master_granted_system_0_burst_11_upstream                        (cpu_0_data_master_granted_system_0_burst_11_upstream),
      .cpu_0_data_master_granted_system_0_burst_12_upstream                        (cpu_0_data_master_granted_system_0_burst_12_upstream),
      .cpu_0_data_master_granted_system_0_burst_13_upstream                        (cpu_0_data_master_granted_system_0_burst_13_upstream),
      .cpu_0_data_master_granted_system_0_burst_15_upstream                        (cpu_0_data_master_granted_system_0_burst_15_upstream),
      .cpu_0_data_master_granted_system_0_burst_16_upstream                        (cpu_0_data_master_granted_system_0_burst_16_upstream),
      .cpu_0_data_master_granted_system_0_burst_17_upstream                        (cpu_0_data_master_granted_system_0_burst_17_upstream),
      .cpu_0_data_master_granted_system_0_burst_18_upstream                        (cpu_0_data_master_granted_system_0_burst_18_upstream),
      .cpu_0_data_master_granted_system_0_burst_19_upstream                        (cpu_0_data_master_granted_system_0_burst_19_upstream),
      .cpu_0_data_master_granted_system_0_burst_1_upstream                         (cpu_0_data_master_granted_system_0_burst_1_upstream),
      .cpu_0_data_master_granted_system_0_burst_20_upstream                        (cpu_0_data_master_granted_system_0_burst_20_upstream),
      .cpu_0_data_master_granted_system_0_burst_21_upstream                        (cpu_0_data_master_granted_system_0_burst_21_upstream),
      .cpu_0_data_master_granted_system_0_burst_22_upstream                        (cpu_0_data_master_granted_system_0_burst_22_upstream),
      .cpu_0_data_master_granted_system_0_burst_23_upstream                        (cpu_0_data_master_granted_system_0_burst_23_upstream),
      .cpu_0_data_master_granted_system_0_burst_24_upstream                        (cpu_0_data_master_granted_system_0_burst_24_upstream),
      .cpu_0_data_master_granted_system_0_burst_25_upstream                        (cpu_0_data_master_granted_system_0_burst_25_upstream),
      .cpu_0_data_master_granted_system_0_burst_26_upstream                        (cpu_0_data_master_granted_system_0_burst_26_upstream),
      .cpu_0_data_master_granted_system_0_burst_27_upstream                        (cpu_0_data_master_granted_system_0_burst_27_upstream),
      .cpu_0_data_master_granted_system_0_burst_28_upstream                        (cpu_0_data_master_granted_system_0_burst_28_upstream),
      .cpu_0_data_master_granted_system_0_burst_29_upstream                        (cpu_0_data_master_granted_system_0_burst_29_upstream),
      .cpu_0_data_master_granted_system_0_burst_30_upstream                        (cpu_0_data_master_granted_system_0_burst_30_upstream),
      .cpu_0_data_master_granted_system_0_burst_31_upstream                        (cpu_0_data_master_granted_system_0_burst_31_upstream),
      .cpu_0_data_master_granted_system_0_burst_32_upstream                        (cpu_0_data_master_granted_system_0_burst_32_upstream),
      .cpu_0_data_master_granted_system_0_burst_34_upstream                        (cpu_0_data_master_granted_system_0_burst_34_upstream),
      .cpu_0_data_master_granted_system_0_burst_35_upstream                        (cpu_0_data_master_granted_system_0_burst_35_upstream),
      .cpu_0_data_master_granted_system_0_burst_3_upstream                         (cpu_0_data_master_granted_system_0_burst_3_upstream),
      .cpu_0_data_master_granted_system_0_burst_5_upstream                         (cpu_0_data_master_granted_system_0_burst_5_upstream),
      .cpu_0_data_master_granted_system_0_burst_7_upstream                         (cpu_0_data_master_granted_system_0_burst_7_upstream),
      .cpu_0_data_master_granted_system_0_burst_8_upstream                         (cpu_0_data_master_granted_system_0_burst_8_upstream),
      .cpu_0_data_master_granted_system_0_burst_9_upstream                         (cpu_0_data_master_granted_system_0_burst_9_upstream),
      .cpu_0_data_master_irq                                                       (cpu_0_data_master_irq),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_10_upstream              (cpu_0_data_master_qualified_request_system_0_burst_10_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_11_upstream              (cpu_0_data_master_qualified_request_system_0_burst_11_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_12_upstream              (cpu_0_data_master_qualified_request_system_0_burst_12_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_13_upstream              (cpu_0_data_master_qualified_request_system_0_burst_13_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_15_upstream              (cpu_0_data_master_qualified_request_system_0_burst_15_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_16_upstream              (cpu_0_data_master_qualified_request_system_0_burst_16_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_17_upstream              (cpu_0_data_master_qualified_request_system_0_burst_17_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_18_upstream              (cpu_0_data_master_qualified_request_system_0_burst_18_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_19_upstream              (cpu_0_data_master_qualified_request_system_0_burst_19_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_1_upstream               (cpu_0_data_master_qualified_request_system_0_burst_1_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_20_upstream              (cpu_0_data_master_qualified_request_system_0_burst_20_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_21_upstream              (cpu_0_data_master_qualified_request_system_0_burst_21_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_22_upstream              (cpu_0_data_master_qualified_request_system_0_burst_22_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_23_upstream              (cpu_0_data_master_qualified_request_system_0_burst_23_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_24_upstream              (cpu_0_data_master_qualified_request_system_0_burst_24_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_25_upstream              (cpu_0_data_master_qualified_request_system_0_burst_25_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_26_upstream              (cpu_0_data_master_qualified_request_system_0_burst_26_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_27_upstream              (cpu_0_data_master_qualified_request_system_0_burst_27_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_28_upstream              (cpu_0_data_master_qualified_request_system_0_burst_28_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_29_upstream              (cpu_0_data_master_qualified_request_system_0_burst_29_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_30_upstream              (cpu_0_data_master_qualified_request_system_0_burst_30_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_31_upstream              (cpu_0_data_master_qualified_request_system_0_burst_31_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_32_upstream              (cpu_0_data_master_qualified_request_system_0_burst_32_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_34_upstream              (cpu_0_data_master_qualified_request_system_0_burst_34_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_35_upstream              (cpu_0_data_master_qualified_request_system_0_burst_35_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_3_upstream               (cpu_0_data_master_qualified_request_system_0_burst_3_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_5_upstream               (cpu_0_data_master_qualified_request_system_0_burst_5_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_7_upstream               (cpu_0_data_master_qualified_request_system_0_burst_7_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_8_upstream               (cpu_0_data_master_qualified_request_system_0_burst_8_upstream),
      .cpu_0_data_master_qualified_request_system_0_burst_9_upstream               (cpu_0_data_master_qualified_request_system_0_burst_9_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream                 (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream                 (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream                 (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream                 (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream                 (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream                 (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_readdata                                                  (cpu_0_data_master_readdata),
      .cpu_0_data_master_readdatavalid                                             (cpu_0_data_master_readdatavalid),
      .cpu_0_data_master_requests_system_0_burst_10_upstream                       (cpu_0_data_master_requests_system_0_burst_10_upstream),
      .cpu_0_data_master_requests_system_0_burst_11_upstream                       (cpu_0_data_master_requests_system_0_burst_11_upstream),
      .cpu_0_data_master_requests_system_0_burst_12_upstream                       (cpu_0_data_master_requests_system_0_burst_12_upstream),
      .cpu_0_data_master_requests_system_0_burst_13_upstream                       (cpu_0_data_master_requests_system_0_burst_13_upstream),
      .cpu_0_data_master_requests_system_0_burst_15_upstream                       (cpu_0_data_master_requests_system_0_burst_15_upstream),
      .cpu_0_data_master_requests_system_0_burst_16_upstream                       (cpu_0_data_master_requests_system_0_burst_16_upstream),
      .cpu_0_data_master_requests_system_0_burst_17_upstream                       (cpu_0_data_master_requests_system_0_burst_17_upstream),
      .cpu_0_data_master_requests_system_0_burst_18_upstream                       (cpu_0_data_master_requests_system_0_burst_18_upstream),
      .cpu_0_data_master_requests_system_0_burst_19_upstream                       (cpu_0_data_master_requests_system_0_burst_19_upstream),
      .cpu_0_data_master_requests_system_0_burst_1_upstream                        (cpu_0_data_master_requests_system_0_burst_1_upstream),
      .cpu_0_data_master_requests_system_0_burst_20_upstream                       (cpu_0_data_master_requests_system_0_burst_20_upstream),
      .cpu_0_data_master_requests_system_0_burst_21_upstream                       (cpu_0_data_master_requests_system_0_burst_21_upstream),
      .cpu_0_data_master_requests_system_0_burst_22_upstream                       (cpu_0_data_master_requests_system_0_burst_22_upstream),
      .cpu_0_data_master_requests_system_0_burst_23_upstream                       (cpu_0_data_master_requests_system_0_burst_23_upstream),
      .cpu_0_data_master_requests_system_0_burst_24_upstream                       (cpu_0_data_master_requests_system_0_burst_24_upstream),
      .cpu_0_data_master_requests_system_0_burst_25_upstream                       (cpu_0_data_master_requests_system_0_burst_25_upstream),
      .cpu_0_data_master_requests_system_0_burst_26_upstream                       (cpu_0_data_master_requests_system_0_burst_26_upstream),
      .cpu_0_data_master_requests_system_0_burst_27_upstream                       (cpu_0_data_master_requests_system_0_burst_27_upstream),
      .cpu_0_data_master_requests_system_0_burst_28_upstream                       (cpu_0_data_master_requests_system_0_burst_28_upstream),
      .cpu_0_data_master_requests_system_0_burst_29_upstream                       (cpu_0_data_master_requests_system_0_burst_29_upstream),
      .cpu_0_data_master_requests_system_0_burst_30_upstream                       (cpu_0_data_master_requests_system_0_burst_30_upstream),
      .cpu_0_data_master_requests_system_0_burst_31_upstream                       (cpu_0_data_master_requests_system_0_burst_31_upstream),
      .cpu_0_data_master_requests_system_0_burst_32_upstream                       (cpu_0_data_master_requests_system_0_burst_32_upstream),
      .cpu_0_data_master_requests_system_0_burst_34_upstream                       (cpu_0_data_master_requests_system_0_burst_34_upstream),
      .cpu_0_data_master_requests_system_0_burst_35_upstream                       (cpu_0_data_master_requests_system_0_burst_35_upstream),
      .cpu_0_data_master_requests_system_0_burst_3_upstream                        (cpu_0_data_master_requests_system_0_burst_3_upstream),
      .cpu_0_data_master_requests_system_0_burst_5_upstream                        (cpu_0_data_master_requests_system_0_burst_5_upstream),
      .cpu_0_data_master_requests_system_0_burst_7_upstream                        (cpu_0_data_master_requests_system_0_burst_7_upstream),
      .cpu_0_data_master_requests_system_0_burst_8_upstream                        (cpu_0_data_master_requests_system_0_burst_8_upstream),
      .cpu_0_data_master_requests_system_0_burst_9_upstream                        (cpu_0_data_master_requests_system_0_burst_9_upstream),
      .cpu_0_data_master_waitrequest                                               (cpu_0_data_master_waitrequest),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_10_upstream_end_xfer                                      (d1_system_0_burst_10_upstream_end_xfer),
      .d1_system_0_burst_11_upstream_end_xfer                                      (d1_system_0_burst_11_upstream_end_xfer),
      .d1_system_0_burst_12_upstream_end_xfer                                      (d1_system_0_burst_12_upstream_end_xfer),
      .d1_system_0_burst_13_upstream_end_xfer                                      (d1_system_0_burst_13_upstream_end_xfer),
      .d1_system_0_burst_15_upstream_end_xfer                                      (d1_system_0_burst_15_upstream_end_xfer),
      .d1_system_0_burst_16_upstream_end_xfer                                      (d1_system_0_burst_16_upstream_end_xfer),
      .d1_system_0_burst_17_upstream_end_xfer                                      (d1_system_0_burst_17_upstream_end_xfer),
      .d1_system_0_burst_18_upstream_end_xfer                                      (d1_system_0_burst_18_upstream_end_xfer),
      .d1_system_0_burst_19_upstream_end_xfer                                      (d1_system_0_burst_19_upstream_end_xfer),
      .d1_system_0_burst_1_upstream_end_xfer                                       (d1_system_0_burst_1_upstream_end_xfer),
      .d1_system_0_burst_20_upstream_end_xfer                                      (d1_system_0_burst_20_upstream_end_xfer),
      .d1_system_0_burst_21_upstream_end_xfer                                      (d1_system_0_burst_21_upstream_end_xfer),
      .d1_system_0_burst_22_upstream_end_xfer                                      (d1_system_0_burst_22_upstream_end_xfer),
      .d1_system_0_burst_23_upstream_end_xfer                                      (d1_system_0_burst_23_upstream_end_xfer),
      .d1_system_0_burst_24_upstream_end_xfer                                      (d1_system_0_burst_24_upstream_end_xfer),
      .d1_system_0_burst_25_upstream_end_xfer                                      (d1_system_0_burst_25_upstream_end_xfer),
      .d1_system_0_burst_26_upstream_end_xfer                                      (d1_system_0_burst_26_upstream_end_xfer),
      .d1_system_0_burst_27_upstream_end_xfer                                      (d1_system_0_burst_27_upstream_end_xfer),
      .d1_system_0_burst_28_upstream_end_xfer                                      (d1_system_0_burst_28_upstream_end_xfer),
      .d1_system_0_burst_29_upstream_end_xfer                                      (d1_system_0_burst_29_upstream_end_xfer),
      .d1_system_0_burst_30_upstream_end_xfer                                      (d1_system_0_burst_30_upstream_end_xfer),
      .d1_system_0_burst_31_upstream_end_xfer                                      (d1_system_0_burst_31_upstream_end_xfer),
      .d1_system_0_burst_32_upstream_end_xfer                                      (d1_system_0_burst_32_upstream_end_xfer),
      .d1_system_0_burst_34_upstream_end_xfer                                      (d1_system_0_burst_34_upstream_end_xfer),
      .d1_system_0_burst_35_upstream_end_xfer                                      (d1_system_0_burst_35_upstream_end_xfer),
      .d1_system_0_burst_3_upstream_end_xfer                                       (d1_system_0_burst_3_upstream_end_xfer),
      .d1_system_0_burst_5_upstream_end_xfer                                       (d1_system_0_burst_5_upstream_end_xfer),
      .d1_system_0_burst_7_upstream_end_xfer                                       (d1_system_0_burst_7_upstream_end_xfer),
      .d1_system_0_burst_8_upstream_end_xfer                                       (d1_system_0_burst_8_upstream_end_xfer),
      .d1_system_0_burst_9_upstream_end_xfer                                       (d1_system_0_burst_9_upstream_end_xfer),
      .dist_sensor_s1_irq_from_sa                                                  (dist_sensor_s1_irq_from_sa),
      .epcs_controller_epcs_control_port_irq_from_sa                               (epcs_controller_epcs_control_port_irq_from_sa),
      .i2c_master_avalon_slave_0_irq_from_sa                                       (i2c_master_avalon_slave_0_irq_from_sa),
      .jtag_uart_0_avalon_jtag_slave_irq_from_sa                                   (jtag_uart_0_avalon_jtag_slave_irq_from_sa),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_10_upstream_readdata_from_sa                                 (system_0_burst_10_upstream_readdata_from_sa),
      .system_0_burst_10_upstream_waitrequest_from_sa                              (system_0_burst_10_upstream_waitrequest_from_sa),
      .system_0_burst_11_upstream_readdata_from_sa                                 (system_0_burst_11_upstream_readdata_from_sa),
      .system_0_burst_11_upstream_waitrequest_from_sa                              (system_0_burst_11_upstream_waitrequest_from_sa),
      .system_0_burst_12_upstream_readdata_from_sa                                 (system_0_burst_12_upstream_readdata_from_sa),
      .system_0_burst_12_upstream_waitrequest_from_sa                              (system_0_burst_12_upstream_waitrequest_from_sa),
      .system_0_burst_13_upstream_readdata_from_sa                                 (system_0_burst_13_upstream_readdata_from_sa),
      .system_0_burst_13_upstream_waitrequest_from_sa                              (system_0_burst_13_upstream_waitrequest_from_sa),
      .system_0_burst_15_upstream_readdata_from_sa                                 (system_0_burst_15_upstream_readdata_from_sa),
      .system_0_burst_15_upstream_waitrequest_from_sa                              (system_0_burst_15_upstream_waitrequest_from_sa),
      .system_0_burst_16_upstream_readdata_from_sa                                 (system_0_burst_16_upstream_readdata_from_sa),
      .system_0_burst_16_upstream_waitrequest_from_sa                              (system_0_burst_16_upstream_waitrequest_from_sa),
      .system_0_burst_17_upstream_readdata_from_sa                                 (system_0_burst_17_upstream_readdata_from_sa),
      .system_0_burst_17_upstream_waitrequest_from_sa                              (system_0_burst_17_upstream_waitrequest_from_sa),
      .system_0_burst_18_upstream_readdata_from_sa                                 (system_0_burst_18_upstream_readdata_from_sa),
      .system_0_burst_18_upstream_waitrequest_from_sa                              (system_0_burst_18_upstream_waitrequest_from_sa),
      .system_0_burst_19_upstream_readdata_from_sa                                 (system_0_burst_19_upstream_readdata_from_sa),
      .system_0_burst_19_upstream_waitrequest_from_sa                              (system_0_burst_19_upstream_waitrequest_from_sa),
      .system_0_burst_1_upstream_readdata_from_sa                                  (system_0_burst_1_upstream_readdata_from_sa),
      .system_0_burst_1_upstream_waitrequest_from_sa                               (system_0_burst_1_upstream_waitrequest_from_sa),
      .system_0_burst_20_upstream_readdata_from_sa                                 (system_0_burst_20_upstream_readdata_from_sa),
      .system_0_burst_20_upstream_waitrequest_from_sa                              (system_0_burst_20_upstream_waitrequest_from_sa),
      .system_0_burst_21_upstream_readdata_from_sa                                 (system_0_burst_21_upstream_readdata_from_sa),
      .system_0_burst_21_upstream_waitrequest_from_sa                              (system_0_burst_21_upstream_waitrequest_from_sa),
      .system_0_burst_22_upstream_readdata_from_sa                                 (system_0_burst_22_upstream_readdata_from_sa),
      .system_0_burst_22_upstream_waitrequest_from_sa                              (system_0_burst_22_upstream_waitrequest_from_sa),
      .system_0_burst_23_upstream_readdata_from_sa                                 (system_0_burst_23_upstream_readdata_from_sa),
      .system_0_burst_23_upstream_waitrequest_from_sa                              (system_0_burst_23_upstream_waitrequest_from_sa),
      .system_0_burst_24_upstream_readdata_from_sa                                 (system_0_burst_24_upstream_readdata_from_sa),
      .system_0_burst_24_upstream_waitrequest_from_sa                              (system_0_burst_24_upstream_waitrequest_from_sa),
      .system_0_burst_25_upstream_readdata_from_sa                                 (system_0_burst_25_upstream_readdata_from_sa),
      .system_0_burst_25_upstream_waitrequest_from_sa                              (system_0_burst_25_upstream_waitrequest_from_sa),
      .system_0_burst_26_upstream_readdata_from_sa                                 (system_0_burst_26_upstream_readdata_from_sa),
      .system_0_burst_26_upstream_waitrequest_from_sa                              (system_0_burst_26_upstream_waitrequest_from_sa),
      .system_0_burst_27_upstream_readdata_from_sa                                 (system_0_burst_27_upstream_readdata_from_sa),
      .system_0_burst_27_upstream_waitrequest_from_sa                              (system_0_burst_27_upstream_waitrequest_from_sa),
      .system_0_burst_28_upstream_readdata_from_sa                                 (system_0_burst_28_upstream_readdata_from_sa),
      .system_0_burst_28_upstream_waitrequest_from_sa                              (system_0_burst_28_upstream_waitrequest_from_sa),
      .system_0_burst_29_upstream_readdata_from_sa                                 (system_0_burst_29_upstream_readdata_from_sa),
      .system_0_burst_29_upstream_waitrequest_from_sa                              (system_0_burst_29_upstream_waitrequest_from_sa),
      .system_0_burst_30_upstream_readdata_from_sa                                 (system_0_burst_30_upstream_readdata_from_sa),
      .system_0_burst_30_upstream_waitrequest_from_sa                              (system_0_burst_30_upstream_waitrequest_from_sa),
      .system_0_burst_31_upstream_readdata_from_sa                                 (system_0_burst_31_upstream_readdata_from_sa),
      .system_0_burst_31_upstream_waitrequest_from_sa                              (system_0_burst_31_upstream_waitrequest_from_sa),
      .system_0_burst_32_upstream_readdata_from_sa                                 (system_0_burst_32_upstream_readdata_from_sa),
      .system_0_burst_32_upstream_waitrequest_from_sa                              (system_0_burst_32_upstream_waitrequest_from_sa),
      .system_0_burst_34_upstream_readdata_from_sa                                 (system_0_burst_34_upstream_readdata_from_sa),
      .system_0_burst_34_upstream_waitrequest_from_sa                              (system_0_burst_34_upstream_waitrequest_from_sa),
      .system_0_burst_35_upstream_readdata_from_sa                                 (system_0_burst_35_upstream_readdata_from_sa),
      .system_0_burst_35_upstream_waitrequest_from_sa                              (system_0_burst_35_upstream_waitrequest_from_sa),
      .system_0_burst_3_upstream_readdata_from_sa                                  (system_0_burst_3_upstream_readdata_from_sa),
      .system_0_burst_3_upstream_waitrequest_from_sa                               (system_0_burst_3_upstream_waitrequest_from_sa),
      .system_0_burst_5_upstream_readdata_from_sa                                  (system_0_burst_5_upstream_readdata_from_sa),
      .system_0_burst_5_upstream_waitrequest_from_sa                               (system_0_burst_5_upstream_waitrequest_from_sa),
      .system_0_burst_7_upstream_readdata_from_sa                                  (system_0_burst_7_upstream_readdata_from_sa),
      .system_0_burst_7_upstream_waitrequest_from_sa                               (system_0_burst_7_upstream_waitrequest_from_sa),
      .system_0_burst_8_upstream_readdata_from_sa                                  (system_0_burst_8_upstream_readdata_from_sa),
      .system_0_burst_8_upstream_waitrequest_from_sa                               (system_0_burst_8_upstream_waitrequest_from_sa),
      .system_0_burst_9_upstream_readdata_from_sa                                  (system_0_burst_9_upstream_readdata_from_sa),
      .system_0_burst_9_upstream_waitrequest_from_sa                               (system_0_burst_9_upstream_waitrequest_from_sa),
      .timer_0_s1_irq_from_sa                                                      (timer_0_s1_irq_from_sa),
      .timer_1_s1_irq_from_sa                                                      (timer_1_s1_irq_from_sa),
      .uart_0_s1_irq_from_sa                                                       (uart_0_s1_irq_from_sa)
    );

  cpu_0_instruction_master_arbitrator the_cpu_0_instruction_master
    (
      .clk                                                                                (altpll_0_c1_out),
      .cpu_0_instruction_master_address                                                   (cpu_0_instruction_master_address),
      .cpu_0_instruction_master_address_to_slave                                          (cpu_0_instruction_master_address_to_slave),
      .cpu_0_instruction_master_burstcount                                                (cpu_0_instruction_master_burstcount),
      .cpu_0_instruction_master_dbs_address                                               (cpu_0_instruction_master_dbs_address),
      .cpu_0_instruction_master_granted_system_0_burst_0_upstream                         (cpu_0_instruction_master_granted_system_0_burst_0_upstream),
      .cpu_0_instruction_master_granted_system_0_burst_14_upstream                        (cpu_0_instruction_master_granted_system_0_burst_14_upstream),
      .cpu_0_instruction_master_granted_system_0_burst_2_upstream                         (cpu_0_instruction_master_granted_system_0_burst_2_upstream),
      .cpu_0_instruction_master_granted_system_0_burst_33_upstream                        (cpu_0_instruction_master_granted_system_0_burst_33_upstream),
      .cpu_0_instruction_master_granted_system_0_burst_4_upstream                         (cpu_0_instruction_master_granted_system_0_burst_4_upstream),
      .cpu_0_instruction_master_granted_system_0_burst_6_upstream                         (cpu_0_instruction_master_granted_system_0_burst_6_upstream),
      .cpu_0_instruction_master_latency_counter                                           (cpu_0_instruction_master_latency_counter),
      .cpu_0_instruction_master_qualified_request_system_0_burst_0_upstream               (cpu_0_instruction_master_qualified_request_system_0_burst_0_upstream),
      .cpu_0_instruction_master_qualified_request_system_0_burst_14_upstream              (cpu_0_instruction_master_qualified_request_system_0_burst_14_upstream),
      .cpu_0_instruction_master_qualified_request_system_0_burst_2_upstream               (cpu_0_instruction_master_qualified_request_system_0_burst_2_upstream),
      .cpu_0_instruction_master_qualified_request_system_0_burst_33_upstream              (cpu_0_instruction_master_qualified_request_system_0_burst_33_upstream),
      .cpu_0_instruction_master_qualified_request_system_0_burst_4_upstream               (cpu_0_instruction_master_qualified_request_system_0_burst_4_upstream),
      .cpu_0_instruction_master_qualified_request_system_0_burst_6_upstream               (cpu_0_instruction_master_qualified_request_system_0_burst_6_upstream),
      .cpu_0_instruction_master_read                                                      (cpu_0_instruction_master_read),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream                 (cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream                (cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register (cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream                 (cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream                (cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register (cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream                 (cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream                 (cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register),
      .cpu_0_instruction_master_readdata                                                  (cpu_0_instruction_master_readdata),
      .cpu_0_instruction_master_readdatavalid                                             (cpu_0_instruction_master_readdatavalid),
      .cpu_0_instruction_master_requests_system_0_burst_0_upstream                        (cpu_0_instruction_master_requests_system_0_burst_0_upstream),
      .cpu_0_instruction_master_requests_system_0_burst_14_upstream                       (cpu_0_instruction_master_requests_system_0_burst_14_upstream),
      .cpu_0_instruction_master_requests_system_0_burst_2_upstream                        (cpu_0_instruction_master_requests_system_0_burst_2_upstream),
      .cpu_0_instruction_master_requests_system_0_burst_33_upstream                       (cpu_0_instruction_master_requests_system_0_burst_33_upstream),
      .cpu_0_instruction_master_requests_system_0_burst_4_upstream                        (cpu_0_instruction_master_requests_system_0_burst_4_upstream),
      .cpu_0_instruction_master_requests_system_0_burst_6_upstream                        (cpu_0_instruction_master_requests_system_0_burst_6_upstream),
      .cpu_0_instruction_master_waitrequest                                               (cpu_0_instruction_master_waitrequest),
      .d1_system_0_burst_0_upstream_end_xfer                                              (d1_system_0_burst_0_upstream_end_xfer),
      .d1_system_0_burst_14_upstream_end_xfer                                             (d1_system_0_burst_14_upstream_end_xfer),
      .d1_system_0_burst_2_upstream_end_xfer                                              (d1_system_0_burst_2_upstream_end_xfer),
      .d1_system_0_burst_33_upstream_end_xfer                                             (d1_system_0_burst_33_upstream_end_xfer),
      .d1_system_0_burst_4_upstream_end_xfer                                              (d1_system_0_burst_4_upstream_end_xfer),
      .d1_system_0_burst_6_upstream_end_xfer                                              (d1_system_0_burst_6_upstream_end_xfer),
      .reset_n                                                                            (altpll_0_c1_out_reset_n),
      .system_0_burst_0_upstream_readdata_from_sa                                         (system_0_burst_0_upstream_readdata_from_sa),
      .system_0_burst_0_upstream_waitrequest_from_sa                                      (system_0_burst_0_upstream_waitrequest_from_sa),
      .system_0_burst_14_upstream_readdata_from_sa                                        (system_0_burst_14_upstream_readdata_from_sa),
      .system_0_burst_14_upstream_waitrequest_from_sa                                     (system_0_burst_14_upstream_waitrequest_from_sa),
      .system_0_burst_2_upstream_readdata_from_sa                                         (system_0_burst_2_upstream_readdata_from_sa),
      .system_0_burst_2_upstream_waitrequest_from_sa                                      (system_0_burst_2_upstream_waitrequest_from_sa),
      .system_0_burst_33_upstream_readdata_from_sa                                        (system_0_burst_33_upstream_readdata_from_sa),
      .system_0_burst_33_upstream_waitrequest_from_sa                                     (system_0_burst_33_upstream_waitrequest_from_sa),
      .system_0_burst_4_upstream_readdata_from_sa                                         (system_0_burst_4_upstream_readdata_from_sa),
      .system_0_burst_4_upstream_waitrequest_from_sa                                      (system_0_burst_4_upstream_waitrequest_from_sa),
      .system_0_burst_6_upstream_readdata_from_sa                                         (system_0_burst_6_upstream_readdata_from_sa),
      .system_0_burst_6_upstream_waitrequest_from_sa                                      (system_0_burst_6_upstream_waitrequest_from_sa)
    );

  cpu_0 the_cpu_0
    (
      .clk                                   (altpll_0_c1_out),
      .d_address                             (cpu_0_data_master_address),
      .d_burstcount                          (cpu_0_data_master_burstcount),
      .d_byteenable                          (cpu_0_data_master_byteenable),
      .d_irq                                 (cpu_0_data_master_irq),
      .d_read                                (cpu_0_data_master_read),
      .d_readdata                            (cpu_0_data_master_readdata),
      .d_readdatavalid                       (cpu_0_data_master_readdatavalid),
      .d_waitrequest                         (cpu_0_data_master_waitrequest),
      .d_write                               (cpu_0_data_master_write),
      .d_writedata                           (cpu_0_data_master_writedata),
      .i_address                             (cpu_0_instruction_master_address),
      .i_burstcount                          (cpu_0_instruction_master_burstcount),
      .i_read                                (cpu_0_instruction_master_read),
      .i_readdata                            (cpu_0_instruction_master_readdata),
      .i_readdatavalid                       (cpu_0_instruction_master_readdatavalid),
      .i_waitrequest                         (cpu_0_instruction_master_waitrequest),
      .jtag_debug_module_address             (cpu_0_jtag_debug_module_address),
      .jtag_debug_module_begintransfer       (cpu_0_jtag_debug_module_begintransfer),
      .jtag_debug_module_byteenable          (cpu_0_jtag_debug_module_byteenable),
      .jtag_debug_module_debugaccess         (cpu_0_jtag_debug_module_debugaccess),
      .jtag_debug_module_debugaccess_to_roms (cpu_0_data_master_debugaccess),
      .jtag_debug_module_readdata            (cpu_0_jtag_debug_module_readdata),
      .jtag_debug_module_resetrequest        (cpu_0_jtag_debug_module_resetrequest),
      .jtag_debug_module_select              (cpu_0_jtag_debug_module_chipselect),
      .jtag_debug_module_write               (cpu_0_jtag_debug_module_write),
      .jtag_debug_module_writedata           (cpu_0_jtag_debug_module_writedata),
      .reset_n                               (cpu_0_jtag_debug_module_reset_n)
    );

  dist_sensor_s1_arbitrator the_dist_sensor_s1
    (
      .clk                                                           (altpll_0_c1_out),
      .d1_dist_sensor_s1_end_xfer                                    (d1_dist_sensor_s1_end_xfer),
      .dist_sensor_s1_address                                        (dist_sensor_s1_address),
      .dist_sensor_s1_chipselect                                     (dist_sensor_s1_chipselect),
      .dist_sensor_s1_irq                                            (dist_sensor_s1_irq),
      .dist_sensor_s1_irq_from_sa                                    (dist_sensor_s1_irq_from_sa),
      .dist_sensor_s1_readdata                                       (dist_sensor_s1_readdata),
      .dist_sensor_s1_readdata_from_sa                               (dist_sensor_s1_readdata_from_sa),
      .dist_sensor_s1_reset_n                                        (dist_sensor_s1_reset_n),
      .dist_sensor_s1_write_n                                        (dist_sensor_s1_write_n),
      .dist_sensor_s1_writedata                                      (dist_sensor_s1_writedata),
      .reset_n                                                       (altpll_0_c1_out_reset_n),
      .system_0_burst_28_downstream_address_to_slave                 (system_0_burst_28_downstream_address_to_slave),
      .system_0_burst_28_downstream_arbitrationshare                 (system_0_burst_28_downstream_arbitrationshare),
      .system_0_burst_28_downstream_burstcount                       (system_0_burst_28_downstream_burstcount),
      .system_0_burst_28_downstream_granted_dist_sensor_s1           (system_0_burst_28_downstream_granted_dist_sensor_s1),
      .system_0_burst_28_downstream_latency_counter                  (system_0_burst_28_downstream_latency_counter),
      .system_0_burst_28_downstream_nativeaddress                    (system_0_burst_28_downstream_nativeaddress),
      .system_0_burst_28_downstream_qualified_request_dist_sensor_s1 (system_0_burst_28_downstream_qualified_request_dist_sensor_s1),
      .system_0_burst_28_downstream_read                             (system_0_burst_28_downstream_read),
      .system_0_burst_28_downstream_read_data_valid_dist_sensor_s1   (system_0_burst_28_downstream_read_data_valid_dist_sensor_s1),
      .system_0_burst_28_downstream_requests_dist_sensor_s1          (system_0_burst_28_downstream_requests_dist_sensor_s1),
      .system_0_burst_28_downstream_write                            (system_0_burst_28_downstream_write),
      .system_0_burst_28_downstream_writedata                        (system_0_burst_28_downstream_writedata)
    );

  dist_sensor the_dist_sensor
    (
      .address    (dist_sensor_s1_address),
      .chipselect (dist_sensor_s1_chipselect),
      .clk        (altpll_0_c1_out),
      .in_port    (in_port_to_the_dist_sensor),
      .irq        (dist_sensor_s1_irq),
      .readdata   (dist_sensor_s1_readdata),
      .reset_n    (dist_sensor_s1_reset_n),
      .write_n    (dist_sensor_s1_write_n),
      .writedata  (dist_sensor_s1_writedata)
    );

  epcs_controller_epcs_control_port_arbitrator the_epcs_controller_epcs_control_port
    (
      .clk                                                                             (altpll_0_c1_out),
      .d1_epcs_controller_epcs_control_port_end_xfer                                   (d1_epcs_controller_epcs_control_port_end_xfer),
      .epcs_controller_epcs_control_port_address                                       (epcs_controller_epcs_control_port_address),
      .epcs_controller_epcs_control_port_chipselect                                    (epcs_controller_epcs_control_port_chipselect),
      .epcs_controller_epcs_control_port_dataavailable                                 (epcs_controller_epcs_control_port_dataavailable),
      .epcs_controller_epcs_control_port_dataavailable_from_sa                         (epcs_controller_epcs_control_port_dataavailable_from_sa),
      .epcs_controller_epcs_control_port_endofpacket                                   (epcs_controller_epcs_control_port_endofpacket),
      .epcs_controller_epcs_control_port_endofpacket_from_sa                           (epcs_controller_epcs_control_port_endofpacket_from_sa),
      .epcs_controller_epcs_control_port_irq                                           (epcs_controller_epcs_control_port_irq),
      .epcs_controller_epcs_control_port_irq_from_sa                                   (epcs_controller_epcs_control_port_irq_from_sa),
      .epcs_controller_epcs_control_port_read_n                                        (epcs_controller_epcs_control_port_read_n),
      .epcs_controller_epcs_control_port_readdata                                      (epcs_controller_epcs_control_port_readdata),
      .epcs_controller_epcs_control_port_readdata_from_sa                              (epcs_controller_epcs_control_port_readdata_from_sa),
      .epcs_controller_epcs_control_port_readyfordata                                  (epcs_controller_epcs_control_port_readyfordata),
      .epcs_controller_epcs_control_port_readyfordata_from_sa                          (epcs_controller_epcs_control_port_readyfordata_from_sa),
      .epcs_controller_epcs_control_port_reset_n                                       (epcs_controller_epcs_control_port_reset_n),
      .epcs_controller_epcs_control_port_write_n                                       (epcs_controller_epcs_control_port_write_n),
      .epcs_controller_epcs_control_port_writedata                                     (epcs_controller_epcs_control_port_writedata),
      .reset_n                                                                         (altpll_0_c1_out_reset_n),
      .system_0_burst_6_downstream_address_to_slave                                    (system_0_burst_6_downstream_address_to_slave),
      .system_0_burst_6_downstream_arbitrationshare                                    (system_0_burst_6_downstream_arbitrationshare),
      .system_0_burst_6_downstream_burstcount                                          (system_0_burst_6_downstream_burstcount),
      .system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port           (system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port),
      .system_0_burst_6_downstream_latency_counter                                     (system_0_burst_6_downstream_latency_counter),
      .system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port (system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port),
      .system_0_burst_6_downstream_read                                                (system_0_burst_6_downstream_read),
      .system_0_burst_6_downstream_read_data_valid_epcs_controller_epcs_control_port   (system_0_burst_6_downstream_read_data_valid_epcs_controller_epcs_control_port),
      .system_0_burst_6_downstream_requests_epcs_controller_epcs_control_port          (system_0_burst_6_downstream_requests_epcs_controller_epcs_control_port),
      .system_0_burst_6_downstream_write                                               (system_0_burst_6_downstream_write),
      .system_0_burst_6_downstream_writedata                                           (system_0_burst_6_downstream_writedata),
      .system_0_burst_7_downstream_address_to_slave                                    (system_0_burst_7_downstream_address_to_slave),
      .system_0_burst_7_downstream_arbitrationshare                                    (system_0_burst_7_downstream_arbitrationshare),
      .system_0_burst_7_downstream_burstcount                                          (system_0_burst_7_downstream_burstcount),
      .system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port           (system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port),
      .system_0_burst_7_downstream_latency_counter                                     (system_0_burst_7_downstream_latency_counter),
      .system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port (system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port),
      .system_0_burst_7_downstream_read                                                (system_0_burst_7_downstream_read),
      .system_0_burst_7_downstream_read_data_valid_epcs_controller_epcs_control_port   (system_0_burst_7_downstream_read_data_valid_epcs_controller_epcs_control_port),
      .system_0_burst_7_downstream_requests_epcs_controller_epcs_control_port          (system_0_burst_7_downstream_requests_epcs_controller_epcs_control_port),
      .system_0_burst_7_downstream_write                                               (system_0_burst_7_downstream_write),
      .system_0_burst_7_downstream_writedata                                           (system_0_burst_7_downstream_writedata)
    );

  epcs_controller the_epcs_controller
    (
      .address       (epcs_controller_epcs_control_port_address),
      .chipselect    (epcs_controller_epcs_control_port_chipselect),
      .clk           (altpll_0_c1_out),
      .dataavailable (epcs_controller_epcs_control_port_dataavailable),
      .endofpacket   (epcs_controller_epcs_control_port_endofpacket),
      .irq           (epcs_controller_epcs_control_port_irq),
      .read_n        (epcs_controller_epcs_control_port_read_n),
      .readdata      (epcs_controller_epcs_control_port_readdata),
      .readyfordata  (epcs_controller_epcs_control_port_readyfordata),
      .reset_n       (epcs_controller_epcs_control_port_reset_n),
      .write_n       (epcs_controller_epcs_control_port_write_n),
      .writedata     (epcs_controller_epcs_control_port_writedata)
    );

  i2c_master_avalon_slave_0_arbitrator the_i2c_master_avalon_slave_0
    (
      .clk                                                                      (altpll_0_c1_out),
      .d1_i2c_master_avalon_slave_0_end_xfer                                    (d1_i2c_master_avalon_slave_0_end_xfer),
      .i2c_master_avalon_slave_0_address                                        (i2c_master_avalon_slave_0_address),
      .i2c_master_avalon_slave_0_chipselect                                     (i2c_master_avalon_slave_0_chipselect),
      .i2c_master_avalon_slave_0_irq                                            (i2c_master_avalon_slave_0_irq),
      .i2c_master_avalon_slave_0_irq_from_sa                                    (i2c_master_avalon_slave_0_irq_from_sa),
      .i2c_master_avalon_slave_0_readdata                                       (i2c_master_avalon_slave_0_readdata),
      .i2c_master_avalon_slave_0_readdata_from_sa                               (i2c_master_avalon_slave_0_readdata_from_sa),
      .i2c_master_avalon_slave_0_reset                                          (i2c_master_avalon_slave_0_reset),
      .i2c_master_avalon_slave_0_waitrequest_n                                  (i2c_master_avalon_slave_0_waitrequest_n),
      .i2c_master_avalon_slave_0_waitrequest_n_from_sa                          (i2c_master_avalon_slave_0_waitrequest_n_from_sa),
      .i2c_master_avalon_slave_0_write                                          (i2c_master_avalon_slave_0_write),
      .i2c_master_avalon_slave_0_writedata                                      (i2c_master_avalon_slave_0_writedata),
      .reset_n                                                                  (altpll_0_c1_out_reset_n),
      .system_0_burst_33_downstream_address_to_slave                            (system_0_burst_33_downstream_address_to_slave),
      .system_0_burst_33_downstream_arbitrationshare                            (system_0_burst_33_downstream_arbitrationshare),
      .system_0_burst_33_downstream_burstcount                                  (system_0_burst_33_downstream_burstcount),
      .system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0           (system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0),
      .system_0_burst_33_downstream_latency_counter                             (system_0_burst_33_downstream_latency_counter),
      .system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0 (system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0),
      .system_0_burst_33_downstream_read                                        (system_0_burst_33_downstream_read),
      .system_0_burst_33_downstream_read_data_valid_i2c_master_avalon_slave_0   (system_0_burst_33_downstream_read_data_valid_i2c_master_avalon_slave_0),
      .system_0_burst_33_downstream_requests_i2c_master_avalon_slave_0          (system_0_burst_33_downstream_requests_i2c_master_avalon_slave_0),
      .system_0_burst_33_downstream_write                                       (system_0_burst_33_downstream_write),
      .system_0_burst_33_downstream_writedata                                   (system_0_burst_33_downstream_writedata),
      .system_0_burst_34_downstream_address_to_slave                            (system_0_burst_34_downstream_address_to_slave),
      .system_0_burst_34_downstream_arbitrationshare                            (system_0_burst_34_downstream_arbitrationshare),
      .system_0_burst_34_downstream_burstcount                                  (system_0_burst_34_downstream_burstcount),
      .system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0           (system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0),
      .system_0_burst_34_downstream_latency_counter                             (system_0_burst_34_downstream_latency_counter),
      .system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0 (system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0),
      .system_0_burst_34_downstream_read                                        (system_0_burst_34_downstream_read),
      .system_0_burst_34_downstream_read_data_valid_i2c_master_avalon_slave_0   (system_0_burst_34_downstream_read_data_valid_i2c_master_avalon_slave_0),
      .system_0_burst_34_downstream_requests_i2c_master_avalon_slave_0          (system_0_burst_34_downstream_requests_i2c_master_avalon_slave_0),
      .system_0_burst_34_downstream_write                                       (system_0_burst_34_downstream_write),
      .system_0_burst_34_downstream_writedata                                   (system_0_burst_34_downstream_writedata)
    );

  i2c_master the_i2c_master
    (
      .scl_pad_io     (scl_pad_io_from_the_i2c_master),
      .sda_pad_io     (sda_pad_io_to_and_from_the_i2c_master),
      .sda_padoen_out (sda_padoen_out_from_the_i2c_master),
      .wb_ack_o       (i2c_master_avalon_slave_0_waitrequest_n),
      .wb_adr_i       (i2c_master_avalon_slave_0_address),
      .wb_clk_i       (altpll_0_c1_out),
      .wb_cs_i        (i2c_master_avalon_slave_0_chipselect),
      .wb_dat_i       (i2c_master_avalon_slave_0_writedata),
      .wb_dat_o       (i2c_master_avalon_slave_0_readdata),
      .wb_err_o       (wb_err_o_from_the_i2c_master),
      .wb_inta_o      (i2c_master_avalon_slave_0_irq),
      .wb_rst_i       (i2c_master_avalon_slave_0_reset),
      .wb_we_i        (i2c_master_avalon_slave_0_write)
    );

  jtag_uart_0_avalon_jtag_slave_arbitrator the_jtag_uart_0_avalon_jtag_slave
    (
      .clk                                                                         (altpll_0_c1_out),
      .d1_jtag_uart_0_avalon_jtag_slave_end_xfer                                   (d1_jtag_uart_0_avalon_jtag_slave_end_xfer),
      .jtag_uart_0_avalon_jtag_slave_address                                       (jtag_uart_0_avalon_jtag_slave_address),
      .jtag_uart_0_avalon_jtag_slave_chipselect                                    (jtag_uart_0_avalon_jtag_slave_chipselect),
      .jtag_uart_0_avalon_jtag_slave_dataavailable                                 (jtag_uart_0_avalon_jtag_slave_dataavailable),
      .jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa                         (jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa),
      .jtag_uart_0_avalon_jtag_slave_irq                                           (jtag_uart_0_avalon_jtag_slave_irq),
      .jtag_uart_0_avalon_jtag_slave_irq_from_sa                                   (jtag_uart_0_avalon_jtag_slave_irq_from_sa),
      .jtag_uart_0_avalon_jtag_slave_read_n                                        (jtag_uart_0_avalon_jtag_slave_read_n),
      .jtag_uart_0_avalon_jtag_slave_readdata                                      (jtag_uart_0_avalon_jtag_slave_readdata),
      .jtag_uart_0_avalon_jtag_slave_readdata_from_sa                              (jtag_uart_0_avalon_jtag_slave_readdata_from_sa),
      .jtag_uart_0_avalon_jtag_slave_readyfordata                                  (jtag_uart_0_avalon_jtag_slave_readyfordata),
      .jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa                          (jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa),
      .jtag_uart_0_avalon_jtag_slave_reset_n                                       (jtag_uart_0_avalon_jtag_slave_reset_n),
      .jtag_uart_0_avalon_jtag_slave_waitrequest                                   (jtag_uart_0_avalon_jtag_slave_waitrequest),
      .jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa                           (jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa),
      .jtag_uart_0_avalon_jtag_slave_write_n                                       (jtag_uart_0_avalon_jtag_slave_write_n),
      .jtag_uart_0_avalon_jtag_slave_writedata                                     (jtag_uart_0_avalon_jtag_slave_writedata),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_8_downstream_address_to_slave                                (system_0_burst_8_downstream_address_to_slave),
      .system_0_burst_8_downstream_arbitrationshare                                (system_0_burst_8_downstream_arbitrationshare),
      .system_0_burst_8_downstream_burstcount                                      (system_0_burst_8_downstream_burstcount),
      .system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave           (system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave),
      .system_0_burst_8_downstream_latency_counter                                 (system_0_burst_8_downstream_latency_counter),
      .system_0_burst_8_downstream_nativeaddress                                   (system_0_burst_8_downstream_nativeaddress),
      .system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave (system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave),
      .system_0_burst_8_downstream_read                                            (system_0_burst_8_downstream_read),
      .system_0_burst_8_downstream_read_data_valid_jtag_uart_0_avalon_jtag_slave   (system_0_burst_8_downstream_read_data_valid_jtag_uart_0_avalon_jtag_slave),
      .system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave          (system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave),
      .system_0_burst_8_downstream_write                                           (system_0_burst_8_downstream_write),
      .system_0_burst_8_downstream_writedata                                       (system_0_burst_8_downstream_writedata)
    );

  jtag_uart_0 the_jtag_uart_0
    (
      .av_address     (jtag_uart_0_avalon_jtag_slave_address),
      .av_chipselect  (jtag_uart_0_avalon_jtag_slave_chipselect),
      .av_irq         (jtag_uart_0_avalon_jtag_slave_irq),
      .av_read_n      (jtag_uart_0_avalon_jtag_slave_read_n),
      .av_readdata    (jtag_uart_0_avalon_jtag_slave_readdata),
      .av_waitrequest (jtag_uart_0_avalon_jtag_slave_waitrequest),
      .av_write_n     (jtag_uart_0_avalon_jtag_slave_write_n),
      .av_writedata   (jtag_uart_0_avalon_jtag_slave_writedata),
      .clk            (altpll_0_c1_out),
      .dataavailable  (jtag_uart_0_avalon_jtag_slave_dataavailable),
      .readyfordata   (jtag_uart_0_avalon_jtag_slave_readyfordata),
      .rst_n          (jtag_uart_0_avalon_jtag_slave_reset_n)
    );

  lcd_16207_0_control_slave_arbitrator the_lcd_16207_0_control_slave
    (
      .clk                                                                      (altpll_0_c1_out),
      .d1_lcd_16207_0_control_slave_end_xfer                                    (d1_lcd_16207_0_control_slave_end_xfer),
      .lcd_16207_0_control_slave_address                                        (lcd_16207_0_control_slave_address),
      .lcd_16207_0_control_slave_begintransfer                                  (lcd_16207_0_control_slave_begintransfer),
      .lcd_16207_0_control_slave_read                                           (lcd_16207_0_control_slave_read),
      .lcd_16207_0_control_slave_readdata                                       (lcd_16207_0_control_slave_readdata),
      .lcd_16207_0_control_slave_readdata_from_sa                               (lcd_16207_0_control_slave_readdata_from_sa),
      .lcd_16207_0_control_slave_wait_counter_eq_0                              (lcd_16207_0_control_slave_wait_counter_eq_0),
      .lcd_16207_0_control_slave_write                                          (lcd_16207_0_control_slave_write),
      .lcd_16207_0_control_slave_writedata                                      (lcd_16207_0_control_slave_writedata),
      .reset_n                                                                  (altpll_0_c1_out_reset_n),
      .system_0_burst_12_downstream_address_to_slave                            (system_0_burst_12_downstream_address_to_slave),
      .system_0_burst_12_downstream_arbitrationshare                            (system_0_burst_12_downstream_arbitrationshare),
      .system_0_burst_12_downstream_burstcount                                  (system_0_burst_12_downstream_burstcount),
      .system_0_burst_12_downstream_byteenable                                  (system_0_burst_12_downstream_byteenable),
      .system_0_burst_12_downstream_granted_lcd_16207_0_control_slave           (system_0_burst_12_downstream_granted_lcd_16207_0_control_slave),
      .system_0_burst_12_downstream_latency_counter                             (system_0_burst_12_downstream_latency_counter),
      .system_0_burst_12_downstream_nativeaddress                               (system_0_burst_12_downstream_nativeaddress),
      .system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave (system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave),
      .system_0_burst_12_downstream_read                                        (system_0_burst_12_downstream_read),
      .system_0_burst_12_downstream_read_data_valid_lcd_16207_0_control_slave   (system_0_burst_12_downstream_read_data_valid_lcd_16207_0_control_slave),
      .system_0_burst_12_downstream_requests_lcd_16207_0_control_slave          (system_0_burst_12_downstream_requests_lcd_16207_0_control_slave),
      .system_0_burst_12_downstream_write                                       (system_0_burst_12_downstream_write),
      .system_0_burst_12_downstream_writedata                                   (system_0_burst_12_downstream_writedata)
    );

  lcd_16207_0 the_lcd_16207_0
    (
      .LCD_E         (LCD_E_from_the_lcd_16207_0),
      .LCD_RS        (LCD_RS_from_the_lcd_16207_0),
      .LCD_RW        (LCD_RW_from_the_lcd_16207_0),
      .LCD_data      (LCD_data_to_and_from_the_lcd_16207_0),
      .address       (lcd_16207_0_control_slave_address),
      .begintransfer (lcd_16207_0_control_slave_begintransfer),
      .read          (lcd_16207_0_control_slave_read),
      .readdata      (lcd_16207_0_control_slave_readdata),
      .write         (lcd_16207_0_control_slave_write),
      .writedata     (lcd_16207_0_control_slave_writedata)
    );

  noteA_s1_arbitrator the_noteA_s1
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_noteA_s1_end_xfer                                    (d1_noteA_s1_end_xfer),
      .noteA_s1_address                                        (noteA_s1_address),
      .noteA_s1_readdata                                       (noteA_s1_readdata),
      .noteA_s1_readdata_from_sa                               (noteA_s1_readdata_from_sa),
      .noteA_s1_reset_n                                        (noteA_s1_reset_n),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_20_downstream_address_to_slave           (system_0_burst_20_downstream_address_to_slave),
      .system_0_burst_20_downstream_arbitrationshare           (system_0_burst_20_downstream_arbitrationshare),
      .system_0_burst_20_downstream_burstcount                 (system_0_burst_20_downstream_burstcount),
      .system_0_burst_20_downstream_granted_noteA_s1           (system_0_burst_20_downstream_granted_noteA_s1),
      .system_0_burst_20_downstream_latency_counter            (system_0_burst_20_downstream_latency_counter),
      .system_0_burst_20_downstream_nativeaddress              (system_0_burst_20_downstream_nativeaddress),
      .system_0_burst_20_downstream_qualified_request_noteA_s1 (system_0_burst_20_downstream_qualified_request_noteA_s1),
      .system_0_burst_20_downstream_read                       (system_0_burst_20_downstream_read),
      .system_0_burst_20_downstream_read_data_valid_noteA_s1   (system_0_burst_20_downstream_read_data_valid_noteA_s1),
      .system_0_burst_20_downstream_requests_noteA_s1          (system_0_burst_20_downstream_requests_noteA_s1),
      .system_0_burst_20_downstream_write                      (system_0_burst_20_downstream_write)
    );

  noteA the_noteA
    (
      .address  (noteA_s1_address),
      .clk      (altpll_0_c1_out),
      .in_port  (in_port_to_the_noteA),
      .readdata (noteA_s1_readdata),
      .reset_n  (noteA_s1_reset_n)
    );

  noteB_s1_arbitrator the_noteB_s1
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_noteB_s1_end_xfer                                    (d1_noteB_s1_end_xfer),
      .noteB_s1_address                                        (noteB_s1_address),
      .noteB_s1_readdata                                       (noteB_s1_readdata),
      .noteB_s1_readdata_from_sa                               (noteB_s1_readdata_from_sa),
      .noteB_s1_reset_n                                        (noteB_s1_reset_n),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_21_downstream_address_to_slave           (system_0_burst_21_downstream_address_to_slave),
      .system_0_burst_21_downstream_arbitrationshare           (system_0_burst_21_downstream_arbitrationshare),
      .system_0_burst_21_downstream_burstcount                 (system_0_burst_21_downstream_burstcount),
      .system_0_burst_21_downstream_granted_noteB_s1           (system_0_burst_21_downstream_granted_noteB_s1),
      .system_0_burst_21_downstream_latency_counter            (system_0_burst_21_downstream_latency_counter),
      .system_0_burst_21_downstream_nativeaddress              (system_0_burst_21_downstream_nativeaddress),
      .system_0_burst_21_downstream_qualified_request_noteB_s1 (system_0_burst_21_downstream_qualified_request_noteB_s1),
      .system_0_burst_21_downstream_read                       (system_0_burst_21_downstream_read),
      .system_0_burst_21_downstream_read_data_valid_noteB_s1   (system_0_burst_21_downstream_read_data_valid_noteB_s1),
      .system_0_burst_21_downstream_requests_noteB_s1          (system_0_burst_21_downstream_requests_noteB_s1),
      .system_0_burst_21_downstream_write                      (system_0_burst_21_downstream_write)
    );

  noteB the_noteB
    (
      .address  (noteB_s1_address),
      .clk      (altpll_0_c1_out),
      .in_port  (in_port_to_the_noteB),
      .readdata (noteB_s1_readdata),
      .reset_n  (noteB_s1_reset_n)
    );

  noteC_s1_arbitrator the_noteC_s1
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_noteC_s1_end_xfer                                    (d1_noteC_s1_end_xfer),
      .noteC_s1_address                                        (noteC_s1_address),
      .noteC_s1_readdata                                       (noteC_s1_readdata),
      .noteC_s1_readdata_from_sa                               (noteC_s1_readdata_from_sa),
      .noteC_s1_reset_n                                        (noteC_s1_reset_n),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_22_downstream_address_to_slave           (system_0_burst_22_downstream_address_to_slave),
      .system_0_burst_22_downstream_arbitrationshare           (system_0_burst_22_downstream_arbitrationshare),
      .system_0_burst_22_downstream_burstcount                 (system_0_burst_22_downstream_burstcount),
      .system_0_burst_22_downstream_granted_noteC_s1           (system_0_burst_22_downstream_granted_noteC_s1),
      .system_0_burst_22_downstream_latency_counter            (system_0_burst_22_downstream_latency_counter),
      .system_0_burst_22_downstream_nativeaddress              (system_0_burst_22_downstream_nativeaddress),
      .system_0_burst_22_downstream_qualified_request_noteC_s1 (system_0_burst_22_downstream_qualified_request_noteC_s1),
      .system_0_burst_22_downstream_read                       (system_0_burst_22_downstream_read),
      .system_0_burst_22_downstream_read_data_valid_noteC_s1   (system_0_burst_22_downstream_read_data_valid_noteC_s1),
      .system_0_burst_22_downstream_requests_noteC_s1          (system_0_burst_22_downstream_requests_noteC_s1),
      .system_0_burst_22_downstream_write                      (system_0_burst_22_downstream_write)
    );

  noteC the_noteC
    (
      .address  (noteC_s1_address),
      .clk      (altpll_0_c1_out),
      .in_port  (in_port_to_the_noteC),
      .readdata (noteC_s1_readdata),
      .reset_n  (noteC_s1_reset_n)
    );

  noteD_s1_arbitrator the_noteD_s1
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_noteD_s1_end_xfer                                    (d1_noteD_s1_end_xfer),
      .noteD_s1_address                                        (noteD_s1_address),
      .noteD_s1_readdata                                       (noteD_s1_readdata),
      .noteD_s1_readdata_from_sa                               (noteD_s1_readdata_from_sa),
      .noteD_s1_reset_n                                        (noteD_s1_reset_n),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_23_downstream_address_to_slave           (system_0_burst_23_downstream_address_to_slave),
      .system_0_burst_23_downstream_arbitrationshare           (system_0_burst_23_downstream_arbitrationshare),
      .system_0_burst_23_downstream_burstcount                 (system_0_burst_23_downstream_burstcount),
      .system_0_burst_23_downstream_granted_noteD_s1           (system_0_burst_23_downstream_granted_noteD_s1),
      .system_0_burst_23_downstream_latency_counter            (system_0_burst_23_downstream_latency_counter),
      .system_0_burst_23_downstream_nativeaddress              (system_0_burst_23_downstream_nativeaddress),
      .system_0_burst_23_downstream_qualified_request_noteD_s1 (system_0_burst_23_downstream_qualified_request_noteD_s1),
      .system_0_burst_23_downstream_read                       (system_0_burst_23_downstream_read),
      .system_0_burst_23_downstream_read_data_valid_noteD_s1   (system_0_burst_23_downstream_read_data_valid_noteD_s1),
      .system_0_burst_23_downstream_requests_noteD_s1          (system_0_burst_23_downstream_requests_noteD_s1),
      .system_0_burst_23_downstream_write                      (system_0_burst_23_downstream_write)
    );

  noteD the_noteD
    (
      .address  (noteD_s1_address),
      .clk      (altpll_0_c1_out),
      .in_port  (in_port_to_the_noteD),
      .readdata (noteD_s1_readdata),
      .reset_n  (noteD_s1_reset_n)
    );

  noteE_s1_arbitrator the_noteE_s1
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_noteE_s1_end_xfer                                    (d1_noteE_s1_end_xfer),
      .noteE_s1_address                                        (noteE_s1_address),
      .noteE_s1_readdata                                       (noteE_s1_readdata),
      .noteE_s1_readdata_from_sa                               (noteE_s1_readdata_from_sa),
      .noteE_s1_reset_n                                        (noteE_s1_reset_n),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_24_downstream_address_to_slave           (system_0_burst_24_downstream_address_to_slave),
      .system_0_burst_24_downstream_arbitrationshare           (system_0_burst_24_downstream_arbitrationshare),
      .system_0_burst_24_downstream_burstcount                 (system_0_burst_24_downstream_burstcount),
      .system_0_burst_24_downstream_granted_noteE_s1           (system_0_burst_24_downstream_granted_noteE_s1),
      .system_0_burst_24_downstream_latency_counter            (system_0_burst_24_downstream_latency_counter),
      .system_0_burst_24_downstream_nativeaddress              (system_0_burst_24_downstream_nativeaddress),
      .system_0_burst_24_downstream_qualified_request_noteE_s1 (system_0_burst_24_downstream_qualified_request_noteE_s1),
      .system_0_burst_24_downstream_read                       (system_0_burst_24_downstream_read),
      .system_0_burst_24_downstream_read_data_valid_noteE_s1   (system_0_burst_24_downstream_read_data_valid_noteE_s1),
      .system_0_burst_24_downstream_requests_noteE_s1          (system_0_burst_24_downstream_requests_noteE_s1),
      .system_0_burst_24_downstream_write                      (system_0_burst_24_downstream_write)
    );

  noteE the_noteE
    (
      .address  (noteE_s1_address),
      .clk      (altpll_0_c1_out),
      .in_port  (in_port_to_the_noteE),
      .readdata (noteE_s1_readdata),
      .reset_n  (noteE_s1_reset_n)
    );

  noteF_s1_arbitrator the_noteF_s1
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_noteF_s1_end_xfer                                    (d1_noteF_s1_end_xfer),
      .noteF_s1_address                                        (noteF_s1_address),
      .noteF_s1_readdata                                       (noteF_s1_readdata),
      .noteF_s1_readdata_from_sa                               (noteF_s1_readdata_from_sa),
      .noteF_s1_reset_n                                        (noteF_s1_reset_n),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_25_downstream_address_to_slave           (system_0_burst_25_downstream_address_to_slave),
      .system_0_burst_25_downstream_arbitrationshare           (system_0_burst_25_downstream_arbitrationshare),
      .system_0_burst_25_downstream_burstcount                 (system_0_burst_25_downstream_burstcount),
      .system_0_burst_25_downstream_granted_noteF_s1           (system_0_burst_25_downstream_granted_noteF_s1),
      .system_0_burst_25_downstream_latency_counter            (system_0_burst_25_downstream_latency_counter),
      .system_0_burst_25_downstream_nativeaddress              (system_0_burst_25_downstream_nativeaddress),
      .system_0_burst_25_downstream_qualified_request_noteF_s1 (system_0_burst_25_downstream_qualified_request_noteF_s1),
      .system_0_burst_25_downstream_read                       (system_0_burst_25_downstream_read),
      .system_0_burst_25_downstream_read_data_valid_noteF_s1   (system_0_burst_25_downstream_read_data_valid_noteF_s1),
      .system_0_burst_25_downstream_requests_noteF_s1          (system_0_burst_25_downstream_requests_noteF_s1),
      .system_0_burst_25_downstream_write                      (system_0_burst_25_downstream_write)
    );

  noteF the_noteF
    (
      .address  (noteF_s1_address),
      .clk      (altpll_0_c1_out),
      .in_port  (in_port_to_the_noteF),
      .readdata (noteF_s1_readdata),
      .reset_n  (noteF_s1_reset_n)
    );

  noteG_s1_arbitrator the_noteG_s1
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_noteG_s1_end_xfer                                    (d1_noteG_s1_end_xfer),
      .noteG_s1_address                                        (noteG_s1_address),
      .noteG_s1_readdata                                       (noteG_s1_readdata),
      .noteG_s1_readdata_from_sa                               (noteG_s1_readdata_from_sa),
      .noteG_s1_reset_n                                        (noteG_s1_reset_n),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_26_downstream_address_to_slave           (system_0_burst_26_downstream_address_to_slave),
      .system_0_burst_26_downstream_arbitrationshare           (system_0_burst_26_downstream_arbitrationshare),
      .system_0_burst_26_downstream_burstcount                 (system_0_burst_26_downstream_burstcount),
      .system_0_burst_26_downstream_granted_noteG_s1           (system_0_burst_26_downstream_granted_noteG_s1),
      .system_0_burst_26_downstream_latency_counter            (system_0_burst_26_downstream_latency_counter),
      .system_0_burst_26_downstream_nativeaddress              (system_0_burst_26_downstream_nativeaddress),
      .system_0_burst_26_downstream_qualified_request_noteG_s1 (system_0_burst_26_downstream_qualified_request_noteG_s1),
      .system_0_burst_26_downstream_read                       (system_0_burst_26_downstream_read),
      .system_0_burst_26_downstream_read_data_valid_noteG_s1   (system_0_burst_26_downstream_read_data_valid_noteG_s1),
      .system_0_burst_26_downstream_requests_noteG_s1          (system_0_burst_26_downstream_requests_noteG_s1),
      .system_0_burst_26_downstream_write                      (system_0_burst_26_downstream_write)
    );

  noteG the_noteG
    (
      .address  (noteG_s1_address),
      .clk      (altpll_0_c1_out),
      .in_port  (in_port_to_the_noteG),
      .readdata (noteG_s1_readdata),
      .reset_n  (noteG_s1_reset_n)
    );

  sdram_0_s1_arbitrator the_sdram_0_s1
    (
      .clk                                                                   (altpll_0_c1_out),
      .d1_sdram_0_s1_end_xfer                                                (d1_sdram_0_s1_end_xfer),
      .reset_n                                                               (altpll_0_c1_out_reset_n),
      .sdram_0_s1_address                                                    (sdram_0_s1_address),
      .sdram_0_s1_byteenable_n                                               (sdram_0_s1_byteenable_n),
      .sdram_0_s1_chipselect                                                 (sdram_0_s1_chipselect),
      .sdram_0_s1_read_n                                                     (sdram_0_s1_read_n),
      .sdram_0_s1_readdata                                                   (sdram_0_s1_readdata),
      .sdram_0_s1_readdata_from_sa                                           (sdram_0_s1_readdata_from_sa),
      .sdram_0_s1_readdatavalid                                              (sdram_0_s1_readdatavalid),
      .sdram_0_s1_reset_n                                                    (sdram_0_s1_reset_n),
      .sdram_0_s1_waitrequest                                                (sdram_0_s1_waitrequest),
      .sdram_0_s1_waitrequest_from_sa                                        (sdram_0_s1_waitrequest_from_sa),
      .sdram_0_s1_write_n                                                    (sdram_0_s1_write_n),
      .sdram_0_s1_writedata                                                  (sdram_0_s1_writedata),
      .system_0_burst_4_downstream_address_to_slave                          (system_0_burst_4_downstream_address_to_slave),
      .system_0_burst_4_downstream_arbitrationshare                          (system_0_burst_4_downstream_arbitrationshare),
      .system_0_burst_4_downstream_burstcount                                (system_0_burst_4_downstream_burstcount),
      .system_0_burst_4_downstream_byteenable                                (system_0_burst_4_downstream_byteenable),
      .system_0_burst_4_downstream_granted_sdram_0_s1                        (system_0_burst_4_downstream_granted_sdram_0_s1),
      .system_0_burst_4_downstream_latency_counter                           (system_0_burst_4_downstream_latency_counter),
      .system_0_burst_4_downstream_qualified_request_sdram_0_s1              (system_0_burst_4_downstream_qualified_request_sdram_0_s1),
      .system_0_burst_4_downstream_read                                      (system_0_burst_4_downstream_read),
      .system_0_burst_4_downstream_read_data_valid_sdram_0_s1                (system_0_burst_4_downstream_read_data_valid_sdram_0_s1),
      .system_0_burst_4_downstream_read_data_valid_sdram_0_s1_shift_register (system_0_burst_4_downstream_read_data_valid_sdram_0_s1_shift_register),
      .system_0_burst_4_downstream_requests_sdram_0_s1                       (system_0_burst_4_downstream_requests_sdram_0_s1),
      .system_0_burst_4_downstream_write                                     (system_0_burst_4_downstream_write),
      .system_0_burst_4_downstream_writedata                                 (system_0_burst_4_downstream_writedata),
      .system_0_burst_5_downstream_address_to_slave                          (system_0_burst_5_downstream_address_to_slave),
      .system_0_burst_5_downstream_arbitrationshare                          (system_0_burst_5_downstream_arbitrationshare),
      .system_0_burst_5_downstream_burstcount                                (system_0_burst_5_downstream_burstcount),
      .system_0_burst_5_downstream_byteenable                                (system_0_burst_5_downstream_byteenable),
      .system_0_burst_5_downstream_granted_sdram_0_s1                        (system_0_burst_5_downstream_granted_sdram_0_s1),
      .system_0_burst_5_downstream_latency_counter                           (system_0_burst_5_downstream_latency_counter),
      .system_0_burst_5_downstream_qualified_request_sdram_0_s1              (system_0_burst_5_downstream_qualified_request_sdram_0_s1),
      .system_0_burst_5_downstream_read                                      (system_0_burst_5_downstream_read),
      .system_0_burst_5_downstream_read_data_valid_sdram_0_s1                (system_0_burst_5_downstream_read_data_valid_sdram_0_s1),
      .system_0_burst_5_downstream_read_data_valid_sdram_0_s1_shift_register (system_0_burst_5_downstream_read_data_valid_sdram_0_s1_shift_register),
      .system_0_burst_5_downstream_requests_sdram_0_s1                       (system_0_burst_5_downstream_requests_sdram_0_s1),
      .system_0_burst_5_downstream_write                                     (system_0_burst_5_downstream_write),
      .system_0_burst_5_downstream_writedata                                 (system_0_burst_5_downstream_writedata)
    );

  sdram_0 the_sdram_0
    (
      .az_addr        (sdram_0_s1_address),
      .az_be_n        (sdram_0_s1_byteenable_n),
      .az_cs          (sdram_0_s1_chipselect),
      .az_data        (sdram_0_s1_writedata),
      .az_rd_n        (sdram_0_s1_read_n),
      .az_wr_n        (sdram_0_s1_write_n),
      .clk            (altpll_0_c1_out),
      .reset_n        (sdram_0_s1_reset_n),
      .za_data        (sdram_0_s1_readdata),
      .za_valid       (sdram_0_s1_readdatavalid),
      .za_waitrequest (sdram_0_s1_waitrequest),
      .zs_addr        (zs_addr_from_the_sdram_0),
      .zs_ba          (zs_ba_from_the_sdram_0),
      .zs_cas_n       (zs_cas_n_from_the_sdram_0),
      .zs_cke         (zs_cke_from_the_sdram_0),
      .zs_cs_n        (zs_cs_n_from_the_sdram_0),
      .zs_dq          (zs_dq_to_and_from_the_sdram_0),
      .zs_dqm         (zs_dqm_from_the_sdram_0),
      .zs_ras_n       (zs_ras_n_from_the_sdram_0),
      .zs_we_n        (zs_we_n_from_the_sdram_0)
    );

  sram_0_avalon_slave_0_arbitrator the_sram_0_avalon_slave_0
    (
      .clk                                                                  (altpll_0_c1_out),
      .d1_sram_0_avalon_slave_0_end_xfer                                    (d1_sram_0_avalon_slave_0_end_xfer),
      .reset_n                                                              (altpll_0_c1_out_reset_n),
      .sram_0_avalon_slave_0_address                                        (sram_0_avalon_slave_0_address),
      .sram_0_avalon_slave_0_byteenable_n                                   (sram_0_avalon_slave_0_byteenable_n),
      .sram_0_avalon_slave_0_chipselect_n                                   (sram_0_avalon_slave_0_chipselect_n),
      .sram_0_avalon_slave_0_read_n                                         (sram_0_avalon_slave_0_read_n),
      .sram_0_avalon_slave_0_readdata                                       (sram_0_avalon_slave_0_readdata),
      .sram_0_avalon_slave_0_readdata_from_sa                               (sram_0_avalon_slave_0_readdata_from_sa),
      .sram_0_avalon_slave_0_wait_counter_eq_0                              (sram_0_avalon_slave_0_wait_counter_eq_0),
      .sram_0_avalon_slave_0_write_n                                        (sram_0_avalon_slave_0_write_n),
      .sram_0_avalon_slave_0_writedata                                      (sram_0_avalon_slave_0_writedata),
      .system_0_burst_14_downstream_address_to_slave                        (system_0_burst_14_downstream_address_to_slave),
      .system_0_burst_14_downstream_arbitrationshare                        (system_0_burst_14_downstream_arbitrationshare),
      .system_0_burst_14_downstream_burstcount                              (system_0_burst_14_downstream_burstcount),
      .system_0_burst_14_downstream_byteenable                              (system_0_burst_14_downstream_byteenable),
      .system_0_burst_14_downstream_granted_sram_0_avalon_slave_0           (system_0_burst_14_downstream_granted_sram_0_avalon_slave_0),
      .system_0_burst_14_downstream_latency_counter                         (system_0_burst_14_downstream_latency_counter),
      .system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0 (system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0),
      .system_0_burst_14_downstream_read                                    (system_0_burst_14_downstream_read),
      .system_0_burst_14_downstream_read_data_valid_sram_0_avalon_slave_0   (system_0_burst_14_downstream_read_data_valid_sram_0_avalon_slave_0),
      .system_0_burst_14_downstream_requests_sram_0_avalon_slave_0          (system_0_burst_14_downstream_requests_sram_0_avalon_slave_0),
      .system_0_burst_14_downstream_write                                   (system_0_burst_14_downstream_write),
      .system_0_burst_14_downstream_writedata                               (system_0_burst_14_downstream_writedata),
      .system_0_burst_15_downstream_address_to_slave                        (system_0_burst_15_downstream_address_to_slave),
      .system_0_burst_15_downstream_arbitrationshare                        (system_0_burst_15_downstream_arbitrationshare),
      .system_0_burst_15_downstream_burstcount                              (system_0_burst_15_downstream_burstcount),
      .system_0_burst_15_downstream_byteenable                              (system_0_burst_15_downstream_byteenable),
      .system_0_burst_15_downstream_granted_sram_0_avalon_slave_0           (system_0_burst_15_downstream_granted_sram_0_avalon_slave_0),
      .system_0_burst_15_downstream_latency_counter                         (system_0_burst_15_downstream_latency_counter),
      .system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0 (system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0),
      .system_0_burst_15_downstream_read                                    (system_0_burst_15_downstream_read),
      .system_0_burst_15_downstream_read_data_valid_sram_0_avalon_slave_0   (system_0_burst_15_downstream_read_data_valid_sram_0_avalon_slave_0),
      .system_0_burst_15_downstream_requests_sram_0_avalon_slave_0          (system_0_burst_15_downstream_requests_sram_0_avalon_slave_0),
      .system_0_burst_15_downstream_write                                   (system_0_burst_15_downstream_write),
      .system_0_burst_15_downstream_writedata                               (system_0_burst_15_downstream_writedata)
    );

  sram_0 the_sram_0
    (
      .SRAM_ADDR (SRAM_ADDR_from_the_sram_0),
      .SRAM_CE_N (SRAM_CE_N_from_the_sram_0),
      .SRAM_DQ   (SRAM_DQ_to_and_from_the_sram_0),
      .SRAM_LB_N (SRAM_LB_N_from_the_sram_0),
      .SRAM_OE_N (SRAM_OE_N_from_the_sram_0),
      .SRAM_UB_N (SRAM_UB_N_from_the_sram_0),
      .SRAM_WE_N (SRAM_WE_N_from_the_sram_0),
      .iADDR     (sram_0_avalon_slave_0_address),
      .iBE_N     (sram_0_avalon_slave_0_byteenable_n),
      .iCE_N     (sram_0_avalon_slave_0_chipselect_n),
      .iCLK      (altpll_0_c1_out),
      .iDATA     (sram_0_avalon_slave_0_writedata),
      .iOE_N     (sram_0_avalon_slave_0_read_n),
      .iWE_N     (sram_0_avalon_slave_0_write_n),
      .oDATA     (sram_0_avalon_slave_0_readdata)
    );

  system_0_burst_0_upstream_arbitrator the_system_0_burst_0_upstream
    (
      .clk                                                                                (altpll_0_c1_out),
      .cpu_0_instruction_master_address_to_slave                                          (cpu_0_instruction_master_address_to_slave),
      .cpu_0_instruction_master_burstcount                                                (cpu_0_instruction_master_burstcount),
      .cpu_0_instruction_master_granted_system_0_burst_0_upstream                         (cpu_0_instruction_master_granted_system_0_burst_0_upstream),
      .cpu_0_instruction_master_latency_counter                                           (cpu_0_instruction_master_latency_counter),
      .cpu_0_instruction_master_qualified_request_system_0_burst_0_upstream               (cpu_0_instruction_master_qualified_request_system_0_burst_0_upstream),
      .cpu_0_instruction_master_read                                                      (cpu_0_instruction_master_read),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream                 (cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register (cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register (cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register),
      .cpu_0_instruction_master_requests_system_0_burst_0_upstream                        (cpu_0_instruction_master_requests_system_0_burst_0_upstream),
      .d1_system_0_burst_0_upstream_end_xfer                                              (d1_system_0_burst_0_upstream_end_xfer),
      .reset_n                                                                            (altpll_0_c1_out_reset_n),
      .system_0_burst_0_upstream_address                                                  (system_0_burst_0_upstream_address),
      .system_0_burst_0_upstream_byteaddress                                              (system_0_burst_0_upstream_byteaddress),
      .system_0_burst_0_upstream_byteenable                                               (system_0_burst_0_upstream_byteenable),
      .system_0_burst_0_upstream_debugaccess                                              (system_0_burst_0_upstream_debugaccess),
      .system_0_burst_0_upstream_read                                                     (system_0_burst_0_upstream_read),
      .system_0_burst_0_upstream_readdata                                                 (system_0_burst_0_upstream_readdata),
      .system_0_burst_0_upstream_readdata_from_sa                                         (system_0_burst_0_upstream_readdata_from_sa),
      .system_0_burst_0_upstream_readdatavalid                                            (system_0_burst_0_upstream_readdatavalid),
      .system_0_burst_0_upstream_waitrequest                                              (system_0_burst_0_upstream_waitrequest),
      .system_0_burst_0_upstream_waitrequest_from_sa                                      (system_0_burst_0_upstream_waitrequest_from_sa),
      .system_0_burst_0_upstream_write                                                    (system_0_burst_0_upstream_write)
    );

  system_0_burst_0_downstream_arbitrator the_system_0_burst_0_downstream
    (
      .clk                                                                   (altpll_0_c1_out),
      .cpu_0_jtag_debug_module_readdata_from_sa                              (cpu_0_jtag_debug_module_readdata_from_sa),
      .d1_cpu_0_jtag_debug_module_end_xfer                                   (d1_cpu_0_jtag_debug_module_end_xfer),
      .reset_n                                                               (altpll_0_c1_out_reset_n),
      .system_0_burst_0_downstream_address                                   (system_0_burst_0_downstream_address),
      .system_0_burst_0_downstream_address_to_slave                          (system_0_burst_0_downstream_address_to_slave),
      .system_0_burst_0_downstream_burstcount                                (system_0_burst_0_downstream_burstcount),
      .system_0_burst_0_downstream_byteenable                                (system_0_burst_0_downstream_byteenable),
      .system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module           (system_0_burst_0_downstream_granted_cpu_0_jtag_debug_module),
      .system_0_burst_0_downstream_latency_counter                           (system_0_burst_0_downstream_latency_counter),
      .system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module (system_0_burst_0_downstream_qualified_request_cpu_0_jtag_debug_module),
      .system_0_burst_0_downstream_read                                      (system_0_burst_0_downstream_read),
      .system_0_burst_0_downstream_read_data_valid_cpu_0_jtag_debug_module   (system_0_burst_0_downstream_read_data_valid_cpu_0_jtag_debug_module),
      .system_0_burst_0_downstream_readdata                                  (system_0_burst_0_downstream_readdata),
      .system_0_burst_0_downstream_readdatavalid                             (system_0_burst_0_downstream_readdatavalid),
      .system_0_burst_0_downstream_requests_cpu_0_jtag_debug_module          (system_0_burst_0_downstream_requests_cpu_0_jtag_debug_module),
      .system_0_burst_0_downstream_reset_n                                   (system_0_burst_0_downstream_reset_n),
      .system_0_burst_0_downstream_waitrequest                               (system_0_burst_0_downstream_waitrequest),
      .system_0_burst_0_downstream_write                                     (system_0_burst_0_downstream_write),
      .system_0_burst_0_downstream_writedata                                 (system_0_burst_0_downstream_writedata)
    );

  system_0_burst_0 the_system_0_burst_0
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_0_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_0_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_0_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_0_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_0_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_0_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_0_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_0_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_0_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_0_downstream_read),
      .reg_downstream_write            (system_0_burst_0_downstream_write),
      .reg_downstream_writedata        (system_0_burst_0_downstream_writedata),
      .reset_n                         (system_0_burst_0_downstream_reset_n),
      .upstream_address                (system_0_burst_0_upstream_byteaddress),
      .upstream_byteenable             (system_0_burst_0_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_0_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_0_upstream_address),
      .upstream_read                   (system_0_burst_0_upstream_read),
      .upstream_readdata               (system_0_burst_0_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_0_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_0_upstream_waitrequest),
      .upstream_write                  (system_0_burst_0_upstream_write),
      .upstream_writedata              (system_0_burst_0_upstream_writedata)
    );

  system_0_burst_1_upstream_arbitrator the_system_0_burst_1_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_1_upstream                         (cpu_0_data_master_granted_system_0_burst_1_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_1_upstream               (cpu_0_data_master_qualified_request_system_0_burst_1_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream                 (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_1_upstream                        (cpu_0_data_master_requests_system_0_burst_1_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_1_upstream_end_xfer                                       (d1_system_0_burst_1_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_1_upstream_address                                           (system_0_burst_1_upstream_address),
      .system_0_burst_1_upstream_burstcount                                        (system_0_burst_1_upstream_burstcount),
      .system_0_burst_1_upstream_byteaddress                                       (system_0_burst_1_upstream_byteaddress),
      .system_0_burst_1_upstream_byteenable                                        (system_0_burst_1_upstream_byteenable),
      .system_0_burst_1_upstream_debugaccess                                       (system_0_burst_1_upstream_debugaccess),
      .system_0_burst_1_upstream_read                                              (system_0_burst_1_upstream_read),
      .system_0_burst_1_upstream_readdata                                          (system_0_burst_1_upstream_readdata),
      .system_0_burst_1_upstream_readdata_from_sa                                  (system_0_burst_1_upstream_readdata_from_sa),
      .system_0_burst_1_upstream_readdatavalid                                     (system_0_burst_1_upstream_readdatavalid),
      .system_0_burst_1_upstream_waitrequest                                       (system_0_burst_1_upstream_waitrequest),
      .system_0_burst_1_upstream_waitrequest_from_sa                               (system_0_burst_1_upstream_waitrequest_from_sa),
      .system_0_burst_1_upstream_write                                             (system_0_burst_1_upstream_write),
      .system_0_burst_1_upstream_writedata                                         (system_0_burst_1_upstream_writedata)
    );

  system_0_burst_1_downstream_arbitrator the_system_0_burst_1_downstream
    (
      .clk                                                                   (altpll_0_c1_out),
      .cpu_0_jtag_debug_module_readdata_from_sa                              (cpu_0_jtag_debug_module_readdata_from_sa),
      .d1_cpu_0_jtag_debug_module_end_xfer                                   (d1_cpu_0_jtag_debug_module_end_xfer),
      .reset_n                                                               (altpll_0_c1_out_reset_n),
      .system_0_burst_1_downstream_address                                   (system_0_burst_1_downstream_address),
      .system_0_burst_1_downstream_address_to_slave                          (system_0_burst_1_downstream_address_to_slave),
      .system_0_burst_1_downstream_burstcount                                (system_0_burst_1_downstream_burstcount),
      .system_0_burst_1_downstream_byteenable                                (system_0_burst_1_downstream_byteenable),
      .system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module           (system_0_burst_1_downstream_granted_cpu_0_jtag_debug_module),
      .system_0_burst_1_downstream_latency_counter                           (system_0_burst_1_downstream_latency_counter),
      .system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module (system_0_burst_1_downstream_qualified_request_cpu_0_jtag_debug_module),
      .system_0_burst_1_downstream_read                                      (system_0_burst_1_downstream_read),
      .system_0_burst_1_downstream_read_data_valid_cpu_0_jtag_debug_module   (system_0_burst_1_downstream_read_data_valid_cpu_0_jtag_debug_module),
      .system_0_burst_1_downstream_readdata                                  (system_0_burst_1_downstream_readdata),
      .system_0_burst_1_downstream_readdatavalid                             (system_0_burst_1_downstream_readdatavalid),
      .system_0_burst_1_downstream_requests_cpu_0_jtag_debug_module          (system_0_burst_1_downstream_requests_cpu_0_jtag_debug_module),
      .system_0_burst_1_downstream_reset_n                                   (system_0_burst_1_downstream_reset_n),
      .system_0_burst_1_downstream_waitrequest                               (system_0_burst_1_downstream_waitrequest),
      .system_0_burst_1_downstream_write                                     (system_0_burst_1_downstream_write),
      .system_0_burst_1_downstream_writedata                                 (system_0_burst_1_downstream_writedata)
    );

  system_0_burst_1 the_system_0_burst_1
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_1_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_1_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_1_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_1_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_1_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_1_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_1_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_1_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_1_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_1_downstream_read),
      .reg_downstream_write            (system_0_burst_1_downstream_write),
      .reg_downstream_writedata        (system_0_burst_1_downstream_writedata),
      .reset_n                         (system_0_burst_1_downstream_reset_n),
      .upstream_address                (system_0_burst_1_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_1_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_1_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_1_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_1_upstream_address),
      .upstream_read                   (system_0_burst_1_upstream_read),
      .upstream_readdata               (system_0_burst_1_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_1_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_1_upstream_waitrequest),
      .upstream_write                  (system_0_burst_1_upstream_write),
      .upstream_writedata              (system_0_burst_1_upstream_writedata)
    );

  system_0_burst_10_upstream_arbitrator the_system_0_burst_10_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_10_upstream                        (cpu_0_data_master_granted_system_0_burst_10_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_10_upstream              (cpu_0_data_master_qualified_request_system_0_burst_10_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_10_upstream                       (cpu_0_data_master_requests_system_0_burst_10_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_10_upstream_end_xfer                                      (d1_system_0_burst_10_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_10_upstream_address                                          (system_0_burst_10_upstream_address),
      .system_0_burst_10_upstream_burstcount                                       (system_0_burst_10_upstream_burstcount),
      .system_0_burst_10_upstream_byteaddress                                      (system_0_burst_10_upstream_byteaddress),
      .system_0_burst_10_upstream_byteenable                                       (system_0_burst_10_upstream_byteenable),
      .system_0_burst_10_upstream_debugaccess                                      (system_0_burst_10_upstream_debugaccess),
      .system_0_burst_10_upstream_read                                             (system_0_burst_10_upstream_read),
      .system_0_burst_10_upstream_readdata                                         (system_0_burst_10_upstream_readdata),
      .system_0_burst_10_upstream_readdata_from_sa                                 (system_0_burst_10_upstream_readdata_from_sa),
      .system_0_burst_10_upstream_readdatavalid                                    (system_0_burst_10_upstream_readdatavalid),
      .system_0_burst_10_upstream_waitrequest                                      (system_0_burst_10_upstream_waitrequest),
      .system_0_burst_10_upstream_waitrequest_from_sa                              (system_0_burst_10_upstream_waitrequest_from_sa),
      .system_0_burst_10_upstream_write                                            (system_0_burst_10_upstream_write),
      .system_0_burst_10_upstream_writedata                                        (system_0_burst_10_upstream_writedata)
    );

  system_0_burst_10_downstream_arbitrator the_system_0_burst_10_downstream
    (
      .clk                                                       (altpll_0_c1_out),
      .d1_timer_0_s1_end_xfer                                    (d1_timer_0_s1_end_xfer),
      .reset_n                                                   (altpll_0_c1_out_reset_n),
      .system_0_burst_10_downstream_address                      (system_0_burst_10_downstream_address),
      .system_0_burst_10_downstream_address_to_slave             (system_0_burst_10_downstream_address_to_slave),
      .system_0_burst_10_downstream_burstcount                   (system_0_burst_10_downstream_burstcount),
      .system_0_burst_10_downstream_byteenable                   (system_0_burst_10_downstream_byteenable),
      .system_0_burst_10_downstream_granted_timer_0_s1           (system_0_burst_10_downstream_granted_timer_0_s1),
      .system_0_burst_10_downstream_latency_counter              (system_0_burst_10_downstream_latency_counter),
      .system_0_burst_10_downstream_qualified_request_timer_0_s1 (system_0_burst_10_downstream_qualified_request_timer_0_s1),
      .system_0_burst_10_downstream_read                         (system_0_burst_10_downstream_read),
      .system_0_burst_10_downstream_read_data_valid_timer_0_s1   (system_0_burst_10_downstream_read_data_valid_timer_0_s1),
      .system_0_burst_10_downstream_readdata                     (system_0_burst_10_downstream_readdata),
      .system_0_burst_10_downstream_readdatavalid                (system_0_burst_10_downstream_readdatavalid),
      .system_0_burst_10_downstream_requests_timer_0_s1          (system_0_burst_10_downstream_requests_timer_0_s1),
      .system_0_burst_10_downstream_reset_n                      (system_0_burst_10_downstream_reset_n),
      .system_0_burst_10_downstream_waitrequest                  (system_0_burst_10_downstream_waitrequest),
      .system_0_burst_10_downstream_write                        (system_0_burst_10_downstream_write),
      .system_0_burst_10_downstream_writedata                    (system_0_burst_10_downstream_writedata),
      .timer_0_s1_readdata_from_sa                               (timer_0_s1_readdata_from_sa)
    );

  system_0_burst_10 the_system_0_burst_10
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_10_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_10_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_10_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_10_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_10_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_10_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_10_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_10_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_10_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_10_downstream_read),
      .reg_downstream_write            (system_0_burst_10_downstream_write),
      .reg_downstream_writedata        (system_0_burst_10_downstream_writedata),
      .reset_n                         (system_0_burst_10_downstream_reset_n),
      .upstream_address                (system_0_burst_10_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_10_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_10_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_10_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_10_upstream_address),
      .upstream_read                   (system_0_burst_10_upstream_read),
      .upstream_readdata               (system_0_burst_10_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_10_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_10_upstream_waitrequest),
      .upstream_write                  (system_0_burst_10_upstream_write),
      .upstream_writedata              (system_0_burst_10_upstream_writedata)
    );

  system_0_burst_11_upstream_arbitrator the_system_0_burst_11_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_11_upstream                        (cpu_0_data_master_granted_system_0_burst_11_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_11_upstream              (cpu_0_data_master_qualified_request_system_0_burst_11_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_11_upstream                       (cpu_0_data_master_requests_system_0_burst_11_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_11_upstream_end_xfer                                      (d1_system_0_burst_11_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_11_upstream_address                                          (system_0_burst_11_upstream_address),
      .system_0_burst_11_upstream_burstcount                                       (system_0_burst_11_upstream_burstcount),
      .system_0_burst_11_upstream_byteaddress                                      (system_0_burst_11_upstream_byteaddress),
      .system_0_burst_11_upstream_byteenable                                       (system_0_burst_11_upstream_byteenable),
      .system_0_burst_11_upstream_debugaccess                                      (system_0_burst_11_upstream_debugaccess),
      .system_0_burst_11_upstream_read                                             (system_0_burst_11_upstream_read),
      .system_0_burst_11_upstream_readdata                                         (system_0_burst_11_upstream_readdata),
      .system_0_burst_11_upstream_readdata_from_sa                                 (system_0_burst_11_upstream_readdata_from_sa),
      .system_0_burst_11_upstream_readdatavalid                                    (system_0_burst_11_upstream_readdatavalid),
      .system_0_burst_11_upstream_waitrequest                                      (system_0_burst_11_upstream_waitrequest),
      .system_0_burst_11_upstream_waitrequest_from_sa                              (system_0_burst_11_upstream_waitrequest_from_sa),
      .system_0_burst_11_upstream_write                                            (system_0_burst_11_upstream_write),
      .system_0_burst_11_upstream_writedata                                        (system_0_burst_11_upstream_writedata)
    );

  system_0_burst_11_downstream_arbitrator the_system_0_burst_11_downstream
    (
      .clk                                                       (altpll_0_c1_out),
      .d1_timer_1_s1_end_xfer                                    (d1_timer_1_s1_end_xfer),
      .reset_n                                                   (altpll_0_c1_out_reset_n),
      .system_0_burst_11_downstream_address                      (system_0_burst_11_downstream_address),
      .system_0_burst_11_downstream_address_to_slave             (system_0_burst_11_downstream_address_to_slave),
      .system_0_burst_11_downstream_burstcount                   (system_0_burst_11_downstream_burstcount),
      .system_0_burst_11_downstream_byteenable                   (system_0_burst_11_downstream_byteenable),
      .system_0_burst_11_downstream_granted_timer_1_s1           (system_0_burst_11_downstream_granted_timer_1_s1),
      .system_0_burst_11_downstream_latency_counter              (system_0_burst_11_downstream_latency_counter),
      .system_0_burst_11_downstream_qualified_request_timer_1_s1 (system_0_burst_11_downstream_qualified_request_timer_1_s1),
      .system_0_burst_11_downstream_read                         (system_0_burst_11_downstream_read),
      .system_0_burst_11_downstream_read_data_valid_timer_1_s1   (system_0_burst_11_downstream_read_data_valid_timer_1_s1),
      .system_0_burst_11_downstream_readdata                     (system_0_burst_11_downstream_readdata),
      .system_0_burst_11_downstream_readdatavalid                (system_0_burst_11_downstream_readdatavalid),
      .system_0_burst_11_downstream_requests_timer_1_s1          (system_0_burst_11_downstream_requests_timer_1_s1),
      .system_0_burst_11_downstream_reset_n                      (system_0_burst_11_downstream_reset_n),
      .system_0_burst_11_downstream_waitrequest                  (system_0_burst_11_downstream_waitrequest),
      .system_0_burst_11_downstream_write                        (system_0_burst_11_downstream_write),
      .system_0_burst_11_downstream_writedata                    (system_0_burst_11_downstream_writedata),
      .timer_1_s1_readdata_from_sa                               (timer_1_s1_readdata_from_sa)
    );

  system_0_burst_11 the_system_0_burst_11
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_11_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_11_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_11_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_11_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_11_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_11_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_11_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_11_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_11_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_11_downstream_read),
      .reg_downstream_write            (system_0_burst_11_downstream_write),
      .reg_downstream_writedata        (system_0_burst_11_downstream_writedata),
      .reset_n                         (system_0_burst_11_downstream_reset_n),
      .upstream_address                (system_0_burst_11_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_11_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_11_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_11_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_11_upstream_address),
      .upstream_read                   (system_0_burst_11_upstream_read),
      .upstream_readdata               (system_0_burst_11_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_11_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_11_upstream_waitrequest),
      .upstream_write                  (system_0_burst_11_upstream_write),
      .upstream_writedata              (system_0_burst_11_upstream_writedata)
    );

  system_0_burst_12_upstream_arbitrator the_system_0_burst_12_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_12_upstream                        (cpu_0_data_master_granted_system_0_burst_12_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_12_upstream              (cpu_0_data_master_qualified_request_system_0_burst_12_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_12_upstream                       (cpu_0_data_master_requests_system_0_burst_12_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_12_upstream_end_xfer                                      (d1_system_0_burst_12_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_12_upstream_address                                          (system_0_burst_12_upstream_address),
      .system_0_burst_12_upstream_burstcount                                       (system_0_burst_12_upstream_burstcount),
      .system_0_burst_12_upstream_byteaddress                                      (system_0_burst_12_upstream_byteaddress),
      .system_0_burst_12_upstream_byteenable                                       (system_0_burst_12_upstream_byteenable),
      .system_0_burst_12_upstream_debugaccess                                      (system_0_burst_12_upstream_debugaccess),
      .system_0_burst_12_upstream_read                                             (system_0_burst_12_upstream_read),
      .system_0_burst_12_upstream_readdata                                         (system_0_burst_12_upstream_readdata),
      .system_0_burst_12_upstream_readdata_from_sa                                 (system_0_burst_12_upstream_readdata_from_sa),
      .system_0_burst_12_upstream_readdatavalid                                    (system_0_burst_12_upstream_readdatavalid),
      .system_0_burst_12_upstream_waitrequest                                      (system_0_burst_12_upstream_waitrequest),
      .system_0_burst_12_upstream_waitrequest_from_sa                              (system_0_burst_12_upstream_waitrequest_from_sa),
      .system_0_burst_12_upstream_write                                            (system_0_burst_12_upstream_write),
      .system_0_burst_12_upstream_writedata                                        (system_0_burst_12_upstream_writedata)
    );

  system_0_burst_12_downstream_arbitrator the_system_0_burst_12_downstream
    (
      .clk                                                                      (altpll_0_c1_out),
      .d1_lcd_16207_0_control_slave_end_xfer                                    (d1_lcd_16207_0_control_slave_end_xfer),
      .lcd_16207_0_control_slave_readdata_from_sa                               (lcd_16207_0_control_slave_readdata_from_sa),
      .lcd_16207_0_control_slave_wait_counter_eq_0                              (lcd_16207_0_control_slave_wait_counter_eq_0),
      .reset_n                                                                  (altpll_0_c1_out_reset_n),
      .system_0_burst_12_downstream_address                                     (system_0_burst_12_downstream_address),
      .system_0_burst_12_downstream_address_to_slave                            (system_0_burst_12_downstream_address_to_slave),
      .system_0_burst_12_downstream_burstcount                                  (system_0_burst_12_downstream_burstcount),
      .system_0_burst_12_downstream_byteenable                                  (system_0_burst_12_downstream_byteenable),
      .system_0_burst_12_downstream_granted_lcd_16207_0_control_slave           (system_0_burst_12_downstream_granted_lcd_16207_0_control_slave),
      .system_0_burst_12_downstream_latency_counter                             (system_0_burst_12_downstream_latency_counter),
      .system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave (system_0_burst_12_downstream_qualified_request_lcd_16207_0_control_slave),
      .system_0_burst_12_downstream_read                                        (system_0_burst_12_downstream_read),
      .system_0_burst_12_downstream_read_data_valid_lcd_16207_0_control_slave   (system_0_burst_12_downstream_read_data_valid_lcd_16207_0_control_slave),
      .system_0_burst_12_downstream_readdata                                    (system_0_burst_12_downstream_readdata),
      .system_0_burst_12_downstream_readdatavalid                               (system_0_burst_12_downstream_readdatavalid),
      .system_0_burst_12_downstream_requests_lcd_16207_0_control_slave          (system_0_burst_12_downstream_requests_lcd_16207_0_control_slave),
      .system_0_burst_12_downstream_reset_n                                     (system_0_burst_12_downstream_reset_n),
      .system_0_burst_12_downstream_waitrequest                                 (system_0_burst_12_downstream_waitrequest),
      .system_0_burst_12_downstream_write                                       (system_0_burst_12_downstream_write),
      .system_0_burst_12_downstream_writedata                                   (system_0_burst_12_downstream_writedata)
    );

  system_0_burst_12 the_system_0_burst_12
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_12_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_12_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_12_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_12_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_12_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_12_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_12_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_12_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_12_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_12_downstream_read),
      .reg_downstream_write            (system_0_burst_12_downstream_write),
      .reg_downstream_writedata        (system_0_burst_12_downstream_writedata),
      .reset_n                         (system_0_burst_12_downstream_reset_n),
      .upstream_address                (system_0_burst_12_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_12_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_12_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_12_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_12_upstream_address),
      .upstream_read                   (system_0_burst_12_upstream_read),
      .upstream_readdata               (system_0_burst_12_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_12_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_12_upstream_waitrequest),
      .upstream_write                  (system_0_burst_12_upstream_write),
      .upstream_writedata              (system_0_burst_12_upstream_writedata)
    );

  system_0_burst_13_upstream_arbitrator the_system_0_burst_13_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_13_upstream                        (cpu_0_data_master_granted_system_0_burst_13_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_13_upstream              (cpu_0_data_master_qualified_request_system_0_burst_13_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_13_upstream                       (cpu_0_data_master_requests_system_0_burst_13_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_13_upstream_end_xfer                                      (d1_system_0_burst_13_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_13_upstream_address                                          (system_0_burst_13_upstream_address),
      .system_0_burst_13_upstream_burstcount                                       (system_0_burst_13_upstream_burstcount),
      .system_0_burst_13_upstream_byteaddress                                      (system_0_burst_13_upstream_byteaddress),
      .system_0_burst_13_upstream_byteenable                                       (system_0_burst_13_upstream_byteenable),
      .system_0_burst_13_upstream_debugaccess                                      (system_0_burst_13_upstream_debugaccess),
      .system_0_burst_13_upstream_read                                             (system_0_burst_13_upstream_read),
      .system_0_burst_13_upstream_readdata                                         (system_0_burst_13_upstream_readdata),
      .system_0_burst_13_upstream_readdata_from_sa                                 (system_0_burst_13_upstream_readdata_from_sa),
      .system_0_burst_13_upstream_readdatavalid                                    (system_0_burst_13_upstream_readdatavalid),
      .system_0_burst_13_upstream_waitrequest                                      (system_0_burst_13_upstream_waitrequest),
      .system_0_burst_13_upstream_waitrequest_from_sa                              (system_0_burst_13_upstream_waitrequest_from_sa),
      .system_0_burst_13_upstream_write                                            (system_0_burst_13_upstream_write),
      .system_0_burst_13_upstream_writedata                                        (system_0_burst_13_upstream_writedata)
    );

  system_0_burst_13_downstream_arbitrator the_system_0_burst_13_downstream
    (
      .clk                                                                        (altpll_0_c1_out),
      .d1_SEG7_Display_avalon_slave_0_end_xfer                                    (d1_SEG7_Display_avalon_slave_0_end_xfer),
      .reset_n                                                                    (altpll_0_c1_out_reset_n),
      .system_0_burst_13_downstream_address                                       (system_0_burst_13_downstream_address),
      .system_0_burst_13_downstream_address_to_slave                              (system_0_burst_13_downstream_address_to_slave),
      .system_0_burst_13_downstream_burstcount                                    (system_0_burst_13_downstream_burstcount),
      .system_0_burst_13_downstream_byteenable                                    (system_0_burst_13_downstream_byteenable),
      .system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0           (system_0_burst_13_downstream_granted_SEG7_Display_avalon_slave_0),
      .system_0_burst_13_downstream_latency_counter                               (system_0_burst_13_downstream_latency_counter),
      .system_0_burst_13_downstream_qualified_request_SEG7_Display_avalon_slave_0 (system_0_burst_13_downstream_qualified_request_SEG7_Display_avalon_slave_0),
      .system_0_burst_13_downstream_read                                          (system_0_burst_13_downstream_read),
      .system_0_burst_13_downstream_read_data_valid_SEG7_Display_avalon_slave_0   (system_0_burst_13_downstream_read_data_valid_SEG7_Display_avalon_slave_0),
      .system_0_burst_13_downstream_readdata                                      (system_0_burst_13_downstream_readdata),
      .system_0_burst_13_downstream_readdatavalid                                 (system_0_burst_13_downstream_readdatavalid),
      .system_0_burst_13_downstream_requests_SEG7_Display_avalon_slave_0          (system_0_burst_13_downstream_requests_SEG7_Display_avalon_slave_0),
      .system_0_burst_13_downstream_reset_n                                       (system_0_burst_13_downstream_reset_n),
      .system_0_burst_13_downstream_waitrequest                                   (system_0_burst_13_downstream_waitrequest),
      .system_0_burst_13_downstream_write                                         (system_0_burst_13_downstream_write),
      .system_0_burst_13_downstream_writedata                                     (system_0_burst_13_downstream_writedata)
    );

  system_0_burst_13 the_system_0_burst_13
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_13_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_13_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_13_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_13_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_13_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_13_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_13_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_13_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_13_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_13_downstream_read),
      .reg_downstream_write            (system_0_burst_13_downstream_write),
      .reg_downstream_writedata        (system_0_burst_13_downstream_writedata),
      .reset_n                         (system_0_burst_13_downstream_reset_n),
      .upstream_address                (system_0_burst_13_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_13_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_13_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_13_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_13_upstream_address),
      .upstream_read                   (system_0_burst_13_upstream_read),
      .upstream_readdata               (system_0_burst_13_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_13_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_13_upstream_waitrequest),
      .upstream_write                  (system_0_burst_13_upstream_write),
      .upstream_writedata              (system_0_burst_13_upstream_writedata)
    );

  system_0_burst_14_upstream_arbitrator the_system_0_burst_14_upstream
    (
      .clk                                                                                (altpll_0_c1_out),
      .cpu_0_instruction_master_address_to_slave                                          (cpu_0_instruction_master_address_to_slave),
      .cpu_0_instruction_master_burstcount                                                (cpu_0_instruction_master_burstcount),
      .cpu_0_instruction_master_dbs_address                                               (cpu_0_instruction_master_dbs_address),
      .cpu_0_instruction_master_granted_system_0_burst_14_upstream                        (cpu_0_instruction_master_granted_system_0_burst_14_upstream),
      .cpu_0_instruction_master_latency_counter                                           (cpu_0_instruction_master_latency_counter),
      .cpu_0_instruction_master_qualified_request_system_0_burst_14_upstream              (cpu_0_instruction_master_qualified_request_system_0_burst_14_upstream),
      .cpu_0_instruction_master_read                                                      (cpu_0_instruction_master_read),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream                (cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register (cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register (cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register),
      .cpu_0_instruction_master_requests_system_0_burst_14_upstream                       (cpu_0_instruction_master_requests_system_0_burst_14_upstream),
      .d1_system_0_burst_14_upstream_end_xfer                                             (d1_system_0_burst_14_upstream_end_xfer),
      .reset_n                                                                            (altpll_0_c1_out_reset_n),
      .system_0_burst_14_upstream_address                                                 (system_0_burst_14_upstream_address),
      .system_0_burst_14_upstream_byteaddress                                             (system_0_burst_14_upstream_byteaddress),
      .system_0_burst_14_upstream_byteenable                                              (system_0_burst_14_upstream_byteenable),
      .system_0_burst_14_upstream_debugaccess                                             (system_0_burst_14_upstream_debugaccess),
      .system_0_burst_14_upstream_read                                                    (system_0_burst_14_upstream_read),
      .system_0_burst_14_upstream_readdata                                                (system_0_burst_14_upstream_readdata),
      .system_0_burst_14_upstream_readdata_from_sa                                        (system_0_burst_14_upstream_readdata_from_sa),
      .system_0_burst_14_upstream_readdatavalid                                           (system_0_burst_14_upstream_readdatavalid),
      .system_0_burst_14_upstream_waitrequest                                             (system_0_burst_14_upstream_waitrequest),
      .system_0_burst_14_upstream_waitrequest_from_sa                                     (system_0_burst_14_upstream_waitrequest_from_sa),
      .system_0_burst_14_upstream_write                                                   (system_0_burst_14_upstream_write)
    );

  system_0_burst_14_downstream_arbitrator the_system_0_burst_14_downstream
    (
      .clk                                                                  (altpll_0_c1_out),
      .d1_sram_0_avalon_slave_0_end_xfer                                    (d1_sram_0_avalon_slave_0_end_xfer),
      .reset_n                                                              (altpll_0_c1_out_reset_n),
      .sram_0_avalon_slave_0_readdata_from_sa                               (sram_0_avalon_slave_0_readdata_from_sa),
      .sram_0_avalon_slave_0_wait_counter_eq_0                              (sram_0_avalon_slave_0_wait_counter_eq_0),
      .system_0_burst_14_downstream_address                                 (system_0_burst_14_downstream_address),
      .system_0_burst_14_downstream_address_to_slave                        (system_0_burst_14_downstream_address_to_slave),
      .system_0_burst_14_downstream_burstcount                              (system_0_burst_14_downstream_burstcount),
      .system_0_burst_14_downstream_byteenable                              (system_0_burst_14_downstream_byteenable),
      .system_0_burst_14_downstream_granted_sram_0_avalon_slave_0           (system_0_burst_14_downstream_granted_sram_0_avalon_slave_0),
      .system_0_burst_14_downstream_latency_counter                         (system_0_burst_14_downstream_latency_counter),
      .system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0 (system_0_burst_14_downstream_qualified_request_sram_0_avalon_slave_0),
      .system_0_burst_14_downstream_read                                    (system_0_burst_14_downstream_read),
      .system_0_burst_14_downstream_read_data_valid_sram_0_avalon_slave_0   (system_0_burst_14_downstream_read_data_valid_sram_0_avalon_slave_0),
      .system_0_burst_14_downstream_readdata                                (system_0_burst_14_downstream_readdata),
      .system_0_burst_14_downstream_readdatavalid                           (system_0_burst_14_downstream_readdatavalid),
      .system_0_burst_14_downstream_requests_sram_0_avalon_slave_0          (system_0_burst_14_downstream_requests_sram_0_avalon_slave_0),
      .system_0_burst_14_downstream_reset_n                                 (system_0_burst_14_downstream_reset_n),
      .system_0_burst_14_downstream_waitrequest                             (system_0_burst_14_downstream_waitrequest),
      .system_0_burst_14_downstream_write                                   (system_0_burst_14_downstream_write),
      .system_0_burst_14_downstream_writedata                               (system_0_burst_14_downstream_writedata)
    );

  system_0_burst_14 the_system_0_burst_14
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_14_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_14_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_14_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_14_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_14_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_14_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_14_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_14_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_14_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_14_downstream_read),
      .reg_downstream_write            (system_0_burst_14_downstream_write),
      .reg_downstream_writedata        (system_0_burst_14_downstream_writedata),
      .reset_n                         (system_0_burst_14_downstream_reset_n),
      .upstream_address                (system_0_burst_14_upstream_byteaddress),
      .upstream_byteenable             (system_0_burst_14_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_14_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_14_upstream_address),
      .upstream_read                   (system_0_burst_14_upstream_read),
      .upstream_readdata               (system_0_burst_14_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_14_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_14_upstream_waitrequest),
      .upstream_write                  (system_0_burst_14_upstream_write),
      .upstream_writedata              (system_0_burst_14_upstream_writedata)
    );

  system_0_burst_15_upstream_arbitrator the_system_0_burst_15_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_byteenable_system_0_burst_15_upstream                     (cpu_0_data_master_byteenable_system_0_burst_15_upstream),
      .cpu_0_data_master_dbs_address                                               (cpu_0_data_master_dbs_address),
      .cpu_0_data_master_dbs_write_16                                              (cpu_0_data_master_dbs_write_16),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_15_upstream                        (cpu_0_data_master_granted_system_0_burst_15_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_15_upstream              (cpu_0_data_master_qualified_request_system_0_burst_15_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_15_upstream                       (cpu_0_data_master_requests_system_0_burst_15_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .d1_system_0_burst_15_upstream_end_xfer                                      (d1_system_0_burst_15_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_15_upstream_address                                          (system_0_burst_15_upstream_address),
      .system_0_burst_15_upstream_burstcount                                       (system_0_burst_15_upstream_burstcount),
      .system_0_burst_15_upstream_byteaddress                                      (system_0_burst_15_upstream_byteaddress),
      .system_0_burst_15_upstream_byteenable                                       (system_0_burst_15_upstream_byteenable),
      .system_0_burst_15_upstream_debugaccess                                      (system_0_burst_15_upstream_debugaccess),
      .system_0_burst_15_upstream_read                                             (system_0_burst_15_upstream_read),
      .system_0_burst_15_upstream_readdata                                         (system_0_burst_15_upstream_readdata),
      .system_0_burst_15_upstream_readdata_from_sa                                 (system_0_burst_15_upstream_readdata_from_sa),
      .system_0_burst_15_upstream_readdatavalid                                    (system_0_burst_15_upstream_readdatavalid),
      .system_0_burst_15_upstream_waitrequest                                      (system_0_burst_15_upstream_waitrequest),
      .system_0_burst_15_upstream_waitrequest_from_sa                              (system_0_burst_15_upstream_waitrequest_from_sa),
      .system_0_burst_15_upstream_write                                            (system_0_burst_15_upstream_write),
      .system_0_burst_15_upstream_writedata                                        (system_0_burst_15_upstream_writedata)
    );

  system_0_burst_15_downstream_arbitrator the_system_0_burst_15_downstream
    (
      .clk                                                                  (altpll_0_c1_out),
      .d1_sram_0_avalon_slave_0_end_xfer                                    (d1_sram_0_avalon_slave_0_end_xfer),
      .reset_n                                                              (altpll_0_c1_out_reset_n),
      .sram_0_avalon_slave_0_readdata_from_sa                               (sram_0_avalon_slave_0_readdata_from_sa),
      .sram_0_avalon_slave_0_wait_counter_eq_0                              (sram_0_avalon_slave_0_wait_counter_eq_0),
      .system_0_burst_15_downstream_address                                 (system_0_burst_15_downstream_address),
      .system_0_burst_15_downstream_address_to_slave                        (system_0_burst_15_downstream_address_to_slave),
      .system_0_burst_15_downstream_burstcount                              (system_0_burst_15_downstream_burstcount),
      .system_0_burst_15_downstream_byteenable                              (system_0_burst_15_downstream_byteenable),
      .system_0_burst_15_downstream_granted_sram_0_avalon_slave_0           (system_0_burst_15_downstream_granted_sram_0_avalon_slave_0),
      .system_0_burst_15_downstream_latency_counter                         (system_0_burst_15_downstream_latency_counter),
      .system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0 (system_0_burst_15_downstream_qualified_request_sram_0_avalon_slave_0),
      .system_0_burst_15_downstream_read                                    (system_0_burst_15_downstream_read),
      .system_0_burst_15_downstream_read_data_valid_sram_0_avalon_slave_0   (system_0_burst_15_downstream_read_data_valid_sram_0_avalon_slave_0),
      .system_0_burst_15_downstream_readdata                                (system_0_burst_15_downstream_readdata),
      .system_0_burst_15_downstream_readdatavalid                           (system_0_burst_15_downstream_readdatavalid),
      .system_0_burst_15_downstream_requests_sram_0_avalon_slave_0          (system_0_burst_15_downstream_requests_sram_0_avalon_slave_0),
      .system_0_burst_15_downstream_reset_n                                 (system_0_burst_15_downstream_reset_n),
      .system_0_burst_15_downstream_waitrequest                             (system_0_burst_15_downstream_waitrequest),
      .system_0_burst_15_downstream_write                                   (system_0_burst_15_downstream_write),
      .system_0_burst_15_downstream_writedata                               (system_0_burst_15_downstream_writedata)
    );

  system_0_burst_15 the_system_0_burst_15
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_15_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_15_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_15_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_15_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_15_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_15_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_15_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_15_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_15_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_15_downstream_read),
      .reg_downstream_write            (system_0_burst_15_downstream_write),
      .reg_downstream_writedata        (system_0_burst_15_downstream_writedata),
      .reset_n                         (system_0_burst_15_downstream_reset_n),
      .upstream_address                (system_0_burst_15_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_15_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_15_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_15_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_15_upstream_address),
      .upstream_read                   (system_0_burst_15_upstream_read),
      .upstream_readdata               (system_0_burst_15_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_15_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_15_upstream_waitrequest),
      .upstream_write                  (system_0_burst_15_upstream_write),
      .upstream_writedata              (system_0_burst_15_upstream_writedata)
    );

  system_0_burst_16_upstream_arbitrator the_system_0_burst_16_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_16_upstream                        (cpu_0_data_master_granted_system_0_burst_16_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_16_upstream              (cpu_0_data_master_qualified_request_system_0_burst_16_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_16_upstream                       (cpu_0_data_master_requests_system_0_burst_16_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_16_upstream_end_xfer                                      (d1_system_0_burst_16_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_16_upstream_address                                          (system_0_burst_16_upstream_address),
      .system_0_burst_16_upstream_burstcount                                       (system_0_burst_16_upstream_burstcount),
      .system_0_burst_16_upstream_byteaddress                                      (system_0_burst_16_upstream_byteaddress),
      .system_0_burst_16_upstream_byteenable                                       (system_0_burst_16_upstream_byteenable),
      .system_0_burst_16_upstream_debugaccess                                      (system_0_burst_16_upstream_debugaccess),
      .system_0_burst_16_upstream_read                                             (system_0_burst_16_upstream_read),
      .system_0_burst_16_upstream_readdata                                         (system_0_burst_16_upstream_readdata),
      .system_0_burst_16_upstream_readdata_from_sa                                 (system_0_burst_16_upstream_readdata_from_sa),
      .system_0_burst_16_upstream_readdatavalid                                    (system_0_burst_16_upstream_readdatavalid),
      .system_0_burst_16_upstream_waitrequest                                      (system_0_burst_16_upstream_waitrequest),
      .system_0_burst_16_upstream_waitrequest_from_sa                              (system_0_burst_16_upstream_waitrequest_from_sa),
      .system_0_burst_16_upstream_write                                            (system_0_burst_16_upstream_write),
      .system_0_burst_16_upstream_writedata                                        (system_0_burst_16_upstream_writedata)
    );

  system_0_burst_16_downstream_arbitrator the_system_0_burst_16_downstream
    (
      .Audio_0_avalon_slave_0_readdata_from_sa                               (Audio_0_avalon_slave_0_readdata_from_sa),
      .clk                                                                   (altpll_0_c1_out),
      .d1_Audio_0_avalon_slave_0_end_xfer                                    (d1_Audio_0_avalon_slave_0_end_xfer),
      .reset_n                                                               (altpll_0_c1_out_reset_n),
      .system_0_burst_16_downstream_address                                  (system_0_burst_16_downstream_address),
      .system_0_burst_16_downstream_address_to_slave                         (system_0_burst_16_downstream_address_to_slave),
      .system_0_burst_16_downstream_burstcount                               (system_0_burst_16_downstream_burstcount),
      .system_0_burst_16_downstream_byteenable                               (system_0_burst_16_downstream_byteenable),
      .system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0           (system_0_burst_16_downstream_granted_Audio_0_avalon_slave_0),
      .system_0_burst_16_downstream_latency_counter                          (system_0_burst_16_downstream_latency_counter),
      .system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0 (system_0_burst_16_downstream_qualified_request_Audio_0_avalon_slave_0),
      .system_0_burst_16_downstream_read                                     (system_0_burst_16_downstream_read),
      .system_0_burst_16_downstream_read_data_valid_Audio_0_avalon_slave_0   (system_0_burst_16_downstream_read_data_valid_Audio_0_avalon_slave_0),
      .system_0_burst_16_downstream_readdata                                 (system_0_burst_16_downstream_readdata),
      .system_0_burst_16_downstream_readdatavalid                            (system_0_burst_16_downstream_readdatavalid),
      .system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0          (system_0_burst_16_downstream_requests_Audio_0_avalon_slave_0),
      .system_0_burst_16_downstream_reset_n                                  (system_0_burst_16_downstream_reset_n),
      .system_0_burst_16_downstream_waitrequest                              (system_0_burst_16_downstream_waitrequest),
      .system_0_burst_16_downstream_write                                    (system_0_burst_16_downstream_write),
      .system_0_burst_16_downstream_writedata                                (system_0_burst_16_downstream_writedata)
    );

  system_0_burst_16 the_system_0_burst_16
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_16_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_16_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_16_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_16_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_16_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_16_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_16_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_16_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_16_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_16_downstream_read),
      .reg_downstream_write            (system_0_burst_16_downstream_write),
      .reg_downstream_writedata        (system_0_burst_16_downstream_writedata),
      .reset_n                         (system_0_burst_16_downstream_reset_n),
      .upstream_address                (system_0_burst_16_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_16_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_16_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_16_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_16_upstream_address),
      .upstream_read                   (system_0_burst_16_upstream_read),
      .upstream_readdata               (system_0_burst_16_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_16_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_16_upstream_waitrequest),
      .upstream_write                  (system_0_burst_16_upstream_write),
      .upstream_writedata              (system_0_burst_16_upstream_writedata)
    );

  system_0_burst_17_upstream_arbitrator the_system_0_burst_17_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_17_upstream                        (cpu_0_data_master_granted_system_0_burst_17_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_17_upstream              (cpu_0_data_master_qualified_request_system_0_burst_17_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_17_upstream                       (cpu_0_data_master_requests_system_0_burst_17_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_17_upstream_end_xfer                                      (d1_system_0_burst_17_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_17_upstream_address                                          (system_0_burst_17_upstream_address),
      .system_0_burst_17_upstream_burstcount                                       (system_0_burst_17_upstream_burstcount),
      .system_0_burst_17_upstream_byteaddress                                      (system_0_burst_17_upstream_byteaddress),
      .system_0_burst_17_upstream_byteenable                                       (system_0_burst_17_upstream_byteenable),
      .system_0_burst_17_upstream_debugaccess                                      (system_0_burst_17_upstream_debugaccess),
      .system_0_burst_17_upstream_read                                             (system_0_burst_17_upstream_read),
      .system_0_burst_17_upstream_readdata                                         (system_0_burst_17_upstream_readdata),
      .system_0_burst_17_upstream_readdata_from_sa                                 (system_0_burst_17_upstream_readdata_from_sa),
      .system_0_burst_17_upstream_readdatavalid                                    (system_0_burst_17_upstream_readdatavalid),
      .system_0_burst_17_upstream_waitrequest                                      (system_0_burst_17_upstream_waitrequest),
      .system_0_burst_17_upstream_waitrequest_from_sa                              (system_0_burst_17_upstream_waitrequest_from_sa),
      .system_0_burst_17_upstream_write                                            (system_0_burst_17_upstream_write),
      .system_0_burst_17_upstream_writedata                                        (system_0_burst_17_upstream_writedata)
    );

  system_0_burst_17_downstream_arbitrator the_system_0_burst_17_downstream
    (
      .SD_DAT_s1_readdata_from_sa                               (SD_DAT_s1_readdata_from_sa),
      .clk                                                      (altpll_0_c1_out),
      .d1_SD_DAT_s1_end_xfer                                    (d1_SD_DAT_s1_end_xfer),
      .reset_n                                                  (altpll_0_c1_out_reset_n),
      .system_0_burst_17_downstream_address                     (system_0_burst_17_downstream_address),
      .system_0_burst_17_downstream_address_to_slave            (system_0_burst_17_downstream_address_to_slave),
      .system_0_burst_17_downstream_burstcount                  (system_0_burst_17_downstream_burstcount),
      .system_0_burst_17_downstream_byteenable                  (system_0_burst_17_downstream_byteenable),
      .system_0_burst_17_downstream_granted_SD_DAT_s1           (system_0_burst_17_downstream_granted_SD_DAT_s1),
      .system_0_burst_17_downstream_latency_counter             (system_0_burst_17_downstream_latency_counter),
      .system_0_burst_17_downstream_qualified_request_SD_DAT_s1 (system_0_burst_17_downstream_qualified_request_SD_DAT_s1),
      .system_0_burst_17_downstream_read                        (system_0_burst_17_downstream_read),
      .system_0_burst_17_downstream_read_data_valid_SD_DAT_s1   (system_0_burst_17_downstream_read_data_valid_SD_DAT_s1),
      .system_0_burst_17_downstream_readdata                    (system_0_burst_17_downstream_readdata),
      .system_0_burst_17_downstream_readdatavalid               (system_0_burst_17_downstream_readdatavalid),
      .system_0_burst_17_downstream_requests_SD_DAT_s1          (system_0_burst_17_downstream_requests_SD_DAT_s1),
      .system_0_burst_17_downstream_reset_n                     (system_0_burst_17_downstream_reset_n),
      .system_0_burst_17_downstream_waitrequest                 (system_0_burst_17_downstream_waitrequest),
      .system_0_burst_17_downstream_write                       (system_0_burst_17_downstream_write),
      .system_0_burst_17_downstream_writedata                   (system_0_burst_17_downstream_writedata)
    );

  system_0_burst_17 the_system_0_burst_17
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_17_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_17_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_17_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_17_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_17_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_17_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_17_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_17_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_17_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_17_downstream_read),
      .reg_downstream_write            (system_0_burst_17_downstream_write),
      .reg_downstream_writedata        (system_0_burst_17_downstream_writedata),
      .reset_n                         (system_0_burst_17_downstream_reset_n),
      .upstream_address                (system_0_burst_17_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_17_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_17_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_17_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_17_upstream_address),
      .upstream_read                   (system_0_burst_17_upstream_read),
      .upstream_readdata               (system_0_burst_17_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_17_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_17_upstream_waitrequest),
      .upstream_write                  (system_0_burst_17_upstream_write),
      .upstream_writedata              (system_0_burst_17_upstream_writedata)
    );

  system_0_burst_18_upstream_arbitrator the_system_0_burst_18_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_18_upstream                        (cpu_0_data_master_granted_system_0_burst_18_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_18_upstream              (cpu_0_data_master_qualified_request_system_0_burst_18_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_18_upstream                       (cpu_0_data_master_requests_system_0_burst_18_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_18_upstream_end_xfer                                      (d1_system_0_burst_18_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_18_upstream_address                                          (system_0_burst_18_upstream_address),
      .system_0_burst_18_upstream_burstcount                                       (system_0_burst_18_upstream_burstcount),
      .system_0_burst_18_upstream_byteaddress                                      (system_0_burst_18_upstream_byteaddress),
      .system_0_burst_18_upstream_byteenable                                       (system_0_burst_18_upstream_byteenable),
      .system_0_burst_18_upstream_debugaccess                                      (system_0_burst_18_upstream_debugaccess),
      .system_0_burst_18_upstream_read                                             (system_0_burst_18_upstream_read),
      .system_0_burst_18_upstream_readdata                                         (system_0_burst_18_upstream_readdata),
      .system_0_burst_18_upstream_readdata_from_sa                                 (system_0_burst_18_upstream_readdata_from_sa),
      .system_0_burst_18_upstream_readdatavalid                                    (system_0_burst_18_upstream_readdatavalid),
      .system_0_burst_18_upstream_waitrequest                                      (system_0_burst_18_upstream_waitrequest),
      .system_0_burst_18_upstream_waitrequest_from_sa                              (system_0_burst_18_upstream_waitrequest_from_sa),
      .system_0_burst_18_upstream_write                                            (system_0_burst_18_upstream_write),
      .system_0_burst_18_upstream_writedata                                        (system_0_burst_18_upstream_writedata)
    );

  system_0_burst_18_downstream_arbitrator the_system_0_burst_18_downstream
    (
      .SD_CMD_s1_readdata_from_sa                               (SD_CMD_s1_readdata_from_sa),
      .clk                                                      (altpll_0_c1_out),
      .d1_SD_CMD_s1_end_xfer                                    (d1_SD_CMD_s1_end_xfer),
      .reset_n                                                  (altpll_0_c1_out_reset_n),
      .system_0_burst_18_downstream_address                     (system_0_burst_18_downstream_address),
      .system_0_burst_18_downstream_address_to_slave            (system_0_burst_18_downstream_address_to_slave),
      .system_0_burst_18_downstream_burstcount                  (system_0_burst_18_downstream_burstcount),
      .system_0_burst_18_downstream_byteenable                  (system_0_burst_18_downstream_byteenable),
      .system_0_burst_18_downstream_granted_SD_CMD_s1           (system_0_burst_18_downstream_granted_SD_CMD_s1),
      .system_0_burst_18_downstream_latency_counter             (system_0_burst_18_downstream_latency_counter),
      .system_0_burst_18_downstream_qualified_request_SD_CMD_s1 (system_0_burst_18_downstream_qualified_request_SD_CMD_s1),
      .system_0_burst_18_downstream_read                        (system_0_burst_18_downstream_read),
      .system_0_burst_18_downstream_read_data_valid_SD_CMD_s1   (system_0_burst_18_downstream_read_data_valid_SD_CMD_s1),
      .system_0_burst_18_downstream_readdata                    (system_0_burst_18_downstream_readdata),
      .system_0_burst_18_downstream_readdatavalid               (system_0_burst_18_downstream_readdatavalid),
      .system_0_burst_18_downstream_requests_SD_CMD_s1          (system_0_burst_18_downstream_requests_SD_CMD_s1),
      .system_0_burst_18_downstream_reset_n                     (system_0_burst_18_downstream_reset_n),
      .system_0_burst_18_downstream_waitrequest                 (system_0_burst_18_downstream_waitrequest),
      .system_0_burst_18_downstream_write                       (system_0_burst_18_downstream_write),
      .system_0_burst_18_downstream_writedata                   (system_0_burst_18_downstream_writedata)
    );

  system_0_burst_18 the_system_0_burst_18
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_18_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_18_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_18_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_18_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_18_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_18_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_18_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_18_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_18_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_18_downstream_read),
      .reg_downstream_write            (system_0_burst_18_downstream_write),
      .reg_downstream_writedata        (system_0_burst_18_downstream_writedata),
      .reset_n                         (system_0_burst_18_downstream_reset_n),
      .upstream_address                (system_0_burst_18_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_18_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_18_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_18_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_18_upstream_address),
      .upstream_read                   (system_0_burst_18_upstream_read),
      .upstream_readdata               (system_0_burst_18_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_18_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_18_upstream_waitrequest),
      .upstream_write                  (system_0_burst_18_upstream_write),
      .upstream_writedata              (system_0_burst_18_upstream_writedata)
    );

  system_0_burst_19_upstream_arbitrator the_system_0_burst_19_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_19_upstream                        (cpu_0_data_master_granted_system_0_burst_19_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_19_upstream              (cpu_0_data_master_qualified_request_system_0_burst_19_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_19_upstream                       (cpu_0_data_master_requests_system_0_burst_19_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_19_upstream_end_xfer                                      (d1_system_0_burst_19_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_19_upstream_address                                          (system_0_burst_19_upstream_address),
      .system_0_burst_19_upstream_burstcount                                       (system_0_burst_19_upstream_burstcount),
      .system_0_burst_19_upstream_byteaddress                                      (system_0_burst_19_upstream_byteaddress),
      .system_0_burst_19_upstream_byteenable                                       (system_0_burst_19_upstream_byteenable),
      .system_0_burst_19_upstream_debugaccess                                      (system_0_burst_19_upstream_debugaccess),
      .system_0_burst_19_upstream_read                                             (system_0_burst_19_upstream_read),
      .system_0_burst_19_upstream_readdata                                         (system_0_burst_19_upstream_readdata),
      .system_0_burst_19_upstream_readdata_from_sa                                 (system_0_burst_19_upstream_readdata_from_sa),
      .system_0_burst_19_upstream_readdatavalid                                    (system_0_burst_19_upstream_readdatavalid),
      .system_0_burst_19_upstream_waitrequest                                      (system_0_burst_19_upstream_waitrequest),
      .system_0_burst_19_upstream_waitrequest_from_sa                              (system_0_burst_19_upstream_waitrequest_from_sa),
      .system_0_burst_19_upstream_write                                            (system_0_burst_19_upstream_write),
      .system_0_burst_19_upstream_writedata                                        (system_0_burst_19_upstream_writedata)
    );

  system_0_burst_19_downstream_arbitrator the_system_0_burst_19_downstream
    (
      .SD_CLK_s1_readdata_from_sa                               (SD_CLK_s1_readdata_from_sa),
      .clk                                                      (altpll_0_c1_out),
      .d1_SD_CLK_s1_end_xfer                                    (d1_SD_CLK_s1_end_xfer),
      .reset_n                                                  (altpll_0_c1_out_reset_n),
      .system_0_burst_19_downstream_address                     (system_0_burst_19_downstream_address),
      .system_0_burst_19_downstream_address_to_slave            (system_0_burst_19_downstream_address_to_slave),
      .system_0_burst_19_downstream_burstcount                  (system_0_burst_19_downstream_burstcount),
      .system_0_burst_19_downstream_byteenable                  (system_0_burst_19_downstream_byteenable),
      .system_0_burst_19_downstream_granted_SD_CLK_s1           (system_0_burst_19_downstream_granted_SD_CLK_s1),
      .system_0_burst_19_downstream_latency_counter             (system_0_burst_19_downstream_latency_counter),
      .system_0_burst_19_downstream_qualified_request_SD_CLK_s1 (system_0_burst_19_downstream_qualified_request_SD_CLK_s1),
      .system_0_burst_19_downstream_read                        (system_0_burst_19_downstream_read),
      .system_0_burst_19_downstream_read_data_valid_SD_CLK_s1   (system_0_burst_19_downstream_read_data_valid_SD_CLK_s1),
      .system_0_burst_19_downstream_readdata                    (system_0_burst_19_downstream_readdata),
      .system_0_burst_19_downstream_readdatavalid               (system_0_burst_19_downstream_readdatavalid),
      .system_0_burst_19_downstream_requests_SD_CLK_s1          (system_0_burst_19_downstream_requests_SD_CLK_s1),
      .system_0_burst_19_downstream_reset_n                     (system_0_burst_19_downstream_reset_n),
      .system_0_burst_19_downstream_waitrequest                 (system_0_burst_19_downstream_waitrequest),
      .system_0_burst_19_downstream_write                       (system_0_burst_19_downstream_write),
      .system_0_burst_19_downstream_writedata                   (system_0_burst_19_downstream_writedata)
    );

  system_0_burst_19 the_system_0_burst_19
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_19_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_19_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_19_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_19_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_19_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_19_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_19_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_19_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_19_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_19_downstream_read),
      .reg_downstream_write            (system_0_burst_19_downstream_write),
      .reg_downstream_writedata        (system_0_burst_19_downstream_writedata),
      .reset_n                         (system_0_burst_19_downstream_reset_n),
      .upstream_address                (system_0_burst_19_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_19_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_19_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_19_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_19_upstream_address),
      .upstream_read                   (system_0_burst_19_upstream_read),
      .upstream_readdata               (system_0_burst_19_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_19_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_19_upstream_waitrequest),
      .upstream_write                  (system_0_burst_19_upstream_write),
      .upstream_writedata              (system_0_burst_19_upstream_writedata)
    );

  system_0_burst_2_upstream_arbitrator the_system_0_burst_2_upstream
    (
      .clk                                                                                (altpll_0_c1_out),
      .cpu_0_instruction_master_address_to_slave                                          (cpu_0_instruction_master_address_to_slave),
      .cpu_0_instruction_master_burstcount                                                (cpu_0_instruction_master_burstcount),
      .cpu_0_instruction_master_dbs_address                                               (cpu_0_instruction_master_dbs_address),
      .cpu_0_instruction_master_granted_system_0_burst_2_upstream                         (cpu_0_instruction_master_granted_system_0_burst_2_upstream),
      .cpu_0_instruction_master_latency_counter                                           (cpu_0_instruction_master_latency_counter),
      .cpu_0_instruction_master_qualified_request_system_0_burst_2_upstream               (cpu_0_instruction_master_qualified_request_system_0_burst_2_upstream),
      .cpu_0_instruction_master_read                                                      (cpu_0_instruction_master_read),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register (cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream                 (cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register (cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register),
      .cpu_0_instruction_master_requests_system_0_burst_2_upstream                        (cpu_0_instruction_master_requests_system_0_burst_2_upstream),
      .d1_system_0_burst_2_upstream_end_xfer                                              (d1_system_0_burst_2_upstream_end_xfer),
      .reset_n                                                                            (altpll_0_c1_out_reset_n),
      .system_0_burst_2_upstream_address                                                  (system_0_burst_2_upstream_address),
      .system_0_burst_2_upstream_byteaddress                                              (system_0_burst_2_upstream_byteaddress),
      .system_0_burst_2_upstream_byteenable                                               (system_0_burst_2_upstream_byteenable),
      .system_0_burst_2_upstream_debugaccess                                              (system_0_burst_2_upstream_debugaccess),
      .system_0_burst_2_upstream_read                                                     (system_0_burst_2_upstream_read),
      .system_0_burst_2_upstream_readdata                                                 (system_0_burst_2_upstream_readdata),
      .system_0_burst_2_upstream_readdata_from_sa                                         (system_0_burst_2_upstream_readdata_from_sa),
      .system_0_burst_2_upstream_readdatavalid                                            (system_0_burst_2_upstream_readdatavalid),
      .system_0_burst_2_upstream_waitrequest                                              (system_0_burst_2_upstream_waitrequest),
      .system_0_burst_2_upstream_waitrequest_from_sa                                      (system_0_burst_2_upstream_waitrequest_from_sa),
      .system_0_burst_2_upstream_write                                                    (system_0_burst_2_upstream_write)
    );

  system_0_burst_2_downstream_arbitrator the_system_0_burst_2_downstream
    (
      .cfi_flash_0_s1_wait_counter_eq_0                             (cfi_flash_0_s1_wait_counter_eq_0),
      .clk                                                          (altpll_0_c1_out),
      .d1_tri_state_bridge_0_avalon_slave_end_xfer                  (d1_tri_state_bridge_0_avalon_slave_end_xfer),
      .incoming_tri_state_bridge_0_data_with_Xs_converted_to_0      (incoming_tri_state_bridge_0_data_with_Xs_converted_to_0),
      .reset_n                                                      (altpll_0_c1_out_reset_n),
      .system_0_burst_2_downstream_address                          (system_0_burst_2_downstream_address),
      .system_0_burst_2_downstream_address_to_slave                 (system_0_burst_2_downstream_address_to_slave),
      .system_0_burst_2_downstream_burstcount                       (system_0_burst_2_downstream_burstcount),
      .system_0_burst_2_downstream_byteenable                       (system_0_burst_2_downstream_byteenable),
      .system_0_burst_2_downstream_granted_cfi_flash_0_s1           (system_0_burst_2_downstream_granted_cfi_flash_0_s1),
      .system_0_burst_2_downstream_latency_counter                  (system_0_burst_2_downstream_latency_counter),
      .system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1 (system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1),
      .system_0_burst_2_downstream_read                             (system_0_burst_2_downstream_read),
      .system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1   (system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1),
      .system_0_burst_2_downstream_readdata                         (system_0_burst_2_downstream_readdata),
      .system_0_burst_2_downstream_readdatavalid                    (system_0_burst_2_downstream_readdatavalid),
      .system_0_burst_2_downstream_requests_cfi_flash_0_s1          (system_0_burst_2_downstream_requests_cfi_flash_0_s1),
      .system_0_burst_2_downstream_reset_n                          (system_0_burst_2_downstream_reset_n),
      .system_0_burst_2_downstream_waitrequest                      (system_0_burst_2_downstream_waitrequest),
      .system_0_burst_2_downstream_write                            (system_0_burst_2_downstream_write),
      .system_0_burst_2_downstream_writedata                        (system_0_burst_2_downstream_writedata)
    );

  system_0_burst_2 the_system_0_burst_2
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_2_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_2_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_2_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_2_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_2_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_2_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_2_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_2_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_2_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_2_downstream_read),
      .reg_downstream_write            (system_0_burst_2_downstream_write),
      .reg_downstream_writedata        (system_0_burst_2_downstream_writedata),
      .reset_n                         (system_0_burst_2_downstream_reset_n),
      .upstream_address                (system_0_burst_2_upstream_byteaddress),
      .upstream_byteenable             (system_0_burst_2_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_2_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_2_upstream_address),
      .upstream_read                   (system_0_burst_2_upstream_read),
      .upstream_readdata               (system_0_burst_2_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_2_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_2_upstream_waitrequest),
      .upstream_write                  (system_0_burst_2_upstream_write),
      .upstream_writedata              (system_0_burst_2_upstream_writedata)
    );

  system_0_burst_20_upstream_arbitrator the_system_0_burst_20_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_20_upstream                        (cpu_0_data_master_granted_system_0_burst_20_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_20_upstream              (cpu_0_data_master_qualified_request_system_0_burst_20_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_20_upstream                       (cpu_0_data_master_requests_system_0_burst_20_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_20_upstream_end_xfer                                      (d1_system_0_burst_20_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_20_upstream_address                                          (system_0_burst_20_upstream_address),
      .system_0_burst_20_upstream_burstcount                                       (system_0_burst_20_upstream_burstcount),
      .system_0_burst_20_upstream_byteaddress                                      (system_0_burst_20_upstream_byteaddress),
      .system_0_burst_20_upstream_byteenable                                       (system_0_burst_20_upstream_byteenable),
      .system_0_burst_20_upstream_debugaccess                                      (system_0_burst_20_upstream_debugaccess),
      .system_0_burst_20_upstream_read                                             (system_0_burst_20_upstream_read),
      .system_0_burst_20_upstream_readdata                                         (system_0_burst_20_upstream_readdata),
      .system_0_burst_20_upstream_readdata_from_sa                                 (system_0_burst_20_upstream_readdata_from_sa),
      .system_0_burst_20_upstream_readdatavalid                                    (system_0_burst_20_upstream_readdatavalid),
      .system_0_burst_20_upstream_waitrequest                                      (system_0_burst_20_upstream_waitrequest),
      .system_0_burst_20_upstream_waitrequest_from_sa                              (system_0_burst_20_upstream_waitrequest_from_sa),
      .system_0_burst_20_upstream_write                                            (system_0_burst_20_upstream_write),
      .system_0_burst_20_upstream_writedata                                        (system_0_burst_20_upstream_writedata)
    );

  system_0_burst_20_downstream_arbitrator the_system_0_burst_20_downstream
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_noteA_s1_end_xfer                                    (d1_noteA_s1_end_xfer),
      .noteA_s1_readdata_from_sa                               (noteA_s1_readdata_from_sa),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_20_downstream_address                    (system_0_burst_20_downstream_address),
      .system_0_burst_20_downstream_address_to_slave           (system_0_burst_20_downstream_address_to_slave),
      .system_0_burst_20_downstream_burstcount                 (system_0_burst_20_downstream_burstcount),
      .system_0_burst_20_downstream_byteenable                 (system_0_burst_20_downstream_byteenable),
      .system_0_burst_20_downstream_granted_noteA_s1           (system_0_burst_20_downstream_granted_noteA_s1),
      .system_0_burst_20_downstream_latency_counter            (system_0_burst_20_downstream_latency_counter),
      .system_0_burst_20_downstream_qualified_request_noteA_s1 (system_0_burst_20_downstream_qualified_request_noteA_s1),
      .system_0_burst_20_downstream_read                       (system_0_burst_20_downstream_read),
      .system_0_burst_20_downstream_read_data_valid_noteA_s1   (system_0_burst_20_downstream_read_data_valid_noteA_s1),
      .system_0_burst_20_downstream_readdata                   (system_0_burst_20_downstream_readdata),
      .system_0_burst_20_downstream_readdatavalid              (system_0_burst_20_downstream_readdatavalid),
      .system_0_burst_20_downstream_requests_noteA_s1          (system_0_burst_20_downstream_requests_noteA_s1),
      .system_0_burst_20_downstream_reset_n                    (system_0_burst_20_downstream_reset_n),
      .system_0_burst_20_downstream_waitrequest                (system_0_burst_20_downstream_waitrequest),
      .system_0_burst_20_downstream_write                      (system_0_burst_20_downstream_write),
      .system_0_burst_20_downstream_writedata                  (system_0_burst_20_downstream_writedata)
    );

  system_0_burst_20 the_system_0_burst_20
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_20_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_20_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_20_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_20_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_20_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_20_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_20_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_20_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_20_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_20_downstream_read),
      .reg_downstream_write            (system_0_burst_20_downstream_write),
      .reg_downstream_writedata        (system_0_burst_20_downstream_writedata),
      .reset_n                         (system_0_burst_20_downstream_reset_n),
      .upstream_address                (system_0_burst_20_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_20_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_20_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_20_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_20_upstream_address),
      .upstream_read                   (system_0_burst_20_upstream_read),
      .upstream_readdata               (system_0_burst_20_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_20_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_20_upstream_waitrequest),
      .upstream_write                  (system_0_burst_20_upstream_write),
      .upstream_writedata              (system_0_burst_20_upstream_writedata)
    );

  system_0_burst_21_upstream_arbitrator the_system_0_burst_21_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_21_upstream                        (cpu_0_data_master_granted_system_0_burst_21_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_21_upstream              (cpu_0_data_master_qualified_request_system_0_burst_21_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_21_upstream                       (cpu_0_data_master_requests_system_0_burst_21_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_21_upstream_end_xfer                                      (d1_system_0_burst_21_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_21_upstream_address                                          (system_0_burst_21_upstream_address),
      .system_0_burst_21_upstream_burstcount                                       (system_0_burst_21_upstream_burstcount),
      .system_0_burst_21_upstream_byteaddress                                      (system_0_burst_21_upstream_byteaddress),
      .system_0_burst_21_upstream_byteenable                                       (system_0_burst_21_upstream_byteenable),
      .system_0_burst_21_upstream_debugaccess                                      (system_0_burst_21_upstream_debugaccess),
      .system_0_burst_21_upstream_read                                             (system_0_burst_21_upstream_read),
      .system_0_burst_21_upstream_readdata                                         (system_0_burst_21_upstream_readdata),
      .system_0_burst_21_upstream_readdata_from_sa                                 (system_0_burst_21_upstream_readdata_from_sa),
      .system_0_burst_21_upstream_readdatavalid                                    (system_0_burst_21_upstream_readdatavalid),
      .system_0_burst_21_upstream_waitrequest                                      (system_0_burst_21_upstream_waitrequest),
      .system_0_burst_21_upstream_waitrequest_from_sa                              (system_0_burst_21_upstream_waitrequest_from_sa),
      .system_0_burst_21_upstream_write                                            (system_0_burst_21_upstream_write),
      .system_0_burst_21_upstream_writedata                                        (system_0_burst_21_upstream_writedata)
    );

  system_0_burst_21_downstream_arbitrator the_system_0_burst_21_downstream
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_noteB_s1_end_xfer                                    (d1_noteB_s1_end_xfer),
      .noteB_s1_readdata_from_sa                               (noteB_s1_readdata_from_sa),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_21_downstream_address                    (system_0_burst_21_downstream_address),
      .system_0_burst_21_downstream_address_to_slave           (system_0_burst_21_downstream_address_to_slave),
      .system_0_burst_21_downstream_burstcount                 (system_0_burst_21_downstream_burstcount),
      .system_0_burst_21_downstream_byteenable                 (system_0_burst_21_downstream_byteenable),
      .system_0_burst_21_downstream_granted_noteB_s1           (system_0_burst_21_downstream_granted_noteB_s1),
      .system_0_burst_21_downstream_latency_counter            (system_0_burst_21_downstream_latency_counter),
      .system_0_burst_21_downstream_qualified_request_noteB_s1 (system_0_burst_21_downstream_qualified_request_noteB_s1),
      .system_0_burst_21_downstream_read                       (system_0_burst_21_downstream_read),
      .system_0_burst_21_downstream_read_data_valid_noteB_s1   (system_0_burst_21_downstream_read_data_valid_noteB_s1),
      .system_0_burst_21_downstream_readdata                   (system_0_burst_21_downstream_readdata),
      .system_0_burst_21_downstream_readdatavalid              (system_0_burst_21_downstream_readdatavalid),
      .system_0_burst_21_downstream_requests_noteB_s1          (system_0_burst_21_downstream_requests_noteB_s1),
      .system_0_burst_21_downstream_reset_n                    (system_0_burst_21_downstream_reset_n),
      .system_0_burst_21_downstream_waitrequest                (system_0_burst_21_downstream_waitrequest),
      .system_0_burst_21_downstream_write                      (system_0_burst_21_downstream_write),
      .system_0_burst_21_downstream_writedata                  (system_0_burst_21_downstream_writedata)
    );

  system_0_burst_21 the_system_0_burst_21
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_21_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_21_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_21_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_21_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_21_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_21_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_21_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_21_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_21_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_21_downstream_read),
      .reg_downstream_write            (system_0_burst_21_downstream_write),
      .reg_downstream_writedata        (system_0_burst_21_downstream_writedata),
      .reset_n                         (system_0_burst_21_downstream_reset_n),
      .upstream_address                (system_0_burst_21_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_21_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_21_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_21_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_21_upstream_address),
      .upstream_read                   (system_0_burst_21_upstream_read),
      .upstream_readdata               (system_0_burst_21_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_21_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_21_upstream_waitrequest),
      .upstream_write                  (system_0_burst_21_upstream_write),
      .upstream_writedata              (system_0_burst_21_upstream_writedata)
    );

  system_0_burst_22_upstream_arbitrator the_system_0_burst_22_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_22_upstream                        (cpu_0_data_master_granted_system_0_burst_22_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_22_upstream              (cpu_0_data_master_qualified_request_system_0_burst_22_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_22_upstream                       (cpu_0_data_master_requests_system_0_burst_22_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_22_upstream_end_xfer                                      (d1_system_0_burst_22_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_22_upstream_address                                          (system_0_burst_22_upstream_address),
      .system_0_burst_22_upstream_burstcount                                       (system_0_burst_22_upstream_burstcount),
      .system_0_burst_22_upstream_byteaddress                                      (system_0_burst_22_upstream_byteaddress),
      .system_0_burst_22_upstream_byteenable                                       (system_0_burst_22_upstream_byteenable),
      .system_0_burst_22_upstream_debugaccess                                      (system_0_burst_22_upstream_debugaccess),
      .system_0_burst_22_upstream_read                                             (system_0_burst_22_upstream_read),
      .system_0_burst_22_upstream_readdata                                         (system_0_burst_22_upstream_readdata),
      .system_0_burst_22_upstream_readdata_from_sa                                 (system_0_burst_22_upstream_readdata_from_sa),
      .system_0_burst_22_upstream_readdatavalid                                    (system_0_burst_22_upstream_readdatavalid),
      .system_0_burst_22_upstream_waitrequest                                      (system_0_burst_22_upstream_waitrequest),
      .system_0_burst_22_upstream_waitrequest_from_sa                              (system_0_burst_22_upstream_waitrequest_from_sa),
      .system_0_burst_22_upstream_write                                            (system_0_burst_22_upstream_write),
      .system_0_burst_22_upstream_writedata                                        (system_0_burst_22_upstream_writedata)
    );

  system_0_burst_22_downstream_arbitrator the_system_0_burst_22_downstream
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_noteC_s1_end_xfer                                    (d1_noteC_s1_end_xfer),
      .noteC_s1_readdata_from_sa                               (noteC_s1_readdata_from_sa),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_22_downstream_address                    (system_0_burst_22_downstream_address),
      .system_0_burst_22_downstream_address_to_slave           (system_0_burst_22_downstream_address_to_slave),
      .system_0_burst_22_downstream_burstcount                 (system_0_burst_22_downstream_burstcount),
      .system_0_burst_22_downstream_byteenable                 (system_0_burst_22_downstream_byteenable),
      .system_0_burst_22_downstream_granted_noteC_s1           (system_0_burst_22_downstream_granted_noteC_s1),
      .system_0_burst_22_downstream_latency_counter            (system_0_burst_22_downstream_latency_counter),
      .system_0_burst_22_downstream_qualified_request_noteC_s1 (system_0_burst_22_downstream_qualified_request_noteC_s1),
      .system_0_burst_22_downstream_read                       (system_0_burst_22_downstream_read),
      .system_0_burst_22_downstream_read_data_valid_noteC_s1   (system_0_burst_22_downstream_read_data_valid_noteC_s1),
      .system_0_burst_22_downstream_readdata                   (system_0_burst_22_downstream_readdata),
      .system_0_burst_22_downstream_readdatavalid              (system_0_burst_22_downstream_readdatavalid),
      .system_0_burst_22_downstream_requests_noteC_s1          (system_0_burst_22_downstream_requests_noteC_s1),
      .system_0_burst_22_downstream_reset_n                    (system_0_burst_22_downstream_reset_n),
      .system_0_burst_22_downstream_waitrequest                (system_0_burst_22_downstream_waitrequest),
      .system_0_burst_22_downstream_write                      (system_0_burst_22_downstream_write),
      .system_0_burst_22_downstream_writedata                  (system_0_burst_22_downstream_writedata)
    );

  system_0_burst_22 the_system_0_burst_22
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_22_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_22_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_22_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_22_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_22_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_22_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_22_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_22_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_22_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_22_downstream_read),
      .reg_downstream_write            (system_0_burst_22_downstream_write),
      .reg_downstream_writedata        (system_0_burst_22_downstream_writedata),
      .reset_n                         (system_0_burst_22_downstream_reset_n),
      .upstream_address                (system_0_burst_22_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_22_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_22_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_22_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_22_upstream_address),
      .upstream_read                   (system_0_burst_22_upstream_read),
      .upstream_readdata               (system_0_burst_22_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_22_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_22_upstream_waitrequest),
      .upstream_write                  (system_0_burst_22_upstream_write),
      .upstream_writedata              (system_0_burst_22_upstream_writedata)
    );

  system_0_burst_23_upstream_arbitrator the_system_0_burst_23_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_23_upstream                        (cpu_0_data_master_granted_system_0_burst_23_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_23_upstream              (cpu_0_data_master_qualified_request_system_0_burst_23_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_23_upstream                       (cpu_0_data_master_requests_system_0_burst_23_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_23_upstream_end_xfer                                      (d1_system_0_burst_23_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_23_upstream_address                                          (system_0_burst_23_upstream_address),
      .system_0_burst_23_upstream_burstcount                                       (system_0_burst_23_upstream_burstcount),
      .system_0_burst_23_upstream_byteaddress                                      (system_0_burst_23_upstream_byteaddress),
      .system_0_burst_23_upstream_byteenable                                       (system_0_burst_23_upstream_byteenable),
      .system_0_burst_23_upstream_debugaccess                                      (system_0_burst_23_upstream_debugaccess),
      .system_0_burst_23_upstream_read                                             (system_0_burst_23_upstream_read),
      .system_0_burst_23_upstream_readdata                                         (system_0_burst_23_upstream_readdata),
      .system_0_burst_23_upstream_readdata_from_sa                                 (system_0_burst_23_upstream_readdata_from_sa),
      .system_0_burst_23_upstream_readdatavalid                                    (system_0_burst_23_upstream_readdatavalid),
      .system_0_burst_23_upstream_waitrequest                                      (system_0_burst_23_upstream_waitrequest),
      .system_0_burst_23_upstream_waitrequest_from_sa                              (system_0_burst_23_upstream_waitrequest_from_sa),
      .system_0_burst_23_upstream_write                                            (system_0_burst_23_upstream_write),
      .system_0_burst_23_upstream_writedata                                        (system_0_burst_23_upstream_writedata)
    );

  system_0_burst_23_downstream_arbitrator the_system_0_burst_23_downstream
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_noteD_s1_end_xfer                                    (d1_noteD_s1_end_xfer),
      .noteD_s1_readdata_from_sa                               (noteD_s1_readdata_from_sa),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_23_downstream_address                    (system_0_burst_23_downstream_address),
      .system_0_burst_23_downstream_address_to_slave           (system_0_burst_23_downstream_address_to_slave),
      .system_0_burst_23_downstream_burstcount                 (system_0_burst_23_downstream_burstcount),
      .system_0_burst_23_downstream_byteenable                 (system_0_burst_23_downstream_byteenable),
      .system_0_burst_23_downstream_granted_noteD_s1           (system_0_burst_23_downstream_granted_noteD_s1),
      .system_0_burst_23_downstream_latency_counter            (system_0_burst_23_downstream_latency_counter),
      .system_0_burst_23_downstream_qualified_request_noteD_s1 (system_0_burst_23_downstream_qualified_request_noteD_s1),
      .system_0_burst_23_downstream_read                       (system_0_burst_23_downstream_read),
      .system_0_burst_23_downstream_read_data_valid_noteD_s1   (system_0_burst_23_downstream_read_data_valid_noteD_s1),
      .system_0_burst_23_downstream_readdata                   (system_0_burst_23_downstream_readdata),
      .system_0_burst_23_downstream_readdatavalid              (system_0_burst_23_downstream_readdatavalid),
      .system_0_burst_23_downstream_requests_noteD_s1          (system_0_burst_23_downstream_requests_noteD_s1),
      .system_0_burst_23_downstream_reset_n                    (system_0_burst_23_downstream_reset_n),
      .system_0_burst_23_downstream_waitrequest                (system_0_burst_23_downstream_waitrequest),
      .system_0_burst_23_downstream_write                      (system_0_burst_23_downstream_write),
      .system_0_burst_23_downstream_writedata                  (system_0_burst_23_downstream_writedata)
    );

  system_0_burst_23 the_system_0_burst_23
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_23_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_23_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_23_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_23_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_23_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_23_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_23_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_23_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_23_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_23_downstream_read),
      .reg_downstream_write            (system_0_burst_23_downstream_write),
      .reg_downstream_writedata        (system_0_burst_23_downstream_writedata),
      .reset_n                         (system_0_burst_23_downstream_reset_n),
      .upstream_address                (system_0_burst_23_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_23_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_23_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_23_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_23_upstream_address),
      .upstream_read                   (system_0_burst_23_upstream_read),
      .upstream_readdata               (system_0_burst_23_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_23_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_23_upstream_waitrequest),
      .upstream_write                  (system_0_burst_23_upstream_write),
      .upstream_writedata              (system_0_burst_23_upstream_writedata)
    );

  system_0_burst_24_upstream_arbitrator the_system_0_burst_24_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_24_upstream                        (cpu_0_data_master_granted_system_0_burst_24_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_24_upstream              (cpu_0_data_master_qualified_request_system_0_burst_24_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_24_upstream                       (cpu_0_data_master_requests_system_0_burst_24_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_24_upstream_end_xfer                                      (d1_system_0_burst_24_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_24_upstream_address                                          (system_0_burst_24_upstream_address),
      .system_0_burst_24_upstream_burstcount                                       (system_0_burst_24_upstream_burstcount),
      .system_0_burst_24_upstream_byteaddress                                      (system_0_burst_24_upstream_byteaddress),
      .system_0_burst_24_upstream_byteenable                                       (system_0_burst_24_upstream_byteenable),
      .system_0_burst_24_upstream_debugaccess                                      (system_0_burst_24_upstream_debugaccess),
      .system_0_burst_24_upstream_read                                             (system_0_burst_24_upstream_read),
      .system_0_burst_24_upstream_readdata                                         (system_0_burst_24_upstream_readdata),
      .system_0_burst_24_upstream_readdata_from_sa                                 (system_0_burst_24_upstream_readdata_from_sa),
      .system_0_burst_24_upstream_readdatavalid                                    (system_0_burst_24_upstream_readdatavalid),
      .system_0_burst_24_upstream_waitrequest                                      (system_0_burst_24_upstream_waitrequest),
      .system_0_burst_24_upstream_waitrequest_from_sa                              (system_0_burst_24_upstream_waitrequest_from_sa),
      .system_0_burst_24_upstream_write                                            (system_0_burst_24_upstream_write),
      .system_0_burst_24_upstream_writedata                                        (system_0_burst_24_upstream_writedata)
    );

  system_0_burst_24_downstream_arbitrator the_system_0_burst_24_downstream
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_noteE_s1_end_xfer                                    (d1_noteE_s1_end_xfer),
      .noteE_s1_readdata_from_sa                               (noteE_s1_readdata_from_sa),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_24_downstream_address                    (system_0_burst_24_downstream_address),
      .system_0_burst_24_downstream_address_to_slave           (system_0_burst_24_downstream_address_to_slave),
      .system_0_burst_24_downstream_burstcount                 (system_0_burst_24_downstream_burstcount),
      .system_0_burst_24_downstream_byteenable                 (system_0_burst_24_downstream_byteenable),
      .system_0_burst_24_downstream_granted_noteE_s1           (system_0_burst_24_downstream_granted_noteE_s1),
      .system_0_burst_24_downstream_latency_counter            (system_0_burst_24_downstream_latency_counter),
      .system_0_burst_24_downstream_qualified_request_noteE_s1 (system_0_burst_24_downstream_qualified_request_noteE_s1),
      .system_0_burst_24_downstream_read                       (system_0_burst_24_downstream_read),
      .system_0_burst_24_downstream_read_data_valid_noteE_s1   (system_0_burst_24_downstream_read_data_valid_noteE_s1),
      .system_0_burst_24_downstream_readdata                   (system_0_burst_24_downstream_readdata),
      .system_0_burst_24_downstream_readdatavalid              (system_0_burst_24_downstream_readdatavalid),
      .system_0_burst_24_downstream_requests_noteE_s1          (system_0_burst_24_downstream_requests_noteE_s1),
      .system_0_burst_24_downstream_reset_n                    (system_0_burst_24_downstream_reset_n),
      .system_0_burst_24_downstream_waitrequest                (system_0_burst_24_downstream_waitrequest),
      .system_0_burst_24_downstream_write                      (system_0_burst_24_downstream_write),
      .system_0_burst_24_downstream_writedata                  (system_0_burst_24_downstream_writedata)
    );

  system_0_burst_24 the_system_0_burst_24
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_24_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_24_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_24_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_24_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_24_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_24_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_24_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_24_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_24_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_24_downstream_read),
      .reg_downstream_write            (system_0_burst_24_downstream_write),
      .reg_downstream_writedata        (system_0_burst_24_downstream_writedata),
      .reset_n                         (system_0_burst_24_downstream_reset_n),
      .upstream_address                (system_0_burst_24_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_24_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_24_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_24_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_24_upstream_address),
      .upstream_read                   (system_0_burst_24_upstream_read),
      .upstream_readdata               (system_0_burst_24_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_24_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_24_upstream_waitrequest),
      .upstream_write                  (system_0_burst_24_upstream_write),
      .upstream_writedata              (system_0_burst_24_upstream_writedata)
    );

  system_0_burst_25_upstream_arbitrator the_system_0_burst_25_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_25_upstream                        (cpu_0_data_master_granted_system_0_burst_25_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_25_upstream              (cpu_0_data_master_qualified_request_system_0_burst_25_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_25_upstream                       (cpu_0_data_master_requests_system_0_burst_25_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_25_upstream_end_xfer                                      (d1_system_0_burst_25_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_25_upstream_address                                          (system_0_burst_25_upstream_address),
      .system_0_burst_25_upstream_burstcount                                       (system_0_burst_25_upstream_burstcount),
      .system_0_burst_25_upstream_byteaddress                                      (system_0_burst_25_upstream_byteaddress),
      .system_0_burst_25_upstream_byteenable                                       (system_0_burst_25_upstream_byteenable),
      .system_0_burst_25_upstream_debugaccess                                      (system_0_burst_25_upstream_debugaccess),
      .system_0_burst_25_upstream_read                                             (system_0_burst_25_upstream_read),
      .system_0_burst_25_upstream_readdata                                         (system_0_burst_25_upstream_readdata),
      .system_0_burst_25_upstream_readdata_from_sa                                 (system_0_burst_25_upstream_readdata_from_sa),
      .system_0_burst_25_upstream_readdatavalid                                    (system_0_burst_25_upstream_readdatavalid),
      .system_0_burst_25_upstream_waitrequest                                      (system_0_burst_25_upstream_waitrequest),
      .system_0_burst_25_upstream_waitrequest_from_sa                              (system_0_burst_25_upstream_waitrequest_from_sa),
      .system_0_burst_25_upstream_write                                            (system_0_burst_25_upstream_write),
      .system_0_burst_25_upstream_writedata                                        (system_0_burst_25_upstream_writedata)
    );

  system_0_burst_25_downstream_arbitrator the_system_0_burst_25_downstream
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_noteF_s1_end_xfer                                    (d1_noteF_s1_end_xfer),
      .noteF_s1_readdata_from_sa                               (noteF_s1_readdata_from_sa),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_25_downstream_address                    (system_0_burst_25_downstream_address),
      .system_0_burst_25_downstream_address_to_slave           (system_0_burst_25_downstream_address_to_slave),
      .system_0_burst_25_downstream_burstcount                 (system_0_burst_25_downstream_burstcount),
      .system_0_burst_25_downstream_byteenable                 (system_0_burst_25_downstream_byteenable),
      .system_0_burst_25_downstream_granted_noteF_s1           (system_0_burst_25_downstream_granted_noteF_s1),
      .system_0_burst_25_downstream_latency_counter            (system_0_burst_25_downstream_latency_counter),
      .system_0_burst_25_downstream_qualified_request_noteF_s1 (system_0_burst_25_downstream_qualified_request_noteF_s1),
      .system_0_burst_25_downstream_read                       (system_0_burst_25_downstream_read),
      .system_0_burst_25_downstream_read_data_valid_noteF_s1   (system_0_burst_25_downstream_read_data_valid_noteF_s1),
      .system_0_burst_25_downstream_readdata                   (system_0_burst_25_downstream_readdata),
      .system_0_burst_25_downstream_readdatavalid              (system_0_burst_25_downstream_readdatavalid),
      .system_0_burst_25_downstream_requests_noteF_s1          (system_0_burst_25_downstream_requests_noteF_s1),
      .system_0_burst_25_downstream_reset_n                    (system_0_burst_25_downstream_reset_n),
      .system_0_burst_25_downstream_waitrequest                (system_0_burst_25_downstream_waitrequest),
      .system_0_burst_25_downstream_write                      (system_0_burst_25_downstream_write),
      .system_0_burst_25_downstream_writedata                  (system_0_burst_25_downstream_writedata)
    );

  system_0_burst_25 the_system_0_burst_25
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_25_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_25_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_25_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_25_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_25_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_25_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_25_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_25_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_25_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_25_downstream_read),
      .reg_downstream_write            (system_0_burst_25_downstream_write),
      .reg_downstream_writedata        (system_0_burst_25_downstream_writedata),
      .reset_n                         (system_0_burst_25_downstream_reset_n),
      .upstream_address                (system_0_burst_25_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_25_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_25_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_25_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_25_upstream_address),
      .upstream_read                   (system_0_burst_25_upstream_read),
      .upstream_readdata               (system_0_burst_25_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_25_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_25_upstream_waitrequest),
      .upstream_write                  (system_0_burst_25_upstream_write),
      .upstream_writedata              (system_0_burst_25_upstream_writedata)
    );

  system_0_burst_26_upstream_arbitrator the_system_0_burst_26_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_26_upstream                        (cpu_0_data_master_granted_system_0_burst_26_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_26_upstream              (cpu_0_data_master_qualified_request_system_0_burst_26_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_26_upstream                       (cpu_0_data_master_requests_system_0_burst_26_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_26_upstream_end_xfer                                      (d1_system_0_burst_26_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_26_upstream_address                                          (system_0_burst_26_upstream_address),
      .system_0_burst_26_upstream_burstcount                                       (system_0_burst_26_upstream_burstcount),
      .system_0_burst_26_upstream_byteaddress                                      (system_0_burst_26_upstream_byteaddress),
      .system_0_burst_26_upstream_byteenable                                       (system_0_burst_26_upstream_byteenable),
      .system_0_burst_26_upstream_debugaccess                                      (system_0_burst_26_upstream_debugaccess),
      .system_0_burst_26_upstream_read                                             (system_0_burst_26_upstream_read),
      .system_0_burst_26_upstream_readdata                                         (system_0_burst_26_upstream_readdata),
      .system_0_burst_26_upstream_readdata_from_sa                                 (system_0_burst_26_upstream_readdata_from_sa),
      .system_0_burst_26_upstream_readdatavalid                                    (system_0_burst_26_upstream_readdatavalid),
      .system_0_burst_26_upstream_waitrequest                                      (system_0_burst_26_upstream_waitrequest),
      .system_0_burst_26_upstream_waitrequest_from_sa                              (system_0_burst_26_upstream_waitrequest_from_sa),
      .system_0_burst_26_upstream_write                                            (system_0_burst_26_upstream_write),
      .system_0_burst_26_upstream_writedata                                        (system_0_burst_26_upstream_writedata)
    );

  system_0_burst_26_downstream_arbitrator the_system_0_burst_26_downstream
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_noteG_s1_end_xfer                                    (d1_noteG_s1_end_xfer),
      .noteG_s1_readdata_from_sa                               (noteG_s1_readdata_from_sa),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_26_downstream_address                    (system_0_burst_26_downstream_address),
      .system_0_burst_26_downstream_address_to_slave           (system_0_burst_26_downstream_address_to_slave),
      .system_0_burst_26_downstream_burstcount                 (system_0_burst_26_downstream_burstcount),
      .system_0_burst_26_downstream_byteenable                 (system_0_burst_26_downstream_byteenable),
      .system_0_burst_26_downstream_granted_noteG_s1           (system_0_burst_26_downstream_granted_noteG_s1),
      .system_0_burst_26_downstream_latency_counter            (system_0_burst_26_downstream_latency_counter),
      .system_0_burst_26_downstream_qualified_request_noteG_s1 (system_0_burst_26_downstream_qualified_request_noteG_s1),
      .system_0_burst_26_downstream_read                       (system_0_burst_26_downstream_read),
      .system_0_burst_26_downstream_read_data_valid_noteG_s1   (system_0_burst_26_downstream_read_data_valid_noteG_s1),
      .system_0_burst_26_downstream_readdata                   (system_0_burst_26_downstream_readdata),
      .system_0_burst_26_downstream_readdatavalid              (system_0_burst_26_downstream_readdatavalid),
      .system_0_burst_26_downstream_requests_noteG_s1          (system_0_burst_26_downstream_requests_noteG_s1),
      .system_0_burst_26_downstream_reset_n                    (system_0_burst_26_downstream_reset_n),
      .system_0_burst_26_downstream_waitrequest                (system_0_burst_26_downstream_waitrequest),
      .system_0_burst_26_downstream_write                      (system_0_burst_26_downstream_write),
      .system_0_burst_26_downstream_writedata                  (system_0_burst_26_downstream_writedata)
    );

  system_0_burst_26 the_system_0_burst_26
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_26_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_26_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_26_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_26_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_26_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_26_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_26_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_26_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_26_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_26_downstream_read),
      .reg_downstream_write            (system_0_burst_26_downstream_write),
      .reg_downstream_writedata        (system_0_burst_26_downstream_writedata),
      .reset_n                         (system_0_burst_26_downstream_reset_n),
      .upstream_address                (system_0_burst_26_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_26_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_26_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_26_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_26_upstream_address),
      .upstream_read                   (system_0_burst_26_upstream_read),
      .upstream_readdata               (system_0_burst_26_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_26_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_26_upstream_waitrequest),
      .upstream_write                  (system_0_burst_26_upstream_write),
      .upstream_writedata              (system_0_burst_26_upstream_writedata)
    );

  system_0_burst_27_upstream_arbitrator the_system_0_burst_27_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_27_upstream                        (cpu_0_data_master_granted_system_0_burst_27_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_27_upstream              (cpu_0_data_master_qualified_request_system_0_burst_27_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_27_upstream                       (cpu_0_data_master_requests_system_0_burst_27_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_27_upstream_end_xfer                                      (d1_system_0_burst_27_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_27_upstream_address                                          (system_0_burst_27_upstream_address),
      .system_0_burst_27_upstream_burstcount                                       (system_0_burst_27_upstream_burstcount),
      .system_0_burst_27_upstream_byteaddress                                      (system_0_burst_27_upstream_byteaddress),
      .system_0_burst_27_upstream_byteenable                                       (system_0_burst_27_upstream_byteenable),
      .system_0_burst_27_upstream_debugaccess                                      (system_0_burst_27_upstream_debugaccess),
      .system_0_burst_27_upstream_read                                             (system_0_burst_27_upstream_read),
      .system_0_burst_27_upstream_readdata                                         (system_0_burst_27_upstream_readdata),
      .system_0_burst_27_upstream_readdata_from_sa                                 (system_0_burst_27_upstream_readdata_from_sa),
      .system_0_burst_27_upstream_readdatavalid                                    (system_0_burst_27_upstream_readdatavalid),
      .system_0_burst_27_upstream_waitrequest                                      (system_0_burst_27_upstream_waitrequest),
      .system_0_burst_27_upstream_waitrequest_from_sa                              (system_0_burst_27_upstream_waitrequest_from_sa),
      .system_0_burst_27_upstream_write                                            (system_0_burst_27_upstream_write),
      .system_0_burst_27_upstream_writedata                                        (system_0_burst_27_upstream_writedata)
    );

  system_0_burst_27_downstream_arbitrator the_system_0_burst_27_downstream
    (
      .MS_s1_readdata_from_sa                               (MS_s1_readdata_from_sa),
      .clk                                                  (altpll_0_c1_out),
      .d1_MS_s1_end_xfer                                    (d1_MS_s1_end_xfer),
      .reset_n                                              (altpll_0_c1_out_reset_n),
      .system_0_burst_27_downstream_address                 (system_0_burst_27_downstream_address),
      .system_0_burst_27_downstream_address_to_slave        (system_0_burst_27_downstream_address_to_slave),
      .system_0_burst_27_downstream_burstcount              (system_0_burst_27_downstream_burstcount),
      .system_0_burst_27_downstream_byteenable              (system_0_burst_27_downstream_byteenable),
      .system_0_burst_27_downstream_granted_MS_s1           (system_0_burst_27_downstream_granted_MS_s1),
      .system_0_burst_27_downstream_latency_counter         (system_0_burst_27_downstream_latency_counter),
      .system_0_burst_27_downstream_qualified_request_MS_s1 (system_0_burst_27_downstream_qualified_request_MS_s1),
      .system_0_burst_27_downstream_read                    (system_0_burst_27_downstream_read),
      .system_0_burst_27_downstream_read_data_valid_MS_s1   (system_0_burst_27_downstream_read_data_valid_MS_s1),
      .system_0_burst_27_downstream_readdata                (system_0_burst_27_downstream_readdata),
      .system_0_burst_27_downstream_readdatavalid           (system_0_burst_27_downstream_readdatavalid),
      .system_0_burst_27_downstream_requests_MS_s1          (system_0_burst_27_downstream_requests_MS_s1),
      .system_0_burst_27_downstream_reset_n                 (system_0_burst_27_downstream_reset_n),
      .system_0_burst_27_downstream_waitrequest             (system_0_burst_27_downstream_waitrequest),
      .system_0_burst_27_downstream_write                   (system_0_burst_27_downstream_write),
      .system_0_burst_27_downstream_writedata               (system_0_burst_27_downstream_writedata)
    );

  system_0_burst_27 the_system_0_burst_27
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_27_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_27_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_27_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_27_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_27_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_27_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_27_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_27_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_27_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_27_downstream_read),
      .reg_downstream_write            (system_0_burst_27_downstream_write),
      .reg_downstream_writedata        (system_0_burst_27_downstream_writedata),
      .reset_n                         (system_0_burst_27_downstream_reset_n),
      .upstream_address                (system_0_burst_27_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_27_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_27_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_27_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_27_upstream_address),
      .upstream_read                   (system_0_burst_27_upstream_read),
      .upstream_readdata               (system_0_burst_27_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_27_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_27_upstream_waitrequest),
      .upstream_write                  (system_0_burst_27_upstream_write),
      .upstream_writedata              (system_0_burst_27_upstream_writedata)
    );

  system_0_burst_28_upstream_arbitrator the_system_0_burst_28_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_28_upstream                        (cpu_0_data_master_granted_system_0_burst_28_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_28_upstream              (cpu_0_data_master_qualified_request_system_0_burst_28_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_28_upstream                       (cpu_0_data_master_requests_system_0_burst_28_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_28_upstream_end_xfer                                      (d1_system_0_burst_28_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_28_upstream_address                                          (system_0_burst_28_upstream_address),
      .system_0_burst_28_upstream_burstcount                                       (system_0_burst_28_upstream_burstcount),
      .system_0_burst_28_upstream_byteaddress                                      (system_0_burst_28_upstream_byteaddress),
      .system_0_burst_28_upstream_byteenable                                       (system_0_burst_28_upstream_byteenable),
      .system_0_burst_28_upstream_debugaccess                                      (system_0_burst_28_upstream_debugaccess),
      .system_0_burst_28_upstream_read                                             (system_0_burst_28_upstream_read),
      .system_0_burst_28_upstream_readdata                                         (system_0_burst_28_upstream_readdata),
      .system_0_burst_28_upstream_readdata_from_sa                                 (system_0_burst_28_upstream_readdata_from_sa),
      .system_0_burst_28_upstream_readdatavalid                                    (system_0_burst_28_upstream_readdatavalid),
      .system_0_burst_28_upstream_waitrequest                                      (system_0_burst_28_upstream_waitrequest),
      .system_0_burst_28_upstream_waitrequest_from_sa                              (system_0_burst_28_upstream_waitrequest_from_sa),
      .system_0_burst_28_upstream_write                                            (system_0_burst_28_upstream_write),
      .system_0_burst_28_upstream_writedata                                        (system_0_burst_28_upstream_writedata)
    );

  system_0_burst_28_downstream_arbitrator the_system_0_burst_28_downstream
    (
      .clk                                                           (altpll_0_c1_out),
      .d1_dist_sensor_s1_end_xfer                                    (d1_dist_sensor_s1_end_xfer),
      .dist_sensor_s1_readdata_from_sa                               (dist_sensor_s1_readdata_from_sa),
      .reset_n                                                       (altpll_0_c1_out_reset_n),
      .system_0_burst_28_downstream_address                          (system_0_burst_28_downstream_address),
      .system_0_burst_28_downstream_address_to_slave                 (system_0_burst_28_downstream_address_to_slave),
      .system_0_burst_28_downstream_burstcount                       (system_0_burst_28_downstream_burstcount),
      .system_0_burst_28_downstream_byteenable                       (system_0_burst_28_downstream_byteenable),
      .system_0_burst_28_downstream_granted_dist_sensor_s1           (system_0_burst_28_downstream_granted_dist_sensor_s1),
      .system_0_burst_28_downstream_latency_counter                  (system_0_burst_28_downstream_latency_counter),
      .system_0_burst_28_downstream_qualified_request_dist_sensor_s1 (system_0_burst_28_downstream_qualified_request_dist_sensor_s1),
      .system_0_burst_28_downstream_read                             (system_0_burst_28_downstream_read),
      .system_0_burst_28_downstream_read_data_valid_dist_sensor_s1   (system_0_burst_28_downstream_read_data_valid_dist_sensor_s1),
      .system_0_burst_28_downstream_readdata                         (system_0_burst_28_downstream_readdata),
      .system_0_burst_28_downstream_readdatavalid                    (system_0_burst_28_downstream_readdatavalid),
      .system_0_burst_28_downstream_requests_dist_sensor_s1          (system_0_burst_28_downstream_requests_dist_sensor_s1),
      .system_0_burst_28_downstream_reset_n                          (system_0_burst_28_downstream_reset_n),
      .system_0_burst_28_downstream_waitrequest                      (system_0_burst_28_downstream_waitrequest),
      .system_0_burst_28_downstream_write                            (system_0_burst_28_downstream_write),
      .system_0_burst_28_downstream_writedata                        (system_0_burst_28_downstream_writedata)
    );

  system_0_burst_28 the_system_0_burst_28
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_28_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_28_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_28_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_28_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_28_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_28_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_28_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_28_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_28_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_28_downstream_read),
      .reg_downstream_write            (system_0_burst_28_downstream_write),
      .reg_downstream_writedata        (system_0_burst_28_downstream_writedata),
      .reset_n                         (system_0_burst_28_downstream_reset_n),
      .upstream_address                (system_0_burst_28_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_28_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_28_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_28_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_28_upstream_address),
      .upstream_read                   (system_0_burst_28_upstream_read),
      .upstream_readdata               (system_0_burst_28_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_28_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_28_upstream_waitrequest),
      .upstream_write                  (system_0_burst_28_upstream_write),
      .upstream_writedata              (system_0_burst_28_upstream_writedata)
    );

  system_0_burst_29_upstream_arbitrator the_system_0_burst_29_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_29_upstream                        (cpu_0_data_master_granted_system_0_burst_29_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_29_upstream              (cpu_0_data_master_qualified_request_system_0_burst_29_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_29_upstream                       (cpu_0_data_master_requests_system_0_burst_29_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_29_upstream_end_xfer                                      (d1_system_0_burst_29_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_29_upstream_address                                          (system_0_burst_29_upstream_address),
      .system_0_burst_29_upstream_burstcount                                       (system_0_burst_29_upstream_burstcount),
      .system_0_burst_29_upstream_byteaddress                                      (system_0_burst_29_upstream_byteaddress),
      .system_0_burst_29_upstream_byteenable                                       (system_0_burst_29_upstream_byteenable),
      .system_0_burst_29_upstream_debugaccess                                      (system_0_burst_29_upstream_debugaccess),
      .system_0_burst_29_upstream_read                                             (system_0_burst_29_upstream_read),
      .system_0_burst_29_upstream_readdata                                         (system_0_burst_29_upstream_readdata),
      .system_0_burst_29_upstream_readdata_from_sa                                 (system_0_burst_29_upstream_readdata_from_sa),
      .system_0_burst_29_upstream_readdatavalid                                    (system_0_burst_29_upstream_readdatavalid),
      .system_0_burst_29_upstream_waitrequest                                      (system_0_burst_29_upstream_waitrequest),
      .system_0_burst_29_upstream_waitrequest_from_sa                              (system_0_burst_29_upstream_waitrequest_from_sa),
      .system_0_burst_29_upstream_write                                            (system_0_burst_29_upstream_write),
      .system_0_burst_29_upstream_writedata                                        (system_0_burst_29_upstream_writedata)
    );

  system_0_burst_29_downstream_arbitrator the_system_0_burst_29_downstream
    (
      .RST_s1_readdata_from_sa                               (RST_s1_readdata_from_sa),
      .clk                                                   (altpll_0_c1_out),
      .d1_RST_s1_end_xfer                                    (d1_RST_s1_end_xfer),
      .reset_n                                               (altpll_0_c1_out_reset_n),
      .system_0_burst_29_downstream_address                  (system_0_burst_29_downstream_address),
      .system_0_burst_29_downstream_address_to_slave         (system_0_burst_29_downstream_address_to_slave),
      .system_0_burst_29_downstream_burstcount               (system_0_burst_29_downstream_burstcount),
      .system_0_burst_29_downstream_byteenable               (system_0_burst_29_downstream_byteenable),
      .system_0_burst_29_downstream_granted_RST_s1           (system_0_burst_29_downstream_granted_RST_s1),
      .system_0_burst_29_downstream_latency_counter          (system_0_burst_29_downstream_latency_counter),
      .system_0_burst_29_downstream_qualified_request_RST_s1 (system_0_burst_29_downstream_qualified_request_RST_s1),
      .system_0_burst_29_downstream_read                     (system_0_burst_29_downstream_read),
      .system_0_burst_29_downstream_read_data_valid_RST_s1   (system_0_burst_29_downstream_read_data_valid_RST_s1),
      .system_0_burst_29_downstream_readdata                 (system_0_burst_29_downstream_readdata),
      .system_0_burst_29_downstream_readdatavalid            (system_0_burst_29_downstream_readdatavalid),
      .system_0_burst_29_downstream_requests_RST_s1          (system_0_burst_29_downstream_requests_RST_s1),
      .system_0_burst_29_downstream_reset_n                  (system_0_burst_29_downstream_reset_n),
      .system_0_burst_29_downstream_waitrequest              (system_0_burst_29_downstream_waitrequest),
      .system_0_burst_29_downstream_write                    (system_0_burst_29_downstream_write),
      .system_0_burst_29_downstream_writedata                (system_0_burst_29_downstream_writedata)
    );

  system_0_burst_29 the_system_0_burst_29
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_29_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_29_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_29_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_29_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_29_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_29_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_29_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_29_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_29_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_29_downstream_read),
      .reg_downstream_write            (system_0_burst_29_downstream_write),
      .reg_downstream_writedata        (system_0_burst_29_downstream_writedata),
      .reset_n                         (system_0_burst_29_downstream_reset_n),
      .upstream_address                (system_0_burst_29_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_29_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_29_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_29_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_29_upstream_address),
      .upstream_read                   (system_0_burst_29_upstream_read),
      .upstream_readdata               (system_0_burst_29_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_29_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_29_upstream_waitrequest),
      .upstream_write                  (system_0_burst_29_upstream_write),
      .upstream_writedata              (system_0_burst_29_upstream_writedata)
    );

  system_0_burst_3_upstream_arbitrator the_system_0_burst_3_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_byteenable_system_0_burst_3_upstream                      (cpu_0_data_master_byteenable_system_0_burst_3_upstream),
      .cpu_0_data_master_dbs_address                                               (cpu_0_data_master_dbs_address),
      .cpu_0_data_master_dbs_write_8                                               (cpu_0_data_master_dbs_write_8),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_3_upstream                         (cpu_0_data_master_granted_system_0_burst_3_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_3_upstream               (cpu_0_data_master_qualified_request_system_0_burst_3_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream                 (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_3_upstream                        (cpu_0_data_master_requests_system_0_burst_3_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .d1_system_0_burst_3_upstream_end_xfer                                       (d1_system_0_burst_3_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_3_upstream_address                                           (system_0_burst_3_upstream_address),
      .system_0_burst_3_upstream_burstcount                                        (system_0_burst_3_upstream_burstcount),
      .system_0_burst_3_upstream_byteaddress                                       (system_0_burst_3_upstream_byteaddress),
      .system_0_burst_3_upstream_byteenable                                        (system_0_burst_3_upstream_byteenable),
      .system_0_burst_3_upstream_debugaccess                                       (system_0_burst_3_upstream_debugaccess),
      .system_0_burst_3_upstream_read                                              (system_0_burst_3_upstream_read),
      .system_0_burst_3_upstream_readdata                                          (system_0_burst_3_upstream_readdata),
      .system_0_burst_3_upstream_readdata_from_sa                                  (system_0_burst_3_upstream_readdata_from_sa),
      .system_0_burst_3_upstream_readdatavalid                                     (system_0_burst_3_upstream_readdatavalid),
      .system_0_burst_3_upstream_waitrequest                                       (system_0_burst_3_upstream_waitrequest),
      .system_0_burst_3_upstream_waitrequest_from_sa                               (system_0_burst_3_upstream_waitrequest_from_sa),
      .system_0_burst_3_upstream_write                                             (system_0_burst_3_upstream_write),
      .system_0_burst_3_upstream_writedata                                         (system_0_burst_3_upstream_writedata)
    );

  system_0_burst_3_downstream_arbitrator the_system_0_burst_3_downstream
    (
      .cfi_flash_0_s1_wait_counter_eq_0                             (cfi_flash_0_s1_wait_counter_eq_0),
      .clk                                                          (altpll_0_c1_out),
      .d1_tri_state_bridge_0_avalon_slave_end_xfer                  (d1_tri_state_bridge_0_avalon_slave_end_xfer),
      .incoming_tri_state_bridge_0_data_with_Xs_converted_to_0      (incoming_tri_state_bridge_0_data_with_Xs_converted_to_0),
      .reset_n                                                      (altpll_0_c1_out_reset_n),
      .system_0_burst_3_downstream_address                          (system_0_burst_3_downstream_address),
      .system_0_burst_3_downstream_address_to_slave                 (system_0_burst_3_downstream_address_to_slave),
      .system_0_burst_3_downstream_burstcount                       (system_0_burst_3_downstream_burstcount),
      .system_0_burst_3_downstream_byteenable                       (system_0_burst_3_downstream_byteenable),
      .system_0_burst_3_downstream_granted_cfi_flash_0_s1           (system_0_burst_3_downstream_granted_cfi_flash_0_s1),
      .system_0_burst_3_downstream_latency_counter                  (system_0_burst_3_downstream_latency_counter),
      .system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1 (system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1),
      .system_0_burst_3_downstream_read                             (system_0_burst_3_downstream_read),
      .system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1   (system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1),
      .system_0_burst_3_downstream_readdata                         (system_0_burst_3_downstream_readdata),
      .system_0_burst_3_downstream_readdatavalid                    (system_0_burst_3_downstream_readdatavalid),
      .system_0_burst_3_downstream_requests_cfi_flash_0_s1          (system_0_burst_3_downstream_requests_cfi_flash_0_s1),
      .system_0_burst_3_downstream_reset_n                          (system_0_burst_3_downstream_reset_n),
      .system_0_burst_3_downstream_waitrequest                      (system_0_burst_3_downstream_waitrequest),
      .system_0_burst_3_downstream_write                            (system_0_burst_3_downstream_write),
      .system_0_burst_3_downstream_writedata                        (system_0_burst_3_downstream_writedata)
    );

  system_0_burst_3 the_system_0_burst_3
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_3_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_3_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_3_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_3_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_3_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_3_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_3_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_3_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_3_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_3_downstream_read),
      .reg_downstream_write            (system_0_burst_3_downstream_write),
      .reg_downstream_writedata        (system_0_burst_3_downstream_writedata),
      .reset_n                         (system_0_burst_3_downstream_reset_n),
      .upstream_address                (system_0_burst_3_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_3_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_3_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_3_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_3_upstream_address),
      .upstream_read                   (system_0_burst_3_upstream_read),
      .upstream_readdata               (system_0_burst_3_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_3_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_3_upstream_waitrequest),
      .upstream_write                  (system_0_burst_3_upstream_write),
      .upstream_writedata              (system_0_burst_3_upstream_writedata)
    );

  system_0_burst_30_upstream_arbitrator the_system_0_burst_30_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_30_upstream                        (cpu_0_data_master_granted_system_0_burst_30_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_30_upstream              (cpu_0_data_master_qualified_request_system_0_burst_30_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_30_upstream                       (cpu_0_data_master_requests_system_0_burst_30_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_30_upstream_end_xfer                                      (d1_system_0_burst_30_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_30_upstream_address                                          (system_0_burst_30_upstream_address),
      .system_0_burst_30_upstream_burstcount                                       (system_0_burst_30_upstream_burstcount),
      .system_0_burst_30_upstream_byteaddress                                      (system_0_burst_30_upstream_byteaddress),
      .system_0_burst_30_upstream_byteenable                                       (system_0_burst_30_upstream_byteenable),
      .system_0_burst_30_upstream_debugaccess                                      (system_0_burst_30_upstream_debugaccess),
      .system_0_burst_30_upstream_read                                             (system_0_burst_30_upstream_read),
      .system_0_burst_30_upstream_readdata                                         (system_0_burst_30_upstream_readdata),
      .system_0_burst_30_upstream_readdata_from_sa                                 (system_0_burst_30_upstream_readdata_from_sa),
      .system_0_burst_30_upstream_readdatavalid                                    (system_0_burst_30_upstream_readdatavalid),
      .system_0_burst_30_upstream_waitrequest                                      (system_0_burst_30_upstream_waitrequest),
      .system_0_burst_30_upstream_waitrequest_from_sa                              (system_0_burst_30_upstream_waitrequest_from_sa),
      .system_0_burst_30_upstream_write                                            (system_0_burst_30_upstream_write),
      .system_0_burst_30_upstream_writedata                                        (system_0_burst_30_upstream_writedata)
    );

  system_0_burst_30_downstream_arbitrator the_system_0_burst_30_downstream
    (
      .Oct_UP_s1_readdata_from_sa                               (Oct_UP_s1_readdata_from_sa),
      .clk                                                      (altpll_0_c1_out),
      .d1_Oct_UP_s1_end_xfer                                    (d1_Oct_UP_s1_end_xfer),
      .reset_n                                                  (altpll_0_c1_out_reset_n),
      .system_0_burst_30_downstream_address                     (system_0_burst_30_downstream_address),
      .system_0_burst_30_downstream_address_to_slave            (system_0_burst_30_downstream_address_to_slave),
      .system_0_burst_30_downstream_burstcount                  (system_0_burst_30_downstream_burstcount),
      .system_0_burst_30_downstream_byteenable                  (system_0_burst_30_downstream_byteenable),
      .system_0_burst_30_downstream_granted_Oct_UP_s1           (system_0_burst_30_downstream_granted_Oct_UP_s1),
      .system_0_burst_30_downstream_latency_counter             (system_0_burst_30_downstream_latency_counter),
      .system_0_burst_30_downstream_qualified_request_Oct_UP_s1 (system_0_burst_30_downstream_qualified_request_Oct_UP_s1),
      .system_0_burst_30_downstream_read                        (system_0_burst_30_downstream_read),
      .system_0_burst_30_downstream_read_data_valid_Oct_UP_s1   (system_0_burst_30_downstream_read_data_valid_Oct_UP_s1),
      .system_0_burst_30_downstream_readdata                    (system_0_burst_30_downstream_readdata),
      .system_0_burst_30_downstream_readdatavalid               (system_0_burst_30_downstream_readdatavalid),
      .system_0_burst_30_downstream_requests_Oct_UP_s1          (system_0_burst_30_downstream_requests_Oct_UP_s1),
      .system_0_burst_30_downstream_reset_n                     (system_0_burst_30_downstream_reset_n),
      .system_0_burst_30_downstream_waitrequest                 (system_0_burst_30_downstream_waitrequest),
      .system_0_burst_30_downstream_write                       (system_0_burst_30_downstream_write),
      .system_0_burst_30_downstream_writedata                   (system_0_burst_30_downstream_writedata)
    );

  system_0_burst_30 the_system_0_burst_30
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_30_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_30_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_30_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_30_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_30_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_30_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_30_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_30_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_30_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_30_downstream_read),
      .reg_downstream_write            (system_0_burst_30_downstream_write),
      .reg_downstream_writedata        (system_0_burst_30_downstream_writedata),
      .reset_n                         (system_0_burst_30_downstream_reset_n),
      .upstream_address                (system_0_burst_30_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_30_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_30_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_30_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_30_upstream_address),
      .upstream_read                   (system_0_burst_30_upstream_read),
      .upstream_readdata               (system_0_burst_30_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_30_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_30_upstream_waitrequest),
      .upstream_write                  (system_0_burst_30_upstream_write),
      .upstream_writedata              (system_0_burst_30_upstream_writedata)
    );

  system_0_burst_31_upstream_arbitrator the_system_0_burst_31_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_31_upstream                        (cpu_0_data_master_granted_system_0_burst_31_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_31_upstream              (cpu_0_data_master_qualified_request_system_0_burst_31_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_31_upstream                       (cpu_0_data_master_requests_system_0_burst_31_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_31_upstream_end_xfer                                      (d1_system_0_burst_31_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_31_upstream_address                                          (system_0_burst_31_upstream_address),
      .system_0_burst_31_upstream_burstcount                                       (system_0_burst_31_upstream_burstcount),
      .system_0_burst_31_upstream_byteaddress                                      (system_0_burst_31_upstream_byteaddress),
      .system_0_burst_31_upstream_byteenable                                       (system_0_burst_31_upstream_byteenable),
      .system_0_burst_31_upstream_debugaccess                                      (system_0_burst_31_upstream_debugaccess),
      .system_0_burst_31_upstream_read                                             (system_0_burst_31_upstream_read),
      .system_0_burst_31_upstream_readdata                                         (system_0_burst_31_upstream_readdata),
      .system_0_burst_31_upstream_readdata_from_sa                                 (system_0_burst_31_upstream_readdata_from_sa),
      .system_0_burst_31_upstream_readdatavalid                                    (system_0_burst_31_upstream_readdatavalid),
      .system_0_burst_31_upstream_waitrequest                                      (system_0_burst_31_upstream_waitrequest),
      .system_0_burst_31_upstream_waitrequest_from_sa                              (system_0_burst_31_upstream_waitrequest_from_sa),
      .system_0_burst_31_upstream_write                                            (system_0_burst_31_upstream_write),
      .system_0_burst_31_upstream_writedata                                        (system_0_burst_31_upstream_writedata)
    );

  system_0_burst_31_downstream_arbitrator the_system_0_burst_31_downstream
    (
      .Oct_DOWN_s1_readdata_from_sa                               (Oct_DOWN_s1_readdata_from_sa),
      .clk                                                        (altpll_0_c1_out),
      .d1_Oct_DOWN_s1_end_xfer                                    (d1_Oct_DOWN_s1_end_xfer),
      .reset_n                                                    (altpll_0_c1_out_reset_n),
      .system_0_burst_31_downstream_address                       (system_0_burst_31_downstream_address),
      .system_0_burst_31_downstream_address_to_slave              (system_0_burst_31_downstream_address_to_slave),
      .system_0_burst_31_downstream_burstcount                    (system_0_burst_31_downstream_burstcount),
      .system_0_burst_31_downstream_byteenable                    (system_0_burst_31_downstream_byteenable),
      .system_0_burst_31_downstream_granted_Oct_DOWN_s1           (system_0_burst_31_downstream_granted_Oct_DOWN_s1),
      .system_0_burst_31_downstream_latency_counter               (system_0_burst_31_downstream_latency_counter),
      .system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1 (system_0_burst_31_downstream_qualified_request_Oct_DOWN_s1),
      .system_0_burst_31_downstream_read                          (system_0_burst_31_downstream_read),
      .system_0_burst_31_downstream_read_data_valid_Oct_DOWN_s1   (system_0_burst_31_downstream_read_data_valid_Oct_DOWN_s1),
      .system_0_burst_31_downstream_readdata                      (system_0_burst_31_downstream_readdata),
      .system_0_burst_31_downstream_readdatavalid                 (system_0_burst_31_downstream_readdatavalid),
      .system_0_burst_31_downstream_requests_Oct_DOWN_s1          (system_0_burst_31_downstream_requests_Oct_DOWN_s1),
      .system_0_burst_31_downstream_reset_n                       (system_0_burst_31_downstream_reset_n),
      .system_0_burst_31_downstream_waitrequest                   (system_0_burst_31_downstream_waitrequest),
      .system_0_burst_31_downstream_write                         (system_0_burst_31_downstream_write),
      .system_0_burst_31_downstream_writedata                     (system_0_burst_31_downstream_writedata)
    );

  system_0_burst_31 the_system_0_burst_31
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_31_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_31_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_31_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_31_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_31_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_31_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_31_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_31_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_31_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_31_downstream_read),
      .reg_downstream_write            (system_0_burst_31_downstream_write),
      .reg_downstream_writedata        (system_0_burst_31_downstream_writedata),
      .reset_n                         (system_0_burst_31_downstream_reset_n),
      .upstream_address                (system_0_burst_31_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_31_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_31_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_31_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_31_upstream_address),
      .upstream_read                   (system_0_burst_31_upstream_read),
      .upstream_readdata               (system_0_burst_31_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_31_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_31_upstream_waitrequest),
      .upstream_write                  (system_0_burst_31_upstream_write),
      .upstream_writedata              (system_0_burst_31_upstream_writedata)
    );

  system_0_burst_32_upstream_arbitrator the_system_0_burst_32_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_32_upstream                        (cpu_0_data_master_granted_system_0_burst_32_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_32_upstream              (cpu_0_data_master_qualified_request_system_0_burst_32_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_32_upstream                       (cpu_0_data_master_requests_system_0_burst_32_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_32_upstream_end_xfer                                      (d1_system_0_burst_32_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_32_upstream_address                                          (system_0_burst_32_upstream_address),
      .system_0_burst_32_upstream_burstcount                                       (system_0_burst_32_upstream_burstcount),
      .system_0_burst_32_upstream_byteaddress                                      (system_0_burst_32_upstream_byteaddress),
      .system_0_burst_32_upstream_byteenable                                       (system_0_burst_32_upstream_byteenable),
      .system_0_burst_32_upstream_debugaccess                                      (system_0_burst_32_upstream_debugaccess),
      .system_0_burst_32_upstream_read                                             (system_0_burst_32_upstream_read),
      .system_0_burst_32_upstream_readdata                                         (system_0_burst_32_upstream_readdata),
      .system_0_burst_32_upstream_readdata_from_sa                                 (system_0_burst_32_upstream_readdata_from_sa),
      .system_0_burst_32_upstream_readdatavalid                                    (system_0_burst_32_upstream_readdatavalid),
      .system_0_burst_32_upstream_waitrequest                                      (system_0_burst_32_upstream_waitrequest),
      .system_0_burst_32_upstream_waitrequest_from_sa                              (system_0_burst_32_upstream_waitrequest_from_sa),
      .system_0_burst_32_upstream_write                                            (system_0_burst_32_upstream_write),
      .system_0_burst_32_upstream_writedata                                        (system_0_burst_32_upstream_writedata)
    );

  system_0_burst_32_downstream_arbitrator the_system_0_burst_32_downstream
    (
      .Accel_Control_avalon_slave_readdata_from_sa                               (Accel_Control_avalon_slave_readdata_from_sa),
      .clk                                                                       (altpll_0_c1_out),
      .d1_Accel_Control_avalon_slave_end_xfer                                    (d1_Accel_Control_avalon_slave_end_xfer),
      .reset_n                                                                   (altpll_0_c1_out_reset_n),
      .system_0_burst_32_downstream_address                                      (system_0_burst_32_downstream_address),
      .system_0_burst_32_downstream_address_to_slave                             (system_0_burst_32_downstream_address_to_slave),
      .system_0_burst_32_downstream_burstcount                                   (system_0_burst_32_downstream_burstcount),
      .system_0_burst_32_downstream_byteenable                                   (system_0_burst_32_downstream_byteenable),
      .system_0_burst_32_downstream_granted_Accel_Control_avalon_slave           (system_0_burst_32_downstream_granted_Accel_Control_avalon_slave),
      .system_0_burst_32_downstream_latency_counter                              (system_0_burst_32_downstream_latency_counter),
      .system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave (system_0_burst_32_downstream_qualified_request_Accel_Control_avalon_slave),
      .system_0_burst_32_downstream_read                                         (system_0_burst_32_downstream_read),
      .system_0_burst_32_downstream_read_data_valid_Accel_Control_avalon_slave   (system_0_burst_32_downstream_read_data_valid_Accel_Control_avalon_slave),
      .system_0_burst_32_downstream_readdata                                     (system_0_burst_32_downstream_readdata),
      .system_0_burst_32_downstream_readdatavalid                                (system_0_burst_32_downstream_readdatavalid),
      .system_0_burst_32_downstream_requests_Accel_Control_avalon_slave          (system_0_burst_32_downstream_requests_Accel_Control_avalon_slave),
      .system_0_burst_32_downstream_reset_n                                      (system_0_burst_32_downstream_reset_n),
      .system_0_burst_32_downstream_waitrequest                                  (system_0_burst_32_downstream_waitrequest),
      .system_0_burst_32_downstream_write                                        (system_0_burst_32_downstream_write),
      .system_0_burst_32_downstream_writedata                                    (system_0_burst_32_downstream_writedata)
    );

  system_0_burst_32 the_system_0_burst_32
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_32_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_32_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_32_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_32_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_32_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_32_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_32_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_32_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_32_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_32_downstream_read),
      .reg_downstream_write            (system_0_burst_32_downstream_write),
      .reg_downstream_writedata        (system_0_burst_32_downstream_writedata),
      .reset_n                         (system_0_burst_32_downstream_reset_n),
      .upstream_address                (system_0_burst_32_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_32_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_32_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_32_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_32_upstream_address),
      .upstream_read                   (system_0_burst_32_upstream_read),
      .upstream_readdata               (system_0_burst_32_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_32_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_32_upstream_waitrequest),
      .upstream_write                  (system_0_burst_32_upstream_write),
      .upstream_writedata              (system_0_burst_32_upstream_writedata)
    );

  system_0_burst_33_upstream_arbitrator the_system_0_burst_33_upstream
    (
      .clk                                                                                (altpll_0_c1_out),
      .cpu_0_instruction_master_address_to_slave                                          (cpu_0_instruction_master_address_to_slave),
      .cpu_0_instruction_master_burstcount                                                (cpu_0_instruction_master_burstcount),
      .cpu_0_instruction_master_granted_system_0_burst_33_upstream                        (cpu_0_instruction_master_granted_system_0_burst_33_upstream),
      .cpu_0_instruction_master_latency_counter                                           (cpu_0_instruction_master_latency_counter),
      .cpu_0_instruction_master_qualified_request_system_0_burst_33_upstream              (cpu_0_instruction_master_qualified_request_system_0_burst_33_upstream),
      .cpu_0_instruction_master_read                                                      (cpu_0_instruction_master_read),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register (cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream                (cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register (cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register),
      .cpu_0_instruction_master_requests_system_0_burst_33_upstream                       (cpu_0_instruction_master_requests_system_0_burst_33_upstream),
      .d1_system_0_burst_33_upstream_end_xfer                                             (d1_system_0_burst_33_upstream_end_xfer),
      .reset_n                                                                            (altpll_0_c1_out_reset_n),
      .system_0_burst_33_upstream_address                                                 (system_0_burst_33_upstream_address),
      .system_0_burst_33_upstream_byteaddress                                             (system_0_burst_33_upstream_byteaddress),
      .system_0_burst_33_upstream_byteenable                                              (system_0_burst_33_upstream_byteenable),
      .system_0_burst_33_upstream_debugaccess                                             (system_0_burst_33_upstream_debugaccess),
      .system_0_burst_33_upstream_read                                                    (system_0_burst_33_upstream_read),
      .system_0_burst_33_upstream_readdata                                                (system_0_burst_33_upstream_readdata),
      .system_0_burst_33_upstream_readdata_from_sa                                        (system_0_burst_33_upstream_readdata_from_sa),
      .system_0_burst_33_upstream_readdatavalid                                           (system_0_burst_33_upstream_readdatavalid),
      .system_0_burst_33_upstream_waitrequest                                             (system_0_burst_33_upstream_waitrequest),
      .system_0_burst_33_upstream_waitrequest_from_sa                                     (system_0_burst_33_upstream_waitrequest_from_sa),
      .system_0_burst_33_upstream_write                                                   (system_0_burst_33_upstream_write)
    );

  system_0_burst_33_downstream_arbitrator the_system_0_burst_33_downstream
    (
      .clk                                                                      (altpll_0_c1_out),
      .d1_i2c_master_avalon_slave_0_end_xfer                                    (d1_i2c_master_avalon_slave_0_end_xfer),
      .i2c_master_avalon_slave_0_readdata_from_sa                               (i2c_master_avalon_slave_0_readdata_from_sa),
      .i2c_master_avalon_slave_0_waitrequest_n_from_sa                          (i2c_master_avalon_slave_0_waitrequest_n_from_sa),
      .reset_n                                                                  (altpll_0_c1_out_reset_n),
      .system_0_burst_33_downstream_address                                     (system_0_burst_33_downstream_address),
      .system_0_burst_33_downstream_address_to_slave                            (system_0_burst_33_downstream_address_to_slave),
      .system_0_burst_33_downstream_burstcount                                  (system_0_burst_33_downstream_burstcount),
      .system_0_burst_33_downstream_byteenable                                  (system_0_burst_33_downstream_byteenable),
      .system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0           (system_0_burst_33_downstream_granted_i2c_master_avalon_slave_0),
      .system_0_burst_33_downstream_latency_counter                             (system_0_burst_33_downstream_latency_counter),
      .system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0 (system_0_burst_33_downstream_qualified_request_i2c_master_avalon_slave_0),
      .system_0_burst_33_downstream_read                                        (system_0_burst_33_downstream_read),
      .system_0_burst_33_downstream_read_data_valid_i2c_master_avalon_slave_0   (system_0_burst_33_downstream_read_data_valid_i2c_master_avalon_slave_0),
      .system_0_burst_33_downstream_readdata                                    (system_0_burst_33_downstream_readdata),
      .system_0_burst_33_downstream_readdatavalid                               (system_0_burst_33_downstream_readdatavalid),
      .system_0_burst_33_downstream_requests_i2c_master_avalon_slave_0          (system_0_burst_33_downstream_requests_i2c_master_avalon_slave_0),
      .system_0_burst_33_downstream_reset_n                                     (system_0_burst_33_downstream_reset_n),
      .system_0_burst_33_downstream_waitrequest                                 (system_0_burst_33_downstream_waitrequest),
      .system_0_burst_33_downstream_write                                       (system_0_burst_33_downstream_write),
      .system_0_burst_33_downstream_writedata                                   (system_0_burst_33_downstream_writedata)
    );

  system_0_burst_33 the_system_0_burst_33
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_33_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_33_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_33_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_33_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_33_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_33_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_33_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_33_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_33_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_33_downstream_read),
      .reg_downstream_write            (system_0_burst_33_downstream_write),
      .reg_downstream_writedata        (system_0_burst_33_downstream_writedata),
      .reset_n                         (system_0_burst_33_downstream_reset_n),
      .upstream_address                (system_0_burst_33_upstream_byteaddress),
      .upstream_byteenable             (system_0_burst_33_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_33_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_33_upstream_address),
      .upstream_read                   (system_0_burst_33_upstream_read),
      .upstream_readdata               (system_0_burst_33_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_33_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_33_upstream_waitrequest),
      .upstream_write                  (system_0_burst_33_upstream_write),
      .upstream_writedata              (system_0_burst_33_upstream_writedata)
    );

  system_0_burst_34_upstream_arbitrator the_system_0_burst_34_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_34_upstream                        (cpu_0_data_master_granted_system_0_burst_34_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_34_upstream              (cpu_0_data_master_qualified_request_system_0_burst_34_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_34_upstream                       (cpu_0_data_master_requests_system_0_burst_34_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_34_upstream_end_xfer                                      (d1_system_0_burst_34_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_34_upstream_address                                          (system_0_burst_34_upstream_address),
      .system_0_burst_34_upstream_burstcount                                       (system_0_burst_34_upstream_burstcount),
      .system_0_burst_34_upstream_byteaddress                                      (system_0_burst_34_upstream_byteaddress),
      .system_0_burst_34_upstream_byteenable                                       (system_0_burst_34_upstream_byteenable),
      .system_0_burst_34_upstream_debugaccess                                      (system_0_burst_34_upstream_debugaccess),
      .system_0_burst_34_upstream_read                                             (system_0_burst_34_upstream_read),
      .system_0_burst_34_upstream_readdata                                         (system_0_burst_34_upstream_readdata),
      .system_0_burst_34_upstream_readdata_from_sa                                 (system_0_burst_34_upstream_readdata_from_sa),
      .system_0_burst_34_upstream_readdatavalid                                    (system_0_burst_34_upstream_readdatavalid),
      .system_0_burst_34_upstream_waitrequest                                      (system_0_burst_34_upstream_waitrequest),
      .system_0_burst_34_upstream_waitrequest_from_sa                              (system_0_burst_34_upstream_waitrequest_from_sa),
      .system_0_burst_34_upstream_write                                            (system_0_burst_34_upstream_write),
      .system_0_burst_34_upstream_writedata                                        (system_0_burst_34_upstream_writedata)
    );

  system_0_burst_34_downstream_arbitrator the_system_0_burst_34_downstream
    (
      .clk                                                                      (altpll_0_c1_out),
      .d1_i2c_master_avalon_slave_0_end_xfer                                    (d1_i2c_master_avalon_slave_0_end_xfer),
      .i2c_master_avalon_slave_0_readdata_from_sa                               (i2c_master_avalon_slave_0_readdata_from_sa),
      .i2c_master_avalon_slave_0_waitrequest_n_from_sa                          (i2c_master_avalon_slave_0_waitrequest_n_from_sa),
      .reset_n                                                                  (altpll_0_c1_out_reset_n),
      .system_0_burst_34_downstream_address                                     (system_0_burst_34_downstream_address),
      .system_0_burst_34_downstream_address_to_slave                            (system_0_burst_34_downstream_address_to_slave),
      .system_0_burst_34_downstream_burstcount                                  (system_0_burst_34_downstream_burstcount),
      .system_0_burst_34_downstream_byteenable                                  (system_0_burst_34_downstream_byteenable),
      .system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0           (system_0_burst_34_downstream_granted_i2c_master_avalon_slave_0),
      .system_0_burst_34_downstream_latency_counter                             (system_0_burst_34_downstream_latency_counter),
      .system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0 (system_0_burst_34_downstream_qualified_request_i2c_master_avalon_slave_0),
      .system_0_burst_34_downstream_read                                        (system_0_burst_34_downstream_read),
      .system_0_burst_34_downstream_read_data_valid_i2c_master_avalon_slave_0   (system_0_burst_34_downstream_read_data_valid_i2c_master_avalon_slave_0),
      .system_0_burst_34_downstream_readdata                                    (system_0_burst_34_downstream_readdata),
      .system_0_burst_34_downstream_readdatavalid                               (system_0_burst_34_downstream_readdatavalid),
      .system_0_burst_34_downstream_requests_i2c_master_avalon_slave_0          (system_0_burst_34_downstream_requests_i2c_master_avalon_slave_0),
      .system_0_burst_34_downstream_reset_n                                     (system_0_burst_34_downstream_reset_n),
      .system_0_burst_34_downstream_waitrequest                                 (system_0_burst_34_downstream_waitrequest),
      .system_0_burst_34_downstream_write                                       (system_0_burst_34_downstream_write),
      .system_0_burst_34_downstream_writedata                                   (system_0_burst_34_downstream_writedata)
    );

  system_0_burst_34 the_system_0_burst_34
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_34_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_34_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_34_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_34_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_34_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_34_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_34_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_34_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_34_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_34_downstream_read),
      .reg_downstream_write            (system_0_burst_34_downstream_write),
      .reg_downstream_writedata        (system_0_burst_34_downstream_writedata),
      .reset_n                         (system_0_burst_34_downstream_reset_n),
      .upstream_address                (system_0_burst_34_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_34_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_34_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_34_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_34_upstream_address),
      .upstream_read                   (system_0_burst_34_upstream_read),
      .upstream_readdata               (system_0_burst_34_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_34_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_34_upstream_waitrequest),
      .upstream_write                  (system_0_burst_34_upstream_write),
      .upstream_writedata              (system_0_burst_34_upstream_writedata)
    );

  system_0_burst_35_upstream_arbitrator the_system_0_burst_35_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_35_upstream                        (cpu_0_data_master_granted_system_0_burst_35_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_35_upstream              (cpu_0_data_master_qualified_request_system_0_burst_35_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream                (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_35_upstream                       (cpu_0_data_master_requests_system_0_burst_35_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_35_upstream_end_xfer                                      (d1_system_0_burst_35_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_35_upstream_address                                          (system_0_burst_35_upstream_address),
      .system_0_burst_35_upstream_burstcount                                       (system_0_burst_35_upstream_burstcount),
      .system_0_burst_35_upstream_byteaddress                                      (system_0_burst_35_upstream_byteaddress),
      .system_0_burst_35_upstream_byteenable                                       (system_0_burst_35_upstream_byteenable),
      .system_0_burst_35_upstream_debugaccess                                      (system_0_burst_35_upstream_debugaccess),
      .system_0_burst_35_upstream_read                                             (system_0_burst_35_upstream_read),
      .system_0_burst_35_upstream_readdata                                         (system_0_burst_35_upstream_readdata),
      .system_0_burst_35_upstream_readdata_from_sa                                 (system_0_burst_35_upstream_readdata_from_sa),
      .system_0_burst_35_upstream_readdatavalid                                    (system_0_burst_35_upstream_readdatavalid),
      .system_0_burst_35_upstream_waitrequest                                      (system_0_burst_35_upstream_waitrequest),
      .system_0_burst_35_upstream_waitrequest_from_sa                              (system_0_burst_35_upstream_waitrequest_from_sa),
      .system_0_burst_35_upstream_write                                            (system_0_burst_35_upstream_write),
      .system_0_burst_35_upstream_writedata                                        (system_0_burst_35_upstream_writedata)
    );

  system_0_burst_35_downstream_arbitrator the_system_0_burst_35_downstream
    (
      .clk                                                                (altpll_0_c1_out),
      .d1_system_0_clock_0_in_end_xfer                                    (d1_system_0_clock_0_in_end_xfer),
      .reset_n                                                            (altpll_0_c1_out_reset_n),
      .system_0_burst_35_downstream_address                               (system_0_burst_35_downstream_address),
      .system_0_burst_35_downstream_address_to_slave                      (system_0_burst_35_downstream_address_to_slave),
      .system_0_burst_35_downstream_burstcount                            (system_0_burst_35_downstream_burstcount),
      .system_0_burst_35_downstream_byteenable                            (system_0_burst_35_downstream_byteenable),
      .system_0_burst_35_downstream_granted_system_0_clock_0_in           (system_0_burst_35_downstream_granted_system_0_clock_0_in),
      .system_0_burst_35_downstream_latency_counter                       (system_0_burst_35_downstream_latency_counter),
      .system_0_burst_35_downstream_qualified_request_system_0_clock_0_in (system_0_burst_35_downstream_qualified_request_system_0_clock_0_in),
      .system_0_burst_35_downstream_read                                  (system_0_burst_35_downstream_read),
      .system_0_burst_35_downstream_read_data_valid_system_0_clock_0_in   (system_0_burst_35_downstream_read_data_valid_system_0_clock_0_in),
      .system_0_burst_35_downstream_readdata                              (system_0_burst_35_downstream_readdata),
      .system_0_burst_35_downstream_readdatavalid                         (system_0_burst_35_downstream_readdatavalid),
      .system_0_burst_35_downstream_requests_system_0_clock_0_in          (system_0_burst_35_downstream_requests_system_0_clock_0_in),
      .system_0_burst_35_downstream_reset_n                               (system_0_burst_35_downstream_reset_n),
      .system_0_burst_35_downstream_waitrequest                           (system_0_burst_35_downstream_waitrequest),
      .system_0_burst_35_downstream_write                                 (system_0_burst_35_downstream_write),
      .system_0_burst_35_downstream_writedata                             (system_0_burst_35_downstream_writedata),
      .system_0_clock_0_in_readdata_from_sa                               (system_0_clock_0_in_readdata_from_sa),
      .system_0_clock_0_in_waitrequest_from_sa                            (system_0_clock_0_in_waitrequest_from_sa)
    );

  system_0_burst_35 the_system_0_burst_35
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_35_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_35_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_35_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_35_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_35_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_35_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_35_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_35_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_35_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_35_downstream_read),
      .reg_downstream_write            (system_0_burst_35_downstream_write),
      .reg_downstream_writedata        (system_0_burst_35_downstream_writedata),
      .reset_n                         (system_0_burst_35_downstream_reset_n),
      .upstream_address                (system_0_burst_35_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_35_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_35_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_35_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_35_upstream_address),
      .upstream_read                   (system_0_burst_35_upstream_read),
      .upstream_readdata               (system_0_burst_35_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_35_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_35_upstream_waitrequest),
      .upstream_write                  (system_0_burst_35_upstream_write),
      .upstream_writedata              (system_0_burst_35_upstream_writedata)
    );

  system_0_burst_4_upstream_arbitrator the_system_0_burst_4_upstream
    (
      .clk                                                                                (altpll_0_c1_out),
      .cpu_0_instruction_master_address_to_slave                                          (cpu_0_instruction_master_address_to_slave),
      .cpu_0_instruction_master_burstcount                                                (cpu_0_instruction_master_burstcount),
      .cpu_0_instruction_master_dbs_address                                               (cpu_0_instruction_master_dbs_address),
      .cpu_0_instruction_master_granted_system_0_burst_4_upstream                         (cpu_0_instruction_master_granted_system_0_burst_4_upstream),
      .cpu_0_instruction_master_latency_counter                                           (cpu_0_instruction_master_latency_counter),
      .cpu_0_instruction_master_qualified_request_system_0_burst_4_upstream               (cpu_0_instruction_master_qualified_request_system_0_burst_4_upstream),
      .cpu_0_instruction_master_read                                                      (cpu_0_instruction_master_read),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register (cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register (cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream                 (cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register),
      .cpu_0_instruction_master_requests_system_0_burst_4_upstream                        (cpu_0_instruction_master_requests_system_0_burst_4_upstream),
      .d1_system_0_burst_4_upstream_end_xfer                                              (d1_system_0_burst_4_upstream_end_xfer),
      .reset_n                                                                            (altpll_0_c1_out_reset_n),
      .system_0_burst_4_upstream_address                                                  (system_0_burst_4_upstream_address),
      .system_0_burst_4_upstream_byteaddress                                              (system_0_burst_4_upstream_byteaddress),
      .system_0_burst_4_upstream_byteenable                                               (system_0_burst_4_upstream_byteenable),
      .system_0_burst_4_upstream_debugaccess                                              (system_0_burst_4_upstream_debugaccess),
      .system_0_burst_4_upstream_read                                                     (system_0_burst_4_upstream_read),
      .system_0_burst_4_upstream_readdata                                                 (system_0_burst_4_upstream_readdata),
      .system_0_burst_4_upstream_readdata_from_sa                                         (system_0_burst_4_upstream_readdata_from_sa),
      .system_0_burst_4_upstream_readdatavalid                                            (system_0_burst_4_upstream_readdatavalid),
      .system_0_burst_4_upstream_waitrequest                                              (system_0_burst_4_upstream_waitrequest),
      .system_0_burst_4_upstream_waitrequest_from_sa                                      (system_0_burst_4_upstream_waitrequest_from_sa),
      .system_0_burst_4_upstream_write                                                    (system_0_burst_4_upstream_write)
    );

  system_0_burst_4_downstream_arbitrator the_system_0_burst_4_downstream
    (
      .clk                                                                   (altpll_0_c1_out),
      .d1_sdram_0_s1_end_xfer                                                (d1_sdram_0_s1_end_xfer),
      .reset_n                                                               (altpll_0_c1_out_reset_n),
      .sdram_0_s1_readdata_from_sa                                           (sdram_0_s1_readdata_from_sa),
      .sdram_0_s1_waitrequest_from_sa                                        (sdram_0_s1_waitrequest_from_sa),
      .system_0_burst_4_downstream_address                                   (system_0_burst_4_downstream_address),
      .system_0_burst_4_downstream_address_to_slave                          (system_0_burst_4_downstream_address_to_slave),
      .system_0_burst_4_downstream_burstcount                                (system_0_burst_4_downstream_burstcount),
      .system_0_burst_4_downstream_byteenable                                (system_0_burst_4_downstream_byteenable),
      .system_0_burst_4_downstream_granted_sdram_0_s1                        (system_0_burst_4_downstream_granted_sdram_0_s1),
      .system_0_burst_4_downstream_latency_counter                           (system_0_burst_4_downstream_latency_counter),
      .system_0_burst_4_downstream_qualified_request_sdram_0_s1              (system_0_burst_4_downstream_qualified_request_sdram_0_s1),
      .system_0_burst_4_downstream_read                                      (system_0_burst_4_downstream_read),
      .system_0_burst_4_downstream_read_data_valid_sdram_0_s1                (system_0_burst_4_downstream_read_data_valid_sdram_0_s1),
      .system_0_burst_4_downstream_read_data_valid_sdram_0_s1_shift_register (system_0_burst_4_downstream_read_data_valid_sdram_0_s1_shift_register),
      .system_0_burst_4_downstream_readdata                                  (system_0_burst_4_downstream_readdata),
      .system_0_burst_4_downstream_readdatavalid                             (system_0_burst_4_downstream_readdatavalid),
      .system_0_burst_4_downstream_requests_sdram_0_s1                       (system_0_burst_4_downstream_requests_sdram_0_s1),
      .system_0_burst_4_downstream_reset_n                                   (system_0_burst_4_downstream_reset_n),
      .system_0_burst_4_downstream_waitrequest                               (system_0_burst_4_downstream_waitrequest),
      .system_0_burst_4_downstream_write                                     (system_0_burst_4_downstream_write),
      .system_0_burst_4_downstream_writedata                                 (system_0_burst_4_downstream_writedata)
    );

  system_0_burst_4 the_system_0_burst_4
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_4_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_4_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_4_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_4_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_4_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_4_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_4_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_4_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_4_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_4_downstream_read),
      .reg_downstream_write            (system_0_burst_4_downstream_write),
      .reg_downstream_writedata        (system_0_burst_4_downstream_writedata),
      .reset_n                         (system_0_burst_4_downstream_reset_n),
      .upstream_address                (system_0_burst_4_upstream_byteaddress),
      .upstream_byteenable             (system_0_burst_4_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_4_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_4_upstream_address),
      .upstream_read                   (system_0_burst_4_upstream_read),
      .upstream_readdata               (system_0_burst_4_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_4_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_4_upstream_waitrequest),
      .upstream_write                  (system_0_burst_4_upstream_write),
      .upstream_writedata              (system_0_burst_4_upstream_writedata)
    );

  system_0_burst_5_upstream_arbitrator the_system_0_burst_5_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_byteenable_system_0_burst_5_upstream                      (cpu_0_data_master_byteenable_system_0_burst_5_upstream),
      .cpu_0_data_master_dbs_address                                               (cpu_0_data_master_dbs_address),
      .cpu_0_data_master_dbs_write_16                                              (cpu_0_data_master_dbs_write_16),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_5_upstream                         (cpu_0_data_master_granted_system_0_burst_5_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_5_upstream               (cpu_0_data_master_qualified_request_system_0_burst_5_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream                 (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_5_upstream                        (cpu_0_data_master_requests_system_0_burst_5_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .d1_system_0_burst_5_upstream_end_xfer                                       (d1_system_0_burst_5_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_5_upstream_address                                           (system_0_burst_5_upstream_address),
      .system_0_burst_5_upstream_burstcount                                        (system_0_burst_5_upstream_burstcount),
      .system_0_burst_5_upstream_byteaddress                                       (system_0_burst_5_upstream_byteaddress),
      .system_0_burst_5_upstream_byteenable                                        (system_0_burst_5_upstream_byteenable),
      .system_0_burst_5_upstream_debugaccess                                       (system_0_burst_5_upstream_debugaccess),
      .system_0_burst_5_upstream_read                                              (system_0_burst_5_upstream_read),
      .system_0_burst_5_upstream_readdata                                          (system_0_burst_5_upstream_readdata),
      .system_0_burst_5_upstream_readdata_from_sa                                  (system_0_burst_5_upstream_readdata_from_sa),
      .system_0_burst_5_upstream_readdatavalid                                     (system_0_burst_5_upstream_readdatavalid),
      .system_0_burst_5_upstream_waitrequest                                       (system_0_burst_5_upstream_waitrequest),
      .system_0_burst_5_upstream_waitrequest_from_sa                               (system_0_burst_5_upstream_waitrequest_from_sa),
      .system_0_burst_5_upstream_write                                             (system_0_burst_5_upstream_write),
      .system_0_burst_5_upstream_writedata                                         (system_0_burst_5_upstream_writedata)
    );

  system_0_burst_5_downstream_arbitrator the_system_0_burst_5_downstream
    (
      .clk                                                                   (altpll_0_c1_out),
      .d1_sdram_0_s1_end_xfer                                                (d1_sdram_0_s1_end_xfer),
      .reset_n                                                               (altpll_0_c1_out_reset_n),
      .sdram_0_s1_readdata_from_sa                                           (sdram_0_s1_readdata_from_sa),
      .sdram_0_s1_waitrequest_from_sa                                        (sdram_0_s1_waitrequest_from_sa),
      .system_0_burst_5_downstream_address                                   (system_0_burst_5_downstream_address),
      .system_0_burst_5_downstream_address_to_slave                          (system_0_burst_5_downstream_address_to_slave),
      .system_0_burst_5_downstream_burstcount                                (system_0_burst_5_downstream_burstcount),
      .system_0_burst_5_downstream_byteenable                                (system_0_burst_5_downstream_byteenable),
      .system_0_burst_5_downstream_granted_sdram_0_s1                        (system_0_burst_5_downstream_granted_sdram_0_s1),
      .system_0_burst_5_downstream_latency_counter                           (system_0_burst_5_downstream_latency_counter),
      .system_0_burst_5_downstream_qualified_request_sdram_0_s1              (system_0_burst_5_downstream_qualified_request_sdram_0_s1),
      .system_0_burst_5_downstream_read                                      (system_0_burst_5_downstream_read),
      .system_0_burst_5_downstream_read_data_valid_sdram_0_s1                (system_0_burst_5_downstream_read_data_valid_sdram_0_s1),
      .system_0_burst_5_downstream_read_data_valid_sdram_0_s1_shift_register (system_0_burst_5_downstream_read_data_valid_sdram_0_s1_shift_register),
      .system_0_burst_5_downstream_readdata                                  (system_0_burst_5_downstream_readdata),
      .system_0_burst_5_downstream_readdatavalid                             (system_0_burst_5_downstream_readdatavalid),
      .system_0_burst_5_downstream_requests_sdram_0_s1                       (system_0_burst_5_downstream_requests_sdram_0_s1),
      .system_0_burst_5_downstream_reset_n                                   (system_0_burst_5_downstream_reset_n),
      .system_0_burst_5_downstream_waitrequest                               (system_0_burst_5_downstream_waitrequest),
      .system_0_burst_5_downstream_write                                     (system_0_burst_5_downstream_write),
      .system_0_burst_5_downstream_writedata                                 (system_0_burst_5_downstream_writedata)
    );

  system_0_burst_5 the_system_0_burst_5
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_5_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_5_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_5_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_5_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_5_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_5_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_5_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_5_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_5_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_5_downstream_read),
      .reg_downstream_write            (system_0_burst_5_downstream_write),
      .reg_downstream_writedata        (system_0_burst_5_downstream_writedata),
      .reset_n                         (system_0_burst_5_downstream_reset_n),
      .upstream_address                (system_0_burst_5_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_5_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_5_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_5_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_5_upstream_address),
      .upstream_read                   (system_0_burst_5_upstream_read),
      .upstream_readdata               (system_0_burst_5_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_5_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_5_upstream_waitrequest),
      .upstream_write                  (system_0_burst_5_upstream_write),
      .upstream_writedata              (system_0_burst_5_upstream_writedata)
    );

  system_0_burst_6_upstream_arbitrator the_system_0_burst_6_upstream
    (
      .clk                                                                                (altpll_0_c1_out),
      .cpu_0_instruction_master_address_to_slave                                          (cpu_0_instruction_master_address_to_slave),
      .cpu_0_instruction_master_burstcount                                                (cpu_0_instruction_master_burstcount),
      .cpu_0_instruction_master_granted_system_0_burst_6_upstream                         (cpu_0_instruction_master_granted_system_0_burst_6_upstream),
      .cpu_0_instruction_master_latency_counter                                           (cpu_0_instruction_master_latency_counter),
      .cpu_0_instruction_master_qualified_request_system_0_burst_6_upstream               (cpu_0_instruction_master_qualified_request_system_0_burst_6_upstream),
      .cpu_0_instruction_master_read                                                      (cpu_0_instruction_master_read),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_0_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register (cpu_0_instruction_master_read_data_valid_system_0_burst_14_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_2_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register (cpu_0_instruction_master_read_data_valid_system_0_burst_33_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_4_upstream_shift_register),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream                 (cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream),
      .cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register  (cpu_0_instruction_master_read_data_valid_system_0_burst_6_upstream_shift_register),
      .cpu_0_instruction_master_requests_system_0_burst_6_upstream                        (cpu_0_instruction_master_requests_system_0_burst_6_upstream),
      .d1_system_0_burst_6_upstream_end_xfer                                              (d1_system_0_burst_6_upstream_end_xfer),
      .reset_n                                                                            (altpll_0_c1_out_reset_n),
      .system_0_burst_6_upstream_address                                                  (system_0_burst_6_upstream_address),
      .system_0_burst_6_upstream_byteaddress                                              (system_0_burst_6_upstream_byteaddress),
      .system_0_burst_6_upstream_byteenable                                               (system_0_burst_6_upstream_byteenable),
      .system_0_burst_6_upstream_debugaccess                                              (system_0_burst_6_upstream_debugaccess),
      .system_0_burst_6_upstream_read                                                     (system_0_burst_6_upstream_read),
      .system_0_burst_6_upstream_readdata                                                 (system_0_burst_6_upstream_readdata),
      .system_0_burst_6_upstream_readdata_from_sa                                         (system_0_burst_6_upstream_readdata_from_sa),
      .system_0_burst_6_upstream_readdatavalid                                            (system_0_burst_6_upstream_readdatavalid),
      .system_0_burst_6_upstream_waitrequest                                              (system_0_burst_6_upstream_waitrequest),
      .system_0_burst_6_upstream_waitrequest_from_sa                                      (system_0_burst_6_upstream_waitrequest_from_sa),
      .system_0_burst_6_upstream_write                                                    (system_0_burst_6_upstream_write)
    );

  system_0_burst_6_downstream_arbitrator the_system_0_burst_6_downstream
    (
      .clk                                                                             (altpll_0_c1_out),
      .d1_epcs_controller_epcs_control_port_end_xfer                                   (d1_epcs_controller_epcs_control_port_end_xfer),
      .epcs_controller_epcs_control_port_readdata_from_sa                              (epcs_controller_epcs_control_port_readdata_from_sa),
      .reset_n                                                                         (altpll_0_c1_out_reset_n),
      .system_0_burst_6_downstream_address                                             (system_0_burst_6_downstream_address),
      .system_0_burst_6_downstream_address_to_slave                                    (system_0_burst_6_downstream_address_to_slave),
      .system_0_burst_6_downstream_burstcount                                          (system_0_burst_6_downstream_burstcount),
      .system_0_burst_6_downstream_byteenable                                          (system_0_burst_6_downstream_byteenable),
      .system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port           (system_0_burst_6_downstream_granted_epcs_controller_epcs_control_port),
      .system_0_burst_6_downstream_latency_counter                                     (system_0_burst_6_downstream_latency_counter),
      .system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port (system_0_burst_6_downstream_qualified_request_epcs_controller_epcs_control_port),
      .system_0_burst_6_downstream_read                                                (system_0_burst_6_downstream_read),
      .system_0_burst_6_downstream_read_data_valid_epcs_controller_epcs_control_port   (system_0_burst_6_downstream_read_data_valid_epcs_controller_epcs_control_port),
      .system_0_burst_6_downstream_readdata                                            (system_0_burst_6_downstream_readdata),
      .system_0_burst_6_downstream_readdatavalid                                       (system_0_burst_6_downstream_readdatavalid),
      .system_0_burst_6_downstream_requests_epcs_controller_epcs_control_port          (system_0_burst_6_downstream_requests_epcs_controller_epcs_control_port),
      .system_0_burst_6_downstream_reset_n                                             (system_0_burst_6_downstream_reset_n),
      .system_0_burst_6_downstream_waitrequest                                         (system_0_burst_6_downstream_waitrequest),
      .system_0_burst_6_downstream_write                                               (system_0_burst_6_downstream_write),
      .system_0_burst_6_downstream_writedata                                           (system_0_burst_6_downstream_writedata)
    );

  system_0_burst_6 the_system_0_burst_6
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_6_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_6_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_6_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_6_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_6_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_6_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_6_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_6_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_6_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_6_downstream_read),
      .reg_downstream_write            (system_0_burst_6_downstream_write),
      .reg_downstream_writedata        (system_0_burst_6_downstream_writedata),
      .reset_n                         (system_0_burst_6_downstream_reset_n),
      .upstream_address                (system_0_burst_6_upstream_byteaddress),
      .upstream_byteenable             (system_0_burst_6_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_6_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_6_upstream_address),
      .upstream_read                   (system_0_burst_6_upstream_read),
      .upstream_readdata               (system_0_burst_6_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_6_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_6_upstream_waitrequest),
      .upstream_write                  (system_0_burst_6_upstream_write),
      .upstream_writedata              (system_0_burst_6_upstream_writedata)
    );

  system_0_burst_7_upstream_arbitrator the_system_0_burst_7_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_7_upstream                         (cpu_0_data_master_granted_system_0_burst_7_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_7_upstream               (cpu_0_data_master_qualified_request_system_0_burst_7_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream                 (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_7_upstream                        (cpu_0_data_master_requests_system_0_burst_7_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_7_upstream_end_xfer                                       (d1_system_0_burst_7_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_7_upstream_address                                           (system_0_burst_7_upstream_address),
      .system_0_burst_7_upstream_burstcount                                        (system_0_burst_7_upstream_burstcount),
      .system_0_burst_7_upstream_byteaddress                                       (system_0_burst_7_upstream_byteaddress),
      .system_0_burst_7_upstream_byteenable                                        (system_0_burst_7_upstream_byteenable),
      .system_0_burst_7_upstream_debugaccess                                       (system_0_burst_7_upstream_debugaccess),
      .system_0_burst_7_upstream_read                                              (system_0_burst_7_upstream_read),
      .system_0_burst_7_upstream_readdata                                          (system_0_burst_7_upstream_readdata),
      .system_0_burst_7_upstream_readdata_from_sa                                  (system_0_burst_7_upstream_readdata_from_sa),
      .system_0_burst_7_upstream_readdatavalid                                     (system_0_burst_7_upstream_readdatavalid),
      .system_0_burst_7_upstream_waitrequest                                       (system_0_burst_7_upstream_waitrequest),
      .system_0_burst_7_upstream_waitrequest_from_sa                               (system_0_burst_7_upstream_waitrequest_from_sa),
      .system_0_burst_7_upstream_write                                             (system_0_burst_7_upstream_write),
      .system_0_burst_7_upstream_writedata                                         (system_0_burst_7_upstream_writedata)
    );

  system_0_burst_7_downstream_arbitrator the_system_0_burst_7_downstream
    (
      .clk                                                                             (altpll_0_c1_out),
      .d1_epcs_controller_epcs_control_port_end_xfer                                   (d1_epcs_controller_epcs_control_port_end_xfer),
      .epcs_controller_epcs_control_port_readdata_from_sa                              (epcs_controller_epcs_control_port_readdata_from_sa),
      .reset_n                                                                         (altpll_0_c1_out_reset_n),
      .system_0_burst_7_downstream_address                                             (system_0_burst_7_downstream_address),
      .system_0_burst_7_downstream_address_to_slave                                    (system_0_burst_7_downstream_address_to_slave),
      .system_0_burst_7_downstream_burstcount                                          (system_0_burst_7_downstream_burstcount),
      .system_0_burst_7_downstream_byteenable                                          (system_0_burst_7_downstream_byteenable),
      .system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port           (system_0_burst_7_downstream_granted_epcs_controller_epcs_control_port),
      .system_0_burst_7_downstream_latency_counter                                     (system_0_burst_7_downstream_latency_counter),
      .system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port (system_0_burst_7_downstream_qualified_request_epcs_controller_epcs_control_port),
      .system_0_burst_7_downstream_read                                                (system_0_burst_7_downstream_read),
      .system_0_burst_7_downstream_read_data_valid_epcs_controller_epcs_control_port   (system_0_burst_7_downstream_read_data_valid_epcs_controller_epcs_control_port),
      .system_0_burst_7_downstream_readdata                                            (system_0_burst_7_downstream_readdata),
      .system_0_burst_7_downstream_readdatavalid                                       (system_0_burst_7_downstream_readdatavalid),
      .system_0_burst_7_downstream_requests_epcs_controller_epcs_control_port          (system_0_burst_7_downstream_requests_epcs_controller_epcs_control_port),
      .system_0_burst_7_downstream_reset_n                                             (system_0_burst_7_downstream_reset_n),
      .system_0_burst_7_downstream_waitrequest                                         (system_0_burst_7_downstream_waitrequest),
      .system_0_burst_7_downstream_write                                               (system_0_burst_7_downstream_write),
      .system_0_burst_7_downstream_writedata                                           (system_0_burst_7_downstream_writedata)
    );

  system_0_burst_7 the_system_0_burst_7
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_7_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_7_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_7_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_7_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_7_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_7_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_7_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_7_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_7_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_7_downstream_read),
      .reg_downstream_write            (system_0_burst_7_downstream_write),
      .reg_downstream_writedata        (system_0_burst_7_downstream_writedata),
      .reset_n                         (system_0_burst_7_downstream_reset_n),
      .upstream_address                (system_0_burst_7_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_7_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_7_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_7_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_7_upstream_address),
      .upstream_read                   (system_0_burst_7_upstream_read),
      .upstream_readdata               (system_0_burst_7_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_7_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_7_upstream_waitrequest),
      .upstream_write                  (system_0_burst_7_upstream_write),
      .upstream_writedata              (system_0_burst_7_upstream_writedata)
    );

  system_0_burst_8_upstream_arbitrator the_system_0_burst_8_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_8_upstream                         (cpu_0_data_master_granted_system_0_burst_8_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_8_upstream               (cpu_0_data_master_qualified_request_system_0_burst_8_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream                 (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_8_upstream                        (cpu_0_data_master_requests_system_0_burst_8_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_8_upstream_end_xfer                                       (d1_system_0_burst_8_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_8_upstream_address                                           (system_0_burst_8_upstream_address),
      .system_0_burst_8_upstream_burstcount                                        (system_0_burst_8_upstream_burstcount),
      .system_0_burst_8_upstream_byteaddress                                       (system_0_burst_8_upstream_byteaddress),
      .system_0_burst_8_upstream_byteenable                                        (system_0_burst_8_upstream_byteenable),
      .system_0_burst_8_upstream_debugaccess                                       (system_0_burst_8_upstream_debugaccess),
      .system_0_burst_8_upstream_read                                              (system_0_burst_8_upstream_read),
      .system_0_burst_8_upstream_readdata                                          (system_0_burst_8_upstream_readdata),
      .system_0_burst_8_upstream_readdata_from_sa                                  (system_0_burst_8_upstream_readdata_from_sa),
      .system_0_burst_8_upstream_readdatavalid                                     (system_0_burst_8_upstream_readdatavalid),
      .system_0_burst_8_upstream_waitrequest                                       (system_0_burst_8_upstream_waitrequest),
      .system_0_burst_8_upstream_waitrequest_from_sa                               (system_0_burst_8_upstream_waitrequest_from_sa),
      .system_0_burst_8_upstream_write                                             (system_0_burst_8_upstream_write),
      .system_0_burst_8_upstream_writedata                                         (system_0_burst_8_upstream_writedata)
    );

  system_0_burst_8_downstream_arbitrator the_system_0_burst_8_downstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .d1_jtag_uart_0_avalon_jtag_slave_end_xfer                                   (d1_jtag_uart_0_avalon_jtag_slave_end_xfer),
      .jtag_uart_0_avalon_jtag_slave_readdata_from_sa                              (jtag_uart_0_avalon_jtag_slave_readdata_from_sa),
      .jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa                           (jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_8_downstream_address                                         (system_0_burst_8_downstream_address),
      .system_0_burst_8_downstream_address_to_slave                                (system_0_burst_8_downstream_address_to_slave),
      .system_0_burst_8_downstream_burstcount                                      (system_0_burst_8_downstream_burstcount),
      .system_0_burst_8_downstream_byteenable                                      (system_0_burst_8_downstream_byteenable),
      .system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave           (system_0_burst_8_downstream_granted_jtag_uart_0_avalon_jtag_slave),
      .system_0_burst_8_downstream_latency_counter                                 (system_0_burst_8_downstream_latency_counter),
      .system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave (system_0_burst_8_downstream_qualified_request_jtag_uart_0_avalon_jtag_slave),
      .system_0_burst_8_downstream_read                                            (system_0_burst_8_downstream_read),
      .system_0_burst_8_downstream_read_data_valid_jtag_uart_0_avalon_jtag_slave   (system_0_burst_8_downstream_read_data_valid_jtag_uart_0_avalon_jtag_slave),
      .system_0_burst_8_downstream_readdata                                        (system_0_burst_8_downstream_readdata),
      .system_0_burst_8_downstream_readdatavalid                                   (system_0_burst_8_downstream_readdatavalid),
      .system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave          (system_0_burst_8_downstream_requests_jtag_uart_0_avalon_jtag_slave),
      .system_0_burst_8_downstream_reset_n                                         (system_0_burst_8_downstream_reset_n),
      .system_0_burst_8_downstream_waitrequest                                     (system_0_burst_8_downstream_waitrequest),
      .system_0_burst_8_downstream_write                                           (system_0_burst_8_downstream_write),
      .system_0_burst_8_downstream_writedata                                       (system_0_burst_8_downstream_writedata)
    );

  system_0_burst_8 the_system_0_burst_8
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_8_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_8_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_8_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_8_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_8_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_8_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_8_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_8_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_8_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_8_downstream_read),
      .reg_downstream_write            (system_0_burst_8_downstream_write),
      .reg_downstream_writedata        (system_0_burst_8_downstream_writedata),
      .reset_n                         (system_0_burst_8_downstream_reset_n),
      .upstream_address                (system_0_burst_8_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_8_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_8_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_8_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_8_upstream_address),
      .upstream_read                   (system_0_burst_8_upstream_read),
      .upstream_readdata               (system_0_burst_8_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_8_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_8_upstream_waitrequest),
      .upstream_write                  (system_0_burst_8_upstream_write),
      .upstream_writedata              (system_0_burst_8_upstream_writedata)
    );

  system_0_burst_9_upstream_arbitrator the_system_0_burst_9_upstream
    (
      .clk                                                                         (altpll_0_c1_out),
      .cpu_0_data_master_address_to_slave                                          (cpu_0_data_master_address_to_slave),
      .cpu_0_data_master_burstcount                                                (cpu_0_data_master_burstcount),
      .cpu_0_data_master_byteenable                                                (cpu_0_data_master_byteenable),
      .cpu_0_data_master_debugaccess                                               (cpu_0_data_master_debugaccess),
      .cpu_0_data_master_granted_system_0_burst_9_upstream                         (cpu_0_data_master_granted_system_0_burst_9_upstream),
      .cpu_0_data_master_latency_counter                                           (cpu_0_data_master_latency_counter),
      .cpu_0_data_master_qualified_request_system_0_burst_9_upstream               (cpu_0_data_master_qualified_request_system_0_burst_9_upstream),
      .cpu_0_data_master_read                                                      (cpu_0_data_master_read),
      .cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_10_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_11_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_12_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_13_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_15_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_16_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_17_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_18_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_19_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_1_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_20_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_21_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_22_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_23_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_24_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_25_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_26_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_27_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_28_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_29_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_30_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_31_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_32_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_34_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register (cpu_0_data_master_read_data_valid_system_0_burst_35_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_3_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_5_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_7_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_8_upstream_shift_register),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream                 (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream),
      .cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register  (cpu_0_data_master_read_data_valid_system_0_burst_9_upstream_shift_register),
      .cpu_0_data_master_requests_system_0_burst_9_upstream                        (cpu_0_data_master_requests_system_0_burst_9_upstream),
      .cpu_0_data_master_write                                                     (cpu_0_data_master_write),
      .cpu_0_data_master_writedata                                                 (cpu_0_data_master_writedata),
      .d1_system_0_burst_9_upstream_end_xfer                                       (d1_system_0_burst_9_upstream_end_xfer),
      .reset_n                                                                     (altpll_0_c1_out_reset_n),
      .system_0_burst_9_upstream_address                                           (system_0_burst_9_upstream_address),
      .system_0_burst_9_upstream_burstcount                                        (system_0_burst_9_upstream_burstcount),
      .system_0_burst_9_upstream_byteaddress                                       (system_0_burst_9_upstream_byteaddress),
      .system_0_burst_9_upstream_byteenable                                        (system_0_burst_9_upstream_byteenable),
      .system_0_burst_9_upstream_debugaccess                                       (system_0_burst_9_upstream_debugaccess),
      .system_0_burst_9_upstream_read                                              (system_0_burst_9_upstream_read),
      .system_0_burst_9_upstream_readdata                                          (system_0_burst_9_upstream_readdata),
      .system_0_burst_9_upstream_readdata_from_sa                                  (system_0_burst_9_upstream_readdata_from_sa),
      .system_0_burst_9_upstream_readdatavalid                                     (system_0_burst_9_upstream_readdatavalid),
      .system_0_burst_9_upstream_waitrequest                                       (system_0_burst_9_upstream_waitrequest),
      .system_0_burst_9_upstream_waitrequest_from_sa                               (system_0_burst_9_upstream_waitrequest_from_sa),
      .system_0_burst_9_upstream_write                                             (system_0_burst_9_upstream_write),
      .system_0_burst_9_upstream_writedata                                         (system_0_burst_9_upstream_writedata)
    );

  system_0_burst_9_downstream_arbitrator the_system_0_burst_9_downstream
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_uart_0_s1_end_xfer                                   (d1_uart_0_s1_end_xfer),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_9_downstream_address                     (system_0_burst_9_downstream_address),
      .system_0_burst_9_downstream_address_to_slave            (system_0_burst_9_downstream_address_to_slave),
      .system_0_burst_9_downstream_burstcount                  (system_0_burst_9_downstream_burstcount),
      .system_0_burst_9_downstream_byteenable                  (system_0_burst_9_downstream_byteenable),
      .system_0_burst_9_downstream_granted_uart_0_s1           (system_0_burst_9_downstream_granted_uart_0_s1),
      .system_0_burst_9_downstream_latency_counter             (system_0_burst_9_downstream_latency_counter),
      .system_0_burst_9_downstream_qualified_request_uart_0_s1 (system_0_burst_9_downstream_qualified_request_uart_0_s1),
      .system_0_burst_9_downstream_read                        (system_0_burst_9_downstream_read),
      .system_0_burst_9_downstream_read_data_valid_uart_0_s1   (system_0_burst_9_downstream_read_data_valid_uart_0_s1),
      .system_0_burst_9_downstream_readdata                    (system_0_burst_9_downstream_readdata),
      .system_0_burst_9_downstream_readdatavalid               (system_0_burst_9_downstream_readdatavalid),
      .system_0_burst_9_downstream_requests_uart_0_s1          (system_0_burst_9_downstream_requests_uart_0_s1),
      .system_0_burst_9_downstream_reset_n                     (system_0_burst_9_downstream_reset_n),
      .system_0_burst_9_downstream_waitrequest                 (system_0_burst_9_downstream_waitrequest),
      .system_0_burst_9_downstream_write                       (system_0_burst_9_downstream_write),
      .system_0_burst_9_downstream_writedata                   (system_0_burst_9_downstream_writedata),
      .uart_0_s1_readdata_from_sa                              (uart_0_s1_readdata_from_sa)
    );

  system_0_burst_9 the_system_0_burst_9
    (
      .clk                             (altpll_0_c1_out),
      .downstream_readdata             (system_0_burst_9_downstream_readdata),
      .downstream_readdatavalid        (system_0_burst_9_downstream_readdatavalid),
      .downstream_waitrequest          (system_0_burst_9_downstream_waitrequest),
      .reg_downstream_address          (system_0_burst_9_downstream_address),
      .reg_downstream_arbitrationshare (system_0_burst_9_downstream_arbitrationshare),
      .reg_downstream_burstcount       (system_0_burst_9_downstream_burstcount),
      .reg_downstream_byteenable       (system_0_burst_9_downstream_byteenable),
      .reg_downstream_debugaccess      (system_0_burst_9_downstream_debugaccess),
      .reg_downstream_nativeaddress    (system_0_burst_9_downstream_nativeaddress),
      .reg_downstream_read             (system_0_burst_9_downstream_read),
      .reg_downstream_write            (system_0_burst_9_downstream_write),
      .reg_downstream_writedata        (system_0_burst_9_downstream_writedata),
      .reset_n                         (system_0_burst_9_downstream_reset_n),
      .upstream_address                (system_0_burst_9_upstream_byteaddress),
      .upstream_burstcount             (system_0_burst_9_upstream_burstcount),
      .upstream_byteenable             (system_0_burst_9_upstream_byteenable),
      .upstream_debugaccess            (system_0_burst_9_upstream_debugaccess),
      .upstream_nativeaddress          (system_0_burst_9_upstream_address),
      .upstream_read                   (system_0_burst_9_upstream_read),
      .upstream_readdata               (system_0_burst_9_upstream_readdata),
      .upstream_readdatavalid          (system_0_burst_9_upstream_readdatavalid),
      .upstream_waitrequest            (system_0_burst_9_upstream_waitrequest),
      .upstream_write                  (system_0_burst_9_upstream_write),
      .upstream_writedata              (system_0_burst_9_upstream_writedata)
    );

  system_0_clock_0_in_arbitrator the_system_0_clock_0_in
    (
      .clk                                                                (altpll_0_c1_out),
      .d1_system_0_clock_0_in_end_xfer                                    (d1_system_0_clock_0_in_end_xfer),
      .reset_n                                                            (altpll_0_c1_out_reset_n),
      .system_0_burst_35_downstream_address_to_slave                      (system_0_burst_35_downstream_address_to_slave),
      .system_0_burst_35_downstream_arbitrationshare                      (system_0_burst_35_downstream_arbitrationshare),
      .system_0_burst_35_downstream_burstcount                            (system_0_burst_35_downstream_burstcount),
      .system_0_burst_35_downstream_byteenable                            (system_0_burst_35_downstream_byteenable),
      .system_0_burst_35_downstream_granted_system_0_clock_0_in           (system_0_burst_35_downstream_granted_system_0_clock_0_in),
      .system_0_burst_35_downstream_latency_counter                       (system_0_burst_35_downstream_latency_counter),
      .system_0_burst_35_downstream_nativeaddress                         (system_0_burst_35_downstream_nativeaddress),
      .system_0_burst_35_downstream_qualified_request_system_0_clock_0_in (system_0_burst_35_downstream_qualified_request_system_0_clock_0_in),
      .system_0_burst_35_downstream_read                                  (system_0_burst_35_downstream_read),
      .system_0_burst_35_downstream_read_data_valid_system_0_clock_0_in   (system_0_burst_35_downstream_read_data_valid_system_0_clock_0_in),
      .system_0_burst_35_downstream_requests_system_0_clock_0_in          (system_0_burst_35_downstream_requests_system_0_clock_0_in),
      .system_0_burst_35_downstream_write                                 (system_0_burst_35_downstream_write),
      .system_0_burst_35_downstream_writedata                             (system_0_burst_35_downstream_writedata),
      .system_0_clock_0_in_address                                        (system_0_clock_0_in_address),
      .system_0_clock_0_in_byteenable                                     (system_0_clock_0_in_byteenable),
      .system_0_clock_0_in_endofpacket                                    (system_0_clock_0_in_endofpacket),
      .system_0_clock_0_in_endofpacket_from_sa                            (system_0_clock_0_in_endofpacket_from_sa),
      .system_0_clock_0_in_nativeaddress                                  (system_0_clock_0_in_nativeaddress),
      .system_0_clock_0_in_read                                           (system_0_clock_0_in_read),
      .system_0_clock_0_in_readdata                                       (system_0_clock_0_in_readdata),
      .system_0_clock_0_in_readdata_from_sa                               (system_0_clock_0_in_readdata_from_sa),
      .system_0_clock_0_in_reset_n                                        (system_0_clock_0_in_reset_n),
      .system_0_clock_0_in_waitrequest                                    (system_0_clock_0_in_waitrequest),
      .system_0_clock_0_in_waitrequest_from_sa                            (system_0_clock_0_in_waitrequest_from_sa),
      .system_0_clock_0_in_write                                          (system_0_clock_0_in_write),
      .system_0_clock_0_in_writedata                                      (system_0_clock_0_in_writedata)
    );

  system_0_clock_0_out_arbitrator the_system_0_clock_0_out
    (
      .altpll_0_pll_slave_readdata_from_sa                       (altpll_0_pll_slave_readdata_from_sa),
      .clk                                                       (clk),
      .d1_altpll_0_pll_slave_end_xfer                            (d1_altpll_0_pll_slave_end_xfer),
      .reset_n                                                   (clk_reset_n),
      .system_0_clock_0_out_address                              (system_0_clock_0_out_address),
      .system_0_clock_0_out_address_to_slave                     (system_0_clock_0_out_address_to_slave),
      .system_0_clock_0_out_byteenable                           (system_0_clock_0_out_byteenable),
      .system_0_clock_0_out_granted_altpll_0_pll_slave           (system_0_clock_0_out_granted_altpll_0_pll_slave),
      .system_0_clock_0_out_qualified_request_altpll_0_pll_slave (system_0_clock_0_out_qualified_request_altpll_0_pll_slave),
      .system_0_clock_0_out_read                                 (system_0_clock_0_out_read),
      .system_0_clock_0_out_read_data_valid_altpll_0_pll_slave   (system_0_clock_0_out_read_data_valid_altpll_0_pll_slave),
      .system_0_clock_0_out_readdata                             (system_0_clock_0_out_readdata),
      .system_0_clock_0_out_requests_altpll_0_pll_slave          (system_0_clock_0_out_requests_altpll_0_pll_slave),
      .system_0_clock_0_out_reset_n                              (system_0_clock_0_out_reset_n),
      .system_0_clock_0_out_waitrequest                          (system_0_clock_0_out_waitrequest),
      .system_0_clock_0_out_write                                (system_0_clock_0_out_write),
      .system_0_clock_0_out_writedata                            (system_0_clock_0_out_writedata)
    );

  system_0_clock_0 the_system_0_clock_0
    (
      .master_address       (system_0_clock_0_out_address),
      .master_byteenable    (system_0_clock_0_out_byteenable),
      .master_clk           (clk),
      .master_endofpacket   (system_0_clock_0_out_endofpacket),
      .master_nativeaddress (system_0_clock_0_out_nativeaddress),
      .master_read          (system_0_clock_0_out_read),
      .master_readdata      (system_0_clock_0_out_readdata),
      .master_reset_n       (system_0_clock_0_out_reset_n),
      .master_waitrequest   (system_0_clock_0_out_waitrequest),
      .master_write         (system_0_clock_0_out_write),
      .master_writedata     (system_0_clock_0_out_writedata),
      .slave_address        (system_0_clock_0_in_address),
      .slave_byteenable     (system_0_clock_0_in_byteenable),
      .slave_clk            (altpll_0_c1_out),
      .slave_endofpacket    (system_0_clock_0_in_endofpacket),
      .slave_nativeaddress  (system_0_clock_0_in_nativeaddress),
      .slave_read           (system_0_clock_0_in_read),
      .slave_readdata       (system_0_clock_0_in_readdata),
      .slave_reset_n        (system_0_clock_0_in_reset_n),
      .slave_waitrequest    (system_0_clock_0_in_waitrequest),
      .slave_write          (system_0_clock_0_in_write),
      .slave_writedata      (system_0_clock_0_in_writedata)
    );

  timer_0_s1_arbitrator the_timer_0_s1
    (
      .clk                                                       (altpll_0_c1_out),
      .d1_timer_0_s1_end_xfer                                    (d1_timer_0_s1_end_xfer),
      .reset_n                                                   (altpll_0_c1_out_reset_n),
      .system_0_burst_10_downstream_address_to_slave             (system_0_burst_10_downstream_address_to_slave),
      .system_0_burst_10_downstream_arbitrationshare             (system_0_burst_10_downstream_arbitrationshare),
      .system_0_burst_10_downstream_burstcount                   (system_0_burst_10_downstream_burstcount),
      .system_0_burst_10_downstream_granted_timer_0_s1           (system_0_burst_10_downstream_granted_timer_0_s1),
      .system_0_burst_10_downstream_latency_counter              (system_0_burst_10_downstream_latency_counter),
      .system_0_burst_10_downstream_nativeaddress                (system_0_burst_10_downstream_nativeaddress),
      .system_0_burst_10_downstream_qualified_request_timer_0_s1 (system_0_burst_10_downstream_qualified_request_timer_0_s1),
      .system_0_burst_10_downstream_read                         (system_0_burst_10_downstream_read),
      .system_0_burst_10_downstream_read_data_valid_timer_0_s1   (system_0_burst_10_downstream_read_data_valid_timer_0_s1),
      .system_0_burst_10_downstream_requests_timer_0_s1          (system_0_burst_10_downstream_requests_timer_0_s1),
      .system_0_burst_10_downstream_write                        (system_0_burst_10_downstream_write),
      .system_0_burst_10_downstream_writedata                    (system_0_burst_10_downstream_writedata),
      .timer_0_s1_address                                        (timer_0_s1_address),
      .timer_0_s1_chipselect                                     (timer_0_s1_chipselect),
      .timer_0_s1_irq                                            (timer_0_s1_irq),
      .timer_0_s1_irq_from_sa                                    (timer_0_s1_irq_from_sa),
      .timer_0_s1_readdata                                       (timer_0_s1_readdata),
      .timer_0_s1_readdata_from_sa                               (timer_0_s1_readdata_from_sa),
      .timer_0_s1_reset_n                                        (timer_0_s1_reset_n),
      .timer_0_s1_write_n                                        (timer_0_s1_write_n),
      .timer_0_s1_writedata                                      (timer_0_s1_writedata)
    );

  timer_0 the_timer_0
    (
      .address    (timer_0_s1_address),
      .chipselect (timer_0_s1_chipselect),
      .clk        (altpll_0_c1_out),
      .irq        (timer_0_s1_irq),
      .readdata   (timer_0_s1_readdata),
      .reset_n    (timer_0_s1_reset_n),
      .write_n    (timer_0_s1_write_n),
      .writedata  (timer_0_s1_writedata)
    );

  timer_1_s1_arbitrator the_timer_1_s1
    (
      .clk                                                       (altpll_0_c1_out),
      .d1_timer_1_s1_end_xfer                                    (d1_timer_1_s1_end_xfer),
      .reset_n                                                   (altpll_0_c1_out_reset_n),
      .system_0_burst_11_downstream_address_to_slave             (system_0_burst_11_downstream_address_to_slave),
      .system_0_burst_11_downstream_arbitrationshare             (system_0_burst_11_downstream_arbitrationshare),
      .system_0_burst_11_downstream_burstcount                   (system_0_burst_11_downstream_burstcount),
      .system_0_burst_11_downstream_granted_timer_1_s1           (system_0_burst_11_downstream_granted_timer_1_s1),
      .system_0_burst_11_downstream_latency_counter              (system_0_burst_11_downstream_latency_counter),
      .system_0_burst_11_downstream_nativeaddress                (system_0_burst_11_downstream_nativeaddress),
      .system_0_burst_11_downstream_qualified_request_timer_1_s1 (system_0_burst_11_downstream_qualified_request_timer_1_s1),
      .system_0_burst_11_downstream_read                         (system_0_burst_11_downstream_read),
      .system_0_burst_11_downstream_read_data_valid_timer_1_s1   (system_0_burst_11_downstream_read_data_valid_timer_1_s1),
      .system_0_burst_11_downstream_requests_timer_1_s1          (system_0_burst_11_downstream_requests_timer_1_s1),
      .system_0_burst_11_downstream_write                        (system_0_burst_11_downstream_write),
      .system_0_burst_11_downstream_writedata                    (system_0_burst_11_downstream_writedata),
      .timer_1_s1_address                                        (timer_1_s1_address),
      .timer_1_s1_chipselect                                     (timer_1_s1_chipselect),
      .timer_1_s1_irq                                            (timer_1_s1_irq),
      .timer_1_s1_irq_from_sa                                    (timer_1_s1_irq_from_sa),
      .timer_1_s1_readdata                                       (timer_1_s1_readdata),
      .timer_1_s1_readdata_from_sa                               (timer_1_s1_readdata_from_sa),
      .timer_1_s1_reset_n                                        (timer_1_s1_reset_n),
      .timer_1_s1_write_n                                        (timer_1_s1_write_n),
      .timer_1_s1_writedata                                      (timer_1_s1_writedata)
    );

  timer_1 the_timer_1
    (
      .address    (timer_1_s1_address),
      .chipselect (timer_1_s1_chipselect),
      .clk        (altpll_0_c1_out),
      .irq        (timer_1_s1_irq),
      .readdata   (timer_1_s1_readdata),
      .reset_n    (timer_1_s1_reset_n),
      .write_n    (timer_1_s1_write_n),
      .writedata  (timer_1_s1_writedata)
    );

  tri_state_bridge_0_avalon_slave_arbitrator the_tri_state_bridge_0_avalon_slave
    (
      .cfi_flash_0_s1_wait_counter_eq_0                             (cfi_flash_0_s1_wait_counter_eq_0),
      .clk                                                          (altpll_0_c1_out),
      .d1_tri_state_bridge_0_avalon_slave_end_xfer                  (d1_tri_state_bridge_0_avalon_slave_end_xfer),
      .incoming_tri_state_bridge_0_data_with_Xs_converted_to_0      (incoming_tri_state_bridge_0_data_with_Xs_converted_to_0),
      .reset_n                                                      (altpll_0_c1_out_reset_n),
      .select_n_to_the_cfi_flash_0                                  (select_n_to_the_cfi_flash_0),
      .system_0_burst_2_downstream_address_to_slave                 (system_0_burst_2_downstream_address_to_slave),
      .system_0_burst_2_downstream_arbitrationshare                 (system_0_burst_2_downstream_arbitrationshare),
      .system_0_burst_2_downstream_burstcount                       (system_0_burst_2_downstream_burstcount),
      .system_0_burst_2_downstream_byteenable                       (system_0_burst_2_downstream_byteenable),
      .system_0_burst_2_downstream_granted_cfi_flash_0_s1           (system_0_burst_2_downstream_granted_cfi_flash_0_s1),
      .system_0_burst_2_downstream_latency_counter                  (system_0_burst_2_downstream_latency_counter),
      .system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1 (system_0_burst_2_downstream_qualified_request_cfi_flash_0_s1),
      .system_0_burst_2_downstream_read                             (system_0_burst_2_downstream_read),
      .system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1   (system_0_burst_2_downstream_read_data_valid_cfi_flash_0_s1),
      .system_0_burst_2_downstream_requests_cfi_flash_0_s1          (system_0_burst_2_downstream_requests_cfi_flash_0_s1),
      .system_0_burst_2_downstream_write                            (system_0_burst_2_downstream_write),
      .system_0_burst_2_downstream_writedata                        (system_0_burst_2_downstream_writedata),
      .system_0_burst_3_downstream_address_to_slave                 (system_0_burst_3_downstream_address_to_slave),
      .system_0_burst_3_downstream_arbitrationshare                 (system_0_burst_3_downstream_arbitrationshare),
      .system_0_burst_3_downstream_burstcount                       (system_0_burst_3_downstream_burstcount),
      .system_0_burst_3_downstream_byteenable                       (system_0_burst_3_downstream_byteenable),
      .system_0_burst_3_downstream_granted_cfi_flash_0_s1           (system_0_burst_3_downstream_granted_cfi_flash_0_s1),
      .system_0_burst_3_downstream_latency_counter                  (system_0_burst_3_downstream_latency_counter),
      .system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1 (system_0_burst_3_downstream_qualified_request_cfi_flash_0_s1),
      .system_0_burst_3_downstream_read                             (system_0_burst_3_downstream_read),
      .system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1   (system_0_burst_3_downstream_read_data_valid_cfi_flash_0_s1),
      .system_0_burst_3_downstream_requests_cfi_flash_0_s1          (system_0_burst_3_downstream_requests_cfi_flash_0_s1),
      .system_0_burst_3_downstream_write                            (system_0_burst_3_downstream_write),
      .system_0_burst_3_downstream_writedata                        (system_0_burst_3_downstream_writedata),
      .tri_state_bridge_0_address                                   (tri_state_bridge_0_address),
      .tri_state_bridge_0_data                                      (tri_state_bridge_0_data),
      .tri_state_bridge_0_readn                                     (tri_state_bridge_0_readn),
      .write_n_to_the_cfi_flash_0                                   (write_n_to_the_cfi_flash_0)
    );

  uart_0_s1_arbitrator the_uart_0_s1
    (
      .clk                                                     (altpll_0_c1_out),
      .d1_uart_0_s1_end_xfer                                   (d1_uart_0_s1_end_xfer),
      .reset_n                                                 (altpll_0_c1_out_reset_n),
      .system_0_burst_9_downstream_address_to_slave            (system_0_burst_9_downstream_address_to_slave),
      .system_0_burst_9_downstream_arbitrationshare            (system_0_burst_9_downstream_arbitrationshare),
      .system_0_burst_9_downstream_burstcount                  (system_0_burst_9_downstream_burstcount),
      .system_0_burst_9_downstream_granted_uart_0_s1           (system_0_burst_9_downstream_granted_uart_0_s1),
      .system_0_burst_9_downstream_latency_counter             (system_0_burst_9_downstream_latency_counter),
      .system_0_burst_9_downstream_nativeaddress               (system_0_burst_9_downstream_nativeaddress),
      .system_0_burst_9_downstream_qualified_request_uart_0_s1 (system_0_burst_9_downstream_qualified_request_uart_0_s1),
      .system_0_burst_9_downstream_read                        (system_0_burst_9_downstream_read),
      .system_0_burst_9_downstream_read_data_valid_uart_0_s1   (system_0_burst_9_downstream_read_data_valid_uart_0_s1),
      .system_0_burst_9_downstream_requests_uart_0_s1          (system_0_burst_9_downstream_requests_uart_0_s1),
      .system_0_burst_9_downstream_write                       (system_0_burst_9_downstream_write),
      .system_0_burst_9_downstream_writedata                   (system_0_burst_9_downstream_writedata),
      .uart_0_s1_address                                       (uart_0_s1_address),
      .uart_0_s1_begintransfer                                 (uart_0_s1_begintransfer),
      .uart_0_s1_chipselect                                    (uart_0_s1_chipselect),
      .uart_0_s1_dataavailable                                 (uart_0_s1_dataavailable),
      .uart_0_s1_dataavailable_from_sa                         (uart_0_s1_dataavailable_from_sa),
      .uart_0_s1_irq                                           (uart_0_s1_irq),
      .uart_0_s1_irq_from_sa                                   (uart_0_s1_irq_from_sa),
      .uart_0_s1_read_n                                        (uart_0_s1_read_n),
      .uart_0_s1_readdata                                      (uart_0_s1_readdata),
      .uart_0_s1_readdata_from_sa                              (uart_0_s1_readdata_from_sa),
      .uart_0_s1_readyfordata                                  (uart_0_s1_readyfordata),
      .uart_0_s1_readyfordata_from_sa                          (uart_0_s1_readyfordata_from_sa),
      .uart_0_s1_reset_n                                       (uart_0_s1_reset_n),
      .uart_0_s1_write_n                                       (uart_0_s1_write_n),
      .uart_0_s1_writedata                                     (uart_0_s1_writedata)
    );

  uart_0 the_uart_0
    (
      .address       (uart_0_s1_address),
      .begintransfer (uart_0_s1_begintransfer),
      .chipselect    (uart_0_s1_chipselect),
      .clk           (altpll_0_c1_out),
      .dataavailable (uart_0_s1_dataavailable),
      .irq           (uart_0_s1_irq),
      .read_n        (uart_0_s1_read_n),
      .readdata      (uart_0_s1_readdata),
      .readyfordata  (uart_0_s1_readyfordata),
      .reset_n       (uart_0_s1_reset_n),
      .rxd           (rxd_to_the_uart_0),
      .txd           (txd_from_the_uart_0),
      .write_n       (uart_0_s1_write_n),
      .writedata     (uart_0_s1_writedata)
    );

  //reset is asserted asynchronously and deasserted synchronously
  system_0_reset_altpll_0_c1_out_domain_synch_module system_0_reset_altpll_0_c1_out_domain_synch
    (
      .clk      (altpll_0_c1_out),
      .data_in  (1'b1),
      .data_out (altpll_0_c1_out_reset_n),
      .reset_n  (reset_n_sources)
    );

  //reset sources mux, which is an e_mux
  assign reset_n_sources = ~(~reset_n |
    0 |
    0 |
    cpu_0_jtag_debug_module_resetrequest_from_sa |
    cpu_0_jtag_debug_module_resetrequest_from_sa);

  //reset is asserted asynchronously and deasserted synchronously
  system_0_reset_clk_domain_synch_module system_0_reset_clk_domain_synch
    (
      .clk      (clk),
      .data_in  (1'b1),
      .data_out (clk_reset_n),
      .reset_n  (reset_n_sources)
    );

  //system_0_burst_0_upstream_writedata of type writedata does not connect to anything so wire it to default (0)
  assign system_0_burst_0_upstream_writedata = 0;

  //system_0_burst_14_upstream_writedata of type writedata does not connect to anything so wire it to default (0)
  assign system_0_burst_14_upstream_writedata = 0;

  //system_0_burst_2_upstream_writedata of type writedata does not connect to anything so wire it to default (0)
  assign system_0_burst_2_upstream_writedata = 0;

  //system_0_burst_33_upstream_writedata of type writedata does not connect to anything so wire it to default (0)
  assign system_0_burst_33_upstream_writedata = 0;

  //system_0_burst_4_upstream_writedata of type writedata does not connect to anything so wire it to default (0)
  assign system_0_burst_4_upstream_writedata = 0;

  //system_0_burst_6_upstream_writedata of type writedata does not connect to anything so wire it to default (0)
  assign system_0_burst_6_upstream_writedata = 0;

  //system_0_clock_0_out_endofpacket of type endofpacket does not connect to anything so wire it to default (0)
  assign system_0_clock_0_out_endofpacket = 0;


endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cfi_flash_0_lane0_module (
                                  // inputs:
                                   data,
                                   rdaddress,
                                   rdclken,
                                   wraddress,
                                   wrclock,
                                   wren,

                                  // outputs:
                                   q
                                )
;

  output  [  7: 0] q;
  input   [  7: 0] data;
  input   [ 21: 0] rdaddress;
  input            rdclken;
  input   [ 21: 0] wraddress;
  input            wrclock;
  input            wren;

  reg     [  7: 0] mem_array [4194303: 0];
  wire    [  7: 0] q;
  reg     [ 21: 0] read_address;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  always @(rdaddress)
    begin
      read_address = rdaddress;
    end


  // Data read is asynchronous.
  assign q = mem_array[read_address];

initial
    $readmemh("cfi_flash_0.dat", mem_array);
  always @(posedge wrclock)
    begin
      // Write data
      if (wren)
          mem_array[wraddress] <= data;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  always @(rdaddress)
//    begin
//      read_address = rdaddress;
//    end
//
//
//  lpm_ram_dp lpm_ram_dp_component
//    (
//      .data (data),
//      .q (q),
//      .rdaddress (read_address),
//      .rdclken (rdclken),
//      .wraddress (wraddress),
//      .wrclock (wrclock),
//      .wren (wren)
//    );
//
//  defparam lpm_ram_dp_component.lpm_file = "cfi_flash_0.mif",
//           lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
//           lpm_ram_dp_component.lpm_indata = "REGISTERED",
//           lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
//           lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
//           lpm_ram_dp_component.lpm_width = 8,
//           lpm_ram_dp_component.lpm_widthad = 22,
//           lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
//           lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cfi_flash_0 (
                     // inputs:
                      address,
                      read_n,
                      select_n,
                      write_n,

                     // outputs:
                      data
                   )
;

  inout   [  7: 0] data;
  input   [ 21: 0] address;
  input            read_n;
  input            select_n;
  input            write_n;

  wire    [  7: 0] data;
  wire    [  7: 0] data_0;
  wire    [  7: 0] logic_vector_gasket;
  wire    [  7: 0] q_0;
  //s1, which is an e_ptf_slave

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  assign logic_vector_gasket = data;
  assign data_0 = logic_vector_gasket[7 : 0];
  //cfi_flash_0_lane0, which is an e_ram
  cfi_flash_0_lane0_module cfi_flash_0_lane0
    (
      .data      (data_0),
      .q         (q_0),
      .rdaddress (address),
      .rdclken   (1'b1),
      .wraddress (address),
      .wrclock   (write_n),
      .wren      (~select_n)
    );

  assign data = (~select_n & ~read_n)? q_0: {8{1'bz}};

//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


//synthesis translate_off



// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE

// AND HERE WILL BE PRESERVED </ALTERA_NOTE>


// If user logic components use Altsync_Ram with convert_hex2ver.dll,
// set USE_convert_hex2ver in the user comments section above

// `ifdef USE_convert_hex2ver
// `else
// `define NO_PLI 1
// `endif

`include "/opt/altera/10.1sp1/quartus/eda/sim_lib/altera_mf.v"
`include "/opt/altera/10.1sp1/quartus/eda/sim_lib/220model.v"
`include "/opt/altera/10.1sp1/quartus/eda/sim_lib/sgate.v"
// i2c_master.vhd
`include "altpll_0.vo"
// Accelerometer1/accelerometer.vhd
// Accel_Control.vhd
`include "system_0_burst_21.v"
`include "timer_0.v"
`include "SEG7_LUT.v"
`include "SEG7_LUT_8.v"
`include "SEG7_Display.v"
`include "system_0_burst_30.v"
`include "system_0_burst_17.v"
`include "system_0_burst_0.v"
`include "noteD.v"
`include "sdram_0.v"
`include "sdram_0_test_component.v"
`include "SD_CMD.v"
`include "system_0_burst_18.v"
`include "system_0_burst_12.v"
`include "system_0_burst_23.v"
`include "system_0_burst_34.v"
`include "system_0_burst_11.v"
`include "system_0_burst_33.v"
`include "system_0_burst_1.v"
`include "RST.v"
`include "system_0_burst_9.v"
`include "system_0_burst_22.v"
`include "system_0_burst_16.v"
`include "SD_DAT.v"
`include "system_0_burst_6.v"
`include "system_0_burst_24.v"
`include "system_0_burst_7.v"
`include "noteE.v"
`include "system_0_burst_8.v"
`include "system_0_burst_15.v"
`include "system_0_burst_2.v"
`include "system_0_burst_27.v"
`include "SD_CLK.v"
`include "noteA.v"
`include "SRAM_16Bit_512K.v"
`include "sram_0.v"
`include "Oct_UP.v"
`include "AUDIO_DAC_FIFO.v"
`include "FIFO_16_256.v"
`include "Audio_0.v"
`include "MS.v"
`include "cpu_0_test_bench.v"
`include "cpu_0_mult_cell.v"
`include "cpu_0_oci_test_bench.v"
`include "cpu_0_jtag_debug_module_tck.v"
`include "cpu_0_jtag_debug_module_sysclk.v"
`include "cpu_0_jtag_debug_module_wrapper.v"
`include "cpu_0.v"
`include "system_0_burst_4.v"
`include "system_0_burst_25.v"
`include "system_0_burst_5.v"
`include "system_0_burst_28.v"
`include "uart_0.v"
`include "dist_sensor.v"
`include "Oct_DOWN.v"
`include "jtag_uart_0.v"
`include "noteF.v"
`include "system_0_burst_29.v"
`include "system_0_burst_20.v"
`include "system_0_burst_3.v"
`include "epcs_controller.v"
`include "system_0_burst_26.v"
`include "system_0_burst_19.v"
`include "noteC.v"
`include "timer_1.v"
`include "system_0_burst_13.v"
`include "system_0_burst_14.v"
`include "system_0_burst_35.v"
`include "noteG.v"
`include "system_0_burst_31.v"
`include "lcd_16207_0.v"
`include "noteB.v"
`include "system_0_burst_10.v"
`include "system_0_clock_0.v"
`include "system_0_burst_32.v"

`timescale 1ns / 1ps

module test_bench 
;


  wire             LCD_E_from_the_lcd_16207_0;
  wire             LCD_RS_from_the_lcd_16207_0;
  wire             LCD_RW_from_the_lcd_16207_0;
  wire    [  7: 0] LCD_data_to_and_from_the_lcd_16207_0;
  wire    [ 17: 0] SRAM_ADDR_from_the_sram_0;
  wire             SRAM_CE_N_from_the_sram_0;
  wire    [ 15: 0] SRAM_DQ_to_and_from_the_sram_0;
  wire             SRAM_LB_N_from_the_sram_0;
  wire             SRAM_OE_N_from_the_sram_0;
  wire             SRAM_UB_N_from_the_sram_0;
  wire             SRAM_WE_N_from_the_sram_0;
  wire             altpll_0_c0_out;
  wire             altpll_0_c1_out;
  wire             bidir_port_to_and_from_the_SD_CMD;
  wire             bidir_port_to_and_from_the_SD_DAT;
  reg              clk;
  wire             epcs_controller_epcs_control_port_dataavailable_from_sa;
  wire             epcs_controller_epcs_control_port_endofpacket_from_sa;
  wire             epcs_controller_epcs_control_port_readyfordata_from_sa;
  wire             iCLK_18_4_to_the_Audio_0;
  wire             in_port_to_the_MS;
  wire             in_port_to_the_Oct_DOWN;
  wire             in_port_to_the_Oct_UP;
  wire             in_port_to_the_RST;
  wire             in_port_to_the_dist_sensor;
  wire             in_port_to_the_noteA;
  wire             in_port_to_the_noteB;
  wire             in_port_to_the_noteC;
  wire             in_port_to_the_noteD;
  wire             in_port_to_the_noteE;
  wire             in_port_to_the_noteF;
  wire             in_port_to_the_noteG;
  wire             interrupt2_to_the_Accel_Control;
  wire             jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa;
  wire             locked_from_the_altpll_0;
  wire             oAUD_BCK_from_the_Audio_0;
  wire             oAUD_DATA_from_the_Audio_0;
  wire             oAUD_LRCK_from_the_Audio_0;
  wire             oAUD_XCK_from_the_Audio_0;
  wire    [  6: 0] oSEG0_from_the_SEG7_Display;
  wire    [  6: 0] oSEG1_from_the_SEG7_Display;
  wire    [  6: 0] oSEG2_from_the_SEG7_Display;
  wire    [  6: 0] oSEG3_from_the_SEG7_Display;
  wire    [  6: 0] oSEG4_from_the_SEG7_Display;
  wire    [  6: 0] oSEG5_from_the_SEG7_Display;
  wire    [  6: 0] oSEG6_from_the_SEG7_Display;
  wire    [  6: 0] oSEG7_from_the_SEG7_Display;
  wire             out_port_from_the_SD_CLK;
  wire             phasedone_from_the_altpll_0;
  reg              reset_n;
  wire             rxd_to_the_uart_0;
  wire             scl_i2c_to_accel_from_the_Accel_Control;
  wire             scl_i2c_to_bus_to_the_Accel_Control;
  wire             scl_pad_io_from_the_i2c_master;
  wire             sda_i2c_to_accel_to_and_from_the_Accel_Control;
  wire             sda_i2c_to_bus_to_and_from_the_Accel_Control;
  wire             sda_pad_io_to_and_from_the_i2c_master;
  wire             sda_padoen_o_to_the_Accel_Control;
  wire             sda_padoen_out_from_the_i2c_master;
  wire             select_n_to_the_cfi_flash_0;
  wire    [ 10: 0] system_0_burst_0_downstream_nativeaddress;
  wire    [ 31: 0] system_0_burst_0_upstream_writedata;
  wire             system_0_burst_10_downstream_debugaccess;
  wire             system_0_burst_11_downstream_debugaccess;
  wire             system_0_burst_12_downstream_debugaccess;
  wire             system_0_burst_13_downstream_debugaccess;
  wire    [  1: 0] system_0_burst_13_downstream_nativeaddress;
  wire             system_0_burst_14_downstream_debugaccess;
  wire    [ 18: 0] system_0_burst_14_downstream_nativeaddress;
  wire    [ 15: 0] system_0_burst_14_upstream_writedata;
  wire             system_0_burst_15_downstream_debugaccess;
  wire    [ 18: 0] system_0_burst_15_downstream_nativeaddress;
  wire             system_0_burst_16_downstream_debugaccess;
  wire             system_0_burst_16_downstream_nativeaddress;
  wire             system_0_burst_17_downstream_debugaccess;
  wire             system_0_burst_18_downstream_debugaccess;
  wire             system_0_burst_19_downstream_debugaccess;
  wire    [ 10: 0] system_0_burst_1_downstream_nativeaddress;
  wire             system_0_burst_20_downstream_debugaccess;
  wire             system_0_burst_21_downstream_debugaccess;
  wire             system_0_burst_22_downstream_debugaccess;
  wire             system_0_burst_23_downstream_debugaccess;
  wire             system_0_burst_24_downstream_debugaccess;
  wire             system_0_burst_25_downstream_debugaccess;
  wire             system_0_burst_26_downstream_debugaccess;
  wire             system_0_burst_27_downstream_debugaccess;
  wire             system_0_burst_28_downstream_debugaccess;
  wire             system_0_burst_29_downstream_debugaccess;
  wire             system_0_burst_2_downstream_debugaccess;
  wire    [ 21: 0] system_0_burst_2_downstream_nativeaddress;
  wire    [  7: 0] system_0_burst_2_upstream_writedata;
  wire             system_0_burst_30_downstream_debugaccess;
  wire             system_0_burst_31_downstream_debugaccess;
  wire             system_0_burst_32_downstream_debugaccess;
  wire    [  4: 0] system_0_burst_32_downstream_nativeaddress;
  wire             system_0_burst_33_downstream_debugaccess;
  wire    [  4: 0] system_0_burst_33_downstream_nativeaddress;
  wire    [ 31: 0] system_0_burst_33_upstream_writedata;
  wire             system_0_burst_34_downstream_debugaccess;
  wire    [  4: 0] system_0_burst_34_downstream_nativeaddress;
  wire             system_0_burst_35_downstream_debugaccess;
  wire             system_0_burst_3_downstream_debugaccess;
  wire    [ 21: 0] system_0_burst_3_downstream_nativeaddress;
  wire             system_0_burst_4_downstream_debugaccess;
  wire    [ 22: 0] system_0_burst_4_downstream_nativeaddress;
  wire    [ 15: 0] system_0_burst_4_upstream_writedata;
  wire             system_0_burst_5_downstream_debugaccess;
  wire    [ 22: 0] system_0_burst_5_downstream_nativeaddress;
  wire             system_0_burst_6_downstream_debugaccess;
  wire    [ 10: 0] system_0_burst_6_downstream_nativeaddress;
  wire    [ 31: 0] system_0_burst_6_upstream_writedata;
  wire             system_0_burst_7_downstream_debugaccess;
  wire    [ 10: 0] system_0_burst_7_downstream_nativeaddress;
  wire             system_0_burst_8_downstream_debugaccess;
  wire             system_0_burst_9_downstream_debugaccess;
  wire             system_0_clock_0_in_endofpacket_from_sa;
  wire             system_0_clock_0_out_endofpacket;
  wire    [  1: 0] system_0_clock_0_out_nativeaddress;
  wire    [ 21: 0] tri_state_bridge_0_address;
  wire    [  7: 0] tri_state_bridge_0_data;
  wire             tri_state_bridge_0_readn;
  wire             txd_from_the_uart_0;
  wire             uart_0_s1_dataavailable_from_sa;
  wire             uart_0_s1_readyfordata_from_sa;
  wire             wb_err_o_from_the_i2c_master;
  wire             write_n_to_the_cfi_flash_0;
  wire    [ 11: 0] zs_addr_from_the_sdram_0;
  wire    [  1: 0] zs_ba_from_the_sdram_0;
  wire             zs_cas_n_from_the_sdram_0;
  wire             zs_cke_from_the_sdram_0;
  wire             zs_cs_n_from_the_sdram_0;
  wire    [ 15: 0] zs_dq_to_and_from_the_sdram_0;
  wire    [  1: 0] zs_dqm_from_the_sdram_0;
  wire             zs_ras_n_from_the_sdram_0;
  wire             zs_we_n_from_the_sdram_0;


// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
//  add your signals and additional architecture here
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>

  //Set us up the Dut
  system_0 DUT
    (
      .LCD_E_from_the_lcd_16207_0                     (LCD_E_from_the_lcd_16207_0),
      .LCD_RS_from_the_lcd_16207_0                    (LCD_RS_from_the_lcd_16207_0),
      .LCD_RW_from_the_lcd_16207_0                    (LCD_RW_from_the_lcd_16207_0),
      .LCD_data_to_and_from_the_lcd_16207_0           (LCD_data_to_and_from_the_lcd_16207_0),
      .SRAM_ADDR_from_the_sram_0                      (SRAM_ADDR_from_the_sram_0),
      .SRAM_CE_N_from_the_sram_0                      (SRAM_CE_N_from_the_sram_0),
      .SRAM_DQ_to_and_from_the_sram_0                 (SRAM_DQ_to_and_from_the_sram_0),
      .SRAM_LB_N_from_the_sram_0                      (SRAM_LB_N_from_the_sram_0),
      .SRAM_OE_N_from_the_sram_0                      (SRAM_OE_N_from_the_sram_0),
      .SRAM_UB_N_from_the_sram_0                      (SRAM_UB_N_from_the_sram_0),
      .SRAM_WE_N_from_the_sram_0                      (SRAM_WE_N_from_the_sram_0),
      .altpll_0_c0_out                                (altpll_0_c0_out),
      .altpll_0_c1_out                                (altpll_0_c1_out),
      .bidir_port_to_and_from_the_SD_CMD              (bidir_port_to_and_from_the_SD_CMD),
      .bidir_port_to_and_from_the_SD_DAT              (bidir_port_to_and_from_the_SD_DAT),
      .clk                                            (clk),
      .iCLK_18_4_to_the_Audio_0                       (iCLK_18_4_to_the_Audio_0),
      .in_port_to_the_MS                              (in_port_to_the_MS),
      .in_port_to_the_Oct_DOWN                        (in_port_to_the_Oct_DOWN),
      .in_port_to_the_Oct_UP                          (in_port_to_the_Oct_UP),
      .in_port_to_the_RST                             (in_port_to_the_RST),
      .in_port_to_the_dist_sensor                     (in_port_to_the_dist_sensor),
      .in_port_to_the_noteA                           (in_port_to_the_noteA),
      .in_port_to_the_noteB                           (in_port_to_the_noteB),
      .in_port_to_the_noteC                           (in_port_to_the_noteC),
      .in_port_to_the_noteD                           (in_port_to_the_noteD),
      .in_port_to_the_noteE                           (in_port_to_the_noteE),
      .in_port_to_the_noteF                           (in_port_to_the_noteF),
      .in_port_to_the_noteG                           (in_port_to_the_noteG),
      .interrupt2_to_the_Accel_Control                (interrupt2_to_the_Accel_Control),
      .locked_from_the_altpll_0                       (locked_from_the_altpll_0),
      .oAUD_BCK_from_the_Audio_0                      (oAUD_BCK_from_the_Audio_0),
      .oAUD_DATA_from_the_Audio_0                     (oAUD_DATA_from_the_Audio_0),
      .oAUD_LRCK_from_the_Audio_0                     (oAUD_LRCK_from_the_Audio_0),
      .oAUD_XCK_from_the_Audio_0                      (oAUD_XCK_from_the_Audio_0),
      .oSEG0_from_the_SEG7_Display                    (oSEG0_from_the_SEG7_Display),
      .oSEG1_from_the_SEG7_Display                    (oSEG1_from_the_SEG7_Display),
      .oSEG2_from_the_SEG7_Display                    (oSEG2_from_the_SEG7_Display),
      .oSEG3_from_the_SEG7_Display                    (oSEG3_from_the_SEG7_Display),
      .oSEG4_from_the_SEG7_Display                    (oSEG4_from_the_SEG7_Display),
      .oSEG5_from_the_SEG7_Display                    (oSEG5_from_the_SEG7_Display),
      .oSEG6_from_the_SEG7_Display                    (oSEG6_from_the_SEG7_Display),
      .oSEG7_from_the_SEG7_Display                    (oSEG7_from_the_SEG7_Display),
      .out_port_from_the_SD_CLK                       (out_port_from_the_SD_CLK),
      .phasedone_from_the_altpll_0                    (phasedone_from_the_altpll_0),
      .reset_n                                        (reset_n),
      .rxd_to_the_uart_0                              (rxd_to_the_uart_0),
      .scl_i2c_to_accel_from_the_Accel_Control        (scl_i2c_to_accel_from_the_Accel_Control),
      .scl_i2c_to_bus_to_the_Accel_Control            (scl_i2c_to_bus_to_the_Accel_Control),
      .scl_pad_io_from_the_i2c_master                 (scl_pad_io_from_the_i2c_master),
      .sda_i2c_to_accel_to_and_from_the_Accel_Control (sda_i2c_to_accel_to_and_from_the_Accel_Control),
      .sda_i2c_to_bus_to_and_from_the_Accel_Control   (sda_i2c_to_bus_to_and_from_the_Accel_Control),
      .sda_pad_io_to_and_from_the_i2c_master          (sda_pad_io_to_and_from_the_i2c_master),
      .sda_padoen_o_to_the_Accel_Control              (sda_padoen_o_to_the_Accel_Control),
      .sda_padoen_out_from_the_i2c_master             (sda_padoen_out_from_the_i2c_master),
      .select_n_to_the_cfi_flash_0                    (select_n_to_the_cfi_flash_0),
      .tri_state_bridge_0_address                     (tri_state_bridge_0_address),
      .tri_state_bridge_0_data                        (tri_state_bridge_0_data),
      .tri_state_bridge_0_readn                       (tri_state_bridge_0_readn),
      .txd_from_the_uart_0                            (txd_from_the_uart_0),
      .wb_err_o_from_the_i2c_master                   (wb_err_o_from_the_i2c_master),
      .write_n_to_the_cfi_flash_0                     (write_n_to_the_cfi_flash_0),
      .zs_addr_from_the_sdram_0                       (zs_addr_from_the_sdram_0),
      .zs_ba_from_the_sdram_0                         (zs_ba_from_the_sdram_0),
      .zs_cas_n_from_the_sdram_0                      (zs_cas_n_from_the_sdram_0),
      .zs_cke_from_the_sdram_0                        (zs_cke_from_the_sdram_0),
      .zs_cs_n_from_the_sdram_0                       (zs_cs_n_from_the_sdram_0),
      .zs_dq_to_and_from_the_sdram_0                  (zs_dq_to_and_from_the_sdram_0),
      .zs_dqm_from_the_sdram_0                        (zs_dqm_from_the_sdram_0),
      .zs_ras_n_from_the_sdram_0                      (zs_ras_n_from_the_sdram_0),
      .zs_we_n_from_the_sdram_0                       (zs_we_n_from_the_sdram_0)
    );

  cfi_flash_0 the_cfi_flash_0
    (
      .address  (tri_state_bridge_0_address),
      .data     (tri_state_bridge_0_data),
      .read_n   (tri_state_bridge_0_readn),
      .select_n (select_n_to_the_cfi_flash_0),
      .write_n  (write_n_to_the_cfi_flash_0)
    );

  sdram_0_test_component the_sdram_0_test_component
    (
      .clk      (altpll_0_c1_out),
      .zs_addr  (zs_addr_from_the_sdram_0),
      .zs_ba    (zs_ba_from_the_sdram_0),
      .zs_cas_n (zs_cas_n_from_the_sdram_0),
      .zs_cke   (zs_cke_from_the_sdram_0),
      .zs_cs_n  (zs_cs_n_from_the_sdram_0),
      .zs_dq    (zs_dq_to_and_from_the_sdram_0),
      .zs_dqm   (zs_dqm_from_the_sdram_0),
      .zs_ras_n (zs_ras_n_from_the_sdram_0),
      .zs_we_n  (zs_we_n_from_the_sdram_0)
    );

  initial
    clk = 1'b0;
  always
    #10 clk <= ~clk;
  
  initial 
    begin
      reset_n <= 0;
      #200 reset_n <= 1;
    end

endmodule


//synthesis translate_on