--dcfifo_mixed_widths CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=256 LPM_SHOWAHEAD="OFF" LPM_WIDTH=16 LPM_WIDTH_R=16 LPM_WIDTHU=8 LPM_WIDTHU_R=8 OVERFLOW_CHECKING="ON" RAM_BLOCK_TYPE="M4K" RDSYNC_DELAYPIPE=4 UNDERFLOW_CHECKING="ON" USE_EAB="ON" WRSYNC_DELAYPIPE=4 aclr data q rdclk rdreq wrclk wrfull wrreq CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone II" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=M4K" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 10.1SP1 cbx_a_gray2bin 2011:01:19:21:23:40:SJ cbx_a_graycounter 2011:01:19:21:23:40:SJ cbx_altdpram 2011:01:19:21:23:40:SJ cbx_altsyncram 2011:01:19:21:23:41:SJ cbx_cycloneii 2011:01:19:21:23:41:SJ cbx_dcfifo 2011:01:19:21:23:41:SJ cbx_fifo_common 2011:01:19:21:23:40:SJ cbx_lpm_add_sub 2011:01:19:21:23:41:SJ cbx_lpm_compare 2011:01:19:21:23:41:SJ cbx_lpm_counter 2011:01:19:21:23:41:SJ cbx_lpm_decode 2011:01:19:21:23:41:SJ cbx_lpm_mux 2011:01:19:21:23:41:SJ cbx_mgl 2011:01:19:21:24:50:SJ cbx_scfifo 2011:01:19:21:23:41:SJ cbx_stratix 2011:01:19:21:23:41:SJ cbx_stratixii 2011:01:19:21:23:41:SJ cbx_stratixiii 2011:01:19:21:23:41:SJ cbx_stratixv 2011:01:19:21:23:41:SJ cbx_util_mgl 2011:01:19:21:23:41:SJ  VERSION_END


-- Copyright (C) 1991-2011 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION a_graycounter_g86 (aclr, clock, cnt_en)
RETURNS ( q[8..0]);
FUNCTION a_graycounter_7fc (aclr, clock, cnt_en)
RETURNS ( q[8..0]);
FUNCTION a_graycounter_6fc (aclr, clock, cnt_en)
RETURNS ( q[8..0]);
FUNCTION altsyncram_vk81 (aclr1, address_a[7..0], address_b[7..0], addressstall_b, clock0, clock1, clocken1, data_a[15..0], wren_a)
RETURNS ( q_b[15..0]);
FUNCTION dffpipe_ngh (clock, clrn, d[0..0])
RETURNS ( q[0..0]);
FUNCTION alt_synch_pipe_jcb (clock, clrn, d[8..0])
RETURNS ( q[8..0]);
FUNCTION alt_synch_pipe_nc8 (clock, clrn, d[8..0])
RETURNS ( q[8..0]);
FUNCTION cmpr_t16 (dataa[8..0], datab[8..0])
RETURNS ( aeb);

--synthesis_resources = M4K 1 reg 95 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;suppress_da_rule_internal=s102;{-to p0addr} POWER_UP_LEVEL=LOW;{-to rdptr_g} suppress_da_rule_internal=r105;-name CUT ON -from rdptr_g -to ws_dgrp|dffpipe20|dffe21a;-name SDC_STATEMENT ""set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_id9:dffpipe20|dffe21a* "";-name CUT ON -from delayed_wrptr_g -to rs_dgwp|dffpipe17|dffe18a;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_hd9:dffpipe17|dffe18a* """;

SUBDESIGN dcfifo_hlj1
( 
	aclr	:	input;
	data[15..0]	:	input;
	q[15..0]	:	output;
	rdclk	:	input;
	rdreq	:	input;
	wrclk	:	input;
	wrfull	:	output;
	wrreq	:	input;
) 
VARIABLE 
	rdptr_g1p : a_graycounter_g86;
	wrptr_g1p : a_graycounter_7fc;
	wrptr_gp : a_graycounter_6fc;
	fifo_ram : altsyncram_vk81;
	delayed_wrptr_g[8..0] : dffe;
	p0addr : dffe
		WITH (
			power_up = "low"
		);
	rdptr_g[8..0] : dffe;
	rdaclr : dffpipe_ngh;
	rs_dgwp : alt_synch_pipe_jcb;
	ws_dgrp : alt_synch_pipe_nc8;
	rdempty_eq_comp : cmpr_t16;
	wrfull_eq_comp : cmpr_t16;
	int_rdempty	: WIRE;
	int_wrfull	: WIRE;
	ram_address_a[7..0]	: WIRE;
	ram_address_b[7..0]	: WIRE;
	rdcnt_addr_ena	: WIRE;
	valid_rdreq	: WIRE;
	valid_wrreq	: WIRE;
	wrptr_gs[8..0]	: WIRE;

BEGIN 
	rdptr_g1p.aclr = (! rdaclr.q[]);
	rdptr_g1p.clock = rdclk;
	rdptr_g1p.cnt_en = rdcnt_addr_ena;
	wrptr_g1p.aclr = aclr;
	wrptr_g1p.clock = wrclk;
	wrptr_g1p.cnt_en = valid_wrreq;
	wrptr_gp.aclr = aclr;
	wrptr_gp.clock = wrclk;
	wrptr_gp.cnt_en = valid_wrreq;
	fifo_ram.aclr1 = aclr;
	fifo_ram.address_a[] = ram_address_a[];
	fifo_ram.address_b[] = ram_address_b[];
	fifo_ram.addressstall_b = (! rdcnt_addr_ena);
	fifo_ram.clock0 = wrclk;
	fifo_ram.clock1 = rdclk;
	fifo_ram.clocken1 = valid_rdreq;
	fifo_ram.data_a[] = data[];
	fifo_ram.wren_a = valid_wrreq;
	delayed_wrptr_g[].clk = wrclk;
	delayed_wrptr_g[].clrn = (! aclr);
	delayed_wrptr_g[].d = wrptr_gp.q[];
	p0addr.clk = rdclk;
	p0addr.clrn = rdaclr.q[];
	p0addr.d = B"1";
	rdptr_g[].clk = rdclk;
	rdptr_g[].clrn = (! aclr);
	rdptr_g[].d = rdptr_g1p.q[];
	rdptr_g[].ena = valid_rdreq;
	rdaclr.clock = (! rdclk);
	rdaclr.clrn = (! aclr);
	rdaclr.d[] = B"1";
	rs_dgwp.clock = rdclk;
	rs_dgwp.clrn = (! aclr);
	rs_dgwp.d[] = delayed_wrptr_g[].q;
	ws_dgrp.clock = wrclk;
	ws_dgrp.clrn = (! aclr);
	ws_dgrp.d[] = rdptr_g[].q;
	rdempty_eq_comp.dataa[] = rs_dgwp.q[];
	rdempty_eq_comp.datab[] = rdptr_g[].q;
	wrfull_eq_comp.dataa[] = ws_dgrp.q[];
	wrfull_eq_comp.datab[] = wrptr_gs[];
	int_rdempty = rdempty_eq_comp.aeb;
	int_wrfull = wrfull_eq_comp.aeb;
	q[] = fifo_ram.q_b[];
	ram_address_a[] = ( (wrptr_gp.q[8..8] $ wrptr_gp.q[7..7]), wrptr_gp.q[6..0]);
	ram_address_b[] = ( (rdptr_g1p.q[8..8] $ rdptr_g1p.q[7..7]), rdptr_g1p.q[6..0]);
	rdcnt_addr_ena = (valid_rdreq # (! p0addr.q));
	valid_rdreq = (rdreq & (! int_rdempty));
	valid_wrreq = (wrreq & (! int_wrfull));
	wrfull = int_wrfull;
	wrptr_gs[] = ( (! wrptr_gp.q[8..8]), (! wrptr_gp.q[7..7]), wrptr_gp.q[6..0]);
END;
--VALID FILE
