datasheet for system_0

system_0 |

2013.04.12.14:11:19 | Datasheet

Overview

clk | system_0
| uart_0
| rxd
| txd
| lcd_16207_0
| LCD_data
| LCD_E
| LCD_RS
| LCD_RW
| SEG7_Display
| oSEG0
| oSEG1
| oSEG2
| oSEG3
| oSEG4
| oSEG5
| oSEG6
| oSEG7
| SRAM_DQ
| SRAM_ADDR
| SRAM_UB_N
| SRAM_LB_N
| SRAM_WE_N
| SRAM_CE_N
| SRAM_OE_N
| oAUD_DATA
| oAUD_LRCK
| oAUD_BCK
| oAUD_XCK
| iCLK_18_4
| SD_DAT
| bidir_port
| bidir_port
| out_port
| in_port
| in_port
| in_port
| in_port
| in_port
| in_port
| in_port
| in_port
| in_port
| in_port
| in_port
| in_port

Processor
cpu_0 Nios II 10.1
All Components
cpu_0 altera_nios2 10.1
tri_state_bridge_0 altera_avalon_tri_state_bridge 10.1
sdram_0 altera_avalon_new_sdram_controller 10.1
epcs_controller altera_avalon_epcs_flash_controller 10.1
jtag_uart_0 altera_avalon_jtag_uart 10.1
uart_0 altera_avalon_uart 10.1
timer_0 altera_avalon_timer 10.1
timer_1 altera_avalon_timer 10.1
lcd_16207_0 altera_avalon_lcd_16207 10.1
SEG7_Display seg7_lut_8 1.0
sram_0 sram_16bit_512k 1.0
Audio_0 audio_dac_fifo 1.0
SD_DAT altera_avalon_pio 10.1
SD_CMD altera_avalon_pio 10.1
SD_CLK altera_avalon_pio 10.1
noteA altera_avalon_pio 10.1
noteB altera_avalon_pio 10.1
noteC altera_avalon_pio 10.1
noteD altera_avalon_pio 10.1
noteE altera_avalon_pio 10.1
noteF altera_avalon_pio 10.1
noteG altera_avalon_pio 10.1
MS altera_avalon_pio 10.1
dist_sensor altera_avalon_pio 10.1
RST altera_avalon_pio 10.1
Oct_UP altera_avalon_pio 10.1
Oct_DOWN altera_avalon_pio 10.1
Accel_Control accelerometer 1.0
i2c_master opencores_i2c_master 1.0
altpll_0 altpll 10.1
Memory Map

| cpu_0
instruction_master | data_master
cpu_0 |  |
jtag_debug_module | 0x01909000 | 0x01909000
cfi_flash_0 |  |
s1 | 0x01400000 | 0x01400000
sdram_0 |  |
s1 | 0x00800000 | 0x00800000
epcs_controller |  |
epcs_control_port | 0x01909800 | 0x01909800
jtag_uart_0 |  |
avalon_jtag_slave |  | 0x0190a1d0
uart_0 |  |
s1 |  | 0x0190a020
timer_0 |  |
s1 |  | 0x0190a040
timer_1 |  |
s1 |  | 0x0190a060
lcd_16207_0 |  |
control_slave |  | 0x0190a0c0
SEG7_Display |  |
avalon_slave_0 |  | 0x0190a1d8
sram_0 |  |
avalon_slave_0 | 0x01880000 | 0x01880000
Audio_0 |  |
avalon_slave_0 |  | 0x0190a1dc
SD_DAT |  |
s1 |  | 0x0190a0d0
SD_CMD |  |
s1 |  | 0x0190a0e0
SD_CLK |  |
s1 |  | 0x0190a0f0
noteA |  |
s1 |  | 0x0190a100
noteB |  |
s1 |  | 0x0190a110
noteC |  |
s1 |  | 0x0190a120
noteD |  |
s1 |  | 0x0190a130
noteE |  |
s1 |  | 0x0190a140
noteF |  |
s1 |  | 0x0190a150
noteG |  |
s1 |  | 0x0190a160
MS |  |
s1 |  | 0x0190a170
dist_sensor |  |
s1 |  | 0x0190a180
RST |  |
s1 |  | 0x0190a190
Oct_UP |  |
s1 |  | 0x0190a1a0
Oct_DOWN |  |
s1 |  | 0x0190a1b0
Accel_Control |  |
avalon_slave |  | 0x0190a080
i2c_master |  |
avalon_slave_0 | 0x0190a0a0 | 0x0190a0a0
altpll_0 |  |
pll_slave |  | 0x0190a1c0

## clk

clock_source v10.1

## Parameters

clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## cpu_0

altera_nios2 v10.1

altpll_0 | c1 | cpu_0
clk
|  | instruction_master | tri_state_bridge_0
|  | avalon_slave
|  | data_master
|  | avalon_slave
|  | instruction_master | sdram_0
|  | s1
|  | data_master
|  | s1
|  | instruction_master | epcs_controller
|  | epcs_control_port
|  | data_master
|  | epcs_control_port
|  | d_irq
|  | irq
|  | data_master | jtag_uart_0
|  | avalon_jtag_slave
|  | d_irq
|  | irq
|  | data_master | uart_0
|  | s1
|  | d_irq
|  | irq
|  | data_master | timer_0
|  | s1
|  | d_irq
|  | irq
|  | data_master | timer_1
|  | s1
|  | d_irq
|  | irq
|  | data_master | lcd_16207_0
|  | control_slave
|  | data_master | SEG7_Display
|  | avalon_slave_0
|  | instruction_master | sram_0
|  | avalon_slave_0
|  | data_master
|  | avalon_slave_0
|  | data_master | Audio_0
|  | avalon_slave_0
|  | data_master | SD_DAT
|  | s1
|  | data_master | SD_CMD
|  | s1
|  | data_master | SD_CLK
|  | s1
|  | data_master | noteA
|  | s1
|  | data_master | noteB
|  | s1
|  | data_master | noteC
|  | s1
|  | data_master | noteD
|  | s1
|  | data_master | noteE
|  | s1
|  | data_master | noteF
|  | s1
|  | data_master | noteG
|  | s1
|  | data_master | MS
|  | s1
|  | d_irq
|  | irq
|  | data_master | dist_sensor
|  | s1
|  | d_irq
|  | irq
|  | data_master | RST
|  | s1
|  | d_irq
|  | irq
|  | data_master | Oct_UP
|  | s1
|  | d_irq
|  | irq
|  | data_master | Oct_DOWN
|  | s1
|  | d_irq
|  | irq
|  | data_master | Accel_Control
|  | avalon_slave
|  | instruction_master | i2c_master
|  | avalon_slave_0
|  | data_master
|  | avalon_slave_0
|  | d_irq
|  | avalon_slave_0_irq
|  | data_master | altpll_0
|  | pll_slave

## Parameters

userDefinedSettings |
tightlyCoupledInstructionMaster3MapParam |
tightlyCoupledInstructionMaster3AddrWidth | 1
tightlyCoupledInstructionMaster2MapParam |
tightlyCoupledInstructionMaster2AddrWidth | 1
tightlyCoupledInstructionMaster1MapParam |
tightlyCoupledInstructionMaster1AddrWidth | 1
tightlyCoupledInstructionMaster0MapParam |
tightlyCoupledInstructionMaster0AddrWidth | 1
tightlyCoupledDataMaster3MapParam |
tightlyCoupledDataMaster3AddrWidth | 1
tightlyCoupledDataMaster2MapParam |
tightlyCoupledDataMaster2AddrWidth | 1
tightlyCoupledDataMaster1MapParam |
tightlyCoupledDataMaster1AddrWidth | 1
tightlyCoupledDataMaster0MapParam |
tightlyCoupledDataMaster0AddrWidth | 1
setting_showUnpublishedSettings | false
setting_showInternalSettings | false
setting_shadowRegisterSets | 0
setting_preciseSlaveAccessErrorException | false
setting_preciseIllegalMemAccessException | false
setting_preciseDivisionErrorException | false
setting_performanceCounter | false
setting_perfCounterWidth | _32
setting_interruptControllerType | Internal
setting_illegalMemAccessDetection | false
setting_illegalInstructionsTrap | false
setting_fullWaveformSignals | false
setting_extraExceptionInfo | false
setting_exportPCB | false
setting_debugSimGen | false
setting_clearXBitsLDNonBypass | true
setting_branchPredictionType | Dynamic
setting_bit31BypassDCache | true
setting_bigEndian | false
setting_bhtPtrSz | _8
setting_bhtIndexPcOnly | false
setting_avalonDebugPortPresent | false
setting_alwaysEncrypt | true
setting_allowFullAddressRange | false
setting_activateTrace | true
setting_activateTestEndChecker | false
setting_activateMonitors | true
setting_activateModelChecker | false
setting_HDLSimCachesCleared | true
setting_HBreakTest | false
resetSlave | cfi_flash_0.s1
resetOffset | 0
muldiv_multiplierType | EmbeddedMulFast
muldiv_divider | false
mpu_useLimit | false
mpu_numOfInstRegion | 8
mpu_numOfDataRegion | 8
mpu_minInstRegionSize | _12
mpu_minDataRegionSize | _12
mpu_enabled | false
mmu_uitlbNumEntries | _4
mmu_udtlbNumEntries | _6
mmu_tlbPtrSz | _7
mmu_tlbNumWays | _16
mmu_processIDNumBits | _10
mmu_enabled | false
mmu_autoAssignTlbPtrSz | true
mmu_TLBMissExcSlave |
mmu_TLBMissExcOffset | 0
manuallyAssignCpuID | false
internalIrqMaskSystemInfo | 2047
instSlaveMapParam | <address-map><slave name='sdram_0.s1' start='0x800000' end='0x1000000' /><slave name='cfi_flash_0.s1' start='0x1400000' end='0x1800000' /><slave name='sram_0.avalon_slave_0' start='0x1880000' end='0x1900000' /><slave name='cpu_0.jtag_debug_module' start='0x1909000' end='0x1909800' /><slave name='epcs_controller.epcs_control_port' start='0x1909800' end='0x190A000' /><slave name='i2c_master.avalon_slave_0' start='0x190A0A0' end='0x190A0C0' /></address-map>
instAddrWidth | 25
impl | Fast
icache_size | _8192
icache_ramBlockType | Automatic
icache_numTCIM | _0
icache_burstType | Sequential
exceptionSlave | sdram_0.s1
exceptionOffset | 32
deviceFeaturesSystemInfo | M512_MEMORY 0 M4K_MEMORY 1 M9K_MEMORY 0 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0
deviceFamilyName | Cyclone II
debug_triggerArming | true
debug_level | Level1
debug_jtagInstanceID | 0
debug_embeddedPLL | true
debug_debugReqSignals | false
debug_assignJtagInstanceID | false
debug_OCIOnchipTrace | _128
dcache_size | _8192
dcache_ramBlockType | Automatic
dcache_omitDataMaster | false
dcache_numTCDM | _0
dcache_lineSize | _32
dcache_bursts | true
dataSlaveMapParam | <address-map><slave name='sdram_0.s1' start='0x800000' end='0x1000000' /><slave name='cfi_flash_0.s1' start='0x1400000' end='0x1800000' /><slave name='sram_0.avalon_slave_0' start='0x1880000' end='0x1900000' /><slave name='cpu_0.jtag_debug_module' start='0x1909000' end='0x1909800' /><slave name='epcs_controller.epcs_control_port' start='0x1909800' end='0x190A000' /><slave name='uart_0.s1' start='0x190A020' end='0x190A040' /><slave name='timer_0.s1' start='0x190A040' end='0x190A060' /><slave name='timer_1.s1' start='0x190A060' end='0x190A080' /><slave name='Accel_Control.avalon_slave' start='0x190A080' end='0x190A0A0' /><slave name='i2c_master.avalon_slave_0' start='0x190A0A0' end='0x190A0C0' /><slave name='lcd_16207_0.control_slave' start='0x190A0C0' end='0x190A0D0' /><slave name='SD_DAT.s1' start='0x190A0D0' end='0x190A0E0' /><slave name='SD_CMD.s1' start='0x190A0E0' end='0x190A0F0' /><slave name='SD_CLK.s1' start='0x190A0F0' end='0x190A100' /><slave name='noteA.s1' start='0x190A100' end='0x190A110' /><slave name='noteB.s1' start='0x190A110' end='0x190A120' /><slave name='noteC.s1' start='0x190A120' end='0x190A130' /><slave name='noteD.s1' start='0x190A130' end='0x190A140' /><slave name='noteE.s1' start='0x190A140' end='0x190A150' /><slave name='noteF.s1' start='0x190A150' end='0x190A160' /><slave name='noteG.s1' start='0x190A160' end='0x190A170' /><slave name='MS.s1' start='0x190A170' end='0x190A180' /><slave name='dist_sensor.s1' start='0x190A180' end='0x190A190' /><slave name='RST.s1' start='0x190A190' end='0x190A1A0' /><slave name='Oct_UP.s1' start='0x190A1A0' end='0x190A1B0' /><slave name='Oct_DOWN.s1' start='0x190A1B0' end='0x190A1C0' /><slave name='altpll_0.pll_slave' start='0x190A1C0' end='0x190A1D0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x190A1D0' end='0x190A1D8' /><slave name='SEG7_Display.avalon_slave_0' start='0x190A1D8' end='0x190A1DC' /><slave name='Audio_0.avalon_slave_0' start='0x190A1DC' end='0x190A1E0' /></address-map>
dataAddrWidth | 25
customInstSlavesSystemInfo | <info/>
cpuReset | false
cpuID | 0
clockFrequency | 100000000
breakSlave | cpu_0.jtag_debug_module
breakOffset | 32
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

CPU_IMPLEMENTATION | "fast"
BIG_ENDIAN | 0
CPU_FREQ | 100000000u
ICACHE_LINE_SIZE | 32
ICACHE_LINE_SIZE_LOG2 | 5
ICACHE_SIZE | 8192
DCACHE_LINE_SIZE | 32
DCACHE_LINE_SIZE_LOG2 | 5
DCACHE_SIZE | 8192
INITDA_SUPPORTED |
FLUSHDA_SUPPORTED |
HAS_JMPI_INSTRUCTION |
EXCEPTION_ADDR | 0x800020
RESET_ADDR | 0x1400000
BREAK_ADDR | 0x1909020
HAS_DEBUG_STUB |
HAS_DEBUG_CORE | 1
CPU_ID_SIZE | 1
CPU_ID_VALUE | 0x0
HARDWARE_DIVIDE_PRESENT | 0
HARDWARE_MULTIPLY_PRESENT | 1
HARDWARE_MULX_PRESENT | 0
INST_ADDR_WIDTH | 25
DATA_ADDR_WIDTH | 25
NUM_OF_SHADOW_REG_SETS | 0

## tri_state_bridge_0

altera_avalon_tri_state_bridge v10.1

cpu_0 | instruction_master | tri_state_bridge_0
avalon_slave
data_master
avalon_slave
altpll_0 | c1
clk
|  | tristate_master | cfi_flash_0
|  | s1

## Parameters

registerIncomingSignals | true
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## cfi_flash_0

altera_avalon_cfi_flash v10.1

tri_state_bridge_0 | tristate_master | cfi_flash_0
s1
altpll_0 | c1
clk

## Parameters

actualHoldTime | 40.0
actualSetupTime | 40.0
actualWaitTime | 160.0
addressWidth | 22
clockRate | 100000000
corePreset | CUSTOM
dataWidth | 8
holdTime | 40
setupTime | 40
sharedPorts | s1/data,s1/address,s1/read_n
timingUnits | NS
waitTime | 160
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

SETUP_VALUE | 40
WAIT_VALUE | 160
HOLD_VALUE | 40
TIMING_UNITS | "ns"
SIZE | 4194304u

## sdram_0

altera_avalon_new_sdram_controller v10.1

cpu_0 | instruction_master | sdram_0
s1
data_master
s1
altpll_0 | c1
clk

## Parameters

TAC | 5.5
TMRD | 3
TRCD | 20.0
TRFC | 70.0
TRP | 20.0
TWR | 14.0
casLatency | 3
clockRate | 100000000
columnWidth | 8
dataWidth | 16
generateSimulationModel | true
initNOPDelay | 0.0
initRefreshCommands | 2
masteredTristateBridgeSlave |
model | custom
numberOfBanks | 4
numberOfChipSelects | 1
pinsSharedViaTriState | false
powerUpDelay | 100.0
refreshPeriod | 15.625
registerDataIn | true
rowWidth | 12
size | 8388608
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

REGISTER_DATA_IN | 1
SIM_MODEL_BASE | 1
SDRAM_DATA_WIDTH | 16
SDRAM_ADDR_WIDTH | 22
SDRAM_ROW_WIDTH | 12
SDRAM_COL_WIDTH | 8
SDRAM_NUM_CHIPSELECTS | 1
SDRAM_NUM_BANKS | 4
REFRESH_PERIOD | 15.625
POWERUP_DELAY | 100.0
CAS_LATENCY | 3
T_RFC | 70.0
T_RP | 20.0
T_MRD | 3
T_RCD | 20.0
T_AC | 5.5
T_WR | 14.0
INIT_REFRESH_COMMANDS | 2
INIT_NOP_DELAY | 0.0
SHARED_DATA | 0
STARVATION_INDICATOR | 0
TRISTATE_BRIDGE_SLAVE | ""
IS_INITIALIZED | 1
SDRAM_BANK_WIDTH | 2
CONTENTS_INFO | ""

## epcs_controller

altera_avalon_epcs_flash_controller v10.1

cpu_0 | instruction_master | epcs_controller
epcs_control_port
data_master
epcs_control_port
d_irq
irq
altpll_0 | c1
clk

## Parameters

autoSelectASMIAtom | true
deviceFamilyString | Cyclone II
useASMIAtom | true
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

REGISTER_OFFSET | 512

## jtag_uart_0

altera_avalon_jtag_uart v10.1

cpu_0 | data_master | jtag_uart_0
avalon_jtag_slave
d_irq
irq
altpll_0 | c1
clk

## Parameters

allowMultipleConnections | false
hubInstanceID | 0
readBufferDepth | 64
readIRQThreshold | 8
simInputCharacterStream |
simInteractiveOptions | INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer | false
useRegistersForWriteBuffer | false
useRelativePathForSimFile | false
writeBufferDepth | 64
writeIRQThreshold | 8
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

WRITE_DEPTH | 64
READ_DEPTH | 64
WRITE_THRESHOLD | 8
READ_THRESHOLD | 8

## uart_0

altera_avalon_uart v10.1

cpu_0 | data_master | uart_0
s1
d_irq
irq
altpll_0 | c1
clk

## Parameters

baud | 115200
baudError | 0.01
clockRate | 100000000
dataBits | 8
fixedBaud | true
parity | NONE
simCharStream |
simInteractiveInputEnable | false
simInteractiveOutputEnable | false
simTrueBaud | false
stopBits | 1
syncRegDepth | 2
useCtsRts | false
useEopRegister | false
useRelativePathForSimFile | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BAUD | 115200
DATA_BITS | 8
FIXED_BAUD | 1
PARITY | 'N'
STOP_BITS | 1
SYNC_REG_DEPTH | 2
USE_CTS_RTS | 0
USE_EOP_REGISTER | 0
SIM_TRUE_BAUD | 0
SIM_CHAR_STREAM | ""
FREQ | 100000000u

## timer_0

altera_avalon_timer v10.1

cpu_0 | data_master | timer_0
s1
d_irq
irq
altpll_0 | c1
clk

## Parameters

alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 1
periodUnits | MSEC
resetOutput | false
snapshot | true
systemFrequency | 100000000
timeoutPulseOutput | false
timerPreset | CUSTOM
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

ALWAYS_RUN | 0
FIXED_PERIOD | 0
SNAPSHOT | 1
PERIOD | 1
PERIOD_UNITS | "ms"
RESET_OUTPUT | 0
TIMEOUT_PULSE_OUTPUT | 0
FREQ | 100000000u
LOAD_VALUE | 99999ULL
COUNTER_SIZE | 32
MULT | 0.0010
TICKS_PER_SEC | 1000u

## timer_1

altera_avalon_timer v10.1

cpu_0 | data_master | timer_1
s1
d_irq
irq
altpll_0 | c1
clk

## Parameters

alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 1
periodUnits | MSEC
resetOutput | false
snapshot | true
systemFrequency | 100000000
timeoutPulseOutput | false
timerPreset | CUSTOM
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

ALWAYS_RUN | 0
FIXED_PERIOD | 0
SNAPSHOT | 1
PERIOD | 1
PERIOD_UNITS | "ms"
RESET_OUTPUT | 0
TIMEOUT_PULSE_OUTPUT | 0
FREQ | 100000000u
LOAD_VALUE | 99999ULL
COUNTER_SIZE | 32
MULT | 0.0010
TICKS_PER_SEC | 1000u

## lcd_16207_0

altera_avalon_lcd_16207 v10.1

cpu_0 | data_master | lcd_16207_0
control_slave
altpll_0 | c1
clk

## Parameters

deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## SEG7_Display

seg7_lut_8 v1.0

cpu_0 | data_master | SEG7_Display
avalon_slave_0
altpll_0 | c1
clk

## Parameters

instancePTF | MODULE SEG7_Display { class = "seg7_lut_8"; class_version = "1.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Has_Clock = "1"; Top_Level_Ports_Are_Enumerated = "1"; Is_Enabled = "1"; Clock_Source = "clk"; View { MESSAGES { } Is_Collapsed = "1"; } } COMPONENT_BUILDER { GLS_SETTINGS { } } PORT_WIRING { PORT iCLK { width = "1"; width_expression = ""; direction = "input"; type = "clk"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } } WIZARD_SCRIPT_ARGUMENTS { hdl_parameters { } } SIMULATION { DISPLAY { } } SLAVE avalon_slave_0 { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Group = "1"; Has_Clock = "0"; Address_Width = "0"; Address_Alignment = "native"; Data_Width = "32"; Has_Base_Address = "1"; Has_IRQ = "0"; Setup_Time = "0cycles"; Hold_Time = "0cycles"; Read_Wait_States = "1cycles"; Write_Wait_States = "1cycles"; Read_Latency = "0"; Maximum_Pending_Read_Transactions = "0"; Active_CS_Through_Read_Latency = "0"; Is_Printable_Device = "0"; Is_Memory_Device = "0"; Is_Readable = "0"; Is_Writable = "1"; Minimum_Uninterrupted_Run_Length = "1"; MASTERED_BY cpu_0/data_master { priority = "1"; } Base_Address = "0x00681100"; IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } } COMPONENT_BUILDER { AVS_SETTINGS { Setup_Value = "0"; Read_Wait_Value = "1"; Write_Wait_Value = "1"; Hold_Value = "0"; Timing_Units = "cycles"; Read_Latency_Value = "0"; Minimum_Arbitration_Shares = "1"; Active_CS_Through_Read_Latency = "0"; Max_Pending_Read_Transactions_Value = "1"; Address_Alignment = "native"; Is_Printable_Device = "0"; Interleave_Bursts = "0"; interface_name = "Avalon Slave"; external_wait = "0"; Is_Memory_Device = "0"; } } PORT_WIRING { PORT iDIG { width = "32"; width_expression = ""; direction = "input"; type = "writedata"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iWR { width = "1"; width_expression = ""; direction = "input"; type = "write"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iRST_N { width = "1"; width_expression = ""; direction = "input"; type = "reset_n"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT oSEG0 { width = "7"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT oSEG1 { width = "7"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT oSEG2 { width = "7"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT oSEG3 { width = "7"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT oSEG4 { width = "7"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT oSEG5 { width = "7"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT oSEG6 { width = "7"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT oSEG7 { width = "7"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } } } HDL_INFO { Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/SEG7_LUT.v,__PROJECT_DIRECTORY__/SEG7_LUT_8.v, __PROJECT_DIRECTORY__/SEG7_Display.v"; } }
sharedPorts |
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## sram_0

sram_16bit_512k v1.0

cpu_0 | instruction_master | sram_0
avalon_slave_0
data_master
avalon_slave_0
altpll_0 | c1
clk

## Parameters

instancePTF | MODULE sram_0 { class = "sram_16bit_512k"; class_version = "1.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Has_Clock = "1"; Top_Level_Ports_Are_Enumerated = "1"; Is_Enabled = "1"; Clock_Source = "clk"; View { MESSAGES { } Is_Collapsed = "1"; } } COMPONENT_BUILDER { GLS_SETTINGS { } } PORT_WIRING { PORT iCLK { width = "1"; width_expression = ""; direction = "input"; type = "clk"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } } WIZARD_SCRIPT_ARGUMENTS { hdl_parameters { } } SIMULATION { DISPLAY { } } SLAVE avalon_slave_0 { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Group = "1"; Has_Clock = "0"; Address_Width = "18"; Address_Alignment = "dynamic"; Data_Width = "16"; Has_Base_Address = "1"; Has_IRQ = "0"; Setup_Time = "20ns"; Hold_Time = "20ns"; Read_Wait_States = "20ns"; Write_Wait_States = "20ns"; Read_Latency = "0"; Maximum_Pending_Read_Transactions = "0"; Active_CS_Through_Read_Latency = "0"; Is_Printable_Device = "0"; Is_Memory_Device = "1"; Is_Readable = "1"; Is_Writable = "1"; Minimum_Uninterrupted_Run_Length = "1"; Base_Address = "0x00600000"; } COMPONENT_BUILDER { AVS_SETTINGS { Setup_Value = "20"; Read_Wait_Value = "20"; Write_Wait_Value = "20"; Hold_Value = "20"; Timing_Units = "ns"; Read_Latency_Value = "0"; Minimum_Arbitration_Shares = "1"; Active_CS_Through_Read_Latency = "0"; Max_Pending_Read_Transactions_Value = "1"; Address_Alignment = "dynamic"; Is_Printable_Device = "0"; Interleave_Bursts = "0"; interface_name = "Avalon Slave"; external_wait = "0"; Is_Memory_Device = "1"; } } PORT_WIRING { PORT iDATA { width = "16"; width_expression = ""; direction = "input"; type = "writedata"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT oDATA { width = "16"; width_expression = ""; direction = "output"; type = "readdata"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iADDR { width = "18"; width_expression = ""; direction = "input"; type = "address"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iWE_N { width = "1"; width_expression = ""; direction = "input"; type = "write_n"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iOE_N { width = "1"; width_expression = ""; direction = "input"; type = "read_n"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iCE_N { width = "1"; width_expression = ""; direction = "input"; type = "chipselect_n"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iBE_N { width = "2"; width_expression = ""; direction = "input"; type = "byteenable_n"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT SRAM_DQ { width = "16"; width_expression = ""; direction = "inout"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT SRAM_ADDR { width = "18"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT SRAM_UB_N { width = "1"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT SRAM_LB_N { width = "1"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT SRAM_WE_N { width = "1"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT SRAM_CE_N { width = "1"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT SRAM_OE_N { width = "1"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } } } HDL_INFO { Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/SRAM_16Bit_512K.v, __PROJECT_DIRECTORY__/sram_0.v"; } }
sharedPorts |
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## Audio_0

audio_dac_fifo v1.0

cpu_0 | data_master | Audio_0
avalon_slave_0
altpll_0 | c1
clk

## Parameters

instancePTF | MODULE Audio_0 { class = "audio_dac_fifo"; class_version = "1.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Has_Clock = "1"; Top_Level_Ports_Are_Enumerated = "1"; Is_Enabled = "1"; Clock_Source = "clk"; View { MESSAGES { } Is_Collapsed = "1"; } } COMPONENT_BUILDER { GLS_SETTINGS { } } PORT_WIRING { PORT iWR_CLK { width = "1"; width_expression = ""; direction = "input"; type = "clk"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } } WIZARD_SCRIPT_ARGUMENTS { hdl_parameters { ref_clk = "18432000"; sample_rate = "48000"; data_width = "16"; channel_num = "2"; } } SIMULATION { DISPLAY { } } SLAVE avalon_slave_0 { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Group = "1"; Has_Clock = "0"; Address_Width = "0"; Address_Alignment = "native"; Data_Width = "16"; Has_Base_Address = "1"; Has_IRQ = "0"; Setup_Time = "0cycles"; Hold_Time = "0cycles"; Read_Wait_States = "0cycles"; Write_Wait_States = "0cycles"; Read_Latency = "0"; Maximum_Pending_Read_Transactions = "0"; Active_CS_Through_Read_Latency = "0"; Is_Printable_Device = "0"; Is_Memory_Device = "0"; Is_Readable = "0"; Is_Writable = "1"; Minimum_Uninterrupted_Run_Length = "1"; Base_Address = "0x00681104"; } COMPONENT_BUILDER { AVS_SETTINGS { Setup_Value = "0"; Read_Wait_Value = "0"; Write_Wait_Value = "0"; Hold_Value = "0"; Timing_Units = "cycles"; Read_Latency_Value = "0"; Minimum_Arbitration_Shares = "1"; Active_CS_Through_Read_Latency = "0"; Max_Pending_Read_Transactions_Value = "1"; Address_Alignment = "native"; Is_Printable_Device = "0"; Interleave_Bursts = "0"; interface_name = "Avalon Slave"; external_wait = "0"; Is_Memory_Device = "0"; } } PORT_WIRING { PORT iDATA { width = "16"; width_expression = "((DATA_WIDTH - 1)) - (0) + 1"; direction = "input"; type = "writedata"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iWR { width = "1"; width_expression = ""; direction = "input"; type = "write"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT oDATA { width = "16"; width_expression = "((DATA_WIDTH - 1)) - (0) + 1"; direction = "output"; type = "readdata"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT oAUD_DATA { width = "1"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT oAUD_LRCK { width = "1"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT oAUD_BCK { width = "1"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT oAUD_XCK { width = "1"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iCLK_18_4 { width = "1"; width_expression = ""; direction = "input"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iRST_N { width = "1"; width_expression = ""; direction = "input"; type = "reset_n"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } } } HDL_INFO { Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/AUDIO_DAC_FIFO.v,__PROJECT_DIRECTORY__/FIFO_16_256.v, __PROJECT_DIRECTORY__/Audio_0.v"; } }
sharedPorts |
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## SD_DAT

altera_avalon_pio v10.1

cpu_0 | data_master | SD_DAT
s1
altpll_0 | c1
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Bidir
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 1
HAS_OUT | 0
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## SD_CMD

altera_avalon_pio v10.1

cpu_0 | data_master | SD_CMD
s1
altpll_0 | c1
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Bidir
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 1
HAS_OUT | 0
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## SD_CLK

altera_avalon_pio v10.1

cpu_0 | data_master | SD_CLK
s1
altpll_0 | c1
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## noteA

altera_avalon_pio v10.1

cpu_0 | data_master | noteA
s1
altpll_0 | c1
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## noteB

altera_avalon_pio v10.1

cpu_0 | data_master | noteB
s1
altpll_0 | c1
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## noteC

altera_avalon_pio v10.1

cpu_0 | data_master | noteC
s1
altpll_0 | c1
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## noteD

altera_avalon_pio v10.1

cpu_0 | data_master | noteD
s1
altpll_0 | c1
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## noteE

altera_avalon_pio v10.1

cpu_0 | data_master | noteE
s1
altpll_0 | c1
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## noteF

altera_avalon_pio v10.1

cpu_0 | data_master | noteF
s1
altpll_0 | c1
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## noteG

altera_avalon_pio v10.1

cpu_0 | data_master | noteG
s1
altpll_0 | c1
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## MS

altera_avalon_pio v10.1

cpu_0 | data_master | MS
s1
d_irq
irq
altpll_0 | c1
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | true
clockRate | 100000000
direction | Input
edgeType | FALLING
generateIRQ | true
irqType | EDGE
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 1
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "FALLING"
IRQ_TYPE | "EDGE"
FREQ | 100000000u

## dist_sensor

altera_avalon_pio v10.1

cpu_0 | data_master | dist_sensor
s1
d_irq
irq
altpll_0 | c1
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | true
clockRate | 100000000
direction | Input
edgeType | FALLING
generateIRQ | true
irqType | EDGE
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 1
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "FALLING"
IRQ_TYPE | "EDGE"
FREQ | 100000000u

## RST

altera_avalon_pio v10.1

cpu_0 | data_master | RST
s1
d_irq
irq
altpll_0 | c1
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | true
clockRate | 100000000
direction | Input
edgeType | FALLING
generateIRQ | true
irqType | EDGE
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 1
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "FALLING"
IRQ_TYPE | "EDGE"
FREQ | 100000000u

## Oct_UP

altera_avalon_pio v10.1

cpu_0 | data_master | Oct_UP
s1
d_irq
irq
altpll_0 | c1
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | true
clockRate | 100000000
direction | Input
edgeType | FALLING
generateIRQ | true
irqType | EDGE
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 1
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "FALLING"
IRQ_TYPE | "EDGE"
FREQ | 100000000u

## Oct_DOWN

altera_avalon_pio v10.1

cpu_0 | data_master | Oct_DOWN
s1
d_irq
irq
altpll_0 | c1
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | true
clockRate | 100000000
direction | Input
edgeType | FALLING
generateIRQ | true
irqType | EDGE
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 1
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "FALLING"
IRQ_TYPE | "EDGE"
FREQ | 100000000u

## Accel_Control

accelerometer v1.0

cpu_0 | data_master | Accel_Control
avalon_slave
altpll_0 | c1
clock

## Parameters

AUTO_CLOCK_CLOCK_RATE | 100000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## i2c_master

opencores_i2c_master v1.0

cpu_0 | instruction_master | i2c_master
avalon_slave_0
data_master
avalon_slave_0
d_irq
avalon_slave_0_irq
altpll_0 | c1
avalon_slave_0_clock

## Parameters

AUTO_AVALON_SLAVE_0_CLOCK_CLOCK_RATE | 100000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## altpll_0

altpll v10.1

clk | clk | altpll_0
inclk_interface
cpu_0 | data_master
pll_slave
|  | c1 | sdram_0
|  | clk
|  | c1 | i2c_master
|  | avalon_slave_0_clock
|  | c1 | Accel_Control
|  | clock
|  | c1 | Oct_DOWN
|  | clk
|  | c1 | Oct_UP
|  | clk
|  | c1 | RST
|  | clk
|  | c1 | dist_sensor
|  | clk
|  | c1 | MS
|  | clk
|  | c1 | noteG
|  | clk
|  | c1 | noteF
|  | clk
|  | c1 | noteE
|  | clk
|  | c1 | noteD
|  | clk
|  | c1 | noteC
|  | clk
|  | c1 | noteB
|  | clk
|  | c1 | noteA
|  | clk
|  | c1 | SD_CLK
|  | clk
|  | c1 | SD_CMD
|  | clk
|  | c1 | SD_DAT
|  | clk
|  | c1 | Audio_0
|  | clk
|  | c1 | sram_0
|  | clk
|  | c1 | SEG7_Display
|  | clk
|  | c1 | lcd_16207_0
|  | clk
|  | c1 | timer_1
|  | clk
|  | c1 | timer_0
|  | clk
|  | c1 | uart_0
|  | clk
|  | c1 | jtag_uart_0
|  | clk
|  | c1 | epcs_controller
|  | clk
|  | c1 | cfi_flash_0
|  | clk
|  | c1 | tri_state_bridge_0
|  | clk
|  | c1 | cpu_0
|  | clk

## Parameters

HIDDEN_CUSTOM_ELABORATION | altpll_avalon_elaboration
HIDDEN_CUSTOM_POST_EDIT | altpll_avalon_post_edit
INTENDED_DEVICE_FAMILY | Cyclone II
WIDTH_CLOCK |
WIDTH_PHASECOUNTERSELECT |
PRIMARY_CLOCK |
INCLK0_INPUT_FREQUENCY | 20000
INCLK1_INPUT_FREQUENCY |
OPERATION_MODE | NORMAL
PLL_TYPE |
QUALIFY_CONF_DONE |
COMPENSATE_CLOCK | CLK1
SCAN_CHAIN |
GATE_LOCK_SIGNAL | NO
GATE_LOCK_COUNTER |
LOCK_HIGH |
LOCK_LOW |
VALID_LOCK_MULTIPLIER | 1
INVALID_LOCK_MULTIPLIER | 5
SWITCH_OVER_ON_LOSSCLK |
SWITCH_OVER_ON_GATED_LOCK |
ENABLE_SWITCH_OVER_COUNTER |
SKIP_VCO |
SWITCH_OVER_COUNTER |
SWITCH_OVER_TYPE |
FEEDBACK_SOURCE |
BANDWIDTH |
BANDWIDTH_TYPE |
SPREAD_FREQUENCY |
DOWN_SPREAD |
SELF_RESET_ON_GATED_LOSS_LOCK |
SELF_RESET_ON_LOSS_LOCK |
CLK0_MULTIPLY_BY | 2
CLK1_MULTIPLY_BY | 2
CLK2_MULTIPLY_BY |
CLK3_MULTIPLY_BY |
CLK4_MULTIPLY_BY |
CLK5_MULTIPLY_BY |
CLK6_MULTIPLY_BY |
CLK7_MULTIPLY_BY |
CLK8_MULTIPLY_BY |
CLK9_MULTIPLY_BY |
EXTCLK0_MULTIPLY_BY |
EXTCLK1_MULTIPLY_BY |
EXTCLK2_MULTIPLY_BY |
EXTCLK3_MULTIPLY_BY |
CLK0_DIVIDE_BY | 1
CLK1_DIVIDE_BY | 1
CLK2_DIVIDE_BY |
CLK3_DIVIDE_BY |
CLK4_DIVIDE_BY |
CLK5_DIVIDE_BY |
CLK6_DIVIDE_BY |
CLK7_DIVIDE_BY |
CLK8_DIVIDE_BY |
CLK9_DIVIDE_BY |
EXTCLK0_DIVIDE_BY |
EXTCLK1_DIVIDE_BY |
EXTCLK2_DIVIDE_BY |
EXTCLK3_DIVIDE_BY |
CLK0_PHASE_SHIFT | -3000
CLK1_PHASE_SHIFT | 0
CLK2_PHASE_SHIFT |
CLK3_PHASE_SHIFT |
CLK4_PHASE_SHIFT |
CLK5_PHASE_SHIFT |
CLK6_PHASE_SHIFT |
CLK7_PHASE_SHIFT |
CLK8_PHASE_SHIFT |
CLK9_PHASE_SHIFT |
EXTCLK0_PHASE_SHIFT |
EXTCLK1_PHASE_SHIFT |
EXTCLK2_PHASE_SHIFT |
EXTCLK3_PHASE_SHIFT |
CLK0_DUTY_CYCLE | 50
CLK1_DUTY_CYCLE | 50
CLK2_DUTY_CYCLE |
CLK3_DUTY_CYCLE |
CLK4_DUTY_CYCLE |
CLK5_DUTY_CYCLE |
CLK6_DUTY_CYCLE |
CLK7_DUTY_CYCLE |
CLK8_DUTY_CYCLE |
CLK9_DUTY_CYCLE |
EXTCLK0_DUTY_CYCLE |
EXTCLK1_DUTY_CYCLE |
EXTCLK2_DUTY_CYCLE |
EXTCLK3_DUTY_CYCLE |
PORT_clkena0 | PORT_UNUSED
PORT_clkena1 | PORT_UNUSED
PORT_clkena2 | PORT_UNUSED
PORT_clkena3 | PORT_UNUSED
PORT_clkena4 | PORT_UNUSED
PORT_clkena5 | PORT_UNUSED
PORT_extclkena0 |
PORT_extclkena1 |
PORT_extclkena2 |
PORT_extclkena3 |
PORT_extclk0 | PORT_UNUSED
PORT_extclk1 | PORT_UNUSED
PORT_extclk2 | PORT_UNUSED
PORT_extclk3 | PORT_UNUSED
PORT_CLKBAD0 | PORT_UNUSED
PORT_CLKBAD1 | PORT_UNUSED
PORT_clk0 | PORT_USED
PORT_clk1 | PORT_USED
PORT_clk2 | PORT_UNUSED
PORT_clk3 | PORT_UNUSED
PORT_clk4 | PORT_UNUSED
PORT_clk5 | PORT_UNUSED
PORT_clk6 |
PORT_clk7 |
PORT_clk8 |
PORT_clk9 |
PORT_SCANDATA | PORT_UNUSED
PORT_SCANDATAOUT | PORT_UNUSED
PORT_SCANDONE | PORT_UNUSED
PORT_SCLKOUT1 |
PORT_SCLKOUT0 |
PORT_ACTIVECLOCK | PORT_UNUSED
PORT_CLKLOSS | PORT_UNUSED
PORT_INCLK1 | PORT_UNUSED
PORT_INCLK0 | PORT_USED
PORT_FBIN | PORT_UNUSED
PORT_PLLENA | PORT_UNUSED
PORT_CLKSWITCH | PORT_UNUSED
PORT_ARESET | PORT_USED
PORT_PFDENA | PORT_UNUSED
PORT_SCANCLK | PORT_UNUSED
PORT_SCANACLR | PORT_UNUSED
PORT_SCANREAD | PORT_UNUSED
PORT_SCANWRITE | PORT_UNUSED
PORT_ENABLE0 |
PORT_ENABLE1 |
PORT_LOCKED | PORT_USED
PORT_CONFIGUPDATE | PORT_UNUSED
PORT_FBOUT |
PORT_PHASEDONE | PORT_UNUSED
PORT_PHASESTEP | PORT_UNUSED
PORT_PHASEUPDOWN | PORT_UNUSED
PORT_SCANCLKENA | PORT_UNUSED
PORT_PHASECOUNTERSELECT | PORT_UNUSED
PORT_VCOOVERRANGE |
PORT_VCOUNDERRANGE |
DPA_MULTIPLY_BY |
DPA_DIVIDE_BY |
DPA_DIVIDER |
VCO_MULTIPLY_BY |
VCO_DIVIDE_BY |
SCLKOUT0_PHASE_SHIFT |
SCLKOUT1_PHASE_SHIFT |
VCO_FREQUENCY_CONTROL |
VCO_PHASE_SHIFT_STEP |
USING_FBMIMICBIDIR_PORT |
SCAN_CHAIN_MIF_FILE |
AVALON_USE_SEPARATE_SYSCLK | NO
HIDDEN_CONSTANTS | CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#VALID_LOCK_MULTIPLIER 1 CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#CLK0_PHASE_SHIFT -3000 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 2 CT#COMPENSATE_CLOCK CLK1 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_USED CT#INVALID_LOCK_MULTIPLIER 5 CT#INTENDED_DEVICE_FAMILY {Cyclone II} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#GATE_LOCK_SIGNAL NO CT#PORT_LOCKED PORT_USED
HIDDEN_PRIVATES | PT#GLOCKED_FEATURE_ENABLED 1 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c1 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 0 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 1 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 0 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_ENA_CHECK 0 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 0 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 0.00000000 PT#PHASE_SHIFT0 -3.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#BANDWIDTH_USE_CUSTOM 0 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 100.000000 PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 ns PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone II} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1365795009376962.mif PT#ACTIVECLK_CHECK 0
HIDDEN_USED_PORTS | UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used
HIDDEN_IS_NUMERIC | IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#VALID_LOCK_MULTIPLIER 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#INVALID_LOCK_MULTIPLIER 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1
HIDDEN_MF_PORTS | MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1
HIDDEN_IF_PORTS | IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0}
HIDDEN_IS_FIRST_EDIT | 0
AUTO_INCLK_INTERFACE_CLOCK_RATE | 50000000
AUTO_DEVICE_FAMILY | Cyclone II
deviceFamily | Cyclone II
generateLegacySim | false

## Software Assignments

(none)

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