--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone II" INIT_FILE="cpu_0_dc_tag_ram.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=256 NUMWORDS_B=256 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=14 WIDTH_B=14 WIDTHAD_A=8 WIDTHAD_B=8 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 10.1SP1 cbx_altsyncram 2011:01:19:21:23:41:SJ cbx_cycloneii 2011:01:19:21:23:41:SJ cbx_lpm_add_sub 2011:01:19:21:23:41:SJ cbx_lpm_compare 2011:01:19:21:23:41:SJ cbx_lpm_decode 2011:01:19:21:23:41:SJ cbx_lpm_mux 2011:01:19:21:23:41:SJ cbx_mgl 2011:01:19:21:24:50:SJ cbx_stratix 2011:01:19:21:23:41:SJ cbx_stratixii 2011:01:19:21:23:41:SJ cbx_stratixiii 2011:01:19:21:23:41:SJ cbx_stratixv 2011:01:19:21:23:41:SJ cbx_util_mgl 2011:01:19:21:23:41:SJ  VERSION_END


-- Copyright (C) 1991-2011 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION cycloneii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);

--synthesis_resources = M4K 1 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_8hf1
( 
	address_a[7..0]	:	input;
	address_b[7..0]	:	input;
	clock0	:	input;
	data_a[13..0]	:	input;
	q_b[13..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	ram_block1a0 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			INIT_FILE = "cpu_0_dc_tag_ram.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 14,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 14,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a1 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			INIT_FILE = "cpu_0_dc_tag_ram.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 14,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 1,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 14,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a2 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			INIT_FILE = "cpu_0_dc_tag_ram.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 14,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 2,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 14,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a3 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			INIT_FILE = "cpu_0_dc_tag_ram.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 14,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 3,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 14,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a4 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			INIT_FILE = "cpu_0_dc_tag_ram.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 14,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 4,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 14,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a5 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			INIT_FILE = "cpu_0_dc_tag_ram.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 14,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 5,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 14,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a6 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			INIT_FILE = "cpu_0_dc_tag_ram.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 14,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 6,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 14,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a7 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			INIT_FILE = "cpu_0_dc_tag_ram.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 14,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 7,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 14,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a8 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			INIT_FILE = "cpu_0_dc_tag_ram.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 14,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 8,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 14,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a9 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			INIT_FILE = "cpu_0_dc_tag_ram.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 14,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 9,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 14,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a10 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			INIT_FILE = "cpu_0_dc_tag_ram.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 14,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 10,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 14,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a11 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			INIT_FILE = "cpu_0_dc_tag_ram.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 14,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 11,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 14,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a12 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			INIT_FILE = "cpu_0_dc_tag_ram.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 14,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 12,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 14,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a13 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			INIT_FILE = "cpu_0_dc_tag_ram.mif",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 14,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 13,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 14,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	address_a_wire[7..0]	: WIRE;
	address_b_wire[7..0]	: WIRE;

BEGIN 
	ram_block1a[13..0].clk0 = clock0;
	ram_block1a[13..0].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[0].portadatain[] = ( data_a[0..0]);
	ram_block1a[1].portadatain[] = ( data_a[1..1]);
	ram_block1a[2].portadatain[] = ( data_a[2..2]);
	ram_block1a[3].portadatain[] = ( data_a[3..3]);
	ram_block1a[4].portadatain[] = ( data_a[4..4]);
	ram_block1a[5].portadatain[] = ( data_a[5..5]);
	ram_block1a[6].portadatain[] = ( data_a[6..6]);
	ram_block1a[7].portadatain[] = ( data_a[7..7]);
	ram_block1a[8].portadatain[] = ( data_a[8..8]);
	ram_block1a[9].portadatain[] = ( data_a[9..9]);
	ram_block1a[10].portadatain[] = ( data_a[10..10]);
	ram_block1a[11].portadatain[] = ( data_a[11..11]);
	ram_block1a[12].portadatain[] = ( data_a[12..12]);
	ram_block1a[13].portadatain[] = ( data_a[13..13]);
	ram_block1a[13..0].portawe = wren_a;
	ram_block1a[13..0].portbaddr[] = ( address_b_wire[7..0]);
	ram_block1a[13..0].portbrewe = B"11111111111111";
	address_a_wire[] = address_a[];
	address_b_wire[] = address_b[];
	q_b[] = ( ram_block1a[13..0].portbdataout[0..0]);
END;
--VALID FILE
