NTSC -> VGA using Altera University Program IP Cores

This application note will show how to configure the SOPC builder to facilitate getting an NTSC signal from the TV Decoder and outputting it to the VGA output. It has been confirmed to work with Quartus 10.1 SP1.

Here is the test project as a zip file. Hook up your DE2 to any digital camera via the RCA Video In port and any VGA monitor via the onboard VGA port and program the board with the toplevel.sof file to see results.

The Altera University Program Video documentation is also included. This pdf has extremely useful information about all of the University Program IP cores.

• VideoTest.zip
• Video core documentation

A quick explanation of what is going on.

• Video in decoder: takes an NTSC signal at 480i.
• Clipper: removes some of the vertical lines to output a 640x240 signal.
• Chroma Resampler changes YCbCr 4:2:2 to YCbCr 4:4:4
• Colour Space Converter goes from YCbCr to RGB 24 bit (8 bit per colour, 3 planes).
• Scaler 1: downsamples the signal to 320x240 so that it can fit comfortably in the SRAM.
• DMA Controller 1: This DMA controller is configured as 'From Stream to Memory'
• SRAM Controller: Configured as 'Use as DE2 pixel buffer'
• DMA Controller 2: This DMA controller is configured as 'From Memory to Stream'
• Scaler 2: Scale the video back up to 640*480, our desired output resolution
• RGB Resampler: The VGA controller needs each RGB value to be 10 bits, this core will transform 24 bit RGB values into the required 30 bit values.
• Dual Clock FIFO: VGA controller runs at 25Mhz while the rest of the system runs at 50Mhz. This core helps us cross clock domains.
• VGA Controller

All the components in the project seem to be needed. We've played with removing certain components that we didn't think were crucial (such as the clipper, or the two DMA controllers and SRAM) however doing so results in a noisy video signal being output to the screen. When/if we figure out why we will update this application note with a more thourough explanation

Comments

For the audio/video configuration core make sure that auto initialize is selected.

Change pixel format of clipper to 8 bits and 2 planes (format of 4:2:2 YCbCr)

Ensure that both DMA controllers set their 'Default Buffer Starting Address' to the base address of the SRAM they are connected to.

Remember that the first DMA Controller is configured as 'From Stream to Memory' while the second is configured as 'From Memory to Stream'

The VGA Controller runs at 25MHz!

In Quartus you need to make sure that CLOCK_27 is configured to point at PIN_C16 instead of the usual PIN_D13. If you do not do this you will get a funky output.

Programmability

The following image shows how each frame is represented in hardware. This is useful if you want to do any sort of image processing in hardware (maybe software too). The start of packet signal is asserted for the first pixel in a frame, the end of packet signal is asserted for the last pixel in a frame. The pixels come through the system in a row major order.

All of the components used in this demo have been provided by Altera and have a corresponding software interface which is accessible through the HAL. This application note does not go into it but the included video core pdf has excellent documentation.

References

• Video IP Cores for Altera DE Series Boards, Altera (this is the PDF at the beginning of this article)
• TV Decoder ADV7181B Chip application note, Jordan Tymburski and Rachita Bhatia link