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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:34:49 03/20/2010 
-- Design Name: 
-- Module Name:    pw_output - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pw_output is
	generic
	(
		PULSEWIDTH_PERIOD : integer := 7
	);
	port
	(
		clk		: in std_logic;
		pw			: in std_logic_vector(0 to 31);
		rst	: in std_logic;
		output 	: out std_logic
	);	
end pw_output;

architecture Behavioral of pw_output is

	signal cnt : std_logic_vector(0 to 31); 

begin

count_pw: process(clk,cnt,rst)
begin
	--Off by 2 ticks
	if(rst = '1') then
		cnt <= (others => '0');
	else
		if( clk'event and clk = '1' ) then
			if ( cnt = PULSEWIDTH_PERIOD ) then
				cnt <= (others => '0');
			else
				cnt <= cnt + 1;
			end if;
		end if;	
	end if;	
	
end process count_pw;

do_out: process(cnt)
begin
	if( pw >= cnt) then
		output <= '1';
	else
		output <= '0';
	end if;	
end process do_out;

end Behavioral;