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-- Company: 
-- Engineer:
--
-- Create Date:   14:52:44 03/08/2010
-- Design Name:   
-- Module Name:   D:/Xilinx/Workspace/Failsafe/top_level_tb_long_failsafe_signal_gen_1.vhd
-- Project Name:  Failsafe
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: top2_level
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY top_level_tb_long_failsafe_signal_gen_1 IS
END top_level_tb_long_failsafe_signal_gen_1;
 
ARCHITECTURE behavior OF top_level_tb_long_failsafe_signal_gen_1 IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT top2_level
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         RC_switch : IN  std_logic;
         RC_health : IN  std_logic;
         RC_input : IN  std_logic_vector(6 downto 0);
         AP_input : IN  std_logic_vector(6 downto 0);
         output : OUT  std_logic_vector(6 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal RC_switch : std_logic := '0';
   signal RC_health : std_logic := '0';
   signal RC_input : std_logic_vector(6 downto 0) := (others => '0');
   signal AP_input : std_logic_vector(6 downto 0) := (others => '0');

 	--Outputs
   signal output : std_logic_vector(6 downto 0);

   -- Clock period definitions
   constant clk_period : time := 1us;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: top2_level PORT MAP (
          clk => clk,
          rst => rst,
          RC_switch => RC_switch,
          RC_health => RC_health,
          RC_input => RC_input,
          AP_input => AP_input,
          output => output
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100ms.
      wait for 100ms;	

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;