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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:08:59 03/04/2010 
-- Design Name: 
-- Module Name:    top_level - Structural 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top2_level is

    Port (
			  clk : in std_logic;
			  rst : in std_logic;
			  RC_switch : in std_logic;
--			  AP_switch : in std_logic;
			  RC_health : in std_logic;
--			  AP_health : in std_logic;
			  RC_input : in  STD_LOGIC_VECTOR(6 downto 0);
           AP_input : in  STD_LOGIC_VECTOR(6 downto 0);
			  output : out  STD_LOGIC_VECTOR(6 downto 0);
	--		  			  output2 : out  STD_LOGIC_VECTOR(6 downto 0);
			  			  led: out std_logic_vector(1 downto 0)
--						  			  			  led2: out std_logic_vector(1 downto 0)
			  );
			  
end top2_level;

architecture Structural of top2_level is



component failsafe_unit is

	Generic (	AP_input_size: natural := 7;
					RC_input_size: natural := 7;
					output_size: natural := 7
				 );
    Port (
			  clk : in std_logic;
			  rst : in std_logic;
			  RC_switch : in std_logic;
--			  AP_switch : in std_logic;
			  RC_health : in std_logic;
--			  AP_health : in std_logic;
			  RC_input : in  STD_LOGIC_VECTOR(6 downto 0);
           AP_input : in  STD_LOGIC_VECTOR(6 downto 0);
			  output : out  STD_LOGIC_VECTOR(6 downto 0);
			  led: out std_logic_vector(1 downto 0)
			  );
end component;

component pass is
    Port ( input : in  STD_LOGIC;
           output : out  STD_LOGIC);
end component;


begin


c1:	failsafe_unit port map(clk, rst, RC_switch, RC_health, RC_input, AP_input, output, led);


--sc2:	pass port map (RC_switch, output(0));

--output(0) <= clk;
--output(6 downto 1) <= "111111";
--led <= "11";
--led(0) <= RC_switch;
--led(1) <= '1';

end Structural;