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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:34:24 03/03/2010 
-- Design Name: 
-- Module Name:    timer_unit - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.top_package.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;



entity timer_unit is

    Port ( state : in std_logic_vector(1 downto 0);
			  clk : std_logic;
           timeout : out  std_logic);
end timer_unit;

architecture Structural of timer_unit is

component state_check
	generic( check_state : STD_LOGIC_VECTOR(1 downto 0) := "10");
	port( state: in STD_LOGIC_VECTOR(1 downto 0);
			output : out  STD_LOGIC
	);
end component;
	
component timer
    Port ( 
				clk : in std_logic;
				start : in std_logic;
				timeout : out std_logic);
end component;

component pw_checker is
	generic( lower_pw : natural;
				upper_pw : natural);
    Port ( input : in  STD_LOGIC;
			  rst : in STD_LOGIC;
			  clk : in  STD_LOGIC;
           output : out  STD_LOGIC);
end component;


signal n1: STD_LOGIC;


signal n2: STD_LOGIC;

signal cnt: natural;


begin


do_cnt: process(clk) is
begin

	if(n1 = '1') then
		if(clk'event and clk = '1') then
			if(cnt = timeout_reset_limit) then
				n2 <= '1';
			else
				cnt <= cnt + 1;
			end if;
		end if;	
	else
		n2 <= '0';
		cnt <=  0;
	end if;

end process;


c1:	state_check	port map (state, n1);
			
c2:	timer	port map (clk, n2, timeout);


end Structural;