--------------------------------------------------------------------------------
-- Company: 		 UofA	
-- Engineer:		 Jesse Xi Chen, ID: 1147349
--
-- Create Date:    07:56:04 10/26/09
-- Design Name:    Stop Watch
-- Module Name:    timer - Behavioral
-- Project Name:   Lab 3
-- Target Device:  
-- Tool versions:  
-- Description:	 This is a stop watch which will keep track of time to the
--						 nearest tenth of second. 
--
-- Dependencies:	 clk, En, and Rst
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.top_package.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity timer is
--	Generic (	limit : natural := 32
	Generic (	limit : natural := timeout_limit
--	Generic (	limit : natural := 21E8 --21 seconds
				 );
    Port ( 
				clk : in std_logic;
				start : in std_logic;
				timeout : out std_logic);
end timer;

architecture Behavioral of timer is

signal cnt: Integer range 0 to limit;

begin
	
	main_proc: process (clk, start) is
		begin
			if( start = '1') then
				if( clk'event and clk = '1') then
					if cnt = limit then
						timeout <= '1';
					else 
						cnt <= cnt + 1;
					end if;
				end if;
			else
				cnt <= 0;
				timeout <= '0';
			end if;	
	end process main_proc;		
		
end Behavioral;