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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:48:44 03/03/2010 
-- Design Name: 
-- Module Name:    state_check - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity state_check is
	generic( check_state : STD_LOGIC_VECTOR(1 downto 0));
    Port ( state : in  STD_LOGIC_VECTOR(1 downto 0);
           output : out  STD_LOGIC);
end state_check;

architecture Behavioral of state_check is

begin

main: process(state) is begin
	if( state = check_state) then
		output <= '1';
	else
		output <= '0';
	end if;	
end process main;


end Behavioral;