----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:50:08 04/06/2010 
-- Design Name: 
-- Module Name:    rising_edge_bound - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


entity rising_edge_bound is
--		generic( lower_bound : natural := 2;--195000, --1.9ms to 2ms
--					upper_bound : natural := 5; --215000,
--					check_len   : natural := 5
--		);
--		generic( lower_bound : natural := 2220000;--195000, --1.9ms to 2ms^
--					upper_bound : natural := 2230000; --215000,
--					check_len   : natural := 15
--		);
--		generic( lower_bound : natural := 2220000;--195000, --1.9ms to 2ms^
--					upper_bound : natural := 2224222; --215000,
--					check_len   : natural := 25
--		);
--		
--		generic( lower_bound : natural := 2220000;--195000, --1.9ms to 2ms^
--					upper_bound : natural := 2224444; --215000,
--					check_len   : natural := 25
--		);
		
		generic( lower_bound : natural := 2220000;--195000, --1.9ms to 2ms^
					upper_bound : natural := 2244444; --215000,
					check_len   : natural := 50
		);
		
    Port ( input : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           output : out  STD_LOGIC);
end rising_edge_bound;

architecture Behavioral of rising_edge_bound is

signal cnt : natural;
--signal eval : natural;
signal prev : std_logic;
signal shift_reg : std_logic_vector(check_len-1 downto 0);

begin

do_count: process(clk,input)
begin 

	--if( input'event and input = '1' ) then
	--	eval <= cnt;
	--	cnt <= 0;
	--else
		--if( clk'event and clk = '1' ) then
			--cnt <= cnt + 1;
		--end if;
	--end if;
	
--		if( clk'event and clk = '1' ) then
--			if( input = '0') then 
--				cnt <= 0;
--			else	
--				cnt <= cnt + 1;
--			end if;
--		end if;

--	if( input'event and input = '1' ) then
--		eval <= cnt;
--		--cnt <= 0;
--	end if;	

		if( clk'event and clk = '1' ) then
		--ugly hack to get this to synthesize
			prev <= input;
			if(prev = '0' and input ='1') then --rising edge
				cnt <= 0;
			else	
				cnt <= cnt + 1;
			end if;	
		end if;
		
end process;

--do_eval: process(input)
--begin

--	if( input'event and input = '1' ) then
--		eval <= cnt;
--	end if;	
--	if( input'event and input = '1' ) then
--		rose <= '1';
--	end if;	

--end process; 

--do_shift: process(eval)
--begin
--	if( eval > lower_bound and eval < upper_bound ) then
--		--output <= '0';
--		shift_reg <= '0' & shift_reg(check_len-1 downto 1);
--	else
--		--output <= '1';
--		shift_reg <= '1' & shift_reg(check_len-1 downto 1);
--	end if;	
--end process;

do_shift: process(input)
begin

	if( input'event and input = '1' ) then
		if( cnt > lower_bound and cnt < upper_bound ) then
			shift_reg <= '0' & shift_reg(check_len-1 downto 1);
		else
			shift_reg <= '1' & shift_reg(check_len-1 downto 1);
		end if;
	end if;	

end process;

do_out: process(shift_reg)
variable ones : natural;
begin
--logical or elements of shift_reg
	--output <= '1' when shift_reg != (shift_reg'range => '0') else '0';
--	if(shift_reg = (shift_reg'range => '0')) then
--		output <= '0';
--	else
--		output <= '1';
--	end if;
--	if(shift_reg = (shift_reg'range => '1')) then
--		output <= '1';
--	else
--		output <= '0';
--	end if;
  ones := 0;
  for i in check_len-1 downto 0 loop
    if(shift_reg(i) = '1') then
		ones := ones + 1;
	 end if;
  end loop;
  if(ones > check_len/2) then
	output <= '1';
  else
	output <= '0';
  end if;	
	
	
end process;
	

end Behavioral;