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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:25:18 03/03/2010 
-- Design Name: 
-- Module Name:    failsafe_unit - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity failsafe_unit is

	Generic (	AP_input_size: natural := 7;
					RC_input_size: natural := 7;
					output_size: natural := 7
				 );
    Port (
			  clk : in std_logic;
			  rst : in std_logic;
			  RC_switch : in std_logic;
--			  AP_switch : in std_logic;
			  RC_health : in std_logic;
--			  AP_health : in std_logic;
			  RC_input : in  STD_LOGIC_VECTOR(RC_input_size-1 downto 0);
           AP_input : in  STD_LOGIC_VECTOR(AP_input_size-1 downto 0);
			  output : out  STD_LOGIC_VECTOR(output_size-1 downto 0);
			  led: out std_logic_vector(1 downto 0)
			  );
end failsafe_unit;

architecture Structural of failsafe_unit is

component timer_unit is
Port ( state : in std_logic_vector(1 downto 0);
			  clk : std_logic;
           timeout : out  std_logic);
end component timer_unit;

component MUX is
	generic(n : natural := output_size);
    Port ( 
			  Autopilot_Control : in  STD_LOGIC_VECTOR (n-1 downto 0);
           RC_Control : in  STD_LOGIC_VECTOR (n-1 downto 0);
           Failsafe_Control : in  STD_LOGIC_VECTOR (n-1 downto 0);
			  state: in STD_LOGIC_VECTOR(1 downto 0);
           Servo_out : out  STD_LOGIC_VECTOR (n-1 downto 0));
end component MUX;

component FSM is
    Port ( RC_SW, LOS, TIMEOUT, clk, rst: in std_logic;
           state : out std_logic_vector(1 downto 0));
end component FSM;

component failsafe_signal_gen is
	generic(	n : natural := output_size
	);
    Port ( 	state: in STD_LOGIC_VECTOR(1 downto 0);
				clk: STD_LOGIC;
				rst: STD_LOGIC;
				output : out  STD_LOGIC_VECTOR(n-1 downto 0)
			);
end component;

component unglitched_input is --not going to use this yet
	generic( sample : natural := 3);
    Port ( input : in  STD_LOGIC;
			  clk 	: in  STD_LOGIC;
           output : out  STD_LOGIC);
end component;

--shotty coding style for LOS/SW signal detection
component pw_checker is
	generic( lower_pw : natural := 90000; --0.9ms
				upper_pw : natural := 120000); --1.2ms
    Port ( input : in  STD_LOGIC;
			  rst : in STD_LOGIC;
			  clk : in  STD_LOGIC;
           output : out  STD_LOGIC);
end component;

component los_detecter is
    Port ( input : in  STD_LOGIC;
			  clk : in  STD_LOGIC;
           output : out  STD_LOGIC);
end component;


signal state: std_logic_vector(1 downto 0);
--signal RC_SW: std_logic;
--signal LOS: std_logic;
signal TIMEOUT: std_logic;
signal FAILSAFE_CONTROL : STD_LOGIC_VECTOR (output_size-1 downto 0);
signal switch : std_logic;
--signal health_low : std_logic;
signal health_high : std_logic;
signal LOS: std_logic;

begin

--c1:	FSM port map (RC_SW, LOS, TIMEOUT, clk, rst, state );
--c1:	FSM port map (RC_switch, RC_health, TIMEOUT, clk, rst, state );
--c1:	FSM port map (switch, RC_health, TIMEOUT, clk, rst, state );
c1:	FSM port map (switch, LOS, TIMEOUT, clk, rst, state );
--c1:	FSM port map (switch, RC_health, TIMEOUT, clk, rst, state );
--c1:	FSM port map (RC_switch, RC_health, TIMEOUT, clk, rst, state );

c2:	MUX port map (AP_input, RC_input, FAILSAFE_CONTROL, state, output );

--c2:	MUX port map (AP_input, RC_input, FAILSAFE_CONTROL, state, output );

c3:	failsafe_signal_gen port  map ( state, clk, rst, FAILSAFE_CONTROL );

c4:	timer_unit port  map ( state, clk, TIMEOUT );

--sw_pw_checker:	pw_checker generic map (90000, 120000 ) port map (RC_switch, rst, clk, switch);
--sw_pw_checker:	pw_checker generic map (90000, 120000 ) port map (RC_switch, rst, clk, switch);
sw_pw_checker:	pw_checker generic map (90000, 150000 ) port map (RC_input(0), rst, clk, switch);
--sw_pw_checker:	pw_checker generic map (120001, 150000 ) port map (RC_switch, rst, clk, switch);

--health_high_pw_checker:	pw_checker generic map(150001,180000) port map (RC_switch, rst, clk, health_high);
--health_high_pw_checker:	pw_checker generic map(150001,210000) port map (RC_input(0), rst, clk, health_high);

--LOS <= health_high;

--c5: los_detecter port map (input => RC_switch, clk=>clk, output=>LOS);

c5: los_detecter port map (input => RC_input(0), clk=>clk, output=>LOS);
--LOS <= '0';

led <= state;

end Structural;