----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    03:33:19 03/04/2010 
-- Design Name: 
-- Module Name:    failsafe_signal_gen - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.top_package.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity failsafe_signal_gen is
	generic(	n : natural := 9
				);

    Port ( 	state: in STD_LOGIC_VECTOR(1 downto 0);
				clk: STD_LOGIC;
				rst: STD_LOGIC;
				output : out STD_LOGIC_VECTOR(n-1 downto 0)
			);
end failsafe_signal_gen;

architecture Behavioral of failsafe_signal_gen is

--type array_of_pw is array (n-1 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
--type array_of_pw is array (n-1 downto 0) of integer;

--signal mode: std_logic;

signal pulse_width_vec: array_of_pw;

signal cnt : STD_LOGIC_VECTOR(31 downto 0) ;
--signal cnt : integer;

begin

mode_switch: process(state) is begin
	if(state = "11") then --forced landing
		--pulse_width_vec <= (1=>"00000000000000000000000000000011", others => "00000000000000000000000000000001" ); --MACRO
  	-- pulse_width_vec <= (1=>"00000000000000110011010001010000", others => "00000000000000010101111110010000" );
--		pulse_width_vec <= (0=>41E7, others => 42E7 );		--MACRO
--		mode <= '1';
		pulse_width_vec <= forced_landing_input;
	else
		--pulse_width_vec <=  (1=> "00000000000000000000000000000001", others =>"00000000000000000000000000000011"); --MACRO
		--pulse_width_vec <=(1=>"00000000000000010101111110010000", others => "00000000000000110011010001010000"); --MACRO
--		mode <= '0';
--		pulse_width_vec <= (1=>21E6, others => 9E4 );
		pulse_width_vec <= glide_output; 
	end if;	
end process mode_switch;


gen:FOR i in 0 to n-1 GENERATE

process(clk) is begin


	if(clk'event and clk = '1') then
		if(cnt = pw_period) then
		--if(cnt = "0000000000000000000000000111") then
		--if(cnt = 0) then 
			output(i) <= '1';
		else
			if( pulse_width_vec(i) = cnt ) then
				output(i) <= '0';
		end if;
			
		end if;

	end if; 
	
end process;


END GENERATE gen;


process(clk,rst) is begin
	if(rst = '1') then
		cnt <= "00000000000000000000000000000000";	
	else
		if(clk'event and clk = '1') then
	
--			if(cnt =  "00000000000111101000010010000000") then -- MACRO reset --20ms
			--if(cnt =  "00000000000000000000000000000111") then -- MACRO reset --20ms
			if(cnt =  pw_period) then -- MACRO reset --20ms
				cnt <= "00000000000000000000000000000000";
--			if(cnt = 2E6) then -- MACRO reset --20ms
--				cnt <= 0;
			else
				if(cnt = "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU") then
					cnt <= "00000000000000000000000000000000";
				else	
				cnt <= cnt + 1;
				end if;
			end if;
		end if;
	end if;
end process;

--reset: process(rst) is begin
--	cnt <= "00000000000000000000000000000000";
--end process reset;

end Behavioral;