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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:11:37 02/09/2010 
-- Design Name: 
-- Module Name:    Timeout_Gen - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Timeout_Gen is
    Port ( state, clk : in  STD_LOGIC_VECTOR (1 downto 0);
           timeout : out  STD_LOGIC);
end Timeout_Gen;

architecture Behavioral of Timeout_Gen is

signal it: integer;

begin

	--count: process(clk, state) is begin




end Behavioral;