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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:56:39 02/09/2010 
-- Design Name: 
-- Module Name:    MUX - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MUX is
	generic(n : natural := 9);
    Port ( 
			  Autopilot_Control : in  STD_LOGIC_VECTOR (n-1 downto 0);
           RC_Control : in  STD_LOGIC_VECTOR (n-1 downto 0);
           Failsafe_Control : in  STD_LOGIC_VECTOR (n-1 downto 0);
			  state: in STD_LOGIC_VECTOR(1 downto 0);
           Servo_out : out  STD_LOGIC_VECTOR (n-1 downto 0));
end MUX;

architecture Behavioral of MUX is

begin
	comb_logic: process(state,Autopilot_Control,RC_Control,Failsafe_Control) is begin
		case state is
			when "00" => Servo_out <= Autopilot_Control;
			when "01" => Servo_out <= RC_Control;
			when others => Servo_out <= Failsafe_Control;
			
		end case;
	end process comb_logic;

end Behavioral;